[P0] Synthesis-friendly tile design

[tancheng]

Existing tile design has combinational loop. Let's consider the option 2 towards a hierarchical synthesis-friendly tile design.

[yyan7223]

Hi cheng,

• Do you mean the combinationl loop in option 1 is xbar -> regs -> FU -> xbar, but we have a register in the loop that stablizes the input of xbar.
• I think there might be another issue in option 1. Assume the output data of left FU at cycle 1 will be sent to the input register of right FU at cycle 1 so that right FU can continuously process the data at cycle 2. Then the data should go through the path left xbar -> link -> right xbar during cycle 1, will that be too far for a high frequency like 1GHz?
• Do we still support bypass in option 2? There seems no red bypass lines for registers in the right of 8x8 xbar in option 2.

Regards,
Yufei

[tancheng]

Many issues for Option 1, so I prefer Option 2. Bypass is only for bypassing the register on the right side of the 8x8 xbar, with Option 2, the outputs from FUs automatically bypass those registers.

[tancheng]

Once we decoupled the FU outports control from the routing xbar, we can start to use DC compiler to resolve the potential combinational loops. @yyan7223

[tancheng]

Note that there is also a OrLink between the 2x8 xbar outports and the FU registers inports (didn't draw it).

[yyan7223]

I cannot generate the verilog using CgraTemplateRTL_test.py, CgraRTL_test.py, and TileRTL_test.py. Could you please try on your side?

[tancheng]

I cannot generate the verilog using CgraTemplateRTL_test.py, CgraRTL_test.py, and TileRTL_test.py. Could you please try on your side?

Interesting, CGRA Verilog can be generated via:

VectorCGRA/.github/workflows/python-package.yml

Line 66 in 4688d88

pytest ../cgra/test/CgraTemplateRTL_test.py -xvs --test-verilog --dump-vtb --dump-vcd

Which is already included in the GitHub action test.

@yuqisun Can you try to reproduce @yyan7223's error?

[yyan7223]

Any differences?

[tancheng]

I actually didn't try tile. What is the error for CGRA template?

[yyan7223]

The same %warning-LATCH as tile. The log seems have provided the solution verilator lint_off LATCH.

[tancheng]

@yuqisun verilator and pymtl3 version on ur side?

[yyan7223]

Mine is:
verilator-4.036
pymtl3-3.1.13
pytest-8.3.4

[tancheng]

Anyways, the error msg shows the fu_xbar update block doesn't initialize some signals, i.e., 's.recv_opt.rdy'. U can set it to 0 at beginning and retry.

[yuqisun]

Oops, even worse in my end after update master:
Still checking ...

(py39) syq@ubuntu:~/cgra/VectorCGRA/build$ pytest ../tile/test/TileRTL_test.py -xvs --test-verilog --dump-vtb --dump-vcd
======================================================= test session starts ========================================================
platform linux -- Python 3.9.21, pytest-8.3.4, pluggy-1.5.0 -- /home/syq/anaconda3/envs/py39/bin/python
cachedir: .pytest_cache
hypothesis profile 'default' -> database=DirectoryBasedExampleDatabase(PosixPath('/home/syq/cgra/VectorCGRA/build/.hypothesis/examples'))
rootdir: /home/syq/cgra/VectorCGRA
configfile: pytest.ini
plugins: hypothesis-6.122.3, pymtl3-3.1.13
collected 0 items / 1 error                                                                                                        

===================================================== short test summary info ======================================================
ERROR ../tile/test/TileRTL_test.py
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! stopping after 1 failures !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! Interrupted: 1 error during collection !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
========================================================= 1 error in 0.41s =========================================================

[tancheng]

Oops, even worse in my end after update master: Still checking ...

(py39) syq@ubuntu:~/cgra/VectorCGRA/build$ pytest ../tile/test/TileRTL_test.py -xvs --test-verilog --dump-vtb --dump-vcd
======================================================= test session starts ========================================================
platform linux -- Python 3.9.21, pytest-8.3.4, pluggy-1.5.0 -- /home/syq/anaconda3/envs/py39/bin/python
cachedir: .pytest_cache
hypothesis profile 'default' -> database=DirectoryBasedExampleDatabase(PosixPath('/home/syq/cgra/VectorCGRA/build/.hypothesis/examples'))
rootdir: /home/syq/cgra/VectorCGRA
configfile: pytest.ini
plugins: hypothesis-6.122.3, pymtl3-3.1.13
collected 0 items / 1 error                                                                                                        

===================================================== short test summary info ======================================================
ERROR ../tile/test/TileRTL_test.py
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! stopping after 1 failures !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! Interrupted: 1 error during collection !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
========================================================= 1 error in 0.41s =========================================================

--tb=short for dumping traces?

[yuqisun]

Thanks, good now. Caused by pulling the latest PyOCN (b55a160), test good after checkout 84c9f40.
I cannot reproduce yufei's error, but can double check what is your version of PyOCN @yyan7223 ?

Latest PyOCN build failed, does it matter?

Other dependencies looks same:
pytest-8.3.4
pymtl3-3.1.13
Verilator 4.036 2020-06-06 rev UNKNOWN_REV

---

PyOCN (b55a160) error message:

(py39) syq@ubuntu:~/cgra/VectorCGRA/build$ pytest ../tile/test/TileRTL_test.py -xvs --test-verilog --dump-vtb --dump-vcd --tb=short
=============================================================================== test session starts ===============================================================================
platform linux -- Python 3.9.21, pytest-8.3.4, pluggy-1.5.0 -- /home/syq/anaconda3/envs/py39/bin/python
cachedir: .pytest_cache
hypothesis profile 'default' -> database=DirectoryBasedExampleDatabase(PosixPath('/home/syq/cgra/VectorCGRA/build/.hypothesis/examples'))
rootdir: /home/syq/cgra/VectorCGRA
configfile: pytest.ini
plugins: hypothesis-6.122.3, pymtl3-3.1.13
collected 0 items / 1 error                                                                                                                                                       

===================================================================================== ERRORS ======================================================================================
___________________________________________________________________ ERROR collecting tile/test/TileRTL_test.py ____________________________________________________________________
ImportError while importing test module '/home/syq/cgra/VectorCGRA/tile/test/TileRTL_test.py'.
Hint: make sure your test modules/packages have valid Python names.
Traceback:
../../../anaconda3/envs/py39/lib/python3.9/importlib/__init__.py:127: in import_module
    return _bootstrap._gcd_import(name[level:], package, level)
../tile/test/TileRTL_test.py:18: in <module>
    from ..TileRTL import TileRTL
../tile/TileRTL.py:30: in <module>
    from ..noc.PyOCN.pymtl3_net.channel.ChannelRTL import ChannelRTL
../noc/PyOCN/pymtl3_net/channel/ChannelRTL.py:10: in <module>
    from pymtl3_net.ocnlib.ifcs.PhysicalDimension import PhysicalDimension
E   ModuleNotFoundError: No module named 'pymtl3_net'
============================================================================= short test summary info =============================================================================
ERROR ../tile/test/TileRTL_test.py
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! stopping after 1 failures !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! Interrupted: 1 error during collection !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
================================================================================ 1 error in 0.33s =================================================================================

Thanks,

[yyan7223]

All the errors are about pymtl3, not PyOCN

[yyan7223]

Anyways, the error msg shows the fu_xbar update block doesn't initialize some signals, i.e., 's.recv_opt.rdy'. U can set it to 0 at beginning and retry.

There are two many similar errors, I think it's possible because I fail to build pytml3?

The command I use is pip install -U git+https:///github.com/tancheng/pymtl3.1@yo-struct-list-fix posted on README.md

[tancheng]

Are you able to pytest without verilog generation? If yes, pymtl3 might be good.

It seems to me your verilator is over-thinking or too rigorous. Can you check how to disallow treating warning as error for verilator? (we definitely need to fix the latch issue @yo96)

[yyan7223]

Yes, the command works fine without --test-verilog.
I pass a option to the verilator to ignore the LATCH warning, but it reports another file miss error instead.

[yuqisun]

Hi @yyan7223 , please try with docker image: yuqisun/vectorcgra_for_yufei, tested with all cases in workflow.

Start container, run:

conda activate py39
cd /root/cgra/VectorCGRA/build
pytest ../tile/test/TileRTL_test.py -xvs --test-verilog --dump-vtb --dump-vcd
...
...