Adds the GUI for user to manually select constraint.sdc and config.mk

[yyan7223]

Hi cheng,

I have added two file dialogs in the layout pannel for user to choose constraint.sdc and config.mk.
User must choose this file before clicking button RTL->Layout, otherwise a file missing error dialog will pop up:

I once think about letting users to edit those two files within CGRA-Flow GUI, but this function is not directly supported by customtkinter, so I only achieve this in a straighforward way so that I can focus more on addressing the verilog transformation issue.

So, apart from this issue, is there any other GUI stuff that you think can be better optimized for conference demo if we have time left? Here are some of my intuitions:

• We can seperate the internal stages of RTL->Layout including synthesis, floorplan, place, cts, grt, and route to individual pannels, so that we can extract metrics from the OpenRoad stage report and show them on the respective pannels.
• We can also print the logs of each stage to their respective pannels using a text box so that user knows current stage is running.

Best regards,
Yufei

[tancheng]

Hi @yyan7223, thanks a lot for the PR!

The functionality of OpenRoad or synthesis is not on our critical path for the demo. @yuqisun can also help for the editable customTkInter constraint.sdc and config.mk. My suggestion/intuition is to provide the templates for them, and user can fill some parameters, say, latency requirement, area budget, etc. Anyways, such functionalities including the place, cts, grt, and route can be discussed after the demo with @yuqisun. So let's merge this PR after the MICRO demo and after discussion with @yuqisun.

The most important blocker for now is to reproduce Deepak's 2x2 using the CGRA-Flow GUI. Plz help check whether by default disabling FUs is needed or not. I appreciate that! Reporting area/power using OpenRoad instead of old version yosys is also blocked by this, and can be done after the demo.

[yyan7223]

Hi Cheng,

Now we can directly use the generated verilog from CGRA-FLow GUI to generate the layout. Here is the layout for 4x4 CGRA with 16 tiles connected through 8bits mesh interconnections, and FU that only have Adder and MemUnit. The frequency is 10MHz.

For verilog generation, Deepak uses VectorCGRA/cgra/translate/CGRARTL_test.py while the CGRA-Flow uses VectorCGRA/cgra/translate/CGRATemplateRTL_test.py by default. The latter generates a complex CGRA that contains 32bits kingmesh topology and FU with all functions, that is why previously it cannot be normally synthesis and placed. So I simply modify the clickGenerateVerilog() to call CGRARTL_test.py that generates a simple CGRA, and everything works fine.

So now in the CGRA-Flow GUI, you can click the Generate button to generate verilog, then select constriant.sdc and config.mk, finally click RTL-> Layout button and wait for 4 hours (on my machine), you can see the layout image in the pannel.

Feel free to tell me if you have more requirements.

Best regards,
Yufei

[tancheng]

lol, thanks @yyan7223! This is awesome!

The reason we use CGRATemplateRTL_test.py is to be able to customize the topology.. If only the 8-bit mesh with Adder+MemUnit is synthesizable, the proper fix on the GUI side should be (rather than simply changing to CGRARTL_test.py):

• enable the CGRATemplate with only Adder+MemUnit by default
• provide two buttons for topology, one for applying/modeling kingmesh, the other one for mesh
• a field to allow user to set mesh/link/channel bit-width (e.g., 8 bit)

I believe @yuqisun can help with above GUI changes.

Meanwhile, @yyan7223 can you help:

• use CGRATemplateRTL_test.py to generate the 2x2 CGRA with mesh & adder+memUnit? You can just invoke the test_cgra_universal() with param = None using the command pytest CGRATemplateRTL_test.py -xvs --tb=short --test-verilog --dump-vtb --dump-vcd to generate the 2x2 kingmesh CGRA. If you think kingmesh won't work, you can disable/remove the diagonal connections here; If you think 32-bit channel is too wide for synthesis, you can change it to 8-bit here.

How does this sound to you @yyan7223?

[yuqisun]

Hi both,

Could you help clarify where to add button/field? You can mark in blow screenshot.

Thanks,

[yyan7223]

It sounds good to me.
I will fristly try whether 2x2 CGRA with Kingmesh, adder+memUnit, and 32bits channel can be normally synthesised.

[tancheng]

Hi @yuqisun, I think:

• We can add another panel (sibling panel of Tile x crossbar outgoing links, and can be called Topology) under the Tile x crossbar outgoing links panel.
• Blue is the field for bitwidth setting while red are the two buttons. (Actually, let's put two red before the blue..)

How does it sound to you?

[yyan7223]

Hi all,

I successfully generate the layout of 2x2 CGRA with kingmesh and all functions enable, which means we probably don't need to change any default settings in the CGRA pannel.

And Yuqi @yuqisun , could you please also try to reproduce this layout on your side. Just simply:

• Checkout the CGRA-Flow/tools/OpenRoad-flow-scripts to any version committed on Oct 1st (The latest commits bring many bugs)
• Open CGRA-Flow GUI, change the Rows Columns to both 2, click Update button.
• Click Generate button to automatically generate the verilog file.
• Select constraint.sdc and config.mk, and finally click RTL->Layout.
  It take about 5 hours to generate layout on my machine (Intel i7-12700H, 16 theads). I strongly recommend that do not use your computer to do any other things because the routing stage optimization almost runs out of all the memory.

Best regards,
Yufei

[tancheng]

@yyan7223 The layout looks awesome!

• Did you use @yuqisun's docker? If not, which version of the CGRA-Flow it is, and it is dark-mode, right?
• What is the version of the sub-module: VectorCGRA. Please make sure you two are synced in the same version.
• Should @yuqisun invoke the docker with --memory= to avoid running out of memory? What is the budget you provided?

@yuqisun, if you can reproduce, we don't need the new 3 buttons for now, though it is better to have them in the future.

[tancheng]

@yuqisun note that you need to pull latest (before following @yyan7223's steps) as we just merged this PR.

[yyan7223]

@tancheng @yuqisun

• Yeah I use yuqi's latest docker docker.io/yuqisun/cgra-flow-openroad.
• VectorCGRA is the version contained in yuqi's docker image.
• The virtual machine I set is 32GB RAM, which should be inherited to the docker.

[yuqisun]

Hi,

It's running on my computer now, should cost more time than Yufei, my machine: i5-9400F, 2.9G, 6 cores.
Will push image once all good.

And I'm using the last commit on Oct.1: f1bc7bc5891dc29ad94f248ec7ceaed892402958 of CGRA-Flow/tools/OpenRoad-flow-scripts repo: Merge pull request The-OpenROAD-Project/OpenROAD-flow-scripts#2390 from jeffng-or/orfs-v2.2-migration

Thanks,

[tancheng]

lol, let me try it on my side as well.

[yuqisun]

Hi Yufei @yyan7223,

Took 17 hours finally, but not lucky in my end, have any idea, do I need to adjust some settings to avoid this error?

Attached congestion.rpt
congestion.zip

[INFO GRT-0103] Extra Run for hard benchmark.
[INFO GRT-0197] Via related to pin nodes: 3698741
[INFO GRT-0198] Via related Steiner nodes: 196645
[INFO GRT-0199] Via filling finished.
[INFO GRT-0111] Final number of vias: 6314414
[INFO GRT-0112] Final usage 3D: 27992893
[ERROR GRT-0119] Routing congestion too high. Check the congestion heatmap in the GUI and load ./reports/asap7/CGRATemplateRTL/base/congestion.rpt in the DRC viewer.
Error: global_route.tcl, 111 GRT-0119
Command exited with non-zero status 1
Elapsed time: 17:22:47[h:]min:sec. CPU time: user 62566.87 sys 3.71 (100%). Peak memory: 8355792KB.
make[1]: *** [Makefile:827: do-5_1_grt] Error 1
make: *** [Makefile:825: results/asap7/CGRATemplateRTL/base/5_1_grt.odb] Error 2
OpenROAD 9b28074f5d04c68a9ddcc5c571583c1950e326a2
Features included (+) or not (-): +Charts +GPU +GUI +Python : None
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[ERROR ORD-0007] /WORK_REPO/CGRA-Flow/tools/OpenROAD-flow-scripts/flow/results/asap7/CGRATemplateRTL/base/6_final.odb does not exist.
Error: cmd.tcl, 1 ORD-0007
openroad>
Exception in Tkinter callback
Traceback (most recent call last):
File "/usr/lib/python3.7/tkinter/init.py", line 1708, in call
return self.func(*args)
File "/WORK_REPO/venv/lib/python3.7/site-packages/customtkinter/windows/widgets/ctk_button.py", line 554, in _clicked
self._command()
File "../mode_dark_light.py", line 2258, in clickRTL2Layout
File "../mode_dark_light.py", line 2275, in display_layout_image
File "/WORK_REPO/venv/lib/python3.7/site-packages/PIL/Image.py", line 3227, in open
fp = builtins.open(filename, "rb")
FileNotFoundError: [Errno 2] No such file or directory: '/WORK_REPO/CGRA-Flow/tools/OpenROAD-flow-scripts/flow/layout.png'

Thanks,

[tancheng]

@yyan7223 Same here. But it automatically exits at:

[INFO GRT-0101] Running extra iterations to remove overflow.

Should also be around step 5_1 that is related to global_route.

• @yyan7223 Are we on the same commit (f1bc7bc5891dc29ad94f248ec7ceaed892402958) of OpenRoad with @yuqisun?
• I didn't change anything after pulling @yuqisun's docker except checkout to above OpenRoad--flow-scripts commit.
• What is the VectorCGRA commit on your side?
• I will start over another launch with 16 cores.

[tancheng]

• Well, my laptop only has 4 cores :-)
• I need to remove all the outstanding changes in the CGRA-Flow folder/repo before pulling the latest one to avoid conflict.
  • @yuqisun Let's keep the repo clean without local changes next time when we push a docker image.
• I am using ASAP7.
• I disable MAC and the kingmesh, let's see this round.
• I didn't touch verilator version.

[yyan7223]

Hi both,

• I'm so sorry that I forget to tell you the clock_period in constraint sdc has been changed to 100000, and that's probably why it has the congestion issue. Really sorry about that...
• Yes we are on the same commit of OpenRoad, and the VectorCGRA commit is (b9859b7e66fab514427cddeb0abe44a8008c2ab1).

[tancheng]

No worry, let us re-try. Can you please also try 50000 on your side?

[tancheng]

@yyan7223 We do it on 7nm, right? 10MHz still hangs on my side at the same place. Removing MAC and kingmesh to retry now.

[yyan7223]

• Yes we use asap7, and 20MHz does not work on my side.
• I will package a docker image today, let's see whether it's the issue of dependencies and parameters or the number of cores.

[yyan7223]

Hi alls,

I have pushed the docker image, using docker pull yufeiyang277/cgra-flow:latest to download it.
To reproduce the 2x2 CGRA RTL->Layout, please go through follow steps:

1. Goes into the container and runs git clone https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts.git, then checkout to the commit f1bc7bc5891dc29ad94f248ec7ceaed892402958 on Oct 1st, finally copies OpenROAD-flow-scripts folder to path WORK_REPO/CGRA-Flow/tools/.
2. Opens CGRA-Flow GUI, changes the Rows Columns to both 2, clicks Update button.
3. Clicks Generate button to automatically generate the verilog file, selects constraint.sdc and config.mk, and finally clicks RTL->Layout and wait.

I will also try it again on my side.

Best regards,
Yufei

[yuqisun]

Hi Yufei,

Ran with your image, got some warning and 6_final.odb not found error.

[INFO DRT-0149] Reading tech and libs.
[WARNING DRT-0340] LEF58_ENCLOSURE EOL is not supported. Skipping for layer V3
[WARNING DRT-0340] LEF58_ENCLOSURE EOL is not supported. Skipping for layer V3
[WARNING DRT-0340] LEF58_ENCLOSURE EOL is not supported. Skipping for layer V4
[WARNING DRT-0340] LEF58_ENCLOSURE EOL is not supported. Skipping for layer V5
[WARNING DRT-0340] LEF58_ENCLOSURE EOL is not supported. Skipping for layer V6
...
...
[INFO DRT-0194] Start detail routing.
[INFO DRT-0195] Start 0th optimization iteration.
Completing 10% with 5990 violations.
elapsed time = 00:03:41, memory = 14193.73 (MB).
Command terminated by signal 9
Elapsed time: 12:34.37[h:]min:sec. CPU time: user 4021.05 sys 34.21 (537%). Peak memory: 14845372KB.
make[1]: *** [Makefile:831: do-5_2_route] Error 137
make: *** [Makefile:829: results/asap7/CGRATemplateRTL/base/5_2_route.odb] Error 2
OpenROAD 9b28074f5d04c68a9ddcc5c571583c1950e326a2
Features included (+) or not (-): +Charts +GPU +GUI +Python : None
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[ERROR ORD-0007] /WORK_REPO/CGRA-Flow/tools/OpenROAD-flow-scripts/flow/results/asap7/CGRATemplateRTL/base/6_final.odb does not exist.
Error: cmd.tcl, 1 ORD-0007
openroad>

(venv) root@b74eee7ebdfc OpenROAD-flow-scripts# git status
Refresh index: 100% (2284/2284), done.
HEAD detached at f1bc7bc5

Thanks,

[yyan7223]

Hi Yuqi,

• Well the true issue is actually the Command terminated by signal 9, which is caused by insufficient memory (my machine has 32GB RAM). You can try to simplify the design by enabling only Adder and LD&ST in functional unit.
• 6_final.odb does not exist is simply because OpenRoad doesn't finish the final stage but my code still want to request the corresponding report. Don't need to worry about this.

Best regards,
Yufei

[tancheng]

@yyan7223 another concern is that in the video demo, we show the DFG being mapped onto the 2x2 tiles. But if a tile can only support add and mul, the DFG cannot be mapped then..