synth.yosys

# BSD 3-Clause License

# Copyright (c) 2022, Sylvain Lefebvre (@sylefeb)
# All rights reserved.

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#    list of conditions and the following disclaimer.

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read_verilog ../build/synth.v

techmap -map +/adff2dff.v

hierarchy -check -auto-top

proc
# async2sync
flatten
opt_expr
opt_clean
check
opt -nodffe -nosdff
fsm
opt -nodffe -nosdff
wreduce
peepopt
opt_clean
techmap -map +/cmp2lut.v -D LUT_WIDTH=4
# alumacc
share
opt  -nodffe -nosdff
memory -nomap
opt_clean

opt -fast -full -nodffe -nosdff
memory_map
opt -full -nodffe -nosdff
techmap
opt -fast -nodffe -nosdff
abc -fast -lut 4
opt -fast -nodffe -nosdff

hierarchy -check
stat
check

write_blif ../build/synth.blif