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chore(u5): update to latest STM32CubeU5 v1.7.0 #2592

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Jan 20, 2025
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chore(u5): update to latest STM32CubeU5 v1.7.0 #2592

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d8a556f
system(U5) update STM32U5xx HAL Drivers to v1.6.1
fpistm Jan 10, 2025
ad802bb
system(U5): update STM32U5xx CMSIS Drivers to v1.4.1
fpistm Jan 9, 2025
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9 changes: 6 additions & 3 deletions system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u535xx.h
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Original file line number Diff line number Diff line change
Expand Up @@ -216,7 +216,7 @@ typedef enum

/** @} */ /* End of group Configuration_of_CMSIS */

#include <core_cm33.h> /*!< ARM Cortex-M33 processor and core peripherals */
#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */
#include "system_stm32u5xx.h" /*!< STM32U5xx System */


Expand Down Expand Up @@ -4796,6 +4796,9 @@ typedef struct
#define RNG_HTCR_HTCFG_Pos (0U)
#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */
#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk
/******************** RNG Nist Compliance Values *******************/
#define RNG_CR_NIST_VALUE (0x00F00D00U)
#define RNG_HTCR_NIST_VALUE (0xAAC7U)

/******************************************************************************/
/* */
Expand Down Expand Up @@ -16168,7 +16171,7 @@ typedef struct
#define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */
#define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk
#define TAMP_CR3_ITAMP7NOER_Pos (6U)
#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER)
#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER_Pos)
#define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk
#define TAMP_CR3_ITAMP8NOER_Pos (7U)
#define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000040 */
Expand Down Expand Up @@ -20293,7 +20296,7 @@ typedef struct
#define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<Voltage reference scale */
#define VREFBUF_CSR_VRS_0 (0x01UL<< VREFBUF_CSR_VRS_Pos) /*!< 0x000O0010 */
#define VREFBUF_CSR_VRS_1 (0x02UL<< VREFBUF_CSR_VRS_Pos) /*!< 0x00000020 */
#define VREFBUF_CSR_VRS_2 (0x04UL<< VREFBUF_CSR_VRS_Pos) /*!< 0x00000030 */
#define VREFBUF_CSR_VRS_2 (0x04UL<< VREFBUF_CSR_VRS_Pos) /*!< 0x00000040 */
#define VREFBUF_CSR_VRR_Pos (3U)
#define VREFBUF_CSR_VRR_Msk (0x1UL << VREFBUF_CSR_VRR_Pos) /*!< 0x00000008 */
#define VREFBUF_CSR_VRR VREFBUF_CSR_VRR_Msk /*!<Voltage reference buffer ready */
Expand Down
9 changes: 6 additions & 3 deletions system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u545xx.h
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Original file line number Diff line number Diff line change
Expand Up @@ -220,7 +220,7 @@ typedef enum

/** @} */ /* End of group Configuration_of_CMSIS */

#include <core_cm33.h> /*!< ARM Cortex-M33 processor and core peripherals */
#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */
#include "system_stm32u5xx.h" /*!< STM32U5xx System */


Expand Down Expand Up @@ -4960,6 +4960,9 @@ typedef struct
#define RNG_HTCR_HTCFG_Pos (0U)
#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */
#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk
/******************** RNG Nist Compliance Values *******************/
#define RNG_CR_NIST_VALUE (0x00F00D00U)
#define RNG_HTCR_NIST_VALUE (0xAAC7U)

/******************************************************************************/
/* */
Expand Down Expand Up @@ -16720,7 +16723,7 @@ typedef struct
#define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */
#define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk
#define TAMP_CR3_ITAMP7NOER_Pos (6U)
#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER)
#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER_Pos)
#define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk
#define TAMP_CR3_ITAMP8NOER_Pos (7U)
#define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000040 */
Expand Down Expand Up @@ -20889,7 +20892,7 @@ typedef struct
#define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<Voltage reference scale */
#define VREFBUF_CSR_VRS_0 (0x01UL<< VREFBUF_CSR_VRS_Pos) /*!< 0x000O0010 */
#define VREFBUF_CSR_VRS_1 (0x02UL<< VREFBUF_CSR_VRS_Pos) /*!< 0x00000020 */
#define VREFBUF_CSR_VRS_2 (0x04UL<< VREFBUF_CSR_VRS_Pos) /*!< 0x00000030 */
#define VREFBUF_CSR_VRS_2 (0x04UL<< VREFBUF_CSR_VRS_Pos) /*!< 0x00000040 */
#define VREFBUF_CSR_VRR_Pos (3U)
#define VREFBUF_CSR_VRR_Msk (0x1UL << VREFBUF_CSR_VRR_Pos) /*!< 0x00000008 */
#define VREFBUF_CSR_VRR VREFBUF_CSR_VRR_Msk /*!<Voltage reference buffer ready */
Expand Down
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