Maintenance release of HAL and Low layers drivers supporting STM32WB55xx devices.
This release is compatible with the previous versions.
-
Main Changes
+
Main Changes
First release
First official release of HAL (Hardware Abstraction Layer) and LL (Low layers) drivers to support STM32WB55xx.
diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
index 2dcc929e61..8fcb2d2401 100644
--- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
@@ -56,7 +56,7 @@
*/
#define __STM32WBxx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define __STM32WBxx_HAL_VERSION_SUB1 (0x0EU) /*!< [23:16] sub1 version */
-#define __STM32WBxx_HAL_VERSION_SUB2 (0x03U) /*!< [15:8] sub2 version */
+#define __STM32WBxx_HAL_VERSION_SUB2 (0x04U) /*!< [15:8] sub2 version */
#define __STM32WBxx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32WBxx_HAL_VERSION ((__STM32WBxx_HAL_VERSION_MAIN << 24U)\
|(__STM32WBxx_HAL_VERSION_SUB1 << 16U)\
diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_adc.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_adc.c
index cd10e10227..026cdea0db 100644
--- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_adc.c
+++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_adc.c
@@ -1016,27 +1016,25 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc)
#else
/* Reset register IER */
- __HAL_ADC_DISABLE_IT(hadc, (
#if defined(ADC_SUPPORT_2_5_MSPS)
- ADC_IT_AWD3 | ADC_IT_AWD2 | ADC_IT_AWD1 |
- ADC_IT_EOCAL | ADC_IT_CCRDY |
+ __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD3 | ADC_IT_AWD2 | ADC_IT_AWD1 |
+ ADC_IT_EOCAL | ADC_IT_CCRDY));
#else
- ADC_IT_AWD3 | ADC_IT_AWD2 | ADC_IT_AWD1 |
- ADC_IT_JEOS | ADC_IT_JEOC | ADC_IT_JQOVF |
+ __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD3 | ADC_IT_AWD2 | ADC_IT_AWD1 |
+ ADC_IT_JEOS | ADC_IT_JEOC | ADC_IT_JQOVF));
#endif /* ADC_SUPPORT_2_5_MSPS */
- ADC_IT_EOS | ADC_IT_EOC | ADC_IT_OVR |
+ __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOS | ADC_IT_EOC | ADC_IT_OVR |
ADC_IT_EOSMP | ADC_IT_RDY));
/* Reset register ISR */
- __HAL_ADC_CLEAR_FLAG(hadc, (
#if defined(ADC_SUPPORT_2_5_MSPS)
- ADC_FLAG_AWD3 | ADC_FLAG_AWD2 | ADC_FLAG_AWD1 |
- ADC_FLAG_EOCAL | ADC_FLAG_CCRDY |
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD3 | ADC_FLAG_AWD2 | ADC_FLAG_AWD1 |
+ ADC_FLAG_EOCAL | ADC_FLAG_CCRDY));
#else
- ADC_FLAG_AWD3 | ADC_FLAG_AWD2 | ADC_FLAG_AWD1 |
- ADC_FLAG_JEOS | ADC_FLAG_JEOC | ADC_FLAG_JQOVF |
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD3 | ADC_FLAG_AWD2 | ADC_FLAG_AWD1 |
+ ADC_FLAG_JEOS | ADC_FLAG_JEOC | ADC_FLAG_JQOVF));
#endif /* ADC_SUPPORT_2_5_MSPS */
- ADC_FLAG_EOS | ADC_FLAG_EOC | ADC_FLAG_OVR |
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOS | ADC_FLAG_EOC | ADC_FLAG_OVR |
ADC_FLAG_EOSMP | ADC_FLAG_RDY));
/* Reset register CR */
diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_crc_ex.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_crc_ex.c
index 3cd8e96110..20b66d3c44 100644
--- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_crc_ex.c
+++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_crc_ex.c
@@ -210,8 +210,6 @@ HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_
}
-
-
/**
* @}
*/
diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_lptim.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_lptim.c
index cbace79f81..7d75346870 100644
--- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_lptim.c
+++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_lptim.c
@@ -2388,7 +2388,6 @@ static HAL_StatusTypeDef LPTIM_WaitForFlag(const LPTIM_HandleTypeDef *hlptim, ui
*/
void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim)
{
- uint32_t tmpclksource = 0;
uint32_t tmpIER;
uint32_t tmpCFGR;
uint32_t tmpCMP;
@@ -2403,22 +2402,6 @@ void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim)
__set_PRIMASK(1) ;
/*********** Save LPTIM Config ***********/
- /* Save LPTIM source clock */
- switch ((uint32_t)hlptim->Instance)
- {
- case LPTIM1_BASE:
- tmpclksource = __HAL_RCC_GET_LPTIM1_SOURCE();
- break;
-#if defined(LPTIM2)
- case LPTIM2_BASE:
- tmpclksource = __HAL_RCC_GET_LPTIM2_SOURCE();
- break;
-#endif /* LPTIM2 */
- default:
- break;
- }
-
- /* Save LPTIM configuration registers */
tmpIER = hlptim->Instance->IER;
tmpCFGR = hlptim->Instance->CFGR;
tmpCMP = hlptim->Instance->CMP;
@@ -2447,21 +2430,6 @@ void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim)
/*********** Restore LPTIM Config ***********/
if ((tmpCMP != 0UL) || (tmpARR != 0UL))
{
- /* Force LPTIM source kernel clock from APB */
- switch ((uint32_t)hlptim->Instance)
- {
- case LPTIM1_BASE:
- __HAL_RCC_LPTIM1_CONFIG(RCC_LPTIM1CLKSOURCE_PCLK1);
- break;
-#if defined(LPTIM2)
- case LPTIM2_BASE:
- __HAL_RCC_LPTIM2_CONFIG(RCC_LPTIM2CLKSOURCE_PCLK1);
- break;
-#endif /* LPTIM2 */
- default:
- break;
- }
-
if (tmpCMP != 0UL)
{
/* Restore CMP register (LPTIM should be enabled first) */
@@ -2490,21 +2458,6 @@ void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim)
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
}
-
- /* Restore LPTIM source kernel clock */
- switch ((uint32_t)hlptim->Instance)
- {
- case LPTIM1_BASE:
- __HAL_RCC_LPTIM1_CONFIG(tmpclksource);
- break;
-#if defined(LPTIM2)
- case LPTIM2_BASE:
- __HAL_RCC_LPTIM2_CONFIG(tmpclksource);
- break;
-#endif /* LPTIM2 */
- default:
- break;
- }
}
/* Restore configuration registers (LPTIM should be disabled first) */
diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pcd.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pcd.c
index f247475876..4003cad00a 100644
--- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pcd.c
+++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pcd.c
@@ -1389,7 +1389,7 @@ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)
HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
uint16_t ep_mps, uint8_t ep_type)
{
- HAL_StatusTypeDef ret = HAL_OK;
+ HAL_StatusTypeDef ret = HAL_OK;
PCD_EPTypeDef *ep;
if ((ep_addr & 0x80U) == 0x80U)
@@ -1404,7 +1404,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
}
ep->num = ep_addr & EP_ADDR_MSK;
- ep->maxpacket = ep_mps;
+ ep->maxpacket = (uint32_t)ep_mps & 0x7FFU;
ep->type = ep_type;
/* Set initial data PID. */
@@ -1809,7 +1809,6 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
if (((wEPVal & USB_EP_SETUP) == 0U) && ((wEPVal & USB_EP_RX_STRX) != USB_EP_RX_VALID))
{
- PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket);
PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
}
}
@@ -1930,7 +1929,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
/* Manage Single Buffer Transaction */
if ((wEPVal & USB_EP_KIND) == 0U)
{
- /* multi-packet on the NON control IN endpoint */
+ /* Multi-packet on the NON control IN endpoint */
TxPctSize = (uint16_t)PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
if (ep->xfer_len > TxPctSize)
@@ -2006,7 +2005,7 @@ static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd,
if (ep->xfer_len == 0U)
{
- /* set NAK to OUT endpoint since double buffer is enabled */
+ /* Set NAK to OUT endpoint since double buffer is enabled */
PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK);
}
@@ -2038,11 +2037,11 @@ static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd,
if (ep->xfer_len == 0U)
{
- /* set NAK on the current endpoint */
+ /* Set NAK on the current endpoint */
PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK);
}
- /*Need to FreeUser Buffer*/
+ /* Need to FreeUser Buffer */
if ((wEPVal & USB_EP_DTOG_TX) == 0U)
{
PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U);
@@ -2092,6 +2091,12 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd,
PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
+ if (ep->type == EP_TYPE_BULK)
+ {
+ /* Set Bulk endpoint in NAK state */
+ PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_NAK);
+ }
+
/* TX COMPLETE */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataInStageCallback(hpcd, ep->num);
@@ -2103,10 +2108,12 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd,
{
PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U);
}
+
+ return HAL_OK;
}
else /* Transfer is not yet Done */
{
- /* need to Free USB Buff */
+ /* Need to Free USB Buffer */
if ((wEPVal & USB_EP_DTOG_RX) != 0U)
{
PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U);
@@ -2137,7 +2144,7 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd,
}
/* Write remaining Data to Buffer */
- /* Set the Double buffer counter for pma buffer1 */
+ /* Set the Double buffer counter for pma buffer0 */
PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, len);
/* Copy user buffer to USB PMA */
@@ -2165,6 +2172,12 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd,
PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
+ if (ep->type == EP_TYPE_BULK)
+ {
+ /* Set Bulk endpoint in NAK state */
+ PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_NAK);
+ }
+
/* TX COMPLETE */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataInStageCallback(hpcd, ep->num);
@@ -2177,10 +2190,12 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd,
{
PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U);
}
+
+ return HAL_OK;
}
else /* Transfer is not yet Done */
{
- /* need to Free USB Buff */
+ /* Need to Free USB Buffer */
if ((wEPVal & USB_EP_DTOG_RX) == 0U)
{
PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U);
@@ -2210,7 +2225,7 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd,
ep->xfer_fill_db = 0;
}
- /* Set the Double buffer counter for pmabuffer1 */
+ /* Set the Double buffer counter for pma buffer1 */
PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len);
/* Copy the user buffer to USB PMA */
@@ -2219,7 +2234,7 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd,
}
}
- /*enable endpoint IN*/
+ /* Enable endpoint IN */
PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID);
return HAL_OK;
@@ -2227,13 +2242,11 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd,
#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
-
/**
* @}
*/
#endif /* defined (USB) */
#endif /* HAL_PCD_MODULE_ENABLED */
-
/**
* @}
*/
diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pcd_ex.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pcd_ex.c
index 49457712e4..baadd33678 100644
--- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pcd_ex.c
+++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pcd_ex.c
@@ -242,7 +242,6 @@ void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd)
}
}
-
/**
* @brief Activate LPM feature.
* @param hpcd PCD handle
@@ -279,7 +278,6 @@ HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd)
}
-
/**
* @brief Send LPM message to user layer callback.
* @param hpcd PCD handle
diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
index 71d2bc49dc..982b7fdd57 100644
--- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
@@ -125,21 +125,43 @@ void HAL_PWR_DeInit(void)
LL_PWR_WriteReg(C2CR3, PWR_C2CR3_RESET_VALUE);
/* Clear all flags */
+#if defined(PWR_CR3_E802A) && defined(PWR_CR5_SMPSEN)
LL_PWR_WriteReg(SCR,
- LL_PWR_SCR_CC2HF
- | LL_PWR_SCR_CBLEAF
- | LL_PWR_SCR_CCRPEF
-#if defined(PWR_CR3_E802A)
- | LL_PWR_SCR_C802AF
- | LL_PWR_SCR_C802WUF
-#endif /* PWR_CR3_E802A */
- | LL_PWR_SCR_CBLEWUF
-#if defined(PWR_CR5_SMPSEN)
- | LL_PWR_SCR_CBORHF
- | LL_PWR_SCR_CSMPSFBF
-#endif /* PWR_CR5_SMPSEN */
- | LL_PWR_SCR_CWUF
- );
+ LL_PWR_SCR_CC2HF
+ | LL_PWR_SCR_CBLEAF
+ | LL_PWR_SCR_CCRPEF
+ | LL_PWR_SCR_C802AF
+ | LL_PWR_SCR_C802WUF
+ | LL_PWR_SCR_CBLEWUF
+ | LL_PWR_SCR_CBORHF
+ | LL_PWR_SCR_CSMPSFBF
+ | LL_PWR_SCR_CWUF);
+#elif defined(PWR_CR3_E802A)
+ LL_PWR_WriteReg(SCR,
+ LL_PWR_SCR_CC2HF
+ | LL_PWR_SCR_CBLEAF
+ | LL_PWR_SCR_CCRPEF
+ | LL_PWR_SCR_C802AF
+ | LL_PWR_SCR_C802WUF
+ | LL_PWR_SCR_CBLEWUF
+ | LL_PWR_SCR_CWUF);
+#elif defined(PWR_CR5_SMPSEN)
+ LL_PWR_WriteReg(SCR,
+ LL_PWR_SCR_CC2HF
+ | LL_PWR_SCR_CBLEAF
+ | LL_PWR_SCR_CCRPEF
+ | LL_PWR_SCR_CBLEWUF
+ | LL_PWR_SCR_CBORHF
+ | LL_PWR_SCR_CSMPSFBF
+ | LL_PWR_SCR_CWUF);
+#else
+ LL_PWR_WriteReg(SCR,
+ LL_PWR_SCR_CC2HF
+ | LL_PWR_SCR_CBLEAF
+ | LL_PWR_SCR_CCRPEF
+ | LL_PWR_SCR_CBLEWUF
+ | LL_PWR_SCR_CWUF);
+#endif
LL_PWR_WriteReg(EXTSCR,
LL_PWR_EXTSCR_CCRPF
diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_qspi.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_qspi.c
index fc71c19a3e..3696e0ab66 100644
--- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_qspi.c
+++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_qspi.c
@@ -2631,6 +2631,9 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin
cmd->AlternateBytesSize | cmd->AlternateByteMode |
cmd->AddressMode | cmd->InstructionMode |
cmd->Instruction | FunctionalMode));
+
+ /* Clear AR register */
+ CLEAR_REG(hqspi->Instance->AR);
}
}
else
@@ -2658,6 +2661,9 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin
cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
cmd->AlternateByteMode | cmd->AddressMode |
cmd->InstructionMode | cmd->Instruction | FunctionalMode));
+
+ /* Clear AR register */
+ CLEAR_REG(hqspi->Instance->AR);
}
}
}
@@ -2692,6 +2698,9 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin
cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
cmd->AlternateBytesSize | cmd->AlternateByteMode |
cmd->AddressMode | cmd->InstructionMode | FunctionalMode));
+
+ /* Clear AR register */
+ CLEAR_REG(hqspi->Instance->AR);
}
}
else
@@ -2721,6 +2730,9 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin
cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
cmd->AlternateByteMode | cmd->AddressMode |
cmd->InstructionMode | FunctionalMode));
+
+ /* Clear AR register */
+ CLEAR_REG(hqspi->Instance->AR);
}
}
}
diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_spi.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_spi.c
index efcc8af763..cab31ee3da 100644
--- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_spi.c
+++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_spi.c
@@ -44,7 +44,8 @@
(+++) Configure the DMA handle parameters
(+++) Configure the DMA Tx or Rx Stream/Channel
(+++) Associate the initialized hdma_tx(or _rx) handle to the hspi DMA Tx or Rx handle
- (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx
+ or Rx Stream/Channel
(#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
@@ -190,7 +191,8 @@
@note The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16bits),
SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
@note
- (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
+ (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and
+ HAL_SPI_TransmitReceive_DMA()
(#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
(#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
@@ -818,38 +820,35 @@ HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_Ca
* @param Timeout Timeout duration
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
uint32_t tickstart;
- HAL_StatusTypeDef errorcode = HAL_OK;
uint16_t initial_TxXferCount;
/* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
- /* Process Locked */
- __HAL_LOCK(hspi);
-
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
initial_TxXferCount = Size;
if (hspi->State != HAL_SPI_STATE_READY)
{
- errorcode = HAL_BUSY;
- goto error;
+ return HAL_BUSY;
}
if ((pData == NULL) || (Size == 0U))
{
- errorcode = HAL_ERROR;
- goto error;
+ return HAL_ERROR;
}
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
/* Set the transaction information */
hspi->State = HAL_SPI_STATE_BUSY_TX;
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pTxBuffPtr = (uint8_t *)pData;
+ hspi->pTxBuffPtr = (const uint8_t *)pData;
hspi->TxXferSize = Size;
hspi->TxXferCount = Size;
@@ -888,7 +887,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint
{
if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
{
- hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
hspi->pTxBuffPtr += sizeof(uint16_t);
hspi->TxXferCount--;
}
@@ -898,7 +897,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint
/* Wait until TXE flag is set to send data */
if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
{
- hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
hspi->pTxBuffPtr += sizeof(uint16_t);
hspi->TxXferCount--;
}
@@ -907,9 +906,9 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint
/* Timeout management */
if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
{
- errorcode = HAL_TIMEOUT;
hspi->State = HAL_SPI_STATE_READY;
- goto error;
+ __HAL_UNLOCK(hspi);
+ return HAL_TIMEOUT;
}
}
}
@@ -922,13 +921,13 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint
if (hspi->TxXferCount > 1U)
{
/* write on the data register in packing mode */
- hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
hspi->pTxBuffPtr += sizeof(uint16_t);
hspi->TxXferCount -= 2U;
}
else
{
- *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
+ *((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr);
hspi->pTxBuffPtr ++;
hspi->TxXferCount--;
}
@@ -941,13 +940,13 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint
if (hspi->TxXferCount > 1U)
{
/* write on the data register in packing mode */
- hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
hspi->pTxBuffPtr += sizeof(uint16_t);
hspi->TxXferCount -= 2U;
}
else
{
- *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
+ *((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr);
hspi->pTxBuffPtr++;
hspi->TxXferCount--;
}
@@ -957,9 +956,9 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint
/* Timeout management */
if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
{
- errorcode = HAL_TIMEOUT;
hspi->State = HAL_SPI_STATE_READY;
- goto error;
+ __HAL_UNLOCK(hspi);
+ return HAL_TIMEOUT;
}
}
}
@@ -984,19 +983,18 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint
__HAL_SPI_CLEAR_OVRFLAG(hspi);
}
+ hspi->State = HAL_SPI_STATE_READY;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
{
- errorcode = HAL_ERROR;
+ return HAL_ERROR;
}
else
{
- hspi->State = HAL_SPI_STATE_READY;
+ return HAL_OK;
}
-
-error:
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
- return errorcode;
}
/**
@@ -1016,12 +1014,15 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
__IO uint8_t tmpreg8 = 0;
#endif /* USE_SPI_CRC */
uint32_t tickstart;
- HAL_StatusTypeDef errorcode = HAL_OK;
if (hspi->State != HAL_SPI_STATE_READY)
{
- errorcode = HAL_BUSY;
- goto error;
+ return HAL_BUSY;
+ }
+
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
}
if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
@@ -1031,17 +1032,11 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
}
- /* Process Locked */
- __HAL_LOCK(hspi);
-
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
- if ((pData == NULL) || (Size == 0U))
- {
- errorcode = HAL_ERROR;
- goto error;
- }
+ /* Process Locked */
+ __HAL_LOCK(hspi);
/* Set the transaction information */
hspi->State = HAL_SPI_STATE_BUSY_RX;
@@ -1113,9 +1108,9 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
/* Timeout management */
if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
{
- errorcode = HAL_TIMEOUT;
hspi->State = HAL_SPI_STATE_READY;
- goto error;
+ __HAL_UNLOCK(hspi);
+ return HAL_TIMEOUT;
}
}
}
@@ -1137,9 +1132,9 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
/* Timeout management */
if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
{
- errorcode = HAL_TIMEOUT;
hspi->State = HAL_SPI_STATE_READY;
- goto error;
+ __HAL_UNLOCK(hspi);
+ return HAL_TIMEOUT;
}
}
}
@@ -1156,8 +1151,8 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
{
/* the latest data has not been received */
- errorcode = HAL_TIMEOUT;
- goto error;
+ __HAL_UNLOCK(hspi);
+ return HAL_TIMEOUT;
}
/* Receive last data in 16 Bit mode */
@@ -1175,8 +1170,9 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
- errorcode = HAL_TIMEOUT;
- goto error;
+ hspi->State = HAL_SPI_STATE_READY;
+ __HAL_UNLOCK(hspi);
+ return HAL_TIMEOUT;
}
/* Read CRC to Flush DR and RXNE flag */
@@ -1202,8 +1198,9 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
{
/* Error on the CRC reception */
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
- errorcode = HAL_TIMEOUT;
- goto error;
+ hspi->State = HAL_SPI_STATE_READY;
+ __HAL_UNLOCK(hspi);
+ return HAL_TIMEOUT;
}
/* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */
tmpreg8 = *ptmpreg8;
@@ -1229,18 +1226,17 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
}
#endif /* USE_SPI_CRC */
+ hspi->State = HAL_SPI_STATE_READY;
+ /* Unlock the process */
+ __HAL_UNLOCK(hspi);
if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
{
- errorcode = HAL_ERROR;
+ return HAL_ERROR;
}
else
{
- hspi->State = HAL_SPI_STATE_READY;
+ return HAL_OK;
}
-
-error :
- __HAL_UNLOCK(hspi);
- return errorcode;
}
/**
@@ -1253,8 +1249,8 @@ error :
* @param Timeout Timeout duration
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
- uint32_t Timeout)
+HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData,
+ uint16_t Size, uint32_t Timeout)
{
uint16_t initial_TxXferCount;
uint16_t initial_RxXferCount;
@@ -1271,14 +1267,10 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
/* Variable used to alternate Rx and Tx during transfer */
uint32_t txallowed = 1U;
- HAL_StatusTypeDef errorcode = HAL_OK;
/* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
- /* Process Locked */
- __HAL_LOCK(hspi);
-
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
@@ -1293,18 +1285,20 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
#endif /* USE_SPI_CRC */
if (!((tmp_state == HAL_SPI_STATE_READY) || \
- ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
+ ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) &&
+ (tmp_state == HAL_SPI_STATE_BUSY_RX))))
{
- errorcode = HAL_BUSY;
- goto error;
+ return HAL_BUSY;
}
if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
{
- errorcode = HAL_ERROR;
- goto error;
+ return HAL_ERROR;
}
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
if (hspi->State != HAL_SPI_STATE_BUSY_RX)
{
@@ -1316,7 +1310,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
hspi->pRxBuffPtr = (uint8_t *)pRxData;
hspi->RxXferCount = Size;
hspi->RxXferSize = Size;
- hspi->pTxBuffPtr = (uint8_t *)pTxData;
+ hspi->pTxBuffPtr = (const uint8_t *)pTxData;
hspi->TxXferCount = Size;
hspi->TxXferSize = Size;
@@ -1356,7 +1350,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
{
if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
{
- hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
hspi->pTxBuffPtr += sizeof(uint16_t);
hspi->TxXferCount--;
@@ -1379,7 +1373,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
/* Check TXE flag */
if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
{
- hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
hspi->pTxBuffPtr += sizeof(uint16_t);
hspi->TxXferCount--;
/* Next Data is a reception (Rx). Tx not allowed */
@@ -1410,9 +1404,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
}
if (((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY))
{
- errorcode = HAL_TIMEOUT;
hspi->State = HAL_SPI_STATE_READY;
- goto error;
+ __HAL_UNLOCK(hspi);
+ return HAL_TIMEOUT;
}
}
}
@@ -1423,13 +1417,13 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
{
if (hspi->TxXferCount > 1U)
{
- hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
hspi->pTxBuffPtr += sizeof(uint16_t);
hspi->TxXferCount -= 2U;
}
else
{
- *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
+ *(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr);
hspi->pTxBuffPtr++;
hspi->TxXferCount--;
@@ -1454,13 +1448,13 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
{
if (hspi->TxXferCount > 1U)
{
- hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
hspi->pTxBuffPtr += sizeof(uint16_t);
hspi->TxXferCount -= 2U;
}
else
{
- *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
+ *(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr);
hspi->pTxBuffPtr++;
hspi->TxXferCount--;
}
@@ -1506,9 +1500,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
}
if ((((HAL_GetTick() - tickstart) >= Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U))
{
- errorcode = HAL_TIMEOUT;
hspi->State = HAL_SPI_STATE_READY;
- goto error;
+ __HAL_UNLOCK(hspi);
+ return HAL_TIMEOUT;
}
}
}
@@ -1522,8 +1516,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
{
/* Error on the CRC reception */
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
- errorcode = HAL_TIMEOUT;
- goto error;
+ hspi->State = HAL_SPI_STATE_READY;
+ __HAL_UNLOCK(hspi);
+ return HAL_TIMEOUT;
}
/* Read CRC */
if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
@@ -1548,8 +1543,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
{
/* Error on the CRC reception */
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
- errorcode = HAL_TIMEOUT;
- goto error;
+ hspi->State = HAL_SPI_STATE_READY;
+ __HAL_UNLOCK(hspi);
+ return HAL_TIMEOUT;
}
/* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */
tmpreg8 = *ptmpreg8;
@@ -1565,30 +1561,32 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
/* Clear CRC Flag */
__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
-
- errorcode = HAL_ERROR;
+ __HAL_UNLOCK(hspi);
+ return HAL_ERROR;
}
#endif /* USE_SPI_CRC */
/* Check the end of the transaction */
if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
{
- errorcode = HAL_ERROR;
hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
+ __HAL_UNLOCK(hspi);
+ return HAL_ERROR;
}
+
+ hspi->State = HAL_SPI_STATE_READY;
+ /* Unlock the process */
+ __HAL_UNLOCK(hspi);
+
if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
{
- errorcode = HAL_ERROR;
+ return HAL_ERROR;
}
else
{
- hspi->State = HAL_SPI_STATE_READY;
+ return HAL_OK;
}
-
-error :
- __HAL_UNLOCK(hspi);
- return errorcode;
}
/**
@@ -1599,9 +1597,8 @@ error :
* @param Size amount of data to be sent
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
+HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size)
{
- HAL_StatusTypeDef errorcode = HAL_OK;
/* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
@@ -1609,14 +1606,12 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u
if ((pData == NULL) || (Size == 0U))
{
- errorcode = HAL_ERROR;
- goto error;
+ return HAL_ERROR;
}
if (hspi->State != HAL_SPI_STATE_READY)
{
- errorcode = HAL_BUSY;
- goto error;
+ return HAL_BUSY;
}
/* Process Locked */
@@ -1625,7 +1620,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u
/* Set the transaction information */
hspi->State = HAL_SPI_STATE_BUSY_TX;
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pTxBuffPtr = (uint8_t *)pData;
+ hspi->pTxBuffPtr = (const uint8_t *)pData;
hspi->TxXferSize = Size;
hspi->TxXferCount = Size;
@@ -1673,8 +1668,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u
/* Enable TXE and ERR interrupt */
__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
-error :
- return errorcode;
+ return HAL_OK;
}
/**
@@ -1687,13 +1681,15 @@ error :
*/
HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
{
- HAL_StatusTypeDef errorcode = HAL_OK;
-
if (hspi->State != HAL_SPI_STATE_READY)
{
- errorcode = HAL_BUSY;
- goto error;
+ return HAL_BUSY;
+ }
+
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
}
if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
@@ -1704,12 +1700,6 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui
}
- if ((pData == NULL) || (Size == 0U))
- {
- errorcode = HAL_ERROR;
- goto error;
- }
-
/* Process Locked */
__HAL_LOCK(hspi);
@@ -1781,8 +1771,7 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui
/* Enable RXNE and ERR interrupt */
__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
-error :
- return errorcode;
+ return HAL_OK;
}
/**
@@ -1794,11 +1783,11 @@ error :
* @param Size amount of data to be sent and received
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData,
+ uint16_t Size)
{
uint32_t tmp_mode;
HAL_SPI_StateTypeDef tmp_state;
- HAL_StatusTypeDef errorcode = HAL_OK;
/* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
@@ -1808,16 +1797,15 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p
tmp_mode = hspi->Init.Mode;
if (!((tmp_state == HAL_SPI_STATE_READY) || \
- ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
+ ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) &&
+ (tmp_state == HAL_SPI_STATE_BUSY_RX))))
{
- errorcode = HAL_BUSY;
- goto error;
+ return HAL_BUSY;
}
if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
{
- errorcode = HAL_ERROR;
- goto error;
+ return HAL_ERROR;
}
/* Process locked */
@@ -1831,7 +1819,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p
/* Set the transaction information */
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pTxBuffPtr = (uint8_t *)pTxData;
+ hspi->pTxBuffPtr = (const uint8_t *)pTxData;
hspi->TxXferSize = Size;
hspi->TxXferCount = Size;
hspi->pRxBuffPtr = (uint8_t *)pRxData;
@@ -1892,8 +1880,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p
/* Enable TXE, RXNE and ERR interrupt */
__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
-error :
- return errorcode;
+ return HAL_OK;
}
/**
@@ -1904,9 +1891,8 @@ error :
* @param Size amount of data to be sent
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
+HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size)
{
- HAL_StatusTypeDef errorcode = HAL_OK;
/* Check tx dma handle */
assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
@@ -1914,25 +1900,23 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData,
/* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
- /* Process Locked */
- __HAL_LOCK(hspi);
-
if (hspi->State != HAL_SPI_STATE_READY)
{
- errorcode = HAL_BUSY;
- goto error;
+ return HAL_BUSY;
}
if ((pData == NULL) || (Size == 0U))
{
- errorcode = HAL_ERROR;
- goto error;
+ return HAL_ERROR;
}
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
/* Set the transaction information */
hspi->State = HAL_SPI_STATE_BUSY_TX;
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pTxBuffPtr = (uint8_t *)pData;
+ hspi->pTxBuffPtr = (const uint8_t *)pData;
hspi->TxXferSize = Size;
hspi->TxXferCount = Size;
@@ -1994,9 +1978,9 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData,
{
/* Update SPI error code */
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
- errorcode = HAL_ERROR;
-
- goto error;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ return HAL_ERROR;
}
/* Check if the SPI is already enabled */
@@ -2006,16 +1990,16 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData,
__HAL_SPI_ENABLE(hspi);
}
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
/* Enable the SPI Error Interrupt Bit */
__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
/* Enable Tx DMA Request */
SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
-error :
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
- return errorcode;
+ return HAL_OK;
}
/**
@@ -2030,15 +2014,17 @@ error :
*/
HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
{
- HAL_StatusTypeDef errorcode = HAL_OK;
-
/* Check rx dma handle */
assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
if (hspi->State != HAL_SPI_STATE_READY)
{
- errorcode = HAL_BUSY;
- goto error;
+ return HAL_BUSY;
+ }
+
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
}
if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
@@ -2055,12 +2041,6 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u
/* Process Locked */
__HAL_LOCK(hspi);
- if ((pData == NULL) || (Size == 0U))
- {
- errorcode = HAL_ERROR;
- goto error;
- }
-
/* Set the transaction information */
hspi->State = HAL_SPI_STATE_BUSY_RX;
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
@@ -2138,9 +2118,9 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u
{
/* Update SPI error code */
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
- errorcode = HAL_ERROR;
-
- goto error;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ return HAL_ERROR;
}
/* Check if the SPI is already enabled */
@@ -2150,16 +2130,16 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u
__HAL_SPI_ENABLE(hspi);
}
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
/* Enable the SPI Error Interrupt Bit */
__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
/* Enable Rx DMA Request */
SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
-error:
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
- return errorcode;
+ return HAL_OK;
}
/**
@@ -2172,12 +2152,11 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u
* @param Size amount of data to be sent
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData,
uint16_t Size)
{
uint32_t tmp_mode;
HAL_SPI_StateTypeDef tmp_state;
- HAL_StatusTypeDef errorcode = HAL_OK;
/* Check rx & tx dma handles */
assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
@@ -2186,26 +2165,25 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *
/* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
- /* Process locked */
- __HAL_LOCK(hspi);
-
/* Init temporary variables */
tmp_state = hspi->State;
tmp_mode = hspi->Init.Mode;
if (!((tmp_state == HAL_SPI_STATE_READY) ||
- ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
+ ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) &&
+ (tmp_state == HAL_SPI_STATE_BUSY_RX))))
{
- errorcode = HAL_BUSY;
- goto error;
+ return HAL_BUSY;
}
if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
{
- errorcode = HAL_ERROR;
- goto error;
+ return HAL_ERROR;
}
+ /* Process locked */
+ __HAL_LOCK(hspi);
+
/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
if (hspi->State != HAL_SPI_STATE_BUSY_RX)
{
@@ -2214,7 +2192,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *
/* Set the transaction information */
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pTxBuffPtr = (uint8_t *)pTxData;
+ hspi->pTxBuffPtr = (const uint8_t *)pTxData;
hspi->TxXferSize = Size;
hspi->TxXferCount = Size;
hspi->pRxBuffPtr = (uint8_t *)pRxData;
@@ -2305,9 +2283,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *
{
/* Update SPI error code */
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
- errorcode = HAL_ERROR;
-
- goto error;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ return HAL_ERROR;
}
/* Enable Rx DMA Request */
@@ -2326,9 +2304,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *
{
/* Update SPI error code */
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
- errorcode = HAL_ERROR;
-
- goto error;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ return HAL_ERROR;
}
/* Check if the SPI is already enabled */
@@ -2337,16 +2315,17 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *
/* Enable SPI peripheral */
__HAL_SPI_ENABLE(hspi);
}
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
/* Enable the SPI Error Interrupt Bit */
__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
/* Enable Tx DMA Request */
SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
-error :
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
- return errorcode;
+ return HAL_OK;
}
/**
@@ -2439,7 +2418,8 @@ HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
__HAL_SPI_DISABLE(hspi);
/* Empty the FRLVL fifo */
- if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT,
+ HAL_GetTick()) != HAL_OK)
{
hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
}
@@ -2472,7 +2452,8 @@ HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
}
/* Empty the FRLVL fifo */
- if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT,
+ HAL_GetTick()) != HAL_OK)
{
hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
}
@@ -2727,9 +2708,11 @@ HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
{
HAL_StatusTypeDef errorcode = HAL_OK;
/* The Lock is not implemented on this API to allow the user application
- to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
+ to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or
+ HAL_SPI_TxRxCpltCallback():
when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
- and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
+ and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or
+ HAL_SPI_TxRxCpltCallback()
*/
/* Abort the SPI DMA tx Stream/Channel */
@@ -3019,7 +3002,7 @@ __weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi)
* the configuration information for SPI module.
* @retval SPI state
*/
-HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
+HAL_SPI_StateTypeDef HAL_SPI_GetState(const SPI_HandleTypeDef *hspi)
{
/* Return SPI handle state */
return hspi->State;
@@ -3031,7 +3014,7 @@ HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
* the configuration information for SPI module.
* @retval SPI error code in bitmap format
*/
-uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
+uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi)
{
/* Return SPI ErrorCode */
return hspi->ErrorCode;
@@ -3058,7 +3041,7 @@ uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
*/
static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
uint32_t tickstart;
/* Init tickstart for timeout management*/
@@ -3115,7 +3098,7 @@ static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
*/
static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
uint32_t tickstart;
#if (USE_SPI_CRC != 0U)
__IO uint32_t tmpreg = 0U;
@@ -3232,7 +3215,7 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
*/
static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
uint32_t tickstart;
#if (USE_SPI_CRC != 0U)
__IO uint32_t tmpreg = 0U;
@@ -3270,7 +3253,8 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
}
else
{
- if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT,
+ tickstart) != HAL_OK)
{
/* Error on the CRC reception */
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
@@ -3332,7 +3316,7 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
*/
static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
/* Call user Tx half complete callback */
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
@@ -3350,7 +3334,7 @@ static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
*/
static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
/* Call user Rx half complete callback */
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
@@ -3368,7 +3352,7 @@ static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
*/
static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
/* Call user TxRx half complete callback */
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
@@ -3386,7 +3370,7 @@ static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
*/
static void SPI_DMAError(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
/* Stop the disable DMA transfer on SPI side */
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
@@ -3409,7 +3393,7 @@ static void SPI_DMAError(DMA_HandleTypeDef *hdma)
*/
static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
hspi->RxXferCount = 0U;
hspi->TxXferCount = 0U;
@@ -3431,7 +3415,7 @@ static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
*/
static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
hspi->hdmatx->XferAbortCallback = NULL;
@@ -3447,7 +3431,8 @@ static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
__HAL_SPI_DISABLE(hspi);
/* Empty the FRLVL fifo */
- if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT,
+ HAL_GetTick()) != HAL_OK)
{
hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
}
@@ -3497,7 +3482,7 @@ static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
*/
static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
/* Disable SPI Peripheral */
__HAL_SPI_DISABLE(hspi);
@@ -3514,7 +3499,8 @@ static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
}
/* Empty the FRLVL fifo */
- if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT,
+ HAL_GetTick()) != HAL_OK)
{
hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
}
@@ -3650,14 +3636,14 @@ static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
/* Transmit data in packing Bit mode */
if (hspi->TxXferCount >= 2U)
{
- hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
hspi->pTxBuffPtr += sizeof(uint16_t);
hspi->TxXferCount -= 2U;
}
/* Transmit data in 8 Bit mode */
else
{
- *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
+ *(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr);
hspi->pTxBuffPtr++;
hspi->TxXferCount--;
}
@@ -3751,7 +3737,7 @@ static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
{
/* Transmit data in 16 Bit mode */
- hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
hspi->pTxBuffPtr += sizeof(uint16_t);
hspi->TxXferCount--;
@@ -3904,7 +3890,7 @@ static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
*/
static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
{
- *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
+ *(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr);
hspi->pTxBuffPtr++;
hspi->TxXferCount--;
@@ -3930,7 +3916,7 @@ static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
{
/* Transmit data in 16 Bit mode */
- hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
hspi->pTxBuffPtr += sizeof(uint16_t);
hspi->TxXferCount--;
@@ -4032,7 +4018,7 @@ static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi,
__IO uint32_t count;
uint32_t tmp_timeout;
uint32_t tmp_tickstart;
- __IO uint8_t *ptmpreg8;
+ __IO const uint8_t *ptmpreg8;
__IO uint8_t tmpreg8 = 0;
/* Adjust Timeout value in case of end of transfer */
@@ -4387,7 +4373,8 @@ static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi)
}
/* Empty the FRLVL fifo */
- if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT,
+ HAL_GetTick()) != HAL_OK)
{
hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
}
@@ -4430,7 +4417,8 @@ static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi)
__HAL_SPI_DISABLE(hspi);
/* Empty the FRLVL fifo */
- if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT,
+ HAL_GetTick()) != HAL_OK)
{
hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
}
@@ -4459,7 +4447,8 @@ static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi)
}
/* Empty the FRLVL fifo */
- if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT,
+ HAL_GetTick()) != HAL_OK)
{
hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
}
diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_uart.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_uart.c
index 97c320a227..971d8df592 100644
--- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_uart.c
+++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_uart.c
@@ -3907,7 +3907,6 @@ static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
{
UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
huart->RxXferCount = 0U;
- huart->TxXferCount = 0U;
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_adc.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_adc.c
index b891d501b6..99eb0f14cf 100644
--- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_adc.c
+++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_adc.c
@@ -562,46 +562,68 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
{
/* ========== Reset ADC registers ========== */
/* Reset register IER */
+#if !defined(ADC_SUPPORT_2_5_MSPS)
CLEAR_BIT(ADCx->IER,
(LL_ADC_IT_ADRDY
| LL_ADC_IT_EOC
| LL_ADC_IT_EOS
| LL_ADC_IT_OVR
| LL_ADC_IT_EOSMP
-#if !defined(ADC_SUPPORT_2_5_MSPS)
| LL_ADC_IT_JEOC
| LL_ADC_IT_JEOS
| LL_ADC_IT_JQOVF
-#endif /* !ADC_SUPPORT_2_5_MSPS */
| LL_ADC_IT_AWD1
| LL_ADC_IT_AWD2
| LL_ADC_IT_AWD3
+ )
+ );
+#endif /* !ADC_SUPPORT_2_5_MSPS */
#if defined(ADC_SUPPORT_2_5_MSPS)
+ CLEAR_BIT(ADCx->IER,
+ (LL_ADC_IT_ADRDY
+ | LL_ADC_IT_EOC
+ | LL_ADC_IT_EOS
+ | LL_ADC_IT_OVR
+ | LL_ADC_IT_EOSMP
| LL_ADC_IT_CCRDY
-#endif /* ADC_SUPPORT_2_5_MSPS */
+ | LL_ADC_IT_AWD1
+ | LL_ADC_IT_AWD2
+ | LL_ADC_IT_AWD3
)
);
+#endif /* ADC_SUPPORT_2_5_MSPS */
/* Reset register ISR */
+#if !defined(ADC_SUPPORT_2_5_MSPS)
SET_BIT(ADCx->ISR,
(LL_ADC_FLAG_ADRDY
| LL_ADC_FLAG_EOC
| LL_ADC_FLAG_EOS
| LL_ADC_FLAG_OVR
| LL_ADC_FLAG_EOSMP
-#if !defined(ADC_SUPPORT_2_5_MSPS)
| LL_ADC_FLAG_JEOC
| LL_ADC_FLAG_JEOS
| LL_ADC_FLAG_JQOVF
-#endif /* !ADC_SUPPORT_2_5_MSPS */
| LL_ADC_FLAG_AWD1
| LL_ADC_FLAG_AWD2
| LL_ADC_FLAG_AWD3
+ )
+ );
+#endif /* !ADC_SUPPORT_2_5_MSPS */
#if defined(ADC_SUPPORT_2_5_MSPS)
+ SET_BIT(ADCx->ISR,
+ (LL_ADC_FLAG_ADRDY
+ | LL_ADC_FLAG_EOC
+ | LL_ADC_FLAG_EOS
+ | LL_ADC_FLAG_OVR
+ | LL_ADC_FLAG_EOSMP
| LL_ADC_FLAG_CCRDY
-#endif /* ADC_SUPPORT_2_5_MSPS */
+ | LL_ADC_FLAG_AWD1
+ | LL_ADC_FLAG_AWD2
+ | LL_ADC_FLAG_AWD3
)
);
+#endif /* ADC_SUPPORT_2_5_MSPS */
#if defined(ADC_SUPPORT_2_5_MSPS)
/* Reset register CR */
diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
index dbf02092dc..9d8d7115db 100644
--- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
@@ -106,21 +106,43 @@ ErrorStatus LL_PWR_DeInit(void)
LL_PWR_WriteReg(C2CR3, PWR_C2CR3_RESET_VALUE);
/* Clear all flags */
+ #if defined(PWR_CR3_E802A) && defined(PWR_CR5_SMPSEN)
+LL_PWR_WriteReg(SCR,
+ LL_PWR_SCR_CC2HF
+ | LL_PWR_SCR_CBLEAF
+ | LL_PWR_SCR_CCRPEF
+ | LL_PWR_SCR_C802AF
+ | LL_PWR_SCR_C802WUF
+ | LL_PWR_SCR_CBLEWUF
+ | LL_PWR_SCR_CBORHF
+ | LL_PWR_SCR_CSMPSFBF
+ | LL_PWR_SCR_CWUF);
+#elif defined(PWR_CR3_E802A)
LL_PWR_WriteReg(SCR,
- LL_PWR_SCR_CC2HF
- | LL_PWR_SCR_CBLEAF
- | LL_PWR_SCR_CCRPEF
-#if defined(PWR_CR3_E802A)
- | LL_PWR_SCR_C802AF
- | LL_PWR_SCR_C802WUF
-#endif /* PWR_CR3_E802A */
- | LL_PWR_SCR_CBLEWUF
-#if defined(PWR_CR5_SMPSEN)
- | LL_PWR_SCR_CBORHF
- | LL_PWR_SCR_CSMPSFBF
-#endif /* PWR_CR5_SMPSEN */
- | LL_PWR_SCR_CWUF
- );
+ LL_PWR_SCR_CC2HF
+ | LL_PWR_SCR_CBLEAF
+ | LL_PWR_SCR_CCRPEF
+ | LL_PWR_SCR_C802AF
+ | LL_PWR_SCR_C802WUF
+ | LL_PWR_SCR_CBLEWUF
+ | LL_PWR_SCR_CWUF);
+#elif defined(PWR_CR5_SMPSEN)
+ LL_PWR_WriteReg(SCR,
+ LL_PWR_SCR_CC2HF
+ | LL_PWR_SCR_CBLEAF
+ | LL_PWR_SCR_CCRPEF
+ | LL_PWR_SCR_CBLEWUF
+ | LL_PWR_SCR_CBORHF
+ | LL_PWR_SCR_CSMPSFBF
+ | LL_PWR_SCR_CWUF);
+#else
+ LL_PWR_WriteReg(SCR,
+ LL_PWR_SCR_CC2HF
+ | LL_PWR_SCR_CBLEAF
+ | LL_PWR_SCR_CCRPEF
+ | LL_PWR_SCR_CBLEWUF
+ | LL_PWR_SCR_CWUF);
+#endif
LL_PWR_WriteReg(EXTSCR,
LL_PWR_EXTSCR_CCRPF
diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_spi.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_spi.c
index a275d6c739..a35c29fffa 100644
--- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_spi.c
+++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_spi.c
@@ -129,7 +129,7 @@
* - SUCCESS: SPI registers are de-initialized
* - ERROR: SPI registers are not de-initialized
*/
-ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
+ErrorStatus LL_SPI_DeInit(const SPI_TypeDef *SPIx)
{
ErrorStatus status = ERROR;
@@ -166,8 +166,9 @@ ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
/**
* @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
- * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
- * SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
+ * @note As some bits in SPI configuration registers can only be written when the
+ * SPI is disabled (SPI_CR1_SPE bit = 0), SPI peripheral should be in disabled state prior
+ * calling this function. Otherwise, ERROR result will be returned.
* @param SPIx SPI Instance
* @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
* @retval An ErrorStatus enumeration value. (Return always SUCCESS)
diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_usb.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_usb.c
index f3a23b9f39..27662c249a 100644
--- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_usb.c
+++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_usb.c
@@ -319,6 +319,10 @@ HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep)
PCD_CLEAR_RX_DTOG(USBx, ep->num);
PCD_CLEAR_TX_DTOG(USBx, ep->num);
+ /* Set endpoint RX count */
+ PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, ep->maxpacket);
+
+ /* Set endpoint RX to valid state */
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
}
@@ -423,7 +427,7 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep)
/* IN endpoint */
if (ep->is_in == 1U)
{
- /*Multi packet transfer*/
+ /* Multi packet transfer */
if (ep->xfer_len > ep->maxpacket)
{
len = ep->maxpacket;
@@ -525,9 +529,9 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep)
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
}
}
- else /* manage isochronous double buffer IN mode */
+ else /* Manage isochronous double buffer IN mode */
{
- /* each Time to write in PMA xfer_len_db will */
+ /* Each Time to write in PMA xfer_len_db will */
ep->xfer_len_db -= len;
/* Fill the data buffer */
@@ -559,19 +563,25 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep)
{
if (ep->doublebuffer == 0U)
{
+ if ((ep->xfer_len == 0U) && (ep->type == EP_TYPE_CTRL))
+ {
+ /* This is a status out stage set the OUT_STATUS */
+ PCD_SET_OUT_STATUS(USBx, ep->num);
+ }
+ else
+ {
+ PCD_CLEAR_OUT_STATUS(USBx, ep->num);
+ }
+
/* Multi packet transfer */
if (ep->xfer_len > ep->maxpacket)
{
- len = ep->maxpacket;
- ep->xfer_len -= len;
+ ep->xfer_len -= ep->maxpacket;
}
else
{
- len = ep->xfer_len;
ep->xfer_len = 0U;
}
- /* configure and validate Rx endpoint */
- PCD_SET_EP_RX_CNT(USBx, ep->num, len);
}
#if (USE_USB_DOUBLE_BUFFER == 1U)
else
@@ -580,15 +590,13 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep)
/* Set the Double buffer counter */
if (ep->type == EP_TYPE_BULK)
{
- PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, ep->maxpacket);
-
/* Coming from ISR */
if (ep->xfer_count != 0U)
{
- /* update last value to check if there is blocking state */
+ /* Update last value to check if there is blocking state */
wEPVal = PCD_GET_ENDPOINT(USBx, ep->num);
- /*Blocking State */
+ /* Blocking State */
if ((((wEPVal & USB_EP_DTOG_RX) != 0U) && ((wEPVal & USB_EP_DTOG_TX) != 0U)) ||
(((wEPVal & USB_EP_DTOG_RX) == 0U) && ((wEPVal & USB_EP_DTOG_TX) == 0U)))
{
@@ -599,18 +607,8 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep)
/* iso out double */
else if (ep->type == EP_TYPE_ISOC)
{
- /* Multi packet transfer */
- if (ep->xfer_len > ep->maxpacket)
- {
- len = ep->maxpacket;
- ep->xfer_len -= len;
- }
- else
- {
- len = ep->xfer_len;
- ep->xfer_len = 0U;
- }
- PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, len);
+ /* Only single packet transfer supported in FS */
+ ep->xfer_len = 0U;
}
else
{
@@ -654,26 +652,23 @@ HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep)
*/
HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep)
{
- if (ep->doublebuffer == 0U)
+ if (ep->is_in != 0U)
{
- if (ep->is_in != 0U)
- {
- PCD_CLEAR_TX_DTOG(USBx, ep->num);
+ PCD_CLEAR_TX_DTOG(USBx, ep->num);
- if (ep->type != EP_TYPE_ISOC)
- {
- /* Configure NAK status for the Endpoint */
- PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK);
- }
- }
- else
+ if (ep->type != EP_TYPE_ISOC)
{
- PCD_CLEAR_RX_DTOG(USBx, ep->num);
-
- /* Configure VALID status for the Endpoint */
- PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
+ /* Configure NAK status for the Endpoint */
+ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK);
}
}
+ else
+ {
+ PCD_CLEAR_RX_DTOG(USBx, ep->num);
+
+ /* Configure VALID status for the Endpoint */
+ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
+ }
return HAL_OK;
}
diff --git a/system/Drivers/STM32YYxx_HAL_Driver_version.md b/system/Drivers/STM32YYxx_HAL_Driver_version.md
index 0f8b0e5a07..cee30061e2 100644
--- a/system/Drivers/STM32YYxx_HAL_Driver_version.md
+++ b/system/Drivers/STM32YYxx_HAL_Driver_version.md
@@ -18,7 +18,7 @@
* STM32MP1: 1.6.0
* STM32U0: 1.2.0
* STM32U5: 1.6.0
- * STM32WB: 1.14.3
+ * STM32WB: 1.14.4
* STM32WBA: 1.5.0
* STM32WL: 1.3.0