From 4daeccad49648f003f98a26c5783e3a8f6e2fa25 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Mon, 9 Dec 2024 11:47:47 +0100 Subject: [PATCH] fix(h5): review SPI input clock Also prevent to use HSE as it is not operational as oscillator. See Errata sheet. Fixes #2598 Signed-off-by: Frederic Pillon --- .../STM32H5xx/H503CB(T-U)/generic_clock.c | 2 +- variants/STM32H5xx/H503RBT/generic_clock.c | 8 ++- .../H503RBT/variant_NUCLEO_H503RB.cpp | 51 +++++++++++-------- 3 files changed, 37 insertions(+), 24 deletions(-) diff --git a/variants/STM32H5xx/H503CB(T-U)/generic_clock.c b/variants/STM32H5xx/H503CB(T-U)/generic_clock.c index 9bb79e4f8f..9bc92b205a 100644 --- a/variants/STM32H5xx/H503CB(T-U)/generic_clock.c +++ b/variants/STM32H5xx/H503CB(T-U)/generic_clock.c @@ -47,7 +47,7 @@ WEAK void SystemClock_Config(void) RCC_OscInitStruct.PLL.PLLM = 1; RCC_OscInitStruct.PLL.PLLN = 125; RCC_OscInitStruct.PLL.PLLP = 2; - RCC_OscInitStruct.PLL.PLLQ = 2; + RCC_OscInitStruct.PLL.PLLQ = 10; RCC_OscInitStruct.PLL.PLLR = 2; RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_2; RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1_VCORANGE_WIDE; diff --git a/variants/STM32H5xx/H503RBT/generic_clock.c b/variants/STM32H5xx/H503RBT/generic_clock.c index 784645b735..a8e3993712 100644 --- a/variants/STM32H5xx/H503RBT/generic_clock.c +++ b/variants/STM32H5xx/H503RBT/generic_clock.c @@ -43,7 +43,7 @@ WEAK void SystemClock_Config(void) RCC_OscInitStruct.PLL.PLLM = 1; RCC_OscInitStruct.PLL.PLLN = 125; RCC_OscInitStruct.PLL.PLLP = 2; - RCC_OscInitStruct.PLL.PLLQ = 2; + RCC_OscInitStruct.PLL.PLLQ = 10; RCC_OscInitStruct.PLL.PLLR = 2; RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_2; RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1_VCORANGE_WIDE; @@ -64,6 +64,10 @@ WEAK void SystemClock_Config(void) Error_Handler(); } + /** Configure the programming delay + */ + __HAL_FLASH_SET_PROGRAM_DELAY(FLASH_PROGRAMMING_DELAY_2); + /* Initializes the peripherals clock */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_USB; @@ -72,7 +76,7 @@ WEAK void SystemClock_Config(void) PeriphClkInitStruct.PLL2.PLL2N = 125; PeriphClkInitStruct.PLL2.PLL2P = 2; PeriphClkInitStruct.PLL2.PLL2Q = 15; - PeriphClkInitStruct.PLL2.PLL2R = 4; + PeriphClkInitStruct.PLL2.PLL2R = 10; PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2_VCIRANGE_2; PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2_VCORANGE_WIDE; PeriphClkInitStruct.PLL2.PLL2FRACN = 0; diff --git a/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.cpp b/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.cpp index c4a3874d8a..361662cf71 100644 --- a/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.cpp +++ b/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.cpp @@ -114,20 +114,25 @@ WEAK void SystemClock_Config(void) while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} + /** Configure LSE Drive Capability + * Warning : Only applied when the LSE is disabled. + */ + HAL_PWR_EnableBkUpAccess(); + __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW); + /* Initializes the RCC Oscillators according to the specified parameters in the RCC_OscInitTypeDef structure */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSE - | RCC_OSCILLATORTYPE_LSE; - RCC_OscInitStruct.HSEState = RCC_HSE_ON; + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_CSI; RCC_OscInitStruct.LSEState = RCC_LSE_ON; - RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; + RCC_OscInitStruct.CSIState = RCC_CSI_ON; + RCC_OscInitStruct.CSICalibrationValue = RCC_CSICALIBRATION_DEFAULT; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLL1_SOURCE_HSE; - RCC_OscInitStruct.PLL.PLLM = 12; - RCC_OscInitStruct.PLL.PLLN = 250; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLL1_SOURCE_CSI; + RCC_OscInitStruct.PLL.PLLM = 1; + RCC_OscInitStruct.PLL.PLLN = 125; RCC_OscInitStruct.PLL.PLLP = 2; - RCC_OscInitStruct.PLL.PLLQ = 2; + RCC_OscInitStruct.PLL.PLLQ = 10; RCC_OscInitStruct.PLL.PLLR = 2; - RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_1; + RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_2; RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1_VCORANGE_WIDE; RCC_OscInitStruct.PLL.PLLFRACN = 0; if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { @@ -148,23 +153,27 @@ WEAK void SystemClock_Config(void) Error_Handler(); } + /** Configure the programming delay + */ + __HAL_FLASH_SET_PROGRAM_DELAY(FLASH_PROGRAMMING_DELAY_2); + /* Initializes the peripherals clock */ - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_LPUART1 - | RCC_PERIPHCLK_USB; - PeriphClkInitStruct.PLL2.PLL2Source = RCC_PLL2_SOURCE_HSE; - PeriphClkInitStruct.PLL2.PLL2M = 2; - PeriphClkInitStruct.PLL2.PLL2N = 31; - PeriphClkInitStruct.PLL2.PLL2P = 2; - PeriphClkInitStruct.PLL2.PLL2Q = 12; + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB | RCC_PERIPHCLK_ADCDAC + | RCC_PERIPHCLK_LPUART1; + PeriphClkInitStruct.PLL2.PLL2Source = RCC_PLL2_SOURCE_CSI; + PeriphClkInitStruct.PLL2.PLL2M = 1; + PeriphClkInitStruct.PLL2.PLL2N = 36; + PeriphClkInitStruct.PLL2.PLL2P = 3; + PeriphClkInitStruct.PLL2.PLL2Q = 4; PeriphClkInitStruct.PLL2.PLL2R = 3; - PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2_VCIRANGE_3; + PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2_VCIRANGE_2; PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2_VCORANGE_WIDE; - PeriphClkInitStruct.PLL2.PLL2FRACN = 2048; - PeriphClkInitStruct.PLL2.PLL2ClockOut = RCC_PLL2_DIVQ | RCC_PLL2_DIVR; + PeriphClkInitStruct.PLL2.PLL2FRACN = 0; + PeriphClkInitStruct.PLL2.PLL2ClockOut = RCC_PLL2_DIVP | RCC_PLL2_DIVQ + | RCC_PLL2_DIVR; PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PLL2Q; PeriphClkInitStruct.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_PLL2R; - PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; - + PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL2Q; if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { Error_Handler(); }