-
For complete documentation on STM32WLxx, visit: www.st.com/stm32wl
-
This release note uses up to date web standards and, for this reason, should not be opened with Internet Explorer but preferably with popular browsers such as Google Chrome, Mozilla Firefox, Opera or Microsoft Edge.
+
For complete documentation on STM32WLxx, visit: www.st.com/stm32wl
+
This release note uses up to date web standards and, for this
+reason, should not be opened with Internet Explorer but preferably with
+popular browsers such as Google Chrome, Mozilla Firefox, Opera or
+Microsoft Edge.
diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c b/system/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c
index bb438f4d70..0c2dbb42bf 100644
--- a/system/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c
+++ b/system/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c
@@ -57,7 +57,7 @@
*/
#define __STM32WLxx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define __STM32WLxx_HAL_VERSION_SUB1 (0x03U) /*!< [23:16] sub1 version */
-#define __STM32WLxx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
+#define __STM32WLxx_HAL_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */
#define __STM32WLxx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32WLxx_HAL_VERSION ((__STM32WLxx_HAL_VERSION_MAIN << 24U)\
|(__STM32WLxx_HAL_VERSION_SUB1 << 16U)\
@@ -402,7 +402,8 @@ HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq)
/**
* @brief Return tick frequency.
- * @retval tick period in Hz
+ * @retval Tick frequency.
+ * Value of @ref HAL_TickFreqTypeDef.
*/
HAL_TickFreqTypeDef HAL_GetTickFreq(void)
{
diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.c b/system/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.c
index 29ebea1056..82d60e1438 100644
--- a/system/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.c
+++ b/system/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.c
@@ -671,6 +671,10 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc)
| (hadc->ADCGroupRegularSequencerRanks)
);
}
+ else
+ {
+ /* Nothing to do */
+ }
/* Check back that ADC registers have effectively been configured to */
/* ensure of no potential problem of ADC core peripheral clocking. */
@@ -790,25 +794,27 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc)
ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL | ADC_CFGR1_ALIGN | ADC_CFGR1_RES |
ADC_CFGR1_SCANDIR | ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN);
- /* Reset register CFGR2 */
- /* Note: Update of ADC clock mode is conditioned to ADC state disabled: */
- /* already done above. */
- hadc->Instance->CFGR2 &= ~ADC_CFGR2_CKMODE;
-
/* Reset register SMPR */
hadc->Instance->SMPR &= ~ADC_SMPR_SMP1;
- /* Reset registers AWDxTR */
- hadc->Instance->AWD1TR &= ~(ADC_AWD1TR_HT1 | ADC_AWD1TR_LT1);
- hadc->Instance->AWD2TR &= ~(ADC_AWD2TR_HT2 | ADC_AWD2TR_LT2);
- hadc->Instance->AWD3TR &= ~(ADC_AWD3TR_HT3 | ADC_AWD3TR_LT3);
-
/* Reset register CHSELR */
hadc->Instance->CHSELR &= ~(ADC_CHSELR_SQ_ALL);
/* Reset register DR */
/* bits in access mode read only, no direct reset applicable */
+ /* Reset registers AWDxTR */
+ hadc->Instance->AWD1TR &= ~(ADC_AWD1TR_HT1 | ADC_AWD1TR_LT1);
+ hadc->Instance->AWD2TR &= ~(ADC_AWD2TR_HT2 | ADC_AWD2TR_LT2);
+ hadc->Instance->AWD3TR &= ~(ADC_AWD3TR_HT3 | ADC_AWD3TR_LT3);
+
+ /* Reset register CFGR2 */
+ /* Note: CFGR2 reset done at the end of de-initialization due to */
+ /* clock source reset */
+ /* Note: Update of ADC clock mode is conditioned to ADC state disabled: */
+ /* already done above. */
+ hadc->Instance->CFGR2 &= ~ADC_CFGR2_CKMODE;
+
/* Reset register CCR */
ADC_COMMON->CCR &= ~(ADC_CCR_VBATEN | ADC_CCR_TSEN | ADC_CCR_VREFEN | ADC_CCR_PRESC);
diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c b/system/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c
index 05673da75a..1a22076088 100644
--- a/system/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c
+++ b/system/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c
@@ -500,6 +500,37 @@ void HAL_MPU_Disable(void)
MPU->CTRL = 0;
}
+/**
+ * @brief Enable the MPU Region.
+ * @retval None
+ */
+void HAL_MPU_EnableRegion(uint32_t RegionNumber)
+{
+ /* Check the parameters */
+ assert_param(IS_MPU_REGION_NUMBER(RegionNumber));
+
+ /* Set the Region number */
+ MPU->RNR = RegionNumber;
+
+ /* Enable the Region */
+ SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
+}
+
+/**
+ * @brief Disable the MPU Region.
+ * @retval None
+ */
+void HAL_MPU_DisableRegion(uint32_t RegionNumber)
+{
+ /* Check the parameters */
+ assert_param(IS_MPU_REGION_NUMBER(RegionNumber));
+
+ /* Set the Region number */
+ MPU->RNR = RegionNumber;
+
+ /* Disable the Region */
+ CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
+}
/**
* @brief Initialize and configure the Region and the memory to be protected.
@@ -512,38 +543,32 @@ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
/* Check the parameters */
assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
+ assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
+ assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
+ assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
+ assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
+ assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
+ assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
+ assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
+ assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
/* Set the Region number */
MPU->RNR = MPU_Init->Number;
- if ((MPU_Init->Enable) != 0U)
- {
- /* Check the parameters */
- assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
- assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
- assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
- assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
- assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
- assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
- assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
- assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
-
- MPU->RBAR = MPU_Init->BaseAddress;
- MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
- ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
- ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
- ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
- ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
- ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
- ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
- ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
- ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
- }
- else
- {
- MPU->RBAR = 0x00U;
- MPU->RASR = 0x00U;
- }
+ /* Disable the Region */
+ CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
+
+ /* Apply configuration */
+ MPU->RBAR = MPU_Init->BaseAddress;
+ MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
+ ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
+ ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
+ ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
+ ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
+ ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
+ ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
+ ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
+ ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
}
#endif /* __MPU_PRESENT */
diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cryp.c b/system/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cryp.c
index 632449d7ca..e713fc5fd7 100644
--- a/system/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cryp.c
+++ b/system/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cryp.c
@@ -78,7 +78,7 @@
the CRYP peripheral is configured and processes the buffer in input.
At second call, no need to Initialize the CRYP, user have to get current configuration via
HAL_CRYP_GetConfig() API, then only HAL_CRYP_SetConfig() is requested to set
- new parametres, finally user can start encryption/decryption.
+ new parameters, finally user can start encryption/decryption.
(#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral.
@@ -200,7 +200,7 @@
(##) To perform message payload encryption or decryption AES is configured in CTR mode.
(##) For authentication two phases are performed :
- Header phase: peripheral processes the Additional Authenticated Data (AAD) first, then the cleartext message
- only cleartext payload (not the ciphertext payload) is used and no outpout.
+ only cleartext payload (not the ciphertext payload) is used and no output.
(##) Final phase: peripheral generates the authenticated tag (T) using the last block of data.
*** Callback registration ***
@@ -2221,15 +2221,17 @@ static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp)
/* Enable CRYP */
__HAL_CRYP_ENABLE(hcryp);
- /* Write the input block in the IN FIFO */
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ /* Increment the pointer before writing the input block in the IN FIFO to make sure that
+ when Computation Completed IRQ fires, the hcryp->CrypInCount has always a consistent value
+ and it is ready for the next operation. */
hcryp->CrypInCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U));
hcryp->CrypInCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U));
hcryp->CrypInCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U));
hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U));
}
else
{
@@ -2522,15 +2524,17 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp)
/* Enable CRYP */
__HAL_CRYP_ENABLE(hcryp);
- /* Write the input block in the IN FIFO */
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ /* Increment the pointer before writing the input block in the IN FIFO to make sure that
+ when Computation Completed IRQ fires, the hcryp->CrypInCount has always a consistent value
+ and it is ready for the next operation. */
hcryp->CrypInCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U));
hcryp->CrypInCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U));
hcryp->CrypInCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U));
hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U));
}
else
{
@@ -3696,10 +3700,6 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp)
header has already been processed;
only process here message payload */
{
-
- /* Enable computation complete flag and error interrupts */
- __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
-
/* Set to 0 the number of non-valid bytes using NPBLB register*/
MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U);
@@ -3736,6 +3736,9 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp)
HAL_CRYP_InCpltCallback(hcryp);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
+
+ /* Enable computation complete flag and error interrupts */
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
}
else /* Size < 16Bytes : first block is the last block*/
{
@@ -3784,6 +3787,9 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp)
/*Call legacy weak Input complete callback*/
HAL_CRYP_InCpltCallback(hcryp);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+
+ /* Enable computation complete flag and error interrupts */
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
}
}
@@ -4240,14 +4246,14 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp)
}
else if (hcryp->Size >= 16U)
{
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U));
hcryp->CrypInCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U));
hcryp->CrypInCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U));
hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U));
if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
{
@@ -4353,14 +4359,14 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp)
{
/* Write the first input header block in the Input FIFO,
the following header data will be fed after interrupt occurrence */
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount - 1U);
hcryp->CrypHeaderCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount - 1U);
hcryp->CrypHeaderCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount - 1U);
hcryp->CrypHeaderCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount - 1U);
}/* if (hcryp->Init.HeaderSize == 0U) */ /* Header phase is skipped*/
} /* end of if (dokeyivconfig == 1U) */
else /* Key and IV have already been configured,
@@ -4381,14 +4387,14 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp)
}
else if (hcryp->Size >= 16U)
{
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U));
hcryp->CrypInCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U));
hcryp->CrypInCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U));
hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U));
if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
{
diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dac_ex.c b/system/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dac_ex.c
index f5c872a669..939e195545 100644
--- a/system/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dac_ex.c
+++ b/system/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dac_ex.c
@@ -211,7 +211,6 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelCo
{
HAL_StatusTypeDef status = HAL_OK;
- __IO uint32_t tmp;
uint32_t trimmingvalue;
uint32_t delta;
__IO uint32_t wait_loop_index;
@@ -246,16 +245,6 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelCo
/* Set mode in MCR for calibration */
MODIFY_REG(hdac->Instance->MCR, (DAC_MCR_MODE1 << (Channel & 0x10UL)), 0U);
- /* Set DAC Channel1 DHR register to the middle value */
- tmp = (uint32_t)hdac->Instance;
-
- if (Channel == DAC_CHANNEL_1)
- {
- tmp += DAC_DHR12R1_ALIGNMENT(DAC_ALIGN_12B_R);
- }
-
- *(__IO uint32_t *) tmp = 0x0800UL;
-
/* Enable the selected DAC channel calibration */
/* i.e. set DAC_CR_CENx bit */
SET_BIT((hdac->Instance->CR), (DAC_CR_CEN1 << (Channel & 0x10UL)));
@@ -309,8 +298,12 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelCo
if ((hdac->Instance->SR & (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL))) == 0UL)
{
- /* Trimming is actually one value more */
- trimmingvalue++;
+ /* Check trimming value below maximum */
+ if (trimmingvalue < 0x1FU)
+ {
+ /* Trimming is actually one value more */
+ trimmingvalue++;
+ }
/* Set right trimming */
MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL)));
}
diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_i2c.c b/system/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_i2c.c
index a785ee9d5b..c898c16945 100644
--- a/system/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_i2c.c
+++ b/system/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_i2c.c
@@ -401,8 +401,10 @@
*/
/* Private macro -------------------------------------------------------------*/
+#if defined(HAL_DMA_MODULE_ENABLED)
/* Macro to get remaining data to transfer on DMA side */
#define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) __HAL_DMA_GET_COUNTER(__HANDLE__)
+#endif /*HAL_DMA_MODULE_ENABLED*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
@@ -410,6 +412,7 @@
/** @defgroup I2C_Private_Functions I2C Private Functions
* @{
*/
+#if defined(HAL_DMA_MODULE_ENABLED)
/* Private functions to handle DMA transfer */
static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma);
static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma);
@@ -418,6 +421,8 @@ static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma);
static void I2C_DMAError(DMA_HandleTypeDef *hdma);
static void I2C_DMAAbort(DMA_HandleTypeDef *hdma);
+#endif /*HAL_DMA_MODULE_ENABLED*/
+
/* Private functions to handle IT transfer */
static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c);
@@ -442,12 +447,14 @@ static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32
uint32_t ITSources);
static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
uint32_t ITSources);
+#if defined(HAL_DMA_MODULE_ENABLED)
static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
uint32_t ITSources);
static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
uint32_t ITSources);
static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
uint32_t ITSources);
+#endif /*HAL_DMA_MODULE_ENABLED*/
/* Private functions to handle flags during polling transfer */
static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status,
@@ -601,7 +608,12 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
/* Configure I2Cx: Addressing Master mode */
if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
{
- hi2c->Instance->CR2 = (I2C_CR2_ADD10);
+ SET_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10);;
+ }
+ else
+ {
+ /* Clear the I2C ADD10 bit */
+ CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10);
}
/* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
@@ -1108,6 +1120,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA
uint16_t Size, uint32_t Timeout)
{
uint32_t tickstart;
+ uint32_t xfermode;
if (hi2c->State == HAL_I2C_STATE_READY)
{
@@ -1131,18 +1144,39 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA
hi2c->XferCount = Size;
hi2c->XferISR = NULL;
- /* Send Slave Address */
- /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
- I2C_GENERATE_START_WRITE);
+ xfermode = I2C_RELOAD_MODE;
}
else
{
hi2c->XferSize = hi2c->XferCount;
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+ xfermode = I2C_AUTOEND_MODE;
+ }
+
+ if (hi2c->XferSize > 0U)
+ {
+ /* Preload TX register */
+ /* Write data to TXDR */
+ hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ hi2c->XferCount--;
+ hi2c->XferSize--;
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)(hi2c->XferSize + 1U), xfermode,
+ I2C_GENERATE_START_WRITE);
+ }
+ else
+ {
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode,
I2C_GENERATE_START_WRITE);
}
@@ -1345,6 +1379,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
uint32_t Timeout)
{
uint32_t tickstart;
+ uint16_t tmpXferCount;
+ HAL_StatusTypeDef error;
if (hi2c->State == HAL_I2C_STATE_READY)
{
@@ -1379,6 +1415,19 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
return HAL_ERROR;
}
+ /* Preload TX data if no stretch enable */
+ if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE)
+ {
+ /* Preload TX register */
+ /* Write data to TXDR */
+ hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ hi2c->XferCount--;
+ }
+
/* Clear ADDR flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
@@ -1425,31 +1474,48 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
}
/* Wait until AF flag is set */
- if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK)
+ error = I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart);
+
+ if (error != HAL_OK)
{
- /* Disable Address Acknowledge */
- hi2c->Instance->CR2 |= I2C_CR2_NACK;
- return HAL_ERROR;
+ /* Check that I2C transfer finished */
+ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
+ /* Mean XferCount == 0 */
+
+ tmpXferCount = hi2c->XferCount;
+ if ((hi2c->ErrorCode == HAL_I2C_ERROR_AF) && (tmpXferCount == 0U))
+ {
+ /* Reset ErrorCode to NONE */
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ }
+ else
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+ return HAL_ERROR;
+ }
}
+ else
+ {
+ /* Flush TX register */
+ I2C_Flush_TXDR(hi2c);
- /* Flush TX register */
- I2C_Flush_TXDR(hi2c);
+ /* Clear AF flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
- /* Clear AF flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+ /* Wait until STOP flag is set */
+ if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
- /* Wait until STOP flag is set */
- if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
- {
- /* Disable Address Acknowledge */
- hi2c->Instance->CR2 |= I2C_CR2_NACK;
+ return HAL_ERROR;
+ }
- return HAL_ERROR;
+ /* Clear STOP flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
}
- /* Clear STOP flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
/* Wait until BUSY flag is reset */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
{
@@ -1652,7 +1718,26 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D
/* Send Slave Address */
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
+ if (hi2c->XferSize > 0U)
+ {
+ /* Preload TX register */
+ /* Write data to TXDR */
+ hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ hi2c->XferCount--;
+ hi2c->XferSize--;
+
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)(hi2c->XferSize + 1U), xfermode,
+ I2C_GENERATE_START_WRITE);
+ }
+ else
+ {
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode,
+ I2C_GENERATE_START_WRITE);
+ }
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -1775,6 +1860,20 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pD
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->XferISR = I2C_Slave_ISR_IT;
+ /* Preload TX data if no stretch enable */
+ if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE)
+ {
+ /* Preload TX register */
+ /* Write data to TXDR */
+ hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ hi2c->XferCount--;
+ hi2c->XferSize--;
+ }
+
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -1846,6 +1945,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pDa
}
}
+#if defined(HAL_DMA_MODULE_ENABLED)
/**
* @brief Transmit in master mode an amount of data in non-blocking mode with DMA
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
@@ -1861,6 +1961,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t
{
uint32_t xfermode;
HAL_StatusTypeDef dmaxferstatus;
+ uint32_t sizetoxfer = 0U;
if (hi2c->State == HAL_I2C_STATE_READY)
{
@@ -1893,6 +1994,20 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t
xfermode = I2C_AUTOEND_MODE;
}
+ if (hi2c->XferSize > 0U)
+ {
+ /* Preload TX register */
+ /* Write data to TXDR */
+ hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ sizetoxfer = hi2c->XferSize;
+ hi2c->XferCount--;
+ hi2c->XferSize--;
+ }
+
if (hi2c->XferSize > 0U)
{
if (hi2c->hdmatx != NULL)
@@ -1908,7 +2023,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t
hi2c->hdmatx->XferAbortCallback = NULL;
/* Enable the DMA channel */
- dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR,
hi2c->XferSize);
}
else
@@ -1930,7 +2045,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t
{
/* Send Slave Address */
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)(hi2c->XferSize + 1U), xfermode, I2C_GENERATE_START_WRITE);
/* Update XferCount value */
hi2c->XferCount -= hi2c->XferSize;
@@ -1969,7 +2084,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t
/* Send Slave Address */
/* Set NBYTES to write and generate START condition */
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, I2C_AUTOEND_MODE,
I2C_GENERATE_START_WRITE);
/* Process Unlocked */
@@ -2173,67 +2288,99 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->XferISR = I2C_Slave_ISR_DMA;
- if (hi2c->hdmatx != NULL)
+ /* Preload TX data if no stretch enable */
+ if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE)
{
- /* Set the I2C DMA transfer complete callback */
- hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
-
- /* Set the DMA error callback */
- hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+ /* Preload TX register */
+ /* Write data to TXDR */
+ hi2c->Instance->TXDR = *hi2c->pBuffPtr;
- /* Set the unused DMA callbacks to NULL */
- hi2c->hdmatx->XferHalfCpltCallback = NULL;
- hi2c->hdmatx->XferAbortCallback = NULL;
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
- /* Enable the DMA channel */
- dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
- hi2c->XferSize);
+ hi2c->XferCount--;
+ hi2c->XferSize--;
}
- else
+
+ if (hi2c->XferCount != 0U)
{
- /* Update I2C state */
- hi2c->State = HAL_I2C_STATE_LISTEN;
- hi2c->Mode = HAL_I2C_MODE_NONE;
+ if (hi2c->hdmatx != NULL)
+ {
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
- /* Update I2C error code */
- hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+ /* Set the DMA error callback */
+ hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmatx->XferHalfCpltCallback = NULL;
+ hi2c->hdmatx->XferAbortCallback = NULL;
- return HAL_ERROR;
- }
+ /* Enable the DMA channel */
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx,
+ (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR,
+ hi2c->XferSize);
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_LISTEN;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
- if (dmaxferstatus == HAL_OK)
- {
- /* Enable Address Acknowledge */
- hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
- /* Enable ERR, STOP, NACK, ADDR interrupts */
- I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+ return HAL_ERROR;
+ }
- /* Enable DMA Request */
- hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+ if (dmaxferstatus == HAL_OK)
+ {
+ /* Enable Address Acknowledge */
+ hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR, STOP, NACK, ADDR interrupts */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+ /* Enable DMA Request */
+ hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_LISTEN;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
}
else
{
- /* Update I2C state */
- hi2c->State = HAL_I2C_STATE_LISTEN;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Update I2C error code */
- hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+ /* Enable Address Acknowledge */
+ hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
- return HAL_ERROR;
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR, STOP, NACK, ADDR interrupts */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
}
return HAL_OK;
@@ -2347,6 +2494,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD
return HAL_BUSY;
}
}
+#endif /*HAL_DMA_MODULE_ENABLED*/
+
/**
* @brief Write an amount of data in blocking mode to a specific memory address
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
@@ -2661,6 +2810,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
/* Prepare transfer parameters */
+ hi2c->XferSize = 0U;
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
@@ -2795,6 +2945,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre
return HAL_BUSY;
}
}
+
+#if defined(HAL_DMA_MODULE_ENABLED)
/**
* @brief Write an amount of data in non-blocking mode with DMA to a specific memory address
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
@@ -3086,6 +3238,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
return HAL_BUSY;
}
}
+#endif /*HAL_DMA_MODULE_ENABLED*/
/**
* @brief Checks if target device is ready for communication.
@@ -3191,22 +3344,6 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
}
- /* Check if the maximum allowed number of trials has been reached */
- if (I2C_Trials == Trials)
- {
- /* Generate Stop */
- hi2c->Instance->CR2 |= I2C_CR2_STOP;
-
- /* Wait until STOPF flag is reset */
- if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
- {
- return HAL_ERROR;
- }
-
- /* Clear STOP Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
- }
-
/* Increment Trials */
I2C_Trials++;
} while (I2C_Trials < Trials);
@@ -3245,6 +3382,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16
{
uint32_t xfermode;
uint32_t xferrequest = I2C_GENERATE_START_WRITE;
+ uint32_t sizetoxfer = 0U;
/* Check the parameters */
assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
@@ -3276,6 +3414,20 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16
xfermode = hi2c->XferOptions;
}
+ if ((hi2c->XferSize > 0U) && ((XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_FIRST_AND_LAST_FRAME)))
+ {
+ /* Preload TX register */
+ /* Write data to TXDR */
+ hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ sizetoxfer = hi2c->XferSize;
+ hi2c->XferCount--;
+ hi2c->XferSize--;
+ }
+
/* If transfer direction not change and there is no request to start another frame,
do not generate Restart Condition */
/* Mean Previous state is same as current state */
@@ -3297,7 +3449,14 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16
}
/* Send Slave Address and set NBYTES to write */
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
+ if ((XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_FIRST_AND_LAST_FRAME))
+ {
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, xfermode, xferrequest);
+ }
+ else
+ {
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
+ }
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -3319,6 +3478,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16
}
}
+#if defined(HAL_DMA_MODULE_ENABLED)
/**
* @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA.
* @note This interface allow to manage repeated start condition when a direction change during transfer
@@ -3337,6 +3497,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1
uint32_t xfermode;
uint32_t xferrequest = I2C_GENERATE_START_WRITE;
HAL_StatusTypeDef dmaxferstatus;
+ uint32_t sizetoxfer = 0U;
/* Check the parameters */
assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
@@ -3368,6 +3529,20 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1
xfermode = hi2c->XferOptions;
}
+ if ((hi2c->XferSize > 0U) && ((XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_FIRST_AND_LAST_FRAME)))
+ {
+ /* Preload TX register */
+ /* Write data to TXDR */
+ hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ sizetoxfer = hi2c->XferSize;
+ hi2c->XferCount--;
+ hi2c->XferSize--;
+ }
+
/* If transfer direction not change and there is no request to start another frame,
do not generate Restart Condition */
/* Mean Previous state is same as current state */
@@ -3403,7 +3578,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1
hi2c->hdmatx->XferAbortCallback = NULL;
/* Enable the DMA channel */
- dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR,
hi2c->XferSize);
}
else
@@ -3424,7 +3599,14 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1
if (dmaxferstatus == HAL_OK)
{
/* Send Slave Address and set NBYTES to write */
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
+ if ((XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_FIRST_AND_LAST_FRAME))
+ {
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, xfermode, xferrequest);
+ }
+ else
+ {
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
+ }
/* Update XferCount value */
hi2c->XferCount -= hi2c->XferSize;
@@ -3463,8 +3645,14 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1
/* Send Slave Address */
/* Set NBYTES to write and generate START condition */
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
- I2C_GENERATE_START_WRITE);
+ if ((XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_FIRST_AND_LAST_FRAME))
+ {
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, xfermode, xferrequest);
+ }
+ else
+ {
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
+ }
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -3486,6 +3674,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1
return HAL_BUSY;
}
}
+#endif /*HAL_DMA_MODULE_ENABLED*/
/**
* @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt
@@ -3574,6 +3763,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_
}
}
+#if defined(HAL_DMA_MODULE_ENABLED)
/**
* @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with DMA
* @note This interface allow to manage repeated start condition when a direction change during transfer
@@ -3741,6 +3931,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16
return HAL_BUSY;
}
}
+#endif /*HAL_DMA_MODULE_ENABLED*/
/**
* @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
@@ -3782,6 +3973,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t
/* Disable associated Interrupts */
I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+#if defined(HAL_DMA_MODULE_ENABLED)
/* Abort DMA Xfer if any */
if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
{
@@ -3801,6 +3993,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t
}
}
}
+#endif /*HAL_DMA_MODULE_ENABLED*/
}
hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;
@@ -3842,6 +4035,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t
}
}
+#if defined(HAL_DMA_MODULE_ENABLED)
/**
* @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with DMA
* @note This interface allow to manage repeated start condition when a direction change during transfer
@@ -3891,7 +4085,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_
hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
/* Set the I2C DMA Abort callback :
- will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+ will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
/* Abort DMA RX */
@@ -3913,7 +4107,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_
if (hi2c->hdmatx != NULL)
{
/* Set the I2C DMA Abort callback :
- will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+ will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
/* Abort DMA TX */
@@ -4025,6 +4219,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_
return HAL_ERROR;
}
}
+#endif /*HAL_DMA_MODULE_ENABLED*/
/**
* @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
@@ -4066,6 +4261,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t
/* Disable associated Interrupts */
I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+#if defined(HAL_DMA_MODULE_ENABLED)
if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
{
hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
@@ -4085,6 +4281,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t
}
}
}
+#endif /*HAL_DMA_MODULE_ENABLED*/
}
hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
@@ -4126,6 +4323,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t
}
}
+#if defined(HAL_DMA_MODULE_ENABLED)
/**
* @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with DMA
* @note This interface allow to manage repeated start condition when a direction change during transfer
@@ -4309,6 +4507,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t
return HAL_ERROR;
}
}
+#endif /*HAL_DMA_MODULE_ENABLED*/
/**
* @brief Enable the Address listen mode with Interrupt.
@@ -4688,7 +4887,7 @@ __weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
* the configuration information for the specified I2C.
* @retval HAL state
*/
-HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
+HAL_I2C_StateTypeDef HAL_I2C_GetState(const I2C_HandleTypeDef *hi2c)
{
/* Return I2C handle state */
return hi2c->State;
@@ -4700,7 +4899,7 @@ HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
* the configuration information for I2C module
* @retval HAL mode
*/
-HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c)
+HAL_I2C_ModeTypeDef HAL_I2C_GetMode(const I2C_HandleTypeDef *hi2c)
{
return hi2c->Mode;
}
@@ -4711,7 +4910,7 @@ HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c)
* the configuration information for the specified I2C.
* @retval I2C Error Code
*/
-uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
+uint32_t HAL_I2C_GetError(const I2C_HandleTypeDef *hi2c)
{
return hi2c->ErrorCode;
}
@@ -4774,17 +4973,22 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin
hi2c->XferSize--;
hi2c->XferCount--;
}
- else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
- (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
+ else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) == RESET) && \
+ ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)))
{
/* Write data to TXDR */
- hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+ if (hi2c->XferCount != 0U)
+ {
+ /* Write data to TXDR */
+ hi2c->Instance->TXDR = *hi2c->pBuffPtr;
- /* Increment Buffer pointer */
- hi2c->pBuffPtr++;
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
- hi2c->XferSize--;
- hi2c->XferCount--;
+ hi2c->XferSize--;
+ hi2c->XferCount--;
+ }
}
else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
@@ -4883,7 +5087,7 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
- uint32_t ITSources)
+ uint32_t ITSources)
{
uint32_t direction = I2C_GENERATE_START_WRITE;
uint32_t tmpITFlags = ITFlags;
@@ -5035,9 +5239,8 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint
/* Call I2C Slave complete process */
I2C_ITSlaveCplt(hi2c, tmpITFlags);
}
-
- if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
- (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+ else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
{
/* Check that I2C transfer finished */
/* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
@@ -5152,6 +5355,7 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint
return HAL_OK;
}
+#if defined(HAL_DMA_MODULE_ENABLED)
/**
* @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
@@ -5301,7 +5505,7 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
- uint32_t ITSources)
+ uint32_t ITSources)
{
uint32_t direction = I2C_GENERATE_START_WRITE;
@@ -5456,9 +5660,8 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin
/* Call I2C Slave complete process */
I2C_ITSlaveCplt(hi2c, ITFlags);
}
-
- if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
- (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+ else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
{
/* Check that I2C transfer finished */
/* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
@@ -5571,6 +5774,7 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin
return HAL_OK;
}
+#endif /*HAL_DMA_MODULE_ENABLED*/
/**
* @brief Master sends target device address followed by internal memory address for write request.
@@ -5843,6 +6047,7 @@ static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c)
/* Reset I2C handle mode */
hi2c->Mode = HAL_I2C_MODE_NONE;
+#if defined(HAL_DMA_MODULE_ENABLED)
/* If a DMA is ongoing, Update handle size context */
if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
{
@@ -5858,6 +6063,7 @@ static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c)
{
/* Do nothing */
}
+#endif /*HAL_DMA_MODULE_ENABLED*/
if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
{
@@ -6057,6 +6263,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
{
uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
uint32_t tmpITFlags = ITFlags;
+ uint32_t tmpoptions = hi2c->XferOptions;
HAL_I2C_StateTypeDef tmpstate = hi2c->State;
/* Clear STOP Flag */
@@ -6087,6 +6294,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
/* Flush TX register */
I2C_Flush_TXDR(hi2c);
+#if defined(HAL_DMA_MODULE_ENABLED)
/* If a DMA is ongoing, Update handle size context */
if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
{
@@ -6112,6 +6320,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
{
/* Do nothing */
}
+#endif /*HAL_DMA_MODULE_ENABLED*/
/* Store Last receive data if any */
if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET)
@@ -6139,6 +6348,57 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
}
+ if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_IT_NACKI) != RESET))
+ {
+ /* Check that I2C transfer finished */
+ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
+ /* Mean XferCount == 0*/
+ /* So clear Flag NACKF only */
+ if (hi2c->XferCount == 0U)
+ {
+ if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
+ /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
+ Warning[Pa134]: left and right operands are identical */
+ {
+ /* Call I2C Listen complete process */
+ I2C_ITListenCplt(hi2c, tmpITFlags);
+ }
+ else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
+ {
+ /* Clear NACK Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ /* Flush TX register */
+ I2C_Flush_TXDR(hi2c);
+
+ /* Last Byte is Transmitted */
+ /* Call I2C Slave Sequential complete process */
+ I2C_ITSlaveSeqCplt(hi2c);
+ }
+ else
+ {
+ /* Clear NACK Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+ }
+ }
+ else
+ {
+ /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
+ /* Clear NACK Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ /* Set ErrorCode corresponding to a Non-Acknowledge */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+
+ if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
+ {
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ I2C_ITError(hi2c, hi2c->ErrorCode);
+ }
+ }
+ }
+
hi2c->Mode = HAL_I2C_MODE_NONE;
hi2c->XferISR = NULL;
@@ -6266,7 +6526,10 @@ static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
{
HAL_I2C_StateTypeDef tmpstate = hi2c->State;
+
+#if defined(HAL_DMA_MODULE_ENABLED)
uint32_t tmppreviousstate;
+#endif /*HAL_DMA_MODULE_ENABLED*/
/* Reset handle parameters */
hi2c->Mode = HAL_I2C_MODE_NONE;
@@ -6293,18 +6556,37 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
/* Disable all interrupts */
I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
+ /* Flush TX register */
+ I2C_Flush_TXDR(hi2c);
+
/* If state is an abort treatment on going, don't change state */
/* This change will be do later */
if (hi2c->State != HAL_I2C_STATE_ABORT)
{
/* Set HAL_I2C_STATE_READY */
hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Check if a STOPF is detected */
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
+ {
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
+ {
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+ }
+
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+ }
+
}
hi2c->XferISR = NULL;
}
+#if defined(HAL_DMA_MODULE_ENABLED)
/* Abort DMA TX transfer if any */
tmppreviousstate = hi2c->PreviousState;
+
if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || \
(tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX)))
{
@@ -6365,6 +6647,7 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
}
}
else
+#endif /*HAL_DMA_MODULE_ENABLED*/
{
I2C_TreatErrorCallback(hi2c);
}
@@ -6429,6 +6712,7 @@ static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c)
}
}
+#if defined(HAL_DMA_MODULE_ENABLED)
/**
* @brief DMA I2C master transmit process complete callback.
* @param hdma DMA handle
@@ -6479,6 +6763,7 @@ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
}
}
+
/**
* @brief DMA I2C slave transmit process complete callback.
* @param hdma DMA handle
@@ -6507,6 +6792,7 @@ static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
}
}
+
/**
* @brief DMA I2C master receive process complete callback.
* @param hdma DMA handle
@@ -6557,6 +6843,7 @@ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
}
}
+
/**
* @brief DMA I2C slave receive process complete callback.
* @param hdma DMA handle
@@ -6585,6 +6872,7 @@ static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
}
}
+
/**
* @brief DMA I2C communication error callback.
* @param hdma DMA handle
@@ -6602,6 +6890,7 @@ static void I2C_DMAError(DMA_HandleTypeDef *hdma)
I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
}
+
/**
* @brief DMA I2C communication abort callback
* (To be called at end of DMA Abort procedure).
@@ -6626,6 +6915,8 @@ static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
I2C_TreatErrorCallback(hi2c);
}
+#endif /*HAL_DMA_MODULE_ENABLED*/
+
/**
* @brief This function handles I2C Communication Timeout. It waits
* until a flag is no longer in the specified status.
@@ -6642,18 +6933,27 @@ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uin
{
while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
{
+ /* Check if an error is detected */
+ if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
{
- hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
+ if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == Status))
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_ERROR;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_ERROR;
+ }
}
}
}
@@ -6684,14 +6984,17 @@ static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
{
- hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
+ if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET))
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
- return HAL_ERROR;
+ return HAL_ERROR;
+ }
}
}
}
@@ -6720,14 +7023,17 @@ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
/* Check for the Timeout */
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
{
- hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
+ if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET))
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
- return HAL_ERROR;
+ return HAL_ERROR;
+ }
}
}
return HAL_OK;
@@ -6744,16 +7050,18 @@ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
uint32_t Tickstart)
{
- while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
+ HAL_StatusTypeDef status = HAL_OK;
+
+ while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) && (status == HAL_OK))
{
/* Check if an error is detected */
if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
{
- return HAL_ERROR;
+ status = HAL_ERROR;
}
/* Check if a STOPF is detected */
- if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
+ if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) && (status == HAL_OK))
{
/* Check if an RXNE is pending */
/* Store Last receive data if any */
@@ -6761,19 +7069,14 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
{
/* Return HAL_OK */
/* The Reading of data from RXDR will be done in caller function */
- return HAL_OK;
+ status = HAL_OK;
}
- else
+
+ /* Check a no-acknowledge have been detected */
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
{
- if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
- {
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
- hi2c->ErrorCode = HAL_I2C_ERROR_AF;
- }
- else
- {
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
- }
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+ hi2c->ErrorCode = HAL_I2C_ERROR_AF;
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
@@ -6787,23 +7090,30 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
- return HAL_ERROR;
+ status = HAL_ERROR;
+ }
+ else
+ {
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
}
}
/* Check for the Timeout */
- if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+ if ((((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) && (status == HAL_OK))
{
- hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
- hi2c->State = HAL_I2C_STATE_READY;
+ if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET))
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ hi2c->State = HAL_I2C_STATE_READY;
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
- return HAL_ERROR;
+ status = HAL_ERROR;
+ }
}
}
- return HAL_OK;
+ return status;
}
/**
@@ -6986,15 +7296,30 @@ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
{
uint32_t tmpisr = 0U;
- if ((hi2c->XferISR == I2C_Master_ISR_DMA) || \
- (hi2c->XferISR == I2C_Slave_ISR_DMA))
+#if defined(HAL_DMA_MODULE_ENABLED)
+ if ((hi2c->XferISR != I2C_Master_ISR_DMA) && \
+ (hi2c->XferISR != I2C_Slave_ISR_DMA) && \
+ (hi2c->XferISR != I2C_Mem_ISR_DMA))
+#endif /*HAL_DMA_MODULE_ENABLED*/
{
if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
{
- /* Enable ERR, STOP, NACK and ADDR interrupts */
+ /* Enable ERR, STOP, NACK, and ADDR interrupts */
tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
}
+ if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
+ {
+ /* Enable ERR, TC, STOP, NACK and RXI interrupts */
+ tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
+ }
+
+ if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
+ {
+ /* Enable ERR, TC, STOP, NACK and TXI interrupts */
+ tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
+ }
+
if (InterruptRequest == I2C_XFER_ERROR_IT)
{
/* Enable ERR and NACK interrupts */
@@ -7004,20 +7329,16 @@ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
if (InterruptRequest == I2C_XFER_CPLT_IT)
{
/* Enable STOP interrupts */
- tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI);
- }
-
- if (InterruptRequest == I2C_XFER_RELOAD_IT)
- {
- /* Enable TC interrupts */
- tmpisr |= I2C_IT_TCI;
+ tmpisr |= I2C_IT_STOPI;
}
}
+
+#if defined(HAL_DMA_MODULE_ENABLED)
else
{
if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
{
- /* Enable ERR, STOP, NACK, and ADDR interrupts */
+ /* Enable ERR, STOP, NACK and ADDR interrupts */
tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
}
@@ -7042,9 +7363,16 @@ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
if (InterruptRequest == I2C_XFER_CPLT_IT)
{
/* Enable STOP interrupts */
- tmpisr |= I2C_IT_STOPI;
+ tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI);
+ }
+
+ if ((hi2c->XferISR != I2C_Mem_ISR_DMA) && (InterruptRequest == I2C_XFER_RELOAD_IT))
+ {
+ /* Enable TC interrupts */
+ tmpisr |= I2C_IT_TCI;
}
}
+#endif /*HAL_DMA_MODULE_ENABLED*/
/* Enable interrupts only at the end */
/* to avoid the risk of I2C interrupt handle execution before */
@@ -7052,6 +7380,7 @@ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
__HAL_I2C_ENABLE_IT(hi2c, tmpisr);
}
+
/**
* @brief Manage the disabling of Interrupts.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_smbus.c b/system/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_smbus.c
index b288885ea5..0fef7c691d 100644
--- a/system/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_smbus.c
+++ b/system/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_smbus.c
@@ -926,6 +926,7 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint
uint8_t *pData, uint16_t Size, uint32_t XferOptions)
{
uint32_t tmp;
+ uint32_t sizetoxfer = 0U;
/* Check the parameters */
assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
@@ -958,11 +959,28 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint
hsmbus->XferSize = Size;
}
+ sizetoxfer = hsmbus->XferSize;
+ if ((hsmbus->XferSize > 0U) && ((XferOptions == SMBUS_FIRST_FRAME) ||
+ (XferOptions == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) ||
+ (XferOptions == SMBUS_FIRST_FRAME_WITH_PEC) ||
+ (XferOptions == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC)))
+ {
+ /* Preload TX register */
+ /* Write data to TXDR */
+ hsmbus->Instance->TXDR = *hsmbus->pBuffPtr;
+
+ /* Increment Buffer pointer */
+ hsmbus->pBuffPtr++;
+
+ hsmbus->XferCount--;
+ hsmbus->XferSize--;
+ }
+
/* Send Slave Address */
/* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
- if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE))
+ if ((sizetoxfer < hsmbus->XferCount) && (sizetoxfer == MAX_NBYTE_SIZE))
{
- SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize,
+ SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)sizetoxfer,
SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE),
SMBUS_GENERATE_START_WRITE);
}
@@ -977,7 +995,7 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint
if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) && \
(IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0))
{
- SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions,
+ SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)sizetoxfer, hsmbus->XferOptions,
SMBUS_NO_STARTSTOP);
}
/* Else transfer direction change, so generate Restart with new transfer direction */
@@ -987,7 +1005,7 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint
SMBUS_ConvertOtherXferOptions(hsmbus);
/* Handle Transfer */
- SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize,
+ SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)sizetoxfer,
hsmbus->XferOptions,
SMBUS_GENERATE_START_WRITE);
}
@@ -1813,7 +1831,7 @@ __weak void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus)
* the configuration information for the specified SMBUS.
* @retval HAL state
*/
-uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus)
+uint32_t HAL_SMBUS_GetState(const SMBUS_HandleTypeDef *hsmbus)
{
/* Return SMBUS handle state */
return hsmbus->State;
@@ -1825,7 +1843,7 @@ uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus)
* the configuration information for the specified SMBUS.
* @retval SMBUS Error Code
*/
-uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus)
+uint32_t HAL_SMBUS_GetError(const SMBUS_HandleTypeDef *hsmbus)
{
return hsmbus->ErrorCode;
}
@@ -2587,8 +2605,11 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus)
__HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_PECERR);
}
- /* Flush TX register */
- SMBUS_Flush_TXDR(hsmbus);
+ if (hsmbus->ErrorCode != HAL_SMBUS_ERROR_NONE)
+ {
+ /* Flush TX register */
+ SMBUS_Flush_TXDR(hsmbus);
+ }
/* Store current volatile hsmbus->ErrorCode, misra rule */
tmperror = hsmbus->ErrorCode;
diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_spi.c b/system/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_spi.c
index 118bc5a2c6..aa7a9f7a1e 100644
--- a/system/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_spi.c
+++ b/system/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_spi.c
@@ -908,6 +908,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint
if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
{
errorcode = HAL_TIMEOUT;
+ hspi->State = HAL_SPI_STATE_READY;
goto error;
}
}
@@ -957,6 +958,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint
if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
{
errorcode = HAL_TIMEOUT;
+ hspi->State = HAL_SPI_STATE_READY;
goto error;
}
}
@@ -986,9 +988,12 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint
{
errorcode = HAL_ERROR;
}
+ else
+ {
+ hspi->State = HAL_SPI_STATE_READY;
+ }
error:
- hspi->State = HAL_SPI_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hspi);
return errorcode;
@@ -1013,6 +1018,12 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
uint32_t tickstart;
HAL_StatusTypeDef errorcode = HAL_OK;
+ if (hspi->State != HAL_SPI_STATE_READY)
+ {
+ errorcode = HAL_BUSY;
+ goto error;
+ }
+
if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
{
hspi->State = HAL_SPI_STATE_BUSY_RX;
@@ -1026,12 +1037,6 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
- if (hspi->State != HAL_SPI_STATE_READY)
- {
- errorcode = HAL_BUSY;
- goto error;
- }
-
if ((pData == NULL) || (Size == 0U))
{
errorcode = HAL_ERROR;
@@ -1109,6 +1114,7 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
{
errorcode = HAL_TIMEOUT;
+ hspi->State = HAL_SPI_STATE_READY;
goto error;
}
}
@@ -1132,6 +1138,7 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
{
errorcode = HAL_TIMEOUT;
+ hspi->State = HAL_SPI_STATE_READY;
goto error;
}
}
@@ -1226,9 +1233,12 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
{
errorcode = HAL_ERROR;
}
+ else
+ {
+ hspi->State = HAL_SPI_STATE_READY;
+ }
error :
- hspi->State = HAL_SPI_STATE_READY;
__HAL_UNLOCK(hspi);
return errorcode;
}
@@ -1349,6 +1359,20 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
hspi->pTxBuffPtr += sizeof(uint16_t);
hspi->TxXferCount--;
+
+#if (USE_SPI_CRC != 0U)
+ /* Enable CRC Transmission */
+ if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
+ {
+ /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
+ if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP))
+ {
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
+ }
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+ }
+#endif /* USE_SPI_CRC */
+
}
while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
{
@@ -1387,6 +1411,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
if (((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY))
{
errorcode = HAL_TIMEOUT;
+ hspi->State = HAL_SPI_STATE_READY;
goto error;
}
}
@@ -1407,6 +1432,19 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
*(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
hspi->pTxBuffPtr++;
hspi->TxXferCount--;
+
+#if (USE_SPI_CRC != 0U)
+ /* Enable CRC Transmission */
+ if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
+ {
+ /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
+ if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP))
+ {
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
+ }
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+ }
+#endif /* USE_SPI_CRC */
}
}
while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
@@ -1469,6 +1507,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
if ((((HAL_GetTick() - tickstart) >= Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U))
{
errorcode = HAL_TIMEOUT;
+ hspi->State = HAL_SPI_STATE_READY;
goto error;
}
}
@@ -1538,8 +1577,16 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
}
+ if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ {
+ errorcode = HAL_ERROR;
+ }
+ else
+ {
+ hspi->State = HAL_SPI_STATE_READY;
+ }
+
error :
- hspi->State = HAL_SPI_STATE_READY;
__HAL_UNLOCK(hspi);
return errorcode;
}
@@ -1559,8 +1606,6 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u
/* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
- /* Process Locked */
- __HAL_LOCK(hspi);
if ((pData == NULL) || (Size == 0U))
{
@@ -1574,6 +1619,9 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u
goto error;
}
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
/* Set the transaction information */
hspi->State = HAL_SPI_STATE_BUSY_TX;
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
@@ -1613,10 +1661,6 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u
}
#endif /* USE_SPI_CRC */
- /* Enable TXE and ERR interrupt */
- __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
-
-
/* Check if the SPI is already enabled */
if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
{
@@ -1624,8 +1668,12 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u
__HAL_SPI_ENABLE(hspi);
}
-error :
+ /* Process Unlocked */
__HAL_UNLOCK(hspi);
+ /* Enable TXE and ERR interrupt */
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
+
+error :
return errorcode;
}
@@ -1641,6 +1689,13 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui
{
HAL_StatusTypeDef errorcode = HAL_OK;
+
+ if (hspi->State != HAL_SPI_STATE_READY)
+ {
+ errorcode = HAL_BUSY;
+ goto error;
+ }
+
if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
{
hspi->State = HAL_SPI_STATE_BUSY_RX;
@@ -1648,14 +1703,6 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui
return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
}
- /* Process Locked */
- __HAL_LOCK(hspi);
-
- if (hspi->State != HAL_SPI_STATE_READY)
- {
- errorcode = HAL_BUSY;
- goto error;
- }
if ((pData == NULL) || (Size == 0U))
{
@@ -1663,6 +1710,9 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui
goto error;
}
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
/* Set the transaction information */
hspi->State = HAL_SPI_STATE_BUSY_RX;
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
@@ -1715,9 +1765,6 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui
}
#endif /* USE_SPI_CRC */
- /* Enable TXE and ERR interrupt */
- __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
-
/* Note : The SPI must be enabled after unlocking current process
to avoid the risk of SPI interrupt handle execution before current
process unlock */
@@ -1729,9 +1776,12 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui
__HAL_SPI_ENABLE(hspi);
}
-error :
/* Process Unlocked */
__HAL_UNLOCK(hspi);
+ /* Enable RXNE and ERR interrupt */
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
+
+error :
return errorcode;
}
@@ -1753,9 +1803,6 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p
/* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
- /* Process locked */
- __HAL_LOCK(hspi);
-
/* Init temporary variables */
tmp_state = hspi->State;
tmp_mode = hspi->Init.Mode;
@@ -1773,6 +1820,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p
goto error;
}
+ /* Process locked */
+ __HAL_LOCK(hspi);
+
/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
if (hspi->State != HAL_SPI_STATE_BUSY_RX)
{
@@ -1829,8 +1879,6 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p
SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
}
- /* Enable TXE, RXNE and ERR interrupt */
- __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
/* Check if the SPI is already enabled */
if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
@@ -1839,9 +1887,12 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p
__HAL_SPI_ENABLE(hspi);
}
-error :
/* Process Unlocked */
__HAL_UNLOCK(hspi);
+ /* Enable TXE, RXNE and ERR interrupt */
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
+
+error :
return errorcode;
}
@@ -1945,7 +1996,6 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData,
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
errorcode = HAL_ERROR;
- hspi->State = HAL_SPI_STATE_READY;
goto error;
}
@@ -1985,6 +2035,12 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u
/* Check rx dma handle */
assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
+ if (hspi->State != HAL_SPI_STATE_READY)
+ {
+ errorcode = HAL_BUSY;
+ goto error;
+ }
+
if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
{
hspi->State = HAL_SPI_STATE_BUSY_RX;
@@ -1999,12 +2055,6 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u
/* Process Locked */
__HAL_LOCK(hspi);
- if (hspi->State != HAL_SPI_STATE_READY)
- {
- errorcode = HAL_BUSY;
- goto error;
- }
-
if ((pData == NULL) || (Size == 0U))
{
errorcode = HAL_ERROR;
@@ -2090,7 +2140,6 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
errorcode = HAL_ERROR;
- hspi->State = HAL_SPI_STATE_READY;
goto error;
}
@@ -2258,7 +2307,6 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
errorcode = HAL_ERROR;
- hspi->State = HAL_SPI_STATE_READY;
goto error;
}
@@ -2280,7 +2328,6 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
errorcode = HAL_ERROR;
- hspi->State = HAL_SPI_STATE_READY;
goto error;
}
diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c b/system/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c
index c66c8dbea8..ccd8381f5d 100644
--- a/system/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c
+++ b/system/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c
@@ -266,13 +266,13 @@ HAL_StatusTypeDef HAL_SUBGHZ_Init(SUBGHZ_HandleTypeDef *hsubghz)
HAL_SUBGHZ_MspInit(hsubghz);
#endif /* USE_HAL_ SUBGHZ_REGISTER_CALLBACKS */
-#if defined(CM0PLUS)
+#if defined(CORE_CM0PLUS)
/* Enable EXTI 44 : Radio IRQ ITs for CPU2 */
LL_C2_EXTI_EnableIT_32_63(LL_EXTI_LINE_44);
#else
/* Enable EXTI 44 : Radio IRQ ITs for CPU1 */
LL_EXTI_EnableIT_32_63(LL_EXTI_LINE_44);
-#endif /* CM0PLUS */
+#endif /* CORE_CM0PLUS */
}
if (subghz_state == HAL_SUBGHZ_STATE_RESET)
@@ -300,13 +300,13 @@ HAL_StatusTypeDef HAL_SUBGHZ_Init(SUBGHZ_HandleTypeDef *hsubghz)
/* Asserts the reset signal of the Radio peripheral */
LL_PWR_UnselectSUBGHZSPI_NSS();
-#if defined(CM0PLUS)
+#if defined(CORE_CM0PLUS)
/* Enable wakeup signal of the Radio peripheral */
LL_C2_PWR_SetRadioBusyTrigger(LL_PWR_RADIO_BUSY_TRIGGER_WU_IT);
#else
/* Enable wakeup signal of the Radio peripheral */
LL_PWR_SetRadioBusyTrigger(LL_PWR_RADIO_BUSY_TRIGGER_WU_IT);
-#endif /* CM0PLUS */
+#endif /* CORE_CM0PLUS */
}
/* Clear Pending Flag */
@@ -366,7 +366,7 @@ HAL_StatusTypeDef HAL_SUBGHZ_DeInit(SUBGHZ_HandleTypeDef *hsubghz)
HAL_SUBGHZ_MspDeInit(hsubghz);
#endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */
-#if defined(CM0PLUS)
+#if defined(CORE_CM0PLUS)
/* Disable EXTI 44 : Radio IRQ ITs for CPU2 */
LL_C2_EXTI_DisableIT_32_63(LL_EXTI_LINE_44);
@@ -378,7 +378,7 @@ HAL_StatusTypeDef HAL_SUBGHZ_DeInit(SUBGHZ_HandleTypeDef *hsubghz)
/* Disable wakeup signal of the Radio peripheral */
LL_PWR_SetRadioBusyTrigger(LL_PWR_RADIO_BUSY_TRIGGER_NONE);
-#endif /* CM0PLUS */
+#endif /* CORE_CM0PLUS */
/* Clear Pending Flag */
LL_PWR_ClearFlag_RFBUSY();
@@ -1241,7 +1241,8 @@ void HAL_SUBGHZ_IRQHandler(SUBGHZ_HandleTypeDef *hsubghz)
}
/* Packet received Interrupt */
- if (SUBGHZ_CHECK_IT_SOURCE(itsource, SUBGHZ_IT_RX_CPLT) != RESET)
+ if ((SUBGHZ_CHECK_IT_SOURCE(itsource, SUBGHZ_IT_RX_CPLT) != RESET) && \
+ (SUBGHZ_CHECK_IT_SOURCE(itsource, SUBGHZ_IT_CRC_ERROR) == RESET))
{
#if (USE_HAL_SUBGHZ_REGISTER_CALLBACKS == 1U)
hsubghz->RxCpltCallback(hsubghz);
diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_tim.c b/system/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_tim.c
index 50b146828e..cb2016bac8 100644
--- a/system/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_tim.c
+++ b/system/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_tim.c
@@ -3833,10 +3833,13 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
*/
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
{
+ uint32_t itsource = htim->Instance->DIER;
+ uint32_t itflag = htim->Instance->SR;
+
/* Capture compare 1 event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
+ if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1))
{
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
+ if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1))
{
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
@@ -3867,9 +3870,9 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
}
}
/* Capture compare 2 event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
+ if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2))
{
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
+ if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2))
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
@@ -3897,9 +3900,9 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
}
}
/* Capture compare 3 event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
+ if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3))
{
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
+ if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3))
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
@@ -3927,9 +3930,9 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
}
}
/* Capture compare 4 event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
+ if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4))
{
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
+ if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4))
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
@@ -3957,9 +3960,9 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
}
}
/* TIM Update event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
+ if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE))
{
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
+ if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE))
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
@@ -3970,9 +3973,9 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
}
}
/* TIM Break input event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
+ if ((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK))
{
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
+ if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
@@ -3983,9 +3986,9 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
}
}
/* TIM Break2 input event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET)
+ if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2))
{
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
+ if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
@@ -3996,9 +3999,9 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
}
}
/* TIM Trigger detection event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
+ if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER))
{
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
+ if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER))
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
@@ -4009,9 +4012,9 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
}
}
/* TIM commutation event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
+ if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM))
{
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET)
+ if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM))
{
__HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
@@ -6977,6 +6980,13 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure
/* Generate an update event to reload the Prescaler
and the repetition counter (only for advanced timer) value immediately */
TIMx->EGR = TIM_EGR_UG;
+
+ /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */
+ if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE))
+ {
+ /* Clear the update flag */
+ CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE);
+ }
}
/**
@@ -6991,11 +7001,12 @@ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Co
uint32_t tmpccer;
uint32_t tmpcr2;
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+
/* Disable the Channel 1: Reset the CC1E Bit */
TIMx->CCER &= ~TIM_CCER_CC1E;
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
@@ -7066,11 +7077,12 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
uint32_t tmpccer;
uint32_t tmpcr2;
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+
/* Disable the Channel 2: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC2E;
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
@@ -7142,11 +7154,12 @@ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Co
uint32_t tmpccer;
uint32_t tmpcr2;
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+
/* Disable the Channel 3: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC3E;
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
@@ -7216,11 +7229,12 @@ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Co
uint32_t tmpccer;
uint32_t tmpcr2;
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+
/* Disable the Channel 4: Reset the CC4E Bit */
TIMx->CCER &= ~TIM_CCER_CC4E;
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
@@ -7277,11 +7291,12 @@ static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
uint32_t tmpccer;
uint32_t tmpcr2;
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+
/* Disable the output: Reset the CCxE Bit */
TIMx->CCER &= ~TIM_CCER_CC5E;
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
/* Get the TIMx CCMR1 register value */
@@ -7330,11 +7345,12 @@ static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
uint32_t tmpccer;
uint32_t tmpcr2;
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+
/* Disable the output: Reset the CCxE Bit */
TIMx->CCER &= ~TIM_CCER_CC6E;
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
/* Get the TIMx CCMR1 register value */
@@ -7518,9 +7534,9 @@ void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_
uint32_t tmpccer;
/* Disable the Channel 1: Reset the CC1E Bit */
+ tmpccer = TIMx->CCER;
TIMx->CCER &= ~TIM_CCER_CC1E;
tmpccmr1 = TIMx->CCMR1;
- tmpccer = TIMx->CCER;
/* Select the Input */
if (IS_TIM_CC2_INSTANCE(TIMx) != RESET)
@@ -7608,9 +7624,9 @@ static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32
uint32_t tmpccer;
/* Disable the Channel 2: Reset the CC2E Bit */
+ tmpccer = TIMx->CCER;
TIMx->CCER &= ~TIM_CCER_CC2E;
tmpccmr1 = TIMx->CCMR1;
- tmpccer = TIMx->CCER;
/* Select the Input */
tmpccmr1 &= ~TIM_CCMR1_CC2S;
@@ -7647,9 +7663,9 @@ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity,
uint32_t tmpccer;
/* Disable the Channel 2: Reset the CC2E Bit */
+ tmpccer = TIMx->CCER;
TIMx->CCER &= ~TIM_CCER_CC2E;
tmpccmr1 = TIMx->CCMR1;
- tmpccer = TIMx->CCER;
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC2F;
@@ -7691,9 +7707,9 @@ static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32
uint32_t tmpccer;
/* Disable the Channel 3: Reset the CC3E Bit */
+ tmpccer = TIMx->CCER;
TIMx->CCER &= ~TIM_CCER_CC3E;
tmpccmr2 = TIMx->CCMR2;
- tmpccer = TIMx->CCER;
/* Select the Input */
tmpccmr2 &= ~TIM_CCMR2_CC3S;
@@ -7739,9 +7755,9 @@ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32
uint32_t tmpccer;
/* Disable the Channel 4: Reset the CC4E Bit */
+ tmpccer = TIMx->CCER;
TIMx->CCER &= ~TIM_CCER_CC4E;
tmpccmr2 = TIMx->CCMR2;
- tmpccer = TIMx->CCER;
/* Select the Input */
tmpccmr2 &= ~TIM_CCMR2_CC4S;
diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c b/system/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c
index de8f2477ca..53faed609d 100644
--- a/system/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c
+++ b/system/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c
@@ -348,15 +348,17 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
__HAL_UART_DISABLE(huart);
- /* Set the UART Communication parameters */
- if (UART_SetConfig(huart) == HAL_ERROR)
+ /* Perform advanced settings configuration */
+ /* For some items, configuration requires to be done prior TE and RE bits are set */
+ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
{
- return HAL_ERROR;
+ UART_AdvFeatureConfig(huart);
}
- if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+ /* Set the UART Communication parameters */
+ if (UART_SetConfig(huart) == HAL_ERROR)
{
- UART_AdvFeatureConfig(huart);
+ return HAL_ERROR;
}
/* In asynchronous mode, the following bits must be kept cleared:
@@ -413,15 +415,17 @@ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)
__HAL_UART_DISABLE(huart);
- /* Set the UART Communication parameters */
- if (UART_SetConfig(huart) == HAL_ERROR)
+ /* Perform advanced settings configuration */
+ /* For some items, configuration requires to be done prior TE and RE bits are set */
+ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
{
- return HAL_ERROR;
+ UART_AdvFeatureConfig(huart);
}
- if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+ /* Set the UART Communication parameters */
+ if (UART_SetConfig(huart) == HAL_ERROR)
{
- UART_AdvFeatureConfig(huart);
+ return HAL_ERROR;
}
/* In half-duplex mode, the following bits must be kept cleared:
@@ -499,15 +503,17 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe
__HAL_UART_DISABLE(huart);
- /* Set the UART Communication parameters */
- if (UART_SetConfig(huart) == HAL_ERROR)
+ /* Perform advanced settings configuration */
+ /* For some items, configuration requires to be done prior TE and RE bits are set */
+ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
{
- return HAL_ERROR;
+ UART_AdvFeatureConfig(huart);
}
- if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+ /* Set the UART Communication parameters */
+ if (UART_SetConfig(huart) == HAL_ERROR)
{
- UART_AdvFeatureConfig(huart);
+ return HAL_ERROR;
}
/* In LIN mode, the following bits must be kept cleared:
@@ -583,15 +589,17 @@ HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Add
__HAL_UART_DISABLE(huart);
- /* Set the UART Communication parameters */
- if (UART_SetConfig(huart) == HAL_ERROR)
+ /* Perform advanced settings configuration */
+ /* For some items, configuration requires to be done prior TE and RE bits are set */
+ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
{
- return HAL_ERROR;
+ UART_AdvFeatureConfig(huart);
}
- if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+ /* Set the UART Communication parameters */
+ if (UART_SetConfig(huart) == HAL_ERROR)
{
- UART_AdvFeatureConfig(huart);
+ return HAL_ERROR;
}
/* In multiprocessor mode, the following bits must be kept cleared:
@@ -963,10 +971,7 @@ HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pU
return HAL_ERROR;
}
- /* Process locked */
- __HAL_LOCK(huart);
-
- if (huart->gState == HAL_UART_STATE_READY)
+ if (huart->RxState == HAL_UART_STATE_READY)
{
huart->RxEventCallback = pCallback;
}
@@ -977,9 +982,6 @@ HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pU
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(huart);
-
return status;
}
@@ -993,10 +995,7 @@ HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart)
{
HAL_StatusTypeDef status = HAL_OK;
- /* Process locked */
- __HAL_LOCK(huart);
-
- if (huart->gState == HAL_UART_STATE_READY)
+ if (huart->RxState == HAL_UART_STATE_READY)
{
huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak UART Rx Event Callback */
}
@@ -1007,8 +1006,6 @@ HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart)
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(huart);
return status;
}
@@ -3333,6 +3330,13 @@ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
/* Check whether the set of advanced features to configure is properly set */
assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
+ /* if required, configure RX/TX pins swap */
+ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
+ {
+ assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
+ }
+
/* if required, configure TX pin active level inversion */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
{
@@ -3354,13 +3358,6 @@ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
}
- /* if required, configure RX/TX pins swap */
- if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
- {
- assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
- MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
- }
-
/* if required, configure RX overrun detection disabling */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
{
@@ -3480,7 +3477,7 @@ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_
return HAL_TIMEOUT;
}
- if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U)
+ if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC))
{
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
{
diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c b/system/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c
index 4e972f1f88..765cae6d1b 100644
--- a/system/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c
+++ b/system/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c
@@ -211,15 +211,17 @@ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity,
/* Disable the Peripheral */
__HAL_UART_DISABLE(huart);
- /* Set the UART Communication parameters */
- if (UART_SetConfig(huart) == HAL_ERROR)
+ /* Perform advanced settings configuration */
+ /* For some items, configuration requires to be done prior TE and RE bits are set */
+ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
{
- return HAL_ERROR;
+ UART_AdvFeatureConfig(huart);
}
- if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+ /* Set the UART Communication parameters */
+ if (UART_SetConfig(huart) == HAL_ERROR)
{
- UART_AdvFeatureConfig(huart);
+ return HAL_ERROR;
}
/* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */
diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_ll_adc.c b/system/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_ll_adc.c
index 1f7c69831a..dc802658da 100644
--- a/system/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_ll_adc.c
+++ b/system/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_ll_adc.c
@@ -402,7 +402,7 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
/* Reset register CFGR1 */
CLEAR_BIT(ADCx->CFGR1,
(ADC_CFGR1_AWD1CH | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL | ADC_CFGR1_DISCEN
- | ADC_CFGR1_AUTOFF | ADC_CFGR1_WAIT | ADC_CFGR1_CONT | ADC_CFGR1_OVRMOD
+ | ADC_CFGR1_CHSELRMOD | ADC_CFGR1_AUTOFF | ADC_CFGR1_WAIT | ADC_CFGR1_CONT | ADC_CFGR1_OVRMOD
| ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL | ADC_CFGR1_ALIGN | ADC_CFGR1_RES
| ADC_CFGR1_SCANDIR | ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN)
);
@@ -410,15 +410,6 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
/* Reset register SMPR */
CLEAR_BIT(ADCx->SMPR, ADC_SMPR_SMP1 | ADC_SMPR_SMP2 | ADC_SMPR_SMPSEL);
- /* Reset register AWD1TR */
- MODIFY_REG(ADCx->AWD1TR, ADC_AWD1TR_HT1 | ADC_AWD1TR_LT1, ADC_AWD1TR_HT1);
-
- /* Reset register AWD2TR */
- MODIFY_REG(ADCx->AWD2TR, ADC_AWD2TR_HT2 | ADC_AWD2TR_LT2, ADC_AWD2TR_HT2);
-
- /* Reset register AWD3TR */
- MODIFY_REG(ADCx->AWD3TR, ADC_AWD3TR_HT3 | ADC_AWD3TR_LT3, ADC_AWD3TR_HT3);
-
/* Reset register CHSELR */
CLEAR_BIT(ADCx->CHSELR,
(ADC_CHSELR_CHSEL17 | ADC_CHSELR_CHSEL16
@@ -428,6 +419,15 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
| ADC_CHSELR_CHSEL3 | ADC_CHSELR_CHSEL2 | ADC_CHSELR_CHSEL1 | ADC_CHSELR_CHSEL0)
);
+ /* Reset register AWD1TR */
+ MODIFY_REG(ADCx->AWD1TR, ADC_AWD1TR_HT1 | ADC_AWD1TR_LT1, ADC_AWD1TR_HT1);
+
+ /* Reset register AWD2TR */
+ MODIFY_REG(ADCx->AWD2TR, ADC_AWD2TR_HT2 | ADC_AWD2TR_LT2, ADC_AWD2TR_HT2);
+
+ /* Reset register AWD3TR */
+ MODIFY_REG(ADCx->AWD3TR, ADC_AWD3TR_HT3 | ADC_AWD3TR_LT3, ADC_AWD3TR_HT3);
+
/* Wait for ADC channel configuration ready */
timeout_cpu_cycles = ADC_TIMEOUT_CCRDY_CPU_CYCLES;
while (LL_ADC_IsActiveFlag_CCRDY(ADCx) == 0UL)
@@ -451,11 +451,10 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT);
/* Reset register CFGR2 */
+ /* Note: CFGR2 reset done at the end of de-initialization due to */
+ /* clock source reset */
/* Note: Update of ADC clock mode is conditioned to ADC state disabled: */
/* already done above. */
- /* Note: ADC clock reset at the end of de-initialization because select */
- /* asynchronous clock source, corresponding to no clock by default */
- /* on STM32WL. Refer to function "LL_RCC_SetADCClockSource()". */
CLEAR_BIT(ADCx->CFGR2,
(ADC_CFGR2_CKMODE
| ADC_CFGR2_TOVS | ADC_CFGR2_OVSS | ADC_CFGR2_OVSR
diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_ll_gpio.c b/system/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_ll_gpio.c
index efb04e80a1..d179f7aee9 100644
--- a/system/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_ll_gpio.c
+++ b/system/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_ll_gpio.c
@@ -174,8 +174,6 @@ ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStru
if (currentpin != 0x00u)
{
- /* Pin Mode configuration */
- LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode);
if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE))
{
diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_ll_tim.c b/system/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_ll_tim.c
index de9c89fe70..0611041ed3 100644
--- a/system/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_ll_tim.c
+++ b/system/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_ll_tim.c
@@ -706,7 +706,6 @@ ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *T
MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
- MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput);
assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter));
assert_param(IS_LL_TIM_BREAK_AFMODE(TIM_BDTRInitStruct->BreakAFMode));
MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter);
diff --git a/system/Drivers/STM32YYxx_HAL_Driver_version.md b/system/Drivers/STM32YYxx_HAL_Driver_version.md
index 6b5af8d613..463f68e0c2 100644
--- a/system/Drivers/STM32YYxx_HAL_Driver_version.md
+++ b/system/Drivers/STM32YYxx_HAL_Driver_version.md
@@ -20,7 +20,7 @@
* STM32U5: 1.6.1
* STM32WB: 1.14.4
* STM32WBA: 1.5.0
- * STM32WL: 1.3.0
+ * STM32WL: 1.3.1
Release notes of each STM32YYxx HAL Drivers available here:
