diff --git a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g030xx.h b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g030xx.h
index af20715c2c..2d51ab5392 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g030xx.h
+++ b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g030xx.h
@@ -4045,6 +4045,12 @@ typedef struct
 #define RCC_CFGR_SWS_1                 (0x2UL << RCC_CFGR_SWS_Pos)             /*!< 0x00000010 */
 #define RCC_CFGR_SWS_2                 (0x4UL << RCC_CFGR_SWS_Pos)             /*!< 0x00000020 */
 
+#define RCC_CFGR_SWS_HSISYS            (0x00000000UL)                          /*!< HSISYS used as system clock */
+#define RCC_CFGR_SWS_HSE               (0x00000008UL)                          /*!< HSE used as system clock */
+#define RCC_CFGR_SWS_PLLRCLK           (0x00000010UL)                          /*!< PLLRCLK used as system clock */
+#define RCC_CFGR_SWS_LSI               (0x00000018UL)                          /*!< LSI used as system clock */
+#define RCC_CFGR_SWS_LSE               (0x00000100UL)                          /*!< LSE used as system clock */
+
 /*!< HPRE configuration */
 #define RCC_CFGR_HPRE_Pos              (8U)
 #define RCC_CFGR_HPRE_Msk              (0xFUL << RCC_CFGR_HPRE_Pos)            /*!< 0x00000F00 */
diff --git a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g031xx.h b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g031xx.h
index 62f929b4ba..941f888120 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g031xx.h
+++ b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g031xx.h
@@ -4225,6 +4225,12 @@ typedef struct
 #define RCC_CFGR_SWS_1                 (0x2UL << RCC_CFGR_SWS_Pos)             /*!< 0x00000010 */
 #define RCC_CFGR_SWS_2                 (0x4UL << RCC_CFGR_SWS_Pos)             /*!< 0x00000020 */
 
+#define RCC_CFGR_SWS_HSISYS            (0x00000000UL)                          /*!< HSISYS used as system clock */
+#define RCC_CFGR_SWS_HSE               (0x00000008UL)                          /*!< HSE used as system clock */
+#define RCC_CFGR_SWS_PLLRCLK           (0x00000010UL)                          /*!< PLLRCLK used as system clock */
+#define RCC_CFGR_SWS_LSI               (0x00000018UL)                          /*!< LSI used as system clock */
+#define RCC_CFGR_SWS_LSE               (0x00000100UL)                          /*!< LSE used as system clock */
+
 /*!< HPRE configuration */
 #define RCC_CFGR_HPRE_Pos              (8U)
 #define RCC_CFGR_HPRE_Msk              (0xFUL << RCC_CFGR_HPRE_Pos)            /*!< 0x00000F00 */
diff --git a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g041xx.h b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g041xx.h
index d8ede70694..23ce34d604 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g041xx.h
+++ b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g041xx.h
@@ -4461,6 +4461,12 @@ typedef struct
 #define RCC_CFGR_SWS_1                 (0x2UL << RCC_CFGR_SWS_Pos)             /*!< 0x00000010 */
 #define RCC_CFGR_SWS_2                 (0x4UL << RCC_CFGR_SWS_Pos)             /*!< 0x00000020 */
 
+#define RCC_CFGR_SWS_HSISYS            (0x00000000UL)                          /*!< HSISYS used as system clock */
+#define RCC_CFGR_SWS_HSE               (0x00000008UL)                          /*!< HSE used as system clock */
+#define RCC_CFGR_SWS_PLLRCLK           (0x00000010UL)                          /*!< PLLRCLK used as system clock */
+#define RCC_CFGR_SWS_LSI               (0x00000018UL)                          /*!< LSI used as system clock */
+#define RCC_CFGR_SWS_LSE               (0x00000100UL)                          /*!< LSE used as system clock */
+
 /*!< HPRE configuration */
 #define RCC_CFGR_HPRE_Pos              (8U)
 #define RCC_CFGR_HPRE_Msk              (0xFUL << RCC_CFGR_HPRE_Pos)            /*!< 0x00000F00 */
diff --git a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g050xx.h b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g050xx.h
index 53490b7e6e..20130942a4 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g050xx.h
+++ b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g050xx.h
@@ -4064,6 +4064,12 @@ typedef struct
 #define RCC_CFGR_SWS_1                 (0x2UL << RCC_CFGR_SWS_Pos)             /*!< 0x00000010 */
 #define RCC_CFGR_SWS_2                 (0x4UL << RCC_CFGR_SWS_Pos)             /*!< 0x00000020 */
 
+#define RCC_CFGR_SWS_HSISYS            (0x00000000UL)                          /*!< HSISYS used as system clock */
+#define RCC_CFGR_SWS_HSE               (0x00000008UL)                          /*!< HSE used as system clock */
+#define RCC_CFGR_SWS_PLLRCLK           (0x00000010UL)                          /*!< PLLRCLK used as system clock */
+#define RCC_CFGR_SWS_LSI               (0x00000018UL)                          /*!< LSI used as system clock */
+#define RCC_CFGR_SWS_LSE               (0x00000100UL)                          /*!< LSE used as system clock */
+
 /*!< HPRE configuration */
 #define RCC_CFGR_HPRE_Pos              (8U)
 #define RCC_CFGR_HPRE_Msk              (0xFUL << RCC_CFGR_HPRE_Pos)            /*!< 0x00000F00 */
diff --git a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g051xx.h b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g051xx.h
index dd3e7c999e..dbf1d633fc 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g051xx.h
+++ b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g051xx.h
@@ -4561,6 +4561,12 @@ typedef struct
 #define RCC_CFGR_SWS_1                 (0x2UL << RCC_CFGR_SWS_Pos)             /*!< 0x00000010 */
 #define RCC_CFGR_SWS_2                 (0x4UL << RCC_CFGR_SWS_Pos)             /*!< 0x00000020 */
 
+#define RCC_CFGR_SWS_HSISYS            (0x00000000UL)                          /*!< HSISYS used as system clock */
+#define RCC_CFGR_SWS_HSE               (0x00000008UL)                          /*!< HSE used as system clock */
+#define RCC_CFGR_SWS_PLLRCLK           (0x00000010UL)                          /*!< PLLRCLK used as system clock */
+#define RCC_CFGR_SWS_LSI               (0x00000018UL)                          /*!< LSI used as system clock */
+#define RCC_CFGR_SWS_LSE               (0x00000100UL)                          /*!< LSE used as system clock */
+
 /*!< HPRE configuration */
 #define RCC_CFGR_HPRE_Pos              (8U)
 #define RCC_CFGR_HPRE_Msk              (0xFUL << RCC_CFGR_HPRE_Pos)            /*!< 0x00000F00 */
diff --git a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g061xx.h b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g061xx.h
index 4738a947a9..6e7973946a 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g061xx.h
+++ b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g061xx.h
@@ -4797,6 +4797,12 @@ typedef struct
 #define RCC_CFGR_SWS_1                 (0x2UL << RCC_CFGR_SWS_Pos)             /*!< 0x00000010 */
 #define RCC_CFGR_SWS_2                 (0x4UL << RCC_CFGR_SWS_Pos)             /*!< 0x00000020 */
 
+#define RCC_CFGR_SWS_HSISYS            (0x00000000UL)                          /*!< HSISYS used as system clock */
+#define RCC_CFGR_SWS_HSE               (0x00000008UL)                          /*!< HSE used as system clock */
+#define RCC_CFGR_SWS_PLLRCLK           (0x00000010UL)                          /*!< PLLRCLK used as system clock */
+#define RCC_CFGR_SWS_LSI               (0x00000018UL)                          /*!< LSI used as system clock */
+#define RCC_CFGR_SWS_LSE               (0x00000100UL)                          /*!< LSE used as system clock */
+
 /*!< HPRE configuration */
 #define RCC_CFGR_HPRE_Pos              (8U)
 #define RCC_CFGR_HPRE_Msk              (0xFUL << RCC_CFGR_HPRE_Pos)            /*!< 0x00000F00 */
diff --git a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g070xx.h b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g070xx.h
index 702c42af7e..2d79b255a8 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g070xx.h
+++ b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g070xx.h
@@ -4193,6 +4193,12 @@ typedef struct
 #define RCC_CFGR_SWS_1                 (0x2UL << RCC_CFGR_SWS_Pos)             /*!< 0x00000010 */
 #define RCC_CFGR_SWS_2                 (0x4UL << RCC_CFGR_SWS_Pos)             /*!< 0x00000020 */
 
+#define RCC_CFGR_SWS_HSISYS            (0x00000000UL)                          /*!< HSISYS used as system clock */
+#define RCC_CFGR_SWS_HSE               (0x00000008UL)                          /*!< HSE used as system clock */
+#define RCC_CFGR_SWS_PLLRCLK           (0x00000010UL)                          /*!< PLLRCLK used as system clock */
+#define RCC_CFGR_SWS_LSI               (0x00000018UL)                          /*!< LSI used as system clock */
+#define RCC_CFGR_SWS_LSE               (0x00000100UL)                          /*!< LSE used as system clock */
+
 /*!< HPRE configuration */
 #define RCC_CFGR_HPRE_Pos              (8U)
 #define RCC_CFGR_HPRE_Msk              (0xFUL << RCC_CFGR_HPRE_Pos)            /*!< 0x00000F00 */
diff --git a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g071xx.h b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g071xx.h
index b8b11b384b..1ba718629d 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g071xx.h
+++ b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g071xx.h
@@ -4896,6 +4896,12 @@ typedef struct
 #define RCC_CFGR_SWS_1                 (0x2UL << RCC_CFGR_SWS_Pos)             /*!< 0x00000010 */
 #define RCC_CFGR_SWS_2                 (0x4UL << RCC_CFGR_SWS_Pos)             /*!< 0x00000020 */
 
+#define RCC_CFGR_SWS_HSISYS            (0x00000000UL)                          /*!< HSISYS used as system clock */
+#define RCC_CFGR_SWS_HSE               (0x00000008UL)                          /*!< HSE used as system clock */
+#define RCC_CFGR_SWS_PLLRCLK           (0x00000010UL)                          /*!< PLLRCLK used as system clock */
+#define RCC_CFGR_SWS_LSI               (0x00000018UL)                          /*!< LSI used as system clock */
+#define RCC_CFGR_SWS_LSE               (0x00000100UL)                          /*!< LSE used as system clock */
+
 /*!< HPRE configuration */
 #define RCC_CFGR_HPRE_Pos              (8U)
 #define RCC_CFGR_HPRE_Msk              (0xFUL << RCC_CFGR_HPRE_Pos)            /*!< 0x00000F00 */
diff --git a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g081xx.h b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g081xx.h
index d6ebdd4bea..a552e1bc2a 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g081xx.h
+++ b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g081xx.h
@@ -5132,6 +5132,12 @@ typedef struct
 #define RCC_CFGR_SWS_1                 (0x2UL << RCC_CFGR_SWS_Pos)             /*!< 0x00000010 */
 #define RCC_CFGR_SWS_2                 (0x4UL << RCC_CFGR_SWS_Pos)             /*!< 0x00000020 */
 
+#define RCC_CFGR_SWS_HSISYS            (0x00000000UL)                          /*!< HSISYS used as system clock */
+#define RCC_CFGR_SWS_HSE               (0x00000008UL)                          /*!< HSE used as system clock */
+#define RCC_CFGR_SWS_PLLRCLK           (0x00000010UL)                          /*!< PLLRCLK used as system clock */
+#define RCC_CFGR_SWS_LSI               (0x00000018UL)                          /*!< LSI used as system clock */
+#define RCC_CFGR_SWS_LSE               (0x00000100UL)                          /*!< LSE used as system clock */
+
 /*!< HPRE configuration */
 #define RCC_CFGR_HPRE_Pos              (8U)
 #define RCC_CFGR_HPRE_Msk              (0xFUL << RCC_CFGR_HPRE_Pos)            /*!< 0x00000F00 */
diff --git a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0b0xx.h b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0b0xx.h
index 6c54693572..c693338ed9 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0b0xx.h
+++ b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0b0xx.h
@@ -325,7 +325,7 @@ typedef struct
 typedef struct
 {
   __IO uint32_t CR1;          /*!< PWR Power Control Register 1,                     Address offset: 0x00 */
-       uint32_t RESERVED0;    /*!< Reserved,                                         Address offset: 0x04 */
+  __IO uint32_t CR2;          /*!< PWR Power Control Register 2,                     Address offset: 0x04 */
   __IO uint32_t CR3;          /*!< PWR Power Control Register 3,                     Address offset: 0x08 */
   __IO uint32_t CR4;          /*!< PWR Power Control Register 4,                     Address offset: 0x0C */
   __IO uint32_t SR1;          /*!< PWR Power Status Register 1,                      Address offset: 0x10 */
@@ -4363,6 +4363,9 @@ typedef struct
 #define PWR_CR1_LPR_Msk           (0x1UL << PWR_CR1_LPR_Pos)                   /*!< 0x00004000 */
 #define PWR_CR1_LPR               PWR_CR1_LPR_Msk                              /*!< Regulator Low-Power Run mode */
 
+#define PWR_CR2_USV_Pos           (10U)
+#define PWR_CR2_USV_Msk           (0x1UL << PWR_CR2_USV_Pos)                   /*!< 0x00000400 */
+#define PWR_CR2_USV               PWR_CR2_USV_Msk                              /*!< VDD USB Supply Valid */
 
 /********************  Bit definition for PWR_CR3 register  ********************/
 #define PWR_CR3_EWUP_Pos          (0U)
@@ -5162,6 +5165,12 @@ typedef struct
 #define RCC_CFGR_SWS_1                 (0x2UL << RCC_CFGR_SWS_Pos)             /*!< 0x00000010 */
 #define RCC_CFGR_SWS_2                 (0x4UL << RCC_CFGR_SWS_Pos)             /*!< 0x00000020 */
 
+#define RCC_CFGR_SWS_HSISYS            (0x00000000UL)                          /*!< HSISYS used as system clock */
+#define RCC_CFGR_SWS_HSE               (0x00000008UL)                          /*!< HSE used as system clock */
+#define RCC_CFGR_SWS_PLLRCLK           (0x00000010UL)                          /*!< PLLRCLK used as system clock */
+#define RCC_CFGR_SWS_LSI               (0x00000018UL)                          /*!< LSI used as system clock */
+#define RCC_CFGR_SWS_LSE               (0x00000100UL)                          /*!< LSE used as system clock */
+
 /*!< HPRE configuration */
 #define RCC_CFGR_HPRE_Pos              (8U)
 #define RCC_CFGR_HPRE_Msk              (0xFUL << RCC_CFGR_HPRE_Pos)            /*!< 0x00000F00 */
diff --git a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0b1xx.h b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0b1xx.h
index 36e2cba5d2..b97b0091a8 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0b1xx.h
+++ b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0b1xx.h
@@ -6146,6 +6146,12 @@ typedef struct
 #define RCC_CFGR_SWS_1                 (0x2UL << RCC_CFGR_SWS_Pos)             /*!< 0x00000010 */
 #define RCC_CFGR_SWS_2                 (0x4UL << RCC_CFGR_SWS_Pos)             /*!< 0x00000020 */
 
+#define RCC_CFGR_SWS_HSISYS            (0x00000000UL)                          /*!< HSISYS used as system clock */
+#define RCC_CFGR_SWS_HSE               (0x00000008UL)                          /*!< HSE used as system clock */
+#define RCC_CFGR_SWS_PLLRCLK           (0x00000010UL)                          /*!< PLLRCLK used as system clock */
+#define RCC_CFGR_SWS_LSI               (0x00000018UL)                          /*!< LSI used as system clock */
+#define RCC_CFGR_SWS_LSE               (0x00000100UL)                          /*!< LSE used as system clock */
+
 /*!< HPRE configuration */
 #define RCC_CFGR_HPRE_Pos              (8U)
 #define RCC_CFGR_HPRE_Msk              (0xFUL << RCC_CFGR_HPRE_Pos)            /*!< 0x00000F00 */
diff --git a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0c1xx.h b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0c1xx.h
index 8ebf0a7b55..2c36f00615 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0c1xx.h
+++ b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0c1xx.h
@@ -6382,6 +6382,12 @@ typedef struct
 #define RCC_CFGR_SWS_1                 (0x2UL << RCC_CFGR_SWS_Pos)             /*!< 0x00000010 */
 #define RCC_CFGR_SWS_2                 (0x4UL << RCC_CFGR_SWS_Pos)             /*!< 0x00000020 */
 
+#define RCC_CFGR_SWS_HSISYS            (0x00000000UL)                          /*!< HSISYS used as system clock */
+#define RCC_CFGR_SWS_HSE               (0x00000008UL)                          /*!< HSE used as system clock */
+#define RCC_CFGR_SWS_PLLRCLK           (0x00000010UL)                          /*!< PLLRCLK used as system clock */
+#define RCC_CFGR_SWS_LSI               (0x00000018UL)                          /*!< LSI used as system clock */
+#define RCC_CFGR_SWS_LSE               (0x00000100UL)                          /*!< LSE used as system clock */
+
 /*!< HPRE configuration */
 #define RCC_CFGR_HPRE_Pos              (8U)
 #define RCC_CFGR_HPRE_Msk              (0xFUL << RCC_CFGR_HPRE_Pos)            /*!< 0x00000F00 */
diff --git a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h
index 1749bdf86e..b10d5cfe45 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h
+++ b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h
@@ -90,7 +90,7 @@
   */
 #define __STM32G0_CMSIS_VERSION_MAIN   (0x01U) /*!< [31:24] main version */
 #define __STM32G0_CMSIS_VERSION_SUB1   (0x04U) /*!< [23:16] sub1 version */
-#define __STM32G0_CMSIS_VERSION_SUB2   (0x03U) /*!< [15:8]  sub2 version */
+#define __STM32G0_CMSIS_VERSION_SUB2   (0x04U) /*!< [15:8]  sub2 version */
 #define __STM32G0_CMSIS_VERSION_RC     (0x00U) /*!< [7:0]  release candidate */
 #define __STM32G0_CMSIS_VERSION        ((__STM32G0_CMSIS_VERSION_MAIN << 24)\
                                        |(__STM32G0_CMSIS_VERSION_SUB1 << 16)\
diff --git a/system/Drivers/CMSIS/Device/ST/STM32G0xx/License.md b/system/Drivers/CMSIS/Device/ST/STM32G0xx/LICENSE.md
similarity index 100%
rename from system/Drivers/CMSIS/Device/ST/STM32G0xx/License.md
rename to system/Drivers/CMSIS/Device/ST/STM32G0xx/LICENSE.md
diff --git a/system/Drivers/CMSIS/Device/ST/STM32G0xx/README.md b/system/Drivers/CMSIS/Device/ST/STM32G0xx/README.md
index 1455645d59..6dac671722 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32G0xx/README.md
+++ b/system/Drivers/CMSIS/Device/ST/STM32G0xx/README.md
@@ -1,19 +1,21 @@
 # STM32CubeG0 CMSIS Device MCU Component
 
+![latest tag](https://img.shields.io/github/v/tag/STMicroelectronics/cmsis_device_g0.svg?color=brightgreen)
+
 ## Overview
 
 **STM32Cube** is an STMicroelectronics original initiative to ease the developers life by reducing efforts, time and cost.
 
-**STM32Cube** covers the overall STM32 products portfolio. It includes a comprehensive embedded software platform, delivered for each STM32 series.
-   * The CMSIS modules (core and device) corresponding to the ARM(tm) core implemented in this STM32 product
-   * The STM32 HAL-LL drivers : an abstraction drivers layer, the API ensuring maximized portability across the STM32 portfolio
-   * The BSP Drivers of each evaluation or demonstration board provided by this STM32 series
-   * A consistent set of middlewares components such as RTOS, USB, FatFS, Graphics, STM32_TouchSensing_Library ...
-   * A full set of software projects (basic examples, applications or demonstrations) for each board provided by this STM32 series
+**STM32Cube** covers the overall STM32 products portfolio. It includes a comprehensive embedded software platform delivered for each STM32 series.
+   * The CMSIS modules (core and device) corresponding to the ARM(tm) core implemented in this STM32 product.
+   * The STM32 HAL-LL drivers, an abstraction layer offering a set of APIs ensuring maximized portability across the STM32 portfolio.
+   * The BSP drivers of each evaluation, demonstration or nucleo board provided for this STM32 series.
+   * A consistent set of middleware libraries such as RTOS, USB, FatFS, graphics, touch sensing library...
+   * A full set of software projects (basic examples, applications, and demonstrations) for each board provided for this STM32 series.
 
-Two models of publication are proposed for the STM32Cube embedded software :
-   * The monolithic **MCU Package** : all STM32Cube software modules of one STM32 series are present (Drivers, Middlewares, Projects, Utilities) in the repo (usual name **STM32Cubexx**, xx corresponding to the STM32 series)
-   * The **MCU component** : progressively from November 2019, each STM32Cube software module being part of the STM32Cube MCU Package, will be delivered as an individual repo, allowing the user to select and get only the required software functions.
+Two models of publication are proposed for the STM32Cube embedded software:
+   * The monolithic **MCU Package**: all STM32Cube software modules of one STM32 series are present (Drivers, Middleware, Projects, Utilities) in the repository (usual name **STM32Cubexx**, xx corresponding to the STM32 series).
+   * The **MCU component**: each STM32Cube software module being part of the STM32Cube MCU Package, is delivered as an individual repository, allowing the user to select and get only the required software functions.
 
 ## Description
 
@@ -30,6 +32,5 @@ It is **crucial** that you use a consistent set of versions for the CMSIS Core -
 The full **STM32CubeG0** MCU package is available [here](https://github.com/STMicroelectronics/STM32CubeG0).
 
 ## Troubleshooting
-If you have any issue with the **Software content** of this repo, you can [file an issue on Github](https://github.com/STMicroelectronics/cmsis_device_g0/issues/new).
 
-For any other question related to the product, the tools, the environment, you can submit a topic on the [ST Community/STM32 MCUs forum](https://community.st.com/s/group/0F90X000000AXsASAW/stm32-mcus).
\ No newline at end of file
+Please refer to the [CONTRIBUTING.md](CONTRIBUTING.md) guide.
diff --git a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Release_Notes.html b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Release_Notes.html
index 35c0be0a69..f27e809d6f 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Release_Notes.html
+++ b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Release_Notes.html
@@ -45,10 +45,53 @@ <h1 id="purpose">Purpose</h1>
 <div class="col-sm-12 col-lg-8">
 <h1 id="update-history">Update History</h1>
 <div class="collapse">
-<input type="checkbox" id="collapse-section7" checked aria-hidden="true"> <label for="collapse-section7" area-hidden="true">V1.4.2 / 01-April-2022 </label>
+<input type="checkbox" id="collapse-section9" checked aria-hidden="true"> <label for="collapse-section9" area-hidden="true">V1.4.4 / 15-December-2023 </label>
 <div>
 <h2 id="main-changes">Main Changes</h2>
 <ul>
+<li>Update USB RXBD count mask.</li>
+<li>Add RCC_CFGR_SWS_HSE, HSI, PLL, LSI, LSE system clock definitions.</li>
+<li>Update to support USB supply enable feature for STM32G0B0 devices.</li>
+<li>Fix the location of .size directive in STM32CubeIDE’s startup code to allow proper size information of vector table.</li>
+</ul>
+<h2 id="contents">Contents</h2>
+<ul>
+<li>CMSIS devices files for stm32g0B0xx, stm32g0B1xx, stm32g0C1xx devices.</li>
+<li>CMSIS devices files for stm32g050xx, stm32g051xx, stm32g061xx devices.</li>
+<li>CMSIS devices files for stm32g030xx, stm32g031xx, stm32g041xx devices.</li>
+<li>CMSIS devices files for stm32g070xx, stm32g071xx, stm32g081xx devices.</li>
+</ul>
+<h2 id="known-limitations">Known Limitations</h2>
+<ul>
+<li>None</li>
+</ul>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section8" aria-hidden="true"> <label for="collapse-section8" area-hidden="true">V1.4.3 / 10-June-2023 </label>
+<div>
+<h2 id="main-changes-1">Main Changes</h2>
+<ul>
+<li>README.md update: Remove compatibility table from “Compatibility information” section.</li>
+</ul>
+<h2 id="contents-1">Contents</h2>
+<ul>
+<li>CMSIS devices files for stm32g0B0xx, stm32g0B1xx, stm32g0C1xx devices.</li>
+<li>CMSIS devices files for stm32g050xx, stm32g051xx, stm32g061xx devices.</li>
+<li>CMSIS devices files for stm32g030xx, stm32g031xx, stm32g041xx devices.</li>
+<li>CMSIS devices files for stm32g070xx, stm32g071xx, stm32g081xx devices.</li>
+</ul>
+<h2 id="known-limitations-1">Known Limitations</h2>
+<ul>
+<li>None</li>
+</ul>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section7" aria-hidden="true"> <label for="collapse-section7" area-hidden="true">V1.4.2 / 01-April-2022 </label>
+<div>
+<h2 id="main-changes-2">Main Changes</h2>
+<ul>
 <li>Rename ADC TRx registers AWDxTR to be compliant with the reference manual.</li>
 <li>Fix Doxygen grouping issues.</li>
 <li>Update IRQ handler enumeration structure to be aligned with template CMSIS device.h file defined by ARM.
@@ -60,14 +103,14 @@ <h2 id="main-changes">Main Changes</h2>
 <li>#define SVC_IRQn SVCall_IRQn</li>
 </ul></li>
 </ul>
-<h2 id="contents">Contents</h2>
+<h2 id="contents-2">Contents</h2>
 <ul>
 <li>CMSIS devices files for stm32g0B0xx, stm32g0B1xx, stm32g0C1xx devices.</li>
 <li>CMSIS devices files for stm32g050xx, stm32g051xx, stm32g061xx devices.</li>
 <li>CMSIS devices files for stm32g030xx, stm32g031xx, stm32g041xx devices.</li>
 <li>CMSIS devices files for stm32g070xx, stm32g071xx, stm32g081xx devices.</li>
 </ul>
-<h2 id="known-limitations">Known Limitations</h2>
+<h2 id="known-limitations-2">Known Limitations</h2>
 <ul>
 <li>None</li>
 </ul>
@@ -76,7 +119,7 @@ <h2 id="known-limitations">Known Limitations</h2>
 <div class="collapse">
 <input type="checkbox" id="collapse-section6"  aria-hidden="true"> <label for="collapse-section6" area-hidden="true">V1.4.1 / 17-June-2021 </label>
 <div>
-<h2 id="main-changes-1">Main Changes</h2>
+<h2 id="main-changes-3">Main Changes</h2>
 <ul>
 <li>Update to remove wrong bits defined for DMAMUX Req ID.</li>
 <li>Protect Vector table modification following SRAM or FLASH preprocessor directive by a generic preprocessor directive : USER_VECT_TAB_ADDRESS.</li>
@@ -89,14 +132,14 @@ <h2 id="main-changes-1">Main Changes</h2>
 <li>Update header files with new license format</li>
 </ul></li>
 </ul>
-<h2 id="contents-1">Contents</h2>
+<h2 id="contents-3">Contents</h2>
 <ul>
 <li>CMSIS devices files for stm32g0B0xx, stm32g0B1xx, stm32g0C1xx devices.</li>
 <li>CMSIS devices files for stm32g050xx, stm32g051xx, stm32g061xx devices.</li>
 <li>CMSIS devices files for stm32g030xx, stm32g031xx, stm32g041xx devices.</li>
 <li>CMSIS devices files for stm32g070xx, stm32g071xx, stm32g081xx devices.</li>
 </ul>
-<h2 id="known-limitations-1">Known Limitations</h2>
+<h2 id="known-limitations-3">Known Limitations</h2>
 <ul>
 <li>None</li>
 </ul>
@@ -105,7 +148,7 @@ <h2 id="known-limitations-1">Known Limitations</h2>
 <div class="collapse">
 <input type="checkbox" id="collapse-section5"  aria-hidden="true"> <label for="collapse-section5" area-hidden="true">V1.4.0 / 29-October-2020 </label>
 <div>
-<h2 id="main-changes-2">Main Changes</h2>
+<h2 id="main-changes-4">Main Changes</h2>
 <h3 id="maintenance-release-and-product-update">Maintenance release and Product Update</h3>
 <p>Official release for STM32G0xx CMSIS introducing <strong>stm32g0b0xx, stm32g0b1xx, stm32g0c1xx devices</strong> and <strong>stm32g050xx, stm32g051xx, stm32g061xx devices.</strong></p>
 <p>Maintenance release for STM32G0xx CMSIS supporting stm32g030xx, stm32g031xx, stm32g041xx, stm32g070xx, stm32g071xx, stm32g081xx devices.</p>
@@ -186,19 +229,19 @@ <h3 id="maintenance-release-and-product-update">Maintenance release and Product
 </tr>
 </tbody>
 </table>
-<h2 id="contents-2">Contents</h2>
+<h2 id="contents-4">Contents</h2>
 <p>-<strong>CMSIS devices files for stm32g0B0xx, stm32g0B1xx, stm32g0C1xx devices.</strong></p>
 <p>-<strong>CMSIS devices files for stm32g050xx, stm32g051xx, stm32g061xx devices.</strong></p>
 <p>-CMSIS devices files for stm32g030xx, stm32g031xx, stm32g041xx devices.</p>
 <p>-CMSIS devices files for stm32g070xx, stm32g071xx, stm32g081xx devices.</p>
-<h2 id="known-limitations-2">Known Limitations</h2>
+<h2 id="known-limitations-4">Known Limitations</h2>
 <p>None</p>
 </div>
 </div>
 <div class="collapse">
 <input type="checkbox" id="collapse-section4" aria-hidden="true"> <label for="collapse-section4" aria-hidden="true">V1.3.0 / 25-June-2019 </label>
 <div>
-<h2 id="main-changes-3">Main Changes</h2>
+<h2 id="main-changes-5">Main Changes</h2>
 <h3 id="maintenance-release">Maintenance release</h3>
 <p>Maintenance release for STM32G0xx CMSIS supporting stm32g030xx, stm32g031xx, stm32g041xx, stm32g070xx, stm32g071xx, stm32g081xx devices.</p>
 <p><strong>Fixed bugs list</strong></p>
@@ -214,10 +257,10 @@ <h3 id="maintenance-release">Maintenance release</h3>
 </tr>
 </tbody>
 </table>
-<h2 id="contents-3">Contents</h2>
+<h2 id="contents-5">Contents</h2>
 <p>CMSIS devices files for stm32g030xx, stm32g031xx, stm32g041xx devices.</p>
 <p>CMSIS devices files for stm32g070xx, stm32g071xx, stm32g081xx devices.</p>
-<h2 id="known-limitations-3">Known Limitations</h2>
+<h2 id="known-limitations-5">Known Limitations</h2>
 <p><strong>Requirements not met or planned in a forthcoming release</strong></p>
 <table>
 <thead>
@@ -247,7 +290,7 @@ <h2 id="supported-devices-and-boards">Supported Devices and boards</h2>
 <div class="collapse">
 <input type="checkbox" id="collapse-section3" aria-hidden="true"> <label for="collapse-section3" aria-hidden="true">V1.2.0 / 05-April-2019 </label>
 <div>
-<h2 id="main-changes-4">Main Changes</h2>
+<h2 id="main-changes-6">Main Changes</h2>
 <h3 id="maintenance-release-and-product-update-1">Maintenance release and Product Update</h3>
 <p>First release for STM32G0xx CMSIS introducing <strong>stm32g030xx, stm32g031xx, stm32g041xx</strong> devices.</p>
 <p><strong>Additional features</strong></p>
@@ -279,10 +322,10 @@ <h3 id="maintenance-release-and-product-update-1">Maintenance release and Produc
 </tr>
 </tbody>
 </table>
-<h2 id="contents-4">Contents</h2>
+<h2 id="contents-6">Contents</h2>
 <p>CMSIS devices files for stm32g030xx, stm32g031xx, stm32g041xx devices.</p>
 <p>CMSIS devices files for stm32g070xx, stm32g071xx, stm32g081xx devices.</p>
-<h2 id="known-limitations-4">Known Limitations</h2>
+<h2 id="known-limitations-6">Known Limitations</h2>
 <p><strong>Requirements not met or planned in a forthcoming release</strong></p>
 <table>
 <thead>
@@ -315,7 +358,7 @@ <h2 id="supported-devices-and-boards-1">Supported Devices and boards</h2>
 <div class="collapse">
 <input type="checkbox" id="collapse-section2" aria-hidden="true"> <label for="collapse-section2" aria-hidden="true">V1.1.0 / 06-February-2019 </label>
 <div>
-<h2 id="main-changes-5">Main Changes</h2>
+<h2 id="main-changes-7">Main Changes</h2>
 <h3 id="maintenance-release-1">Maintenance release</h3>
 <p>Maintenance release for <strong>STM32G0xx</strong> devices (stm32g070xx, stm32g071xx, stm32g081xx devices)</p>
 <p><strong>Fixed bugs list</strong></p>
@@ -340,17 +383,17 @@ <h3 id="maintenance-release-1">Maintenance release</h3>
 </tr>
 </tbody>
 </table>
-<h2 id="contents-5">Contents</h2>
+<h2 id="contents-7">Contents</h2>
 <p>CMSIS devices files for stm32g070xx, stm32g071xx, stm32g081xx devices.</p>
 </div>
 </div>
 <div class="collapse">
 <input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" aria-hidden="true"> V1.0.0 / 26-October-2018 </label>
 <div>
-<h2 id="main-changes-6">Main Changes</h2>
+<h2 id="main-changes-8">Main Changes</h2>
 <h3 id="first-release">First release</h3>
 <p>First official release for <strong>STM32G0xx</strong> devices</p>
-<h2 id="contents-6">Contents</h2>
+<h2 id="contents-8">Contents</h2>
 <ul>
 <li>CMSIS devices files for STM32G070xx, STM32G071xx and STM32G081xx</li>
 </ul>
diff --git a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g030xx.s b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g030xx.s
index fd82f1008b..a168383fdd 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g030xx.s
+++ b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g030xx.s
@@ -127,7 +127,6 @@ Infinite_Loop:
 ******************************************************************************/
   .section .isr_vector,"a",%progbits
   .type g_pfnVectors, %object
-  .size g_pfnVectors, .-g_pfnVectors
 
 g_pfnVectors:
   .word _estack
@@ -177,6 +176,8 @@ g_pfnVectors:
   .word USART2_IRQHandler                 /* USART2                       */
   .word 0                                 /* reserved                     */
 
+  .size g_pfnVectors, .-g_pfnVectors
+
 /*******************************************************************************
 *
 * Provide weak aliases for each Exception handler to the Default_Handler.
diff --git a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g031xx.s b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g031xx.s
index 51c922b9f0..473af2c47d 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g031xx.s
+++ b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g031xx.s
@@ -127,7 +127,6 @@ Infinite_Loop:
 ******************************************************************************/
   .section .isr_vector,"a",%progbits
   .type g_pfnVectors, %object
-  .size g_pfnVectors, .-g_pfnVectors
 
 g_pfnVectors:
   .word _estack
@@ -178,6 +177,8 @@ g_pfnVectors:
   .word LPUART1_IRQHandler                /* LPUART1                      */
   .word 0                                 /* reserved                     */
 
+  .size g_pfnVectors, .-g_pfnVectors
+
 /*******************************************************************************
 *
 * Provide weak aliases for each Exception handler to the Default_Handler.
diff --git a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g041xx.s b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g041xx.s
index af334332a1..dd8cb858da 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g041xx.s
+++ b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g041xx.s
@@ -127,7 +127,6 @@ Infinite_Loop:
 ******************************************************************************/
   .section .isr_vector,"a",%progbits
   .type g_pfnVectors, %object
-  .size g_pfnVectors, .-g_pfnVectors
 
 g_pfnVectors:
   .word _estack
@@ -179,6 +178,8 @@ g_pfnVectors:
   .word 0                                 /* reserved                     */
   .word AES_RNG_IRQHandler                /* AES and RNG                  */
 
+  .size g_pfnVectors, .-g_pfnVectors
+
 /*******************************************************************************
 *
 * Provide weak aliases for each Exception handler to the Default_Handler.
diff --git a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g050xx.s b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g050xx.s
index 4f4d13b30b..1b893c8f1a 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g050xx.s
+++ b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g050xx.s
@@ -127,7 +127,6 @@ Infinite_Loop:
 ******************************************************************************/
   .section .isr_vector,"a",%progbits
   .type g_pfnVectors, %object
-  .size g_pfnVectors, .-g_pfnVectors
 
 g_pfnVectors:
   .word _estack
@@ -176,6 +175,8 @@ g_pfnVectors:
   .word USART1_IRQHandler                 /* USART1                       */
   .word USART2_IRQHandler                 /* USART2                       */
 
+  .size g_pfnVectors, .-g_pfnVectors
+
 /*******************************************************************************
 *
 * Provide weak aliases for each Exception handler to the Default_Handler.
diff --git a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g051xx.s b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g051xx.s
index 8a71dec2c7..a38cee68a7 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g051xx.s
+++ b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g051xx.s
@@ -127,7 +127,6 @@ Infinite_Loop:
 ******************************************************************************/
   .section .isr_vector,"a",%progbits
   .type g_pfnVectors, %object
-  .size g_pfnVectors, .-g_pfnVectors
 
 g_pfnVectors:
   .word _estack
@@ -177,6 +176,8 @@ g_pfnVectors:
   .word USART2_IRQHandler                 /* USART2                       */
   .word LPUART1_IRQHandler                /* LPUART1                      */
 
+  .size g_pfnVectors, .-g_pfnVectors
+
 /*******************************************************************************
 *
 * Provide weak aliases for each Exception handler to the Default_Handler.
diff --git a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g061xx.s b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g061xx.s
index 15c8dbb084..79d1e4866e 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g061xx.s
+++ b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g061xx.s
@@ -127,7 +127,6 @@ Infinite_Loop:
 ******************************************************************************/
   .section .isr_vector,"a",%progbits
   .type g_pfnVectors, %object
-  .size g_pfnVectors, .-g_pfnVectors
 
 g_pfnVectors:
   .word _estack
@@ -179,6 +178,8 @@ g_pfnVectors:
   .word 0                                 /* reserved                     */
   .word AES_RNG_IRQHandler                /* AES and RNG                  */
 
+  .size g_pfnVectors, .-g_pfnVectors
+
 /*******************************************************************************
 *
 * Provide weak aliases for each Exception handler to the Default_Handler.
diff --git a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g070xx.s b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g070xx.s
index 7dfdd8445d..83e6c3c891 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g070xx.s
+++ b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g070xx.s
@@ -127,7 +127,6 @@ Infinite_Loop:
 ******************************************************************************/
   .section .isr_vector,"a",%progbits
   .type g_pfnVectors, %object
-  .size g_pfnVectors, .-g_pfnVectors
 
 g_pfnVectors:
   .word _estack
@@ -177,6 +176,8 @@ g_pfnVectors:
   .word USART2_IRQHandler                 /* USART2                       */
   .word USART3_4_IRQHandler               /* USART3, USART4               */
 
+  .size g_pfnVectors, .-g_pfnVectors
+
 /*******************************************************************************
 *
 * Provide weak aliases for each Exception handler to the Default_Handler.
diff --git a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g071xx.s b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g071xx.s
index 5b4d4d8778..ac013044a5 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g071xx.s
+++ b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g071xx.s
@@ -127,7 +127,6 @@ Infinite_Loop:
 ******************************************************************************/
   .section .isr_vector,"a",%progbits
   .type g_pfnVectors, %object
-  .size g_pfnVectors, .-g_pfnVectors
 
 g_pfnVectors:
   .word _estack
@@ -178,6 +177,8 @@ g_pfnVectors:
   .word USART3_4_LPUART1_IRQHandler       /* USART3, USART4 and LPUART1   */
   .word CEC_IRQHandler                    /* CEC                          */
 
+  .size g_pfnVectors, .-g_pfnVectors
+
 /*******************************************************************************
 *
 * Provide weak aliases for each Exception handler to the Default_Handler.
diff --git a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g081xx.s b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g081xx.s
index e4ee41bfb0..60f8caa6d0 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g081xx.s
+++ b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g081xx.s
@@ -127,7 +127,6 @@ Infinite_Loop:
 ******************************************************************************/
   .section .isr_vector,"a",%progbits
   .type g_pfnVectors, %object
-  .size g_pfnVectors, .-g_pfnVectors
 
 g_pfnVectors:
   .word _estack
@@ -179,6 +178,8 @@ g_pfnVectors:
   .word CEC_IRQHandler                    /* CEC                          */
   .word AES_RNG_IRQHandler                /* AES and RNG                  */
 
+  .size g_pfnVectors, .-g_pfnVectors
+
 /*******************************************************************************
 *
 * Provide weak aliases for each Exception handler to the Default_Handler.
diff --git a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g0b0xx.s b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g0b0xx.s
index a32177c4ad..969d388c8a 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g0b0xx.s
+++ b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g0b0xx.s
@@ -127,7 +127,6 @@ Infinite_Loop:
 ******************************************************************************/
   .section .isr_vector,"a",%progbits
   .type g_pfnVectors, %object
-  .size g_pfnVectors, .-g_pfnVectors
 
 g_pfnVectors:
   .word _estack
@@ -177,6 +176,8 @@ g_pfnVectors:
   .word USART2_IRQHandler                 /* USART2                       */
   .word USART3_4_5_6_IRQHandler           /* USART3, USART4, USART5, USART6 */
 
+  .size g_pfnVectors, .-g_pfnVectors
+
 /*******************************************************************************
 *
 * Provide weak aliases for each Exception handler to the Default_Handler.
diff --git a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g0b1xx.s b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g0b1xx.s
index 7bf683abd1..88a1208864 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g0b1xx.s
+++ b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g0b1xx.s
@@ -127,7 +127,6 @@ Infinite_Loop:
 ******************************************************************************/
   .section .isr_vector,"a",%progbits
   .type g_pfnVectors, %object
-  .size g_pfnVectors, .-g_pfnVectors
 
 g_pfnVectors:
   .word _estack
@@ -178,6 +177,8 @@ g_pfnVectors:
   .word USART3_4_5_6_LPUART1_IRQHandler   /* USART3, USART4, USART5, USART6, LPUART1   */
   .word CEC_IRQHandler                    /* CEC                          */
 
+  .size g_pfnVectors, .-g_pfnVectors
+
 /*******************************************************************************
 *
 * Provide weak aliases for each Exception handler to the Default_Handler.
diff --git a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g0c1xx.s b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g0c1xx.s
index 0fd5896d2f..6aaf18f818 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g0c1xx.s
+++ b/system/Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g0c1xx.s
@@ -127,7 +127,6 @@ Infinite_Loop:
 ******************************************************************************/
   .section .isr_vector,"a",%progbits
   .type g_pfnVectors, %object
-  .size g_pfnVectors, .-g_pfnVectors
 
 g_pfnVectors:
   .word _estack
@@ -179,6 +178,8 @@ g_pfnVectors:
   .word CEC_IRQHandler                    /* CEC                          */
   .word AES_RNG_IRQHandler                /* AES and RNG                  */
 
+  .size g_pfnVectors, .-g_pfnVectors
+
 /*******************************************************************************
 *
 * Provide weak aliases for each Exception handler to the Default_Handler.
diff --git a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md
index e40eb0aabc..6a5af926c1 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md
+++ b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md
@@ -7,7 +7,7 @@
   * STM32F3: 2.3.7
   * STM32F4: 2.6.9
   * STM32F7: 1.2.8
-  * STM32G0: 1.4.3
+  * STM32G0: 1.4.4
   * STM32G4: 1.2.2
   * STM32H5: 1.1.0
   * STM32H7: 1.10.3