diff --git a/config/chips/H72x_H73x.chip b/config/chips/H72x_H73x.chip
index 194b740d..c07dc678 100644
--- a/config/chips/H72x_H73x.chip
+++ b/config/chips/H72x_H73x.chip
@@ -9,6 +9,6 @@ flash_pagesize 0x20000       // 128 KB
 sram_size 0x20000            // 128 KB "DTCM"
 bootrom_base 0x1ff00000
 bootrom_size 0x20000         // 128 KB
-option_base 0x5200201c       // STM32_H7_OPTION_BYTES_BASE
+option_base 0x52002020       // STM32_H7_OPTION_BYTES_BASE
 option_size 0x2c             // 44 B
 flags swo
diff --git a/config/chips/H74x_H75x.chip b/config/chips/H74x_H75x.chip
index 2b829f79..2ccad39c 100644
--- a/config/chips/H74x_H75x.chip
+++ b/config/chips/H74x_H75x.chip
@@ -9,6 +9,6 @@ flash_pagesize 0x20000       // 128 KB
 sram_size 0x20000            // 128 KB "DTCM"
 bootrom_base 0x1ff00000
 bootrom_size 0x20000         // 128 KB
-option_base 0x5200201c       // STM32_H7_OPTION_BYTES_BASE
+option_base 0x52002020       // STM32_H7_OPTION_BYTES_BASE
 option_size 0x2c             // 44 B /* FLASH_OPTSR_CUR to FLASH_BOOT_PRGR */
 flags swo dualbank
diff --git a/config/chips/H7Ax_H7Bx.chip b/config/chips/H7Ax_H7Bx.chip
index a0817b77..94f73b47 100644
--- a/config/chips/H7Ax_H7Bx.chip
+++ b/config/chips/H7Ax_H7Bx.chip
@@ -9,6 +9,6 @@ flash_pagesize 0x20000       // 128 KB
 sram_size 0x20000            // 128 KB "DTCM"
 bootrom_base 0x1ff00000
 bootrom_size 0x20000         // 128 KB
-option_base 0x5200201c       // STM32_H7_OPTION_BYTES_BASE
+option_base 0x52002020       // STM32_H7_OPTION_BYTES_BASE
 option_size 0x2c             // 44 B
 flags swo dualbank
diff --git a/inc/stm32.h b/inc/stm32.h
index 928b0323..3b707971 100644
--- a/inc/stm32.h
+++ b/inc/stm32.h
@@ -146,7 +146,7 @@ enum stm32_chipids {
 
 #define STM32_F4_OPTION_BYTES_BASE ((uint32_t) 0x40023c14)
 
-#define STM32_H7_OPTION_BYTES_BASE ((uint32_t) 0x5200201c)
+#define STM32_H7_OPTION_BYTES_BASE ((uint32_t) 0x52002020)
 
 #define STM32_L0_OPTION_BYTES_BASE ((uint32_t) 0x1ff80000)
 #define STM32_L1_OPTION_BYTES_BASE ((uint32_t) 0x1ff80000)