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stg/SYLT-FFT
[doc] How to upscale FFT input and avoid overflow?

Typical use case is to apply fft_fft() to ADC samples (8-12 bits). User should upscale input as much as possible, but avoid saturation/overflow. CMSIS DSP uses Q31 input and downscale result automatically. ...
  • puzrin
  • Opened 
    on Oct 27, 2021
  • #10

stg/SYLT-FFT
[doc] Cycles count info desired

It would be very useful to know total cycles of fft run (with zero flash wait-states). That will help users to make estimates of CPU budget. Examples of such info for CMSIS DSP: - https://community.arm.com/cfs-file/__key/communityserver-blogs-components-weblogfiles/00-00-00-21-42/7563.ARM-white-paper-2D00-DSP-capabilities-of-Cortex_2D00_M4-and-Cortex_2D00_M7.pdf ...
  • puzrin
  • Opened 
    on Oct 24, 2021
  • #9

stg/SYLT-FFT
CPP support

I have cpp project, and need to include fft.h into multiple files. Got build error: .pio/build/hw_v1_stm32g030f6/src/app.o: In function `sine_init() : /home/vitaly/Dropbox/Coding/dc_sc_grinder/lib/SYLT-FFT/include/fpmath.h:63: ...
  • puzrin
  • 3
  • Opened 
    on Oct 23, 2021
  • #8

stg/SYLT-FFT
Refactoring

In continue of https://github.com/stg/SYLT-FFT/issues/6#issuecomment-949832806 and below See proposal draft for v2.0.0: https://github.com/speedcontrols/dc_sc_grinder/tree/dev/lib/SYLT-FFT Goal: simplify ...
  • puzrin
  • 5
  • Opened 
    on Oct 23, 2021
  • #7

stg/SYLT-FFT
how can use the lib?

1.which function can get the result of the FFT transform? 2.where to configure the sampling rate or other parameter for input data?
  • jinxiangwzh
  • 6
  • Opened 
    on Aug 31, 2021
  • #6

stg/SYLT-FFT
DIT mode is broken (at least for mac / no asm instructions). (DIF works)

As also reported on #3, DIT mode does not give correct results. I was testing the trivial input:[0,1000,2000,3000,4000,5000,6000,7000]. Here are the results: DIT: 3500 + 0j ,-1707 + 707j ,-1000 + 0j ,0 ...
bug
  • Alex-EEE
  • 2
  • Opened 
    on Jan 28, 2021
  • #5

stg/SYLT-FFT
Code for FFT radix 2 using verilog

Radix 2 fft program using verilog
  • krithika1708
  • 3
  • Opened 
    on Feb 4, 2020
  • #4

stg/SYLT-FFT
DIT gives different results than DIF

When using the default DIT (division in time), which is supposedly the faster way to calculate an FFT, I get results that are strongly different than with the DIF (division in frequency). Furthermore DIF ...
  • maximevince
  • 2
  • Opened 
    on Jan 6, 2017
  • #3

stg/SYLT-FFT
Compilation for other Processors

Hi, This is not really an issue, sorry, but I am trying to use SYLT-FFT on a Pebble smart watch, which I think is using a ARM Cortex M3 processor. I got a lot of errors about the assembler code in SYLT-FFT, ...
  • jones139
  • 16
  • Opened 
    on Jan 18, 2015
  • #1
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