add "WITH Linux-syscall-note" to SPDX tag of uapi headers #94
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Using ARCH_FOO symbol is preferred than SOC_FOO. Set obj-y for starfive/ in Makefile, so the StarFive drivers can be compiled with COMPILE_TEST=y but ARCH_STARFIVE=n. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
The clock control registers on the StarFive JH7100 and JH7110 work identically, so factor out the code then drivers for the two SoCs can share it without depending on each other. No functional change. Tested-by: Tommaso Merciai <tomm.merciai@gmail.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Rename clk-starfive-jh7100.h to clk-starfive-jh71x0.h for making the code to be common. Tested-by: Tommaso Merciai <tomm.merciai@gmail.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Rename some variables from "jh7100" or "JH7100" to "jh71x0" or "JH71X0". Tested-by: Tommaso Merciai <tomm.merciai@gmail.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Using ARCH_FOO symbol is preferred than SOC_FOO. Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
This moves the StarFive JH7100 reset driver to a new subdirectory in preparation for adding more StarFive reset drivers. Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Tested-by: Tommaso Merciai <tomm.merciai@gmail.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
The StarFive JH7100 SoC has additional reset controllers for audio and video, but the registers follow the same structure. On the JH7110 the reset registers don't get their own memory range, but instead follow the clock control registers. The registers still follow the same structure though, so let's factor out the common code to handle all these cases. Tested-by: Tommaso Merciai <tomm.merciai@gmail.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Extract the common JH71X0 reset code for reusing them to support JH7110 SoC. Tested-by: Tommaso Merciai <tomm.merciai@gmail.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
For the common code will be shared with the StarFive JH7110 SoC. Tested-by: Tommaso Merciai <tomm.merciai@gmail.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
We currently use 64bit I/O on the 32bit registers. This works because there are an even number of assert and status registers, so they're only ever accessed in pairs on 64bit boundaries. There are however other reset controllers for audio and video on the JH7100 SoC with only one status register that isn't 64bit aligned so 64bit I/O results in an unaligned access exception. Switch to 32bit I/O in preparation for supporting these resets too. Tested-by: Tommaso Merciai <tomm.merciai@gmail.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Add bindings for the system clock and reset generator (SYSCRG) on the JH7110 RISC-V SoC by StarFive Ltd. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
…erator Add bindings for the always-on clock and reset generator (AONCRG) on the JH7110 RISC-V SoC by StarFive Ltd. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Add driver for the StarFive JH7110 system clock controller and register an auxiliary device for system reset controller which is named as "reset-sys". Tested-by: Tommaso Merciai <tomm.merciai@gmail.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Co-developed-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Add driver for the StarFive JH7110 always-on clock controller and register an auxiliary device for always-on reset controller which is named as "reset-aon". Tested-by: Tommaso Merciai <tomm.merciai@gmail.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Co-developed-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Add auxiliary driver to support StarFive JH7110 system and always-on resets. Tested-by: Tommaso Merciai <tomm.merciai@gmail.com> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Add compatible string for the StarFive JH7110 clint. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Add compatible string for StarFive JH7110 plic. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Add a new compatible string in cpu.yaml for SiFive S7 CPU core which is used on SiFive U74-MC core complex etc. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Add initial device tree for the JH7110 RISC-V SoC by StarFive Technology Ltd. Tested-by: Tommaso Merciai <tomm.merciai@gmail.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Co-developed-by: Jianlong Huang <jianlong.huang@starfivetech.com> Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com> Co-developed-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Add pin function definitions for StarFive JH7110 SoC. Tested-by: Tommaso Merciai <tomm.merciai@gmail.com> Co-developed-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Add a minimal device tree for StarFive JH7110 VisionFive 2 board which has version A and version B. Support booting and basic clock/reset/pinctrl/uart drivers. Tested-by: Tommaso Merciai <tomm.merciai@gmail.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Co-developed-by: Jianlong Huang <jianlong.huang@starfivetech.com> Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com> Co-developed-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Add the pmu controller node for the Starfive JH7110 SoC. The PMU needs to be used by other modules such as VPU, ISP, etc. Signed-off-by: Walker Chen <walker.chen@starfivetech.com>
Add documentation to describe StarFive System Controller Registers. Signed-off-by: William Qiu <william.qiu@starfivetech.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Add stg_syscon/sys_syscon/aon_syscon node for JH7110 Soc. Signed-off-by: William Qiu <william.qiu@starfivetech.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
…set generator Add bindings for the System-Top-Group clock and reset generator (STGCRG) on the JH7110 RISC-V SoC by StarFive Ltd. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Add auxiliary_device_id to support StarFive JH7110 System-Top-Group resets of which the auxiliary device name is "clk_starfive_jh71x0.reset-stg". Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Add driver for the StarFive JH7110 System-Top-Group clock controller. Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Co-developed-by: Xingyu Wu <xingyu.wu@starfivetech.com> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
…d reset generator Add bindings for the Image-Signal-Process clock and reset generator (ISPCRG) on the JH7110 RISC-V SoC by StarFive Ltd. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Add auxiliary_device_id to support StarFive JH7110 Image-Signal-Process resets of which the auxiliary device name is "clk_starfive_jh71x0.reset-isp". Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Add driver for the StarFive JH7110 Image-Signal-Process clock controller. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Low level Arch functions were created to support hibernation. swsusp_arch_suspend() relies code from __cpu_suspend_enter() to write cpu state onto the stack, then calling swsusp_save() to save the memory image. Arch specific hibernation header is implemented and is utilized by the arch_hibernation_header_restore() and arch_hibernation_header_save() functions. The arch specific hibernation header consists of satp, hartid, and the cpu_resume address. The kernel built version is also need to be saved into the hibernation image header to making sure only the same kernel is restore when resume. swsusp_arch_resume() creates a temporary page table that covering only the linear map. It copies the restore code to a 'safe' page, then start to restore the memory image. Once completed, it restores the original kernel's page table. It then calls into __hibernate_cpu_resume() to restore the CPU context. Finally, it follows the normal hibernation path back to the hibernation core. To enable hibernation/suspend to disk into RISCV, the below config need to be enabled: - CONFIG_ARCH_HIBERNATION_HEADER - CONFIG_ARCH_HIBERNATION_POSSIBLE Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com> Reviewed-by: Ley Foon Tan <leyfoon.tan@starfivetech.com> Reviewed-by: Mason Huo <mason.huo@starfivetech.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
…aders UAPI headers licensed under GPL are supposed to have exception "WITH Linux-syscall-note" so that they can be included into non-GPL user space application code. Signed-off-by: Łukasz Stelmach <l.stelmach@samsung.com>
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UAPI headers licensed under GPL are supposed to have exception "WITH Linux-syscall-note" so that they can be included into non-GPL user space application code.