gateware: peripherals: spi: replaced janky clock delay with more desc…

…riptive `Rose` and `Fell` Torii operators

squishy/gateware/bootloader/rev2.py

@@ -61,7 +61,6 @@
 from torii                 import Elaboratable, Module, Signal
 from torii.lib.fifo        import AsyncFIFO
 from torii.lib.cdc         import FFSynchronizer, PulseSynchronizer
-from torii.hdl.ast         import Rose
 
 from ..core.supervisor_csr import SupervisorCSRMap
 from ..platform            import SquishyPlatformType

squishy/gateware/peripherals/spi.py

@@ -4,12 +4,14 @@
 
 '''
 
-from enum              import IntEnum, Flag, auto, unique
+from enum              import Flag, IntEnum, auto, unique
 
-from torii             import Elaboratable, Signal, Module, Cat, ResetSignal, ClockSignal, ClockDomain
+from torii             import Cat, ClockDomain, ClockSignal, Elaboratable, Module, ResetSignal, Signal
 from torii.build       import Subsignal
-from torii.lib.soc.csr import Multiplexer
+from torii.hdl.ast     import Fell, Rose
 from torii.lib.cdc     import FFSynchronizer
+from torii.lib.soc.csr import Multiplexer
+
 from ..platform        import SquishyPlatformType
 
 __all__ = (
@@ -304,12 +306,10 @@ def elaborate(self, _: SquishyPlatformType | None) -> Module:
 
 		m.domains.spi = ClockDomain()
 
-		# TODO(aki): Replace the use of `clk_dly` with `Rose`/`Fell`
-		clk     = Signal.like(self._clk,  name = 'spi_pclk'    )
-		clk_dly = Signal.like(clk,        name = 'spi_pclk_dly')
-		cs      = Signal.like(self._cs,   name = 'spi_pcs'     )
-		copi    = Signal.like(self._copi, name = 'spi_pcopi'   )
-		cipo    = self._cipo
+		clk  = Signal.like(self._clk,  name = 'spi_pclk' )
+		cs   = Signal.like(self._cs,   name = 'spi_pcs'  )
+		copi = Signal.like(self._copi, name = 'spi_pcopi')
+		cipo = self._cipo
 
 		m.submodules.clk_ff  = FFSynchronizer(self._clk,   clk, o_domain = 'sync')
 		m.submodules.cs_ff   = FFSynchronizer(self._cs,     cs, o_domain = 'sync')
@@ -335,7 +335,7 @@ def elaborate(self, _: SquishyPlatformType | None) -> Module:
 			with m.State('READ_ADDR'):
 				with m.If(~cs):
 					m.next = 'IDLE'
-				with m.Elif(clk & ~clk_dly):
+				with m.Elif(Rose(clk)):
 					m.d.sync += [
 						addr_cntr.eq(addr_cntr + 1),
 						addr.eq(Cat(addr[1:], copi)),
@@ -351,15 +351,15 @@ def elaborate(self, _: SquishyPlatformType | None) -> Module:
 			with m.State('WAIT_DATA'):
 				with m.If(~cs):
 					m.next = 'IDLE'
-				with m.Elif(clk & ~clk_dly):
+				with m.Elif(Rose(clk)):
 					m.d.sync += [ wait_cntr.eq(wait_cntr + 1), ]
 					with m.If(wait_cntr == 7 - (addr.width & 0b111)):
 						m.next = 'PREPARE_DATA'
 
 			with m.State('PREPARE_DATA'):
 				with m.If(~cs):
 					m.next = 'IDLE'
-				with m.Elif(~clk & clk_dly):
+				with m.Elif(Fell(clk)):
 					m.d.comb += [ self._reg_bus.r_stb.eq(1), ]
 					m.d.sync += [ data_prep.eq(1), ]
 					m.next = 'XFR_DATA'
@@ -370,15 +370,15 @@ def elaborate(self, _: SquishyPlatformType | None) -> Module:
 						data_read.eq(self._reg_bus.r_data),
 						data_prep.eq(0),
 					]
-				with m.If(clk & ~clk_dly):
+				with m.If(Rose(clk)):
 					m.d.sync += [
 						# Wiggle in the `data_write` value
 						data_write.eq(Cat(data_write[1:], copi)),
 					]
 					with m.If(~cs):
 						m.next = 'IDLE'
 
-				with m.Elif(~clk & clk_dly):
+				with m.Elif(Fell(clk)):
 					m.d.sync += [
 						data_cntr.eq(data_cntr + 1),
 						# Wiggle out the `data_read` value
@@ -412,10 +412,6 @@ def elaborate(self, _: SquishyPlatformType | None) -> Module:
 				m.d.comb += [ self._reg_bus.r_stb.eq(1), ]
 				m.next = 'XFR_DATA'
 
-		m.d.sync += [
-			clk_dly.eq(clk), # Generate the delayed clock by one cycle for edge detection
-		]
-
 		m.d.comb += [
 			ResetSignal('spi').eq(ClockDomain('sync').rst),
 			ClockSignal('spi').eq(self._clk),