diff --git a/firmware/main.cc b/firmware/main.cc
index b9b94315..30336cb1 100644
--- a/firmware/main.cc
+++ b/firmware/main.cc
@@ -26,7 +26,7 @@ void setup_io() noexcept {
 	PORTA.set_input(pin::DFU_BTN);
 	/* Setup FPGA Side attention lines */
 	/* TODO: This need to be EXTINTs, not normal inputs */
-	PORTA.set_input(pin::DFU_TRIG);
+	PORTA.set_input(pin::BUS_HOLD);
 	PORTA.set_input(pin::SU_ATTN);
 }
 
diff --git a/firmware/pindefs.hh b/firmware/pindefs.hh
index a1e737df..b0ccbcc6 100644
--- a/firmware/pindefs.hh
+++ b/firmware/pindefs.hh
@@ -40,7 +40,7 @@ namespace pin {
 
 	/* FPGA Facing DFU/Comm triggers */
 	inline constexpr std::uint8_t SU_ATTN{15U};
-	inline constexpr std::uint8_t DFU_TRIG{11U};
+	inline constexpr std::uint8_t BUS_HOLD{11U};
 }
 
 #endif /* SQUISHY_SUPERVISOR_PINDEFS_HH */
diff --git a/squishy/gateware/bootloader/rev2.py b/squishy/gateware/bootloader/rev2.py
index 8ac581d4..61c6e814 100644
--- a/squishy/gateware/bootloader/rev2.py
+++ b/squishy/gateware/bootloader/rev2.py
@@ -28,9 +28,9 @@
 Upon the FPGA entering the bootloader:
 
 0. FPGA waits for a DFU upload, and if done stuffs it into the PSRAM
-
-  a. FPGA sticks the destination slot for the DFU payload into the ``dest_slot`` half of the ``slots`` register
-  b. FPGA writes the DFU payload size into the ``txlen`` register
+  a. FPGA Holds ``bus_hold`` high until DFU upload is complete
+  b. FPGA sticks the destination slot for the DFU payload into the ``dest_slot`` half of the ``slots`` register
+  c. FPGA writes the DFU payload size into the ``txlen`` register
 
 1. FPGA sets the IRQ Reason to ``in_boot``
 2. FPGA raises the ``~SU_IRQ`` line to notify the supervisor we are in the bootloader
@@ -132,10 +132,8 @@ def elaborate(self, platform: SquishyPlatformType | None) -> Module:
 
 		sup_int = platform.request('supervisor', 0)
 
-		su_irq = sup_int.su_irq.o
-
-		# NOTE(aki): We are not using this signal for anything at the moment, drive it to a defined state
-		m.d.comb += [ sup_int.dfu_trg.o.eq(0), ]
+		su_irq: Signal   = sup_int.su_irq.o
+		bus_hold: Signal = sup_int.bus_hold.o
 
 		m.submodules.regs = regs = SupervisorCSRMap(name = 'supervisor')
 		m.submodules.spi  = spi  = SPIInterface(
@@ -148,6 +146,11 @@ def elaborate(self, platform: SquishyPlatformType | None) -> Module:
 			controller = spi.controller, write_fifo = self._bit_fifo
 		)
 
+		m.d.comb += [
+			bus_hold.eq(spi.active_mode), # Due to how `spi.active_mode` is defined, we can just tie these together
+			spi.active_mode.eq(0), # We should always be a peripheral unless we're explicitly writing to the PSRAM
+		]
+
 		# TODO(aki): Don't forget to drive spi.active_mode for the controller or peripheral
 
 		return m
diff --git a/squishy/gateware/platform/rev2.py b/squishy/gateware/platform/rev2.py
index a710f76d..0f5cd56c 100644
--- a/squishy/gateware/platform/rev2.py
+++ b/squishy/gateware/platform/rev2.py
@@ -225,7 +225,8 @@ class SquishyRev2(SquishyPlatform, ECP5Platform):
 			Subsignal('attn',    PinsN('T2', dir = 'i')), # This is the CS for the FPGA
 			Subsignal('psram',   PinsN('Y2', dir = 'o')), # The bitstram cache PSRAM CS from our side
 			Subsignal('su_irq',  Pins('W1', dir = 'o')),
-			Subsignal('dfu_trg', PinsN('V1', dir = 'o')),
+			# This /could/ be done by clamping CS on our side but a dedicated signal is fine
+			Subsignal('bus_hold', Pins('V1', dir = 'o')),
 
 			Attrs(IO_TYPE = 'LVCMOS33')
 		),