From 150a646a54ef641809d4f4be739003ace1cf0a67 Mon Sep 17 00:00:00 2001 From: Aki Van Ness Date: Sun, 12 Jan 2025 17:42:49 -0800 Subject: [PATCH] gateware: peripherals: spi: Fixed a bug where CIPO was set up a bit too late in the SPI Peripheral --- squishy/gateware/peripherals/spi.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/squishy/gateware/peripherals/spi.py b/squishy/gateware/peripherals/spi.py index 6998b851..5b940c85 100644 --- a/squishy/gateware/peripherals/spi.py +++ b/squishy/gateware/peripherals/spi.py @@ -374,6 +374,8 @@ def elaborate(self, _: SquishyPlatformType | None) -> Module: m.d.sync += [ # Wiggle in the `data_write` value data_write.eq(Cat(data_write[1:], copi)), + # Wiggle out the `data_read` value + cipo.eq(data_read.bit_select(data_cntr, 1)), ] with m.If(~cs): m.next = 'IDLE' @@ -381,8 +383,6 @@ def elaborate(self, _: SquishyPlatformType | None) -> Module: with m.Elif(Fell(clk)): m.d.sync += [ data_cntr.eq(data_cntr + 1), - # Wiggle out the `data_read` value - cipo.eq(data_read.bit_select(data_cntr, 1)), ] with m.If(data_cntr == (data_write.width - 1)):