gateware: peripherals: spi: Fixed a bug where CIPO was set up a bit t…

…oo late in the SPI Peripheral
squishy-scsi · Jan 13, 2025 · 150a646 · 150a646
1 parent cd91320
commit 150a646
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/squishy/gateware/peripherals/spi.py b/squishy/gateware/peripherals/spi.py
@@ -374,15 +374,15 @@ def elaborate(self, _: SquishyPlatformType | None) -> Module:
 					m.d.sync += [
 						# Wiggle in the `data_write` value
 						data_write.eq(Cat(data_write[1:], copi)),
+						# Wiggle out the `data_read` value
+						cipo.eq(data_read.bit_select(data_cntr, 1)),
 					]
 					with m.If(~cs):
 						m.next = 'IDLE'
 
 				with m.Elif(Fell(clk)):
 					m.d.sync += [
 						data_cntr.eq(data_cntr + 1),
-						# Wiggle out the `data_read` value
-						cipo.eq(data_read.bit_select(data_cntr, 1)),
 					]
 
 					with m.If(data_cntr == (data_write.width - 1)):