zybo.cfg

set FSBL "FSBL.elf"
set bit "top.bit"

source [find interface/ftdi/digilent-hs1.cfg]
reset_config srst_only srst_push_pull
source [find target/zynq_7000.cfg]


proc zynqpl_reset_release {target} {
    # Unlock SLCR
    $target mww 0xf8000008 0xdf0d
    # Enable level shifters, both PL-PS and PS-PL
    $target mww 0xf8000900 0xF
    # Release FPGA reset
    $target mww 0xf8000240 0x0
    # Lock SLCR
    $target mww 0xf8000004 0x767b
}

pld device virtex2 zynq_pl.bs 1

set XC7_JSHUTDOWN 0x0d
set XC7_JPROGRAM 0x0b
set XC7_JSTART 0x0c
set XC7_BYPASS 0x3f

proc zynqpl_program {tap} {
        global XC7_JSHUTDOWN XC7_JPROGRAM XC7_JSTART XC7_BYPASS
        irscan $tap $XC7_JSHUTDOWN
        irscan $tap $XC7_JPROGRAM
        runtest 60000
        #JSTART prevents this from working...
        #irscan $tap $XC7_JSTART
        runtest 2000
        irscan $tap $XC7_BYPASS
        runtest 2000
}
 
# Load FSBL
init
halt
targets zynq.cpu0
echo [format "Loading %s" $FSBL]
load_image $FSBL 0
resume 0
sleep 2000
halt

adapter_khz 20000


# Load Bitstream
echo $bit
zynqpl_program zynq_pl.bs
#pld devices
pld load 0  $bit
sleep 100
zynqpl_reset_release zynq.cpu0


# Load application
load_image os.bin 0x100000
echo os
arm core_state arm
resume 0x100000