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Copy pathDAC8734.json
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DAC8734.json
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{
"verilog" : {
"name" : "DAC8734",
"top": "main_without_capture_waveform_data_v1_00.sv",
"top_module_name" : "main_without_capture_waveform_data",
"gen_ip" : "False",
"files" : [
"ascii2hex.v",
"async_receiver.v",
"async_transmitter.v",
"data_receiver_v1_00.v",
"data_sender_v1_01.sv",
"hex2ascii.v",
"led_intensity_adjust.v",
"clock_divider.sv",
"shift_register_in.sv",
"shift_register_out.sv",
"spi_fsm_module.sv",
"spi_multiple_single_output.sv",
"main_without_capture_waveform_data_v1_00.sv"
]
},
"ip" : {
"fifo_generator_0" : {
"name" : "fifo_generator",
"version" : "13.2",
"vendor" : "xilinx.com",
"library" : "ip",
"tcl_options" : ["name", "version", "vendor", "library", "module_name"],
"config" : {
"ADDRESS_WIDTH" : "32",
"ARUSER_Width" : "0",
"AWUSER_Width" : "0",
"Add_NGC_Constraint_AXI" : "false",
"Almost_Empty_Flag" : "false",
"Almost_Full_Flag" : "false",
"BUSER_Width" : "0",
"CORE_CLK.FREQ_HZ" : "100000000",
"C_SELECT_XPM" : "0",
"Clock_Enable_Type" : "Slave_Interface_Clock_Enable",
"Clock_Type_AXI" : "Common_Clock",
"DATA_WIDTH" : "64",
"Data_Count" : "false",
"Data_Count_Width" : "13",
"Disable_Timing_Violations" : "false",
"Disable_Timing_Violations_AXI" : "false",
"Dout_Reset_Value" : "0",
"Empty_Threshold_Assert_Value" : "4",
"Empty_Threshold_Assert_Value_axis" : "1022",
"Empty_Threshold_Assert_Value_rach" : "1022",
"Empty_Threshold_Assert_Value_rdch" : "1022",
"Empty_Threshold_Assert_Value_wach" : "1022",
"Empty_Threshold_Assert_Value_wdch" : "1022",
"Empty_Threshold_Assert_Value_wrch" : "1022",
"Empty_Threshold_Negate_Value" : "5",
"Enable_Common_Overflow" : "false",
"Enable_Common_Underflow" : "false",
"Enable_Data_Counts_axis" : "false",
"Enable_Data_Counts_rach" : "false",
"Enable_Data_Counts_rdch" : "false",
"Enable_Data_Counts_wach" : "false",
"Enable_Data_Counts_wdch" : "false",
"Enable_Data_Counts_wrch" : "false",
"Enable_ECC" : "false",
"Enable_ECC_Type" : "Hard_ECC",
"Enable_ECC_axis" : "false",
"Enable_ECC_rach" : "false",
"Enable_ECC_rdch" : "false",
"Enable_ECC_wach" : "false",
"Enable_ECC_wdch" : "false",
"Enable_ECC_wrch" : "false",
"Enable_Reset_Synchronization" : "true",
"Enable_Safety_Circuit" : "false",
"Enable_TLAST" : "false",
"Enable_TREADY" : "true",
"FIFO_Application_Type_axis" : "Data_FIFO",
"FIFO_Application_Type_rach" : "Data_FIFO",
"FIFO_Application_Type_rdch" : "Data_FIFO",
"FIFO_Application_Type_wach" : "Data_FIFO",
"FIFO_Application_Type_wdch" : "Data_FIFO",
"FIFO_Application_Type_wrch" : "Data_FIFO",
"FIFO_Implementation_axis" : "Common_Clock_Block_RAM",
"FIFO_Implementation_rach" : "Common_Clock_Block_RAM",
"FIFO_Implementation_rdch" : "Common_Clock_Block_RAM",
"FIFO_Implementation_wach" : "Common_Clock_Block_RAM",
"FIFO_Implementation_wdch" : "Common_Clock_Block_RAM",
"FIFO_Implementation_wrch" : "Common_Clock_Block_RAM",
"Fifo_Implementation" : "Common_Clock_Builtin_FIFO",
"Full_Flags_Reset_Value" : "0",
"Full_Threshold_Assert_Value" : "8191",
"Full_Threshold_Assert_Value_axis" : "1023",
"Full_Threshold_Assert_Value_rach" : "1023",
"Full_Threshold_Assert_Value_rdch" : "1023",
"Full_Threshold_Assert_Value_wach" : "1023",
"Full_Threshold_Assert_Value_wdch" : "1023",
"Full_Threshold_Assert_Value_wrch" : "1023",
"Full_Threshold_Negate_Value" : "8190",
"HAS_ACLKEN" : "false",
"HAS_TKEEP" : "false",
"HAS_TSTRB" : "false",
"ID_WIDTH" : "0",
"INTERFACE_TYPE" : "Native",
"Inject_Dbit_Error" : "false",
"Inject_Dbit_Error_axis" : "false",
"Inject_Dbit_Error_rach" : "false",
"Inject_Dbit_Error_rdch" : "false",
"Inject_Dbit_Error_wach" : "false",
"Inject_Dbit_Error_wdch" : "false",
"Inject_Dbit_Error_wrch" : "false",
"Inject_Sbit_Error" : "false",
"Inject_Sbit_Error_axis" : "false",
"Inject_Sbit_Error_rach" : "false",
"Inject_Sbit_Error_rdch" : "false",
"Inject_Sbit_Error_wach" : "false",
"Inject_Sbit_Error_wdch" : "false",
"Inject_Sbit_Error_wrch" : "false",
"Input_Data_Width" : "8",
"Input_Depth" : "8192",
"Input_Depth_axis" : "1024",
"Input_Depth_rach" : "16",
"Input_Depth_rdch" : "1024",
"Input_Depth_wach" : "16",
"Input_Depth_wdch" : "1024",
"Input_Depth_wrch" : "16",
"MASTER_ACLK.FREQ_HZ" : "100000000",
"Master_interface_Clock_enable_memory_mapped" : "false",
"Output_Data_Width" : "8",
"Output_Depth" : "8192",
"Output_Register_Type" : "Embedded_Reg",
"Overflow_Flag" : "true",
"Overflow_Flag_AXI" : "false",
"Overflow_Sense" : "Active_High",
"Overflow_Sense_AXI" : "Active_High",
"PROTOCOL" : "AXI4",
"Performance_Options" : "First_Word_Fall_Through",
"Programmable_Empty_Type" : "No_Programmable_Empty_Threshold",
"Programmable_Empty_Type_axis" : "No_Programmable_Empty_Threshold",
"Programmable_Empty_Type_rach" : "No_Programmable_Empty_Threshold",
"Programmable_Empty_Type_rdch" : "No_Programmable_Empty_Threshold",
"Programmable_Empty_Type_wach" : "No_Programmable_Empty_Threshold",
"Programmable_Empty_Type_wdch" : "No_Programmable_Empty_Threshold",
"Programmable_Empty_Type_wrch" : "No_Programmable_Empty_Threshold",
"Programmable_Full_Type" : "No_Programmable_Full_Threshold",
"Programmable_Full_Type_axis" : "No_Programmable_Full_Threshold",
"Programmable_Full_Type_rach" : "No_Programmable_Full_Threshold",
"Programmable_Full_Type_rdch" : "No_Programmable_Full_Threshold",
"Programmable_Full_Type_wach" : "No_Programmable_Full_Threshold",
"Programmable_Full_Type_wdch" : "No_Programmable_Full_Threshold",
"Programmable_Full_Type_wrch" : "No_Programmable_Full_Threshold",
"READ_CLK.FREQ_HZ" : "100000000",
"READ_WRITE_MODE" : "READ_WRITE",
"RUSER_Width" : "0",
"Read_Clock_Frequency" : "1",
"Read_Data_Count" : "false",
"Read_Data_Count_Width" : "13",
"Register_Slice_Mode_axis" : "Fully_Registered",
"Register_Slice_Mode_rach" : "Fully_Registered",
"Register_Slice_Mode_rdch" : "Fully_Registered",
"Register_Slice_Mode_wach" : "Fully_Registered",
"Register_Slice_Mode_wdch" : "Fully_Registered",
"Register_Slice_Mode_wrch" : "Fully_Registered",
"Reset_Pin" : "true",
"Reset_Type" : "Asynchronous_Reset",
"SLAVE_ACLK.FREQ_HZ" : "100000000",
"Slave_interface_Clock_enable_memory_mapped" : "false",
"TDATA_NUM_BYTES" : "1",
"TDEST_WIDTH" : "0",
"TID_WIDTH" : "0",
"TKEEP_WIDTH" : "1",
"TSTRB_WIDTH" : "1",
"TUSER_WIDTH" : "4",
"Underflow_Flag" : "true",
"Underflow_Flag_AXI" : "false",
"Underflow_Sense" : "Active_High",
"Underflow_Sense_AXI" : "Active_High",
"Use_Dout_Reset" : "false",
"Use_Embedded_Registers" : "false",
"Use_Embedded_Registers_axis" : "false",
"Use_Extra_Logic" : "false",
"Valid_Flag" : "false",
"Valid_Sense" : "Active_High",
"WRITE_CLK.FREQ_HZ" : "100000000",
"WUSER_Width" : "0",
"Write_Acknowledge_Flag" : "false",
"Write_Acknowledge_Sense" : "Active_High",
"Write_Clock_Frequency" : "1",
"Write_Data_Count" : "false",
"Write_Data_Count_Width" : "13",
"asymmetric_port_width" : "false",
"axis_type" : "FIFO",
"dynamic_power_saving" : "false",
"ecc_pipeline_reg" : "false",
"enable_low_latency" : "false",
"enable_read_pointer_increment_by2" : "false",
"rach_type" : "FIFO",
"rdch_type" : "FIFO",
"synchronization_stages" : "2",
"synchronization_stages_axi" : "2",
"use_dout_register" : "false",
"wach_type" : "FIFO",
"wdch_type" : "FIFO",
"wrch_type" : "FIFO"
}
}
}
}