Help understanding control signals/microcode

[joelburton]

I built my M64x4 a few weeks ago and have been learning the assembly language for it and studying the schematics to understand the digital logic (& a huge thanks to @slu4coder ; this has been a fascinating experience).

I'm now trying to understand the microcode, but are running into questions:

• for OUT instruction, step 1: MZ|AO|IC. Looking at the list of control lines, I see that TI is a virtual signal made up of TI = OR(~MZ, ~AO). However, I read that "TI is set when either MZ or AO are low", which makes no sense, since we're setting MZ|AO in the microcode. It appears that TI is active-low (the schematic shows that /TI_PLS=OR(/MZ, /AO); is there a place that shows the active-high-or-low for the signals? (and is the "PLS" for "pulse"? or something else?)

• for CLC and LL0: I don't understand the use of LL0 --- the only thing that the docs suggest is that it clears the carry bit (C=0). Yet, the real CLC microcode has a two steps AO|BI EO|ES|FI|IC whereas step 1 of LL0 is just FF|IC (put -1 on bus, end instruction). Is it the case that any step that doesn't do ALU stuff just always resets the carry bit? Or is there something I'm not understanding about the digital logic about putting FF on the bus? (and why bother having CLC if LL0 clears the carry bit with fewer steps?)

• for the opcodes that actual shift, like LL1: AO|BI EO|FI|AI|IC, I read as: "output A to bus and get B from bus, then (add A+B and put result onto bus, read flags in, read bus into A`. I must be misunderstanding something here: how would adding A+sameval shift anything?

Thanks for any insight!

[victorliu]

For your third question, a left shift by 1 bit is a doubling of the value, so adding the number to itself achieves that result.

[slu4coder]

H, Joel,
the schematic shows which control signals are active low by that little "invert bar" above them. As you can see, ~MZ as well as ~AO are active low. So whenever you see MZ|AO in the microcode, these two are low. ~CLK_PLS (also active low) will then pass through the OR gate.

LL0 does not set the carry flag. The flags set are listed on the right hand side of the table. The ALU has a "carry in" and a "carry out". LL0 is shifting by 0 steps, so it does nothing. Why have such an instruction? Well, sometimes you want software to control how many bits to shift. You can write the "instruction "LL0" + number of bits 0...7 into memory as self-modifying code to achieve this. CLC actually clears the "carry out flag".

As Victor has already pointed out A<<1 is equivalent to A+A, e.g. 0110 (6) << 1 = 1100 (12) and 0110 + 0110 = 1100 (also 12).

Hope this helps a bit. Cheers!

[joelburton]

Thank you both!