From dedb11e4b8478ed0fa3a6709c7f73fd63df67378 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Tue, 5 Nov 2024 08:35:59 -0800 Subject: [PATCH] Slow down FPGA boot so Zynq comes up before FPGA (Vadj bug fix) --- .../hdl/Simple10GbeRudpKcu105Example.xdc | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/firmware/targets/Simple10GbeRudpKcu105Example/hdl/Simple10GbeRudpKcu105Example.xdc b/firmware/targets/Simple10GbeRudpKcu105Example/hdl/Simple10GbeRudpKcu105Example.xdc index a332324..d416365 100644 --- a/firmware/targets/Simple10GbeRudpKcu105Example/hdl/Simple10GbeRudpKcu105Example.xdc +++ b/firmware/targets/Simple10GbeRudpKcu105Example/hdl/Simple10GbeRudpKcu105Example.xdc @@ -64,9 +64,4 @@ set_property CFGBVS GND [current_design] set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] set_property CONFIG_MODE SPIx8 [current_design] set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 8 [current_design] -set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN div-1 [current_design] -set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] -set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design] -set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR Yes [current_design] -set_property BITSTREAM.STARTUP.LCK_CYCLE NoWait [current_design] -set_property BITSTREAM.STARTUP.MATCH_CYCLE NoWait [current_design] +set_property BITSTREAM.CONFIG.CONFIGRATE 12 [current_design]