Slow down FPGA boot so Zynq comes up before FPGA (Vadj bug fix)

slaclab · Nov 5, 2024 · dedb11e · dedb11e
1 parent 33e484d
commit dedb11e
Showing 1 changed file with 1 addition and 6 deletions.
diff --git a/firmware/targets/Simple10GbeRudpKcu105Example/hdl/Simple10GbeRudpKcu105Example.xdc b/firmware/targets/Simple10GbeRudpKcu105Example/hdl/Simple10GbeRudpKcu105Example.xdc
@@ -64,9 +64,4 @@ set_property CFGBVS GND                              [current_design]
 set_property BITSTREAM.GENERAL.COMPRESS TRUE         [current_design]
 set_property CONFIG_MODE SPIx8                       [current_design]
 set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 8         [current_design]
-set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN div-1 [current_design]
-set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES      [current_design]
-set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup       [current_design]
-set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR Yes     [current_design]
-set_property BITSTREAM.STARTUP.LCK_CYCLE NoWait      [current_design]
-set_property BITSTREAM.STARTUP.MATCH_CYCLE NoWait    [current_design]
+set_property BITSTREAM.CONFIG.CONFIGRATE 12          [current_design]