reverting back to 2023.1

firmware/setup_env_slac.sh

@@ -1,5 +1,5 @@
 # Setup the Xilinx software and licensing
-source /afs/slac.stanford.edu/g/reseng/xilinx/2024.1/Vivado/2024.1/settings64.sh
+source /afs/slac.stanford.edu/g/reseng/xilinx/2023.1/Vivado/2023.1/settings64.sh
 
 # Setup VCS
 source /afs/slac.stanford.edu/g/reseng/synopsys/vcs/T-2022.06-SP2/settings.sh

firmware/targets/Simple10GbeRudpKcu105Example/ruckus.tcl

@@ -1,8 +1,8 @@
 # Load RUCKUS environment and library
 source -quiet $::env(RUCKUS_DIR)/vivado_proc.tcl
 
-# Check for version 2024.1 of Vivado (or later)
-if { [VersionCheck 2024.1] < 0 } {exit -1}
+# Check for version 2023.1 of Vivado (or later)
+if { [VersionCheck 2023.1] < 0 } {exit -1}
 
 # Load common and sub-module ruckus.tcl files
 loadRuckusTcl $::env(TOP_DIR)/submodules/surf

firmware/targets/Simple10GbeRudpKcu105Example/vivado/post_synthesis.tcl

@@ -0,0 +1,76 @@
+##############################################################################
+## This file is part of 'Simple-10GbE-RUDP-KCU105-Example'.
+## It is subject to the license terms in the LICENSE.txt file found in the
+## top-level directory of this distribution and at:
+##    https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
+## No part of 'Simple-10GbE-RUDP-KCU105-Example', including this file,
+## may be copied, modified, propagated, or distributed except according to
+## the terms contained in the LICENSE.txt file.
+##############################################################################
+
+##############################
+# Get variables and procedures
+##############################
+source -quiet $::env(RUCKUS_DIR)/vivado_env_var.tcl
+source -quiet $::env(RUCKUS_DIR)/vivado_proc.tcl
+
+######################################################
+# Bypass the debug chipscope generation via return cmd
+# ELSE ... comment out the return to include chipscope
+######################################################
+#return
+
+############################
+## Open the synthesis design
+############################
+open_run synth_1
+
+###############################
+## Set the name of the ILA core
+###############################
+set ilaName u_ila_0
+
+##################
+## Create the core
+##################
+CreateDebugCore ${ilaName}
+
+#######################
+## Set the record depth
+#######################
+set_property C_DATA_DEPTH 1024 [get_debug_cores ${ilaName}]
+
+#################################
+## Set the clock for the ILA core
+#################################
+SetDebugCoreClk ${ilaName} {axilClk}
+
+#######################
+## Set the debug Probes
+#######################
+
+ConfigProbe ${ilaName} {U_Core/GEN_REAL.U_XbarI2cMux/ack[resp][*]}
+ConfigProbe ${ilaName} {U_Core/GEN_REAL.U_XbarI2cMux/i2cRegMasterOut[regFailCode][*]}
+ConfigProbe ${ilaName} {U_Core/GEN_REAL.U_XbarI2cMux/r_reg[state][*]}
+ConfigProbe ${ilaName} {U_Core/GEN_REAL.U_XbarI2cMux/sAxilReadSlave[rresp][*]}
+ConfigProbe ${ilaName} {U_Core/GEN_REAL.U_XbarI2cMux/xbarReadSlave[rresp][*]}
+ConfigProbe ${ilaName} {U_Core/GEN_REAL.U_XbarI2cMux/ack[done]}
+ConfigProbe ${ilaName} {U_Core/GEN_REAL.U_XbarI2cMux/i2cRegMasterOut[regAck]}
+ConfigProbe ${ilaName} {U_Core/GEN_REAL.U_XbarI2cMux/i2cRegMasterOut[regFail]}
+ConfigProbe ${ilaName} {U_Core/GEN_REAL.U_XbarI2cMux/mAxilReadMasters[*][arvalid]}
+ConfigProbe ${ilaName} {U_Core/GEN_REAL.U_XbarI2cMux/mAxilReadSlaves[*][arready]}
+ConfigProbe ${ilaName} {U_Core/GEN_REAL.U_XbarI2cMux/mAxilReadSlaves[*][rvalid]}
+ConfigProbe ${ilaName} {U_Core/GEN_REAL.U_XbarI2cMux/mAxilReadMasters[*][rready]}
+ConfigProbe ${ilaName} {U_Core/GEN_REAL.U_XbarI2cMux/sAxilReadMaster[arvalid]}
+ConfigProbe ${ilaName} {U_Core/GEN_REAL.U_XbarI2cMux/sAxilReadMaster[rready]}
+ConfigProbe ${ilaName} {U_Core/GEN_REAL.U_XbarI2cMux/sAxilReadSlave[arready]}
+ConfigProbe ${ilaName} {U_Core/GEN_REAL.U_XbarI2cMux/sAxilReadSlave[rvalid]}
+ConfigProbe ${ilaName} {U_Core/GEN_REAL.U_XbarI2cMux/xbarReadMaster[arvalid]}
+ConfigProbe ${ilaName} {U_Core/GEN_REAL.U_XbarI2cMux/xbarReadMaster[rready]}
+ConfigProbe ${ilaName} {U_Core/GEN_REAL.U_XbarI2cMux/xbarReadSlave[arready]}
+ConfigProbe ${ilaName} {U_Core/GEN_REAL.U_XbarI2cMux/xbarReadSlave[rvalid]}
+
+##########################
+## Write the port map file
+##########################
+WriteDebugProbes ${ilaName}

firmware/targets/Simple10GbeRudpKcu105Example/vivado/pre_opt_run.tcl

@@ -1,3 +1,4 @@
+return
 ##############################################################################
 ## This file is part of 'Simple-10GbE-RUDP-KCU105-Example'.
 ## It is subject to the license terms in the LICENSE.txt file found in the