Hello there 👋

My name is Suhas Kudlur Viswanath and I am an avid enthusiast of open Instruction Set Architectures like RISC-V. I mainly develop RTL for processors using the RISC-V ISA, some more RTL for accelerators and interconnects. I used to work as a Hardware Engineer at Arithmic Labs working on the research and development of an accelerator on FPGA. At present, I am a Master's By Research candidate at The University of Edinburgh, School of Informatics.