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Sifive rvv intrinsic temp #6

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Sifive rvv intrinsic temp #6

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386cca4
Mininal Support XSFVQMACC
Liaoshihua May 10, 2024
068706a
RISC-V: Add Xsfvqmacc extension intrinsics support.
yulong18 Sep 29, 2024
5a1a988
Drop blank lines
yulong18 Oct 8, 2024
8f9646a
Add mininal support for XSFVFNRCLIPXFQF extension
yulong18 Oct 15, 2024
e71de7e
Add intrinsic support for XSFVFNRCLIPXFQF extension
yulong18 Oct 25, 2024
b64528a
Rename intrinsics function basename
yulong18 Oct 29, 2024
be28eaa
Add some temporary test cases
yulong18 Oct 29, 2024
584fce9
Add V_SF_FNRCLIPXFQF and V_SF_FNRCLIP iterator
yulong18 Nov 4, 2024
0f05677
Add SiFive Vqmacc Extension testcase
Liaoshihua Nov 15, 2024
4770214
Add SiFive Vfnrclip Extension testcase
Liaoshihua Nov 15, 2024
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10 changes: 8 additions & 2 deletions gcc/common/config/riscv/riscv-common.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -429,6 +429,9 @@ static const struct riscv_ext_version riscv_ext_version_table[] =

{"xsfvcp", ISA_SPEC_CLASS_NONE, 1, 0},
{"xsfcease", ISA_SPEC_CLASS_NONE, 1, 0},
{"xsfvqmaccqoq", ISA_SPEC_CLASS_NONE, 1, 0},
{"xsfvqmaccdod", ISA_SPEC_CLASS_NONE, 1, 0},
{"xsfvfnrclipxfqf", ISA_SPEC_CLASS_NONE, 1, 0},

/* Terminate the list. */
{NULL, ISA_SPEC_CLASS_NONE, 0, 0}
Expand Down Expand Up @@ -1756,8 +1759,11 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =

RISCV_EXT_FLAG_ENTRY ("xventanacondops", x_riscv_xventana_subext, MASK_XVENTANACONDOPS),

RISCV_EXT_FLAG_ENTRY ("xsfvcp", x_riscv_sifive_subext, MASK_XSFVCP),
RISCV_EXT_FLAG_ENTRY ("xsfcease", x_riscv_sifive_subext, MASK_XSFCEASE),
RISCV_EXT_FLAG_ENTRY ("xsfvcp", x_riscv_sifive_subext, MASK_XSFVCP),
RISCV_EXT_FLAG_ENTRY ("xsfcease", x_riscv_sifive_subext, MASK_XSFCEASE),
RISCV_EXT_FLAG_ENTRY ("xsfvqmaccqoq", x_riscv_sifive_subext, MASK_XSFVQMACCQOQ),
RISCV_EXT_FLAG_ENTRY ("xsfvqmaccdod", x_riscv_sifive_subext, MASK_XSFVQMACCDOD),
RISCV_EXT_FLAG_ENTRY ("xsfvfnrclipxfqf", x_riscv_sifive_subext, MASK_XSFVFNRCLIPXFQF),

{NULL, NULL, NULL, 0}
};
Expand Down
3 changes: 2 additions & 1 deletion gcc/config/riscv/riscv-c.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -270,7 +270,8 @@ riscv_pragma_intrinsic (cpp_reader *)
const char *name = TREE_STRING_POINTER (x);

if (strcmp (name, "vector") == 0
|| strcmp (name, "xtheadvector") == 0)
|| strcmp (name, "xtheadvector") == 0
|| strcmp (name, "sifive_vector"))
{
struct pragma_intrinsic_flags backup_flags;

Expand Down
129 changes: 129 additions & 0 deletions gcc/config/riscv/riscv-vector-builtins-bases.cc
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Expand Up @@ -705,6 +705,35 @@ class vnclip : public function_base
}
};

/* Implements vfnrclip. */
class vfnrclip : public function_base
{
public:
bool has_merge_operand_p () const override { return false; }
bool can_be_overloaded_p (enum predication_type_index pred) const override
{
if (pred == PRED_TYPE_mu || pred == PRED_TYPE_tu || pred == PRED_TYPE_tumu)
{
return true;
}
}

rtx expand (function_expander &e) const override
{
if (e.op_info->op == OP_TYPE_x_f_qf)
{
return e.use_exact_insn (
code_for_pred_fnr_clip (ZERO_EXTEND, e.vector_mode ()));
}
if (e.op_info->op == OP_TYPE_xu_f_qf)
{
return e.use_exact_insn (
code_for_pred_fnr_clip_scalar (ZERO_EXTEND, e.vector_mode ()));
}
gcc_unreachable ();
}
};

/* Implements vmseq/vmsne/vmslt/vmsgt/vmsle/vmsge. */
template<rtx_code CODE>
class icmp : public function_base
Expand Down Expand Up @@ -869,6 +898,94 @@ class vwmaccus : public function_base
}
};

/* Implements vqmacc. */
class vqmacc : public function_base
{
public:
bool has_merge_operand_p () const override { return false; }
bool can_be_overloaded_p (enum predication_type_index pred) const override
{
return pred == PRED_TYPE_tu;
}

rtx expand (function_expander &e) const override
{
if (e.op_info->op == OP_TYPE_4x8x4)
return e.use_widen_ternop_insn (
code_for_pred_matrix_mul_plus_qoq (SIGN_EXTEND, e.vector_mode ()));
if (e.op_info->op == OP_TYPE_2x8x2)
return e.use_widen_ternop_insn (
code_for_pred_matrix_mul_plus_dod (SIGN_EXTEND, e.vector_mode ()));
gcc_unreachable ();
}
};

/* Implements vqmaccu. */
class vqmaccu : public function_base
{
public:
bool has_merge_operand_p () const override { return false; }
bool can_be_overloaded_p (enum predication_type_index pred) const override
{
return pred == PRED_TYPE_tu;
}

rtx expand (function_expander &e) const override
{
if (e.op_info->op == OP_TYPE_4x8x4)
return e.use_widen_ternop_insn (
code_for_pred_matrix_mul_plus_qoq (ZERO_EXTEND, e.vector_mode ()));
if (e.op_info->op == OP_TYPE_2x8x2)
return e.use_widen_ternop_insn (
code_for_pred_matrix_mul_plus_dod (SIGN_EXTEND, e.vector_mode ()));
gcc_unreachable ();
}
};

/* Implements vqmaccsu. */
class vqmaccsu : public function_base
{
public:
bool has_merge_operand_p () const override { return false; }
bool can_be_overloaded_p (enum predication_type_index pred) const override
{
return pred == PRED_TYPE_tu;
}

rtx expand (function_expander &e) const override
{
if (e.op_info->op == OP_TYPE_4x8x4)
return e.use_widen_ternop_insn (
code_for_pred_matrix_mul_plussu_qoq (e.vector_mode ()));
if (e.op_info->op == OP_TYPE_2x8x2)
return e.use_widen_ternop_insn (
code_for_pred_matrix_mul_plussu_dod (e.vector_mode ()));
gcc_unreachable ();
}
};

/* Implements vqmaccus. */
class vqmaccus : public function_base
{
public:
bool has_merge_operand_p () const override { return false; }
bool can_be_overloaded_p (enum predication_type_index pred) const override
{
return pred == PRED_TYPE_tu;
}

rtx expand (function_expander &e) const override
{
if (e.op_info->op == OP_TYPE_4x8x4)
return e.use_widen_ternop_insn (
code_for_pred_matrix_mul_plusus_qoq (e.vector_mode ()));
if (e.op_info->op == OP_TYPE_2x8x2)
return e.use_widen_ternop_insn (
code_for_pred_matrix_mul_plusus_dod (e.vector_mode ()));
gcc_unreachable ();
}
};

/* Implements vmand/vmnand/vmandn/vmxor/vmor/vmnor/vmorn/vmxnor */
template<rtx_code CODE>
class mask_logic : public function_base
Expand Down Expand Up @@ -2573,6 +2690,8 @@ static CONSTEXPR const sat_op<UNSPEC_VSSRL> vssrl_obj;
static CONSTEXPR const sat_op<UNSPEC_VSSRA> vssra_obj;
static CONSTEXPR const vnclip<UNSPEC_VNCLIP> vnclip_obj;
static CONSTEXPR const vnclip<UNSPEC_VNCLIPU> vnclipu_obj;
static CONSTEXPR const vfnrclip sf_vfnrclip_x_obj;
static CONSTEXPR const vfnrclip sf_vfnrclip_xu_obj;
static CONSTEXPR const mask_logic<AND> vmand_obj;
static CONSTEXPR const mask_nlogic<AND> vmnand_obj;
static CONSTEXPR const mask_notlogic<AND> vmandn_obj;
Expand Down Expand Up @@ -2762,6 +2881,10 @@ static CONSTEXPR const th_loadstore_width<true, LST_INDEXED, UNSPEC_TH_VSUXB> vs
static CONSTEXPR const th_loadstore_width<true, LST_INDEXED, UNSPEC_TH_VSUXH> vsuxh_obj;
static CONSTEXPR const th_loadstore_width<true, LST_INDEXED, UNSPEC_TH_VSUXW> vsuxw_obj;
static CONSTEXPR const th_extract vext_x_v_obj;
static CONSTEXPR const vqmacc sf_vqmacc_obj;
static CONSTEXPR const vqmaccu sf_vqmaccu_obj;
static CONSTEXPR const vqmaccsu sf_vqmaccsu_obj;
static CONSTEXPR const vqmaccsu sf_vqmaccus_obj;

/* Crypto Vector */
static CONSTEXPR const vandn vandn_obj;
Expand Down Expand Up @@ -2903,6 +3026,8 @@ BASE (vssra)
BASE (vssrl)
BASE (vnclip)
BASE (vnclipu)
BASE (sf_vfnrclip_x)
BASE (sf_vfnrclip_xu)
BASE (vmand)
BASE (vmnand)
BASE (vmandn)
Expand Down Expand Up @@ -3092,6 +3217,10 @@ BASE (vsuxb)
BASE (vsuxh)
BASE (vsuxw)
BASE (vext_x_v)
BASE (sf_vqmacc)
BASE (sf_vqmaccu)
BASE (sf_vqmaccsu)
BASE (sf_vqmaccus)
/* Crypto vector */
BASE (vandn)
BASE (vbrev)
Expand Down
6 changes: 6 additions & 0 deletions gcc/config/riscv/riscv-vector-builtins-bases.h
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Original file line number Diff line number Diff line change
Expand Up @@ -122,6 +122,8 @@ extern const function_base *const vssra;
extern const function_base *const vssrl;
extern const function_base *const vnclip;
extern const function_base *const vnclipu;
extern const function_base *const sf_vfnrclip_x;
extern const function_base *const sf_vfnrclip_xu;
extern const function_base *const vmand;
extern const function_base *const vmnand;
extern const function_base *const vmandn;
Expand Down Expand Up @@ -311,6 +313,10 @@ extern const function_base *const vsuxb;
extern const function_base *const vsuxh;
extern const function_base *const vsuxw;
extern const function_base *const vext_x_v;
extern const function_base *const sf_vqmacc;
extern const function_base *const sf_vqmaccu;
extern const function_base *const sf_vqmaccsu;
extern const function_base *const sf_vqmaccus;
/* Below function_base are Vectro Crypto*/
extern const function_base *const vandn;
extern const function_base *const vbrev;
Expand Down
69 changes: 69 additions & 0 deletions gcc/config/riscv/riscv-vector-builtins-shapes.cc
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Expand Up @@ -1287,6 +1287,73 @@ struct crypto_vv_no_op_type_def : public build_base
}
};

/* sf_vqmacc_def class. */
struct sf_vqmacc_def : public build_base
{
char *get_name (function_builder &b, const function_instance &instance,
bool overloaded_p) const override
{
/* Return nullptr if it can not be overloaded. */
if (overloaded_p && !instance.base->can_be_overloaded_p (instance.pred))
return nullptr;

b.append_base_name (instance.base_name);

/* vop_v --> vop_v_<type>. */
if (!overloaded_p)
{
/* vop --> vop_v. */
b.append_name (operand_suffixes[instance.op_info->op]);
/* vop_v --> vop_v_<type>. */
b.append_name (type_suffixes[instance.type.index].vector);
}

/* According to SIFIVE vector-intrinsic-doc, it does not add "_m" suffix
for vop_m C++ overloaded API.*/
if (overloaded_p && instance.pred == PRED_TYPE_tu)
{
b.append_name (predication_suffixes[instance.pred]);
}

return b.finish_name ();
}
};

/* sf_vfnrclip_def class. Handle instructions like vfnrclip. */
struct sf_vfnrclip_def : public build_base
{
char *get_name (function_builder &b, const function_instance &instance,
bool overloaded_p) const override
{
/* Return nullptr if it can not be overloaded. */
if (overloaded_p && !instance.base->can_be_overloaded_p (instance.pred))
return nullptr;

b.append_base_name (instance.base_name);

if (!overloaded_p)
{
/* vop --> vop_<op>. */
b.append_name ("_f_qf");
/* vop_v --> vop_v_<type>. */
b.append_name (type_suffixes[instance.type.index].vector);
Comment on lines +1338 to +1339
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indent

/* vop_<op> --> vop_<op>_<type>.
vector_type_index ret_type_idx
= instance.op_info->ret.get_function_type_index (instance.type.index);
b.append_name (type_suffixes[ret_type_idx].vector); */
Comment on lines +1340 to +1343
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Drop comment out code

}

/* According to rvv-intrinsic-doc, it does not add "_m" suffix
for vop_m C++ overloaded API.*/
if (overloaded_p && (instance.pred == PRED_TYPE_tu || instance.pred == PRED_TYPE_mu ||
instance.pred == PRED_TYPE_tumu))
Comment on lines +1348 to +1349
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Indent

{
b.append_name (predication_suffixes[instance.pred]);
}
return b.finish_name ();
}
};

SHAPE(vsetvl, vsetvl)
SHAPE(vsetvl, vsetvlmax)
SHAPE(loadstore, loadstore)
Expand Down Expand Up @@ -1321,4 +1388,6 @@ SHAPE(seg_fault_load, seg_fault_load)
SHAPE(crypto_vv, crypto_vv)
SHAPE(crypto_vi, crypto_vi)
SHAPE(crypto_vv_no_op_type, crypto_vv_no_op_type)
SHAPE(sf_vqmacc, sf_vqmacc)
SHAPE(sf_vfnrclip, sf_vfnrclip)
} // end namespace riscv_vector
2 changes: 2 additions & 0 deletions gcc/config/riscv/riscv-vector-builtins-shapes.h
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Expand Up @@ -59,6 +59,8 @@ extern const function_shape *const seg_fault_load;
extern const function_shape *const crypto_vv;
extern const function_shape *const crypto_vi;
extern const function_shape *const crypto_vv_no_op_type;
extern const function_shape *const sf_vqmacc;
extern const function_shape *const sf_vfnrclip;
}

} // end namespace riscv_vector
Expand Down
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