diff --git a/specs/sifive.com/MEM/RO/0.1.0/RO_rtl.json5 b/specs/sifive.com/MEM/RO/0.1.0/RO_rtl.json5 new file mode 100644 index 0000000..fc67bfa --- /dev/null +++ b/specs/sifive.com/MEM/RO/0.1.0/RO_rtl.json5 @@ -0,0 +1,60 @@ +{ + abstractionDefinition: { + vendor: 'sifive.com', + library: 'MEM', + name: 'RO_rtl', + version: '0.1.0', + busType: { + vendor: 'sifive.com', + library: 'MEM', + name: 'RO', + version: '0.1.0', + }, + ports: { + CLK: { + description: 'Memory clock', + requiresDriver: true, + isClock: true, + wire: { + onMaster: {width: 1, direction: 'in', presence: 'optional'}, + onSlave: {width: 1, direction: 'in', presence: 'optional'} + } + }, + RDEN: { + description: 'Read enable', + wire: { + onMaster: {width: 1, direction: 'out', presence: 'required'}, + onSlave: {width: 1, direction: 'in', presence: 'required'} + } + }, + BEN: { + description: 'Byte enable', + wire: { + onMaster: {width: 'BEN_WIDTH', direction: 'out', presence: 'optional'}, + onSlave: {width: 'BEN_WIDTH', direction: 'in', presence: 'optional'} + } + }, + ADDR: { + description: 'Read / Write port address', + wire: { + onMaster: {width: 'ADDR_WIDTH', direction: 'out', presence: 'required'}, + onSlave: {width: 'ADDR_WIDTH', direction: 'in', presence: 'required'} + } + }, + RDDATA: { + description: 'Read port data', + wire: { + onMaster: {width: 'DATA_WIDTH', direction: 'in', presence: 'required'}, + onSlave: {width: 'DATA_WIDTH', direction: 'out', presence: 'required'} + } + }, + RDERR: { + description: 'If ECC feature is present, this signals that an undorrectable error was detected on the read data', + wire: { + onMaster: {direction: 'in', presence: 'optional'}, + onSlave: {direction: 'out', presence: 'optional'} + } + } + } + } +} diff --git a/specs/sifive.com/MEM/WO/0.1.0/WO_rtl.json5 b/specs/sifive.com/MEM/WO/0.1.0/WO_rtl.json5 new file mode 100644 index 0000000..a867a8a --- /dev/null +++ b/specs/sifive.com/MEM/WO/0.1.0/WO_rtl.json5 @@ -0,0 +1,60 @@ +{ + abstractionDefinition: { + vendor: 'sifive.com', + library: 'MEM', + name: 'WO_rtl', + version: '0.1.0', + busType: { + vendor: 'sifive.com', + library: 'MEM', + name: 'WO', + version: '0.1.0', + }, + ports: { + CLK: { + description: 'Memory clock', + requiresDriver: true, + isClock: true, + wire: { + onMaster: {width: 1, direction: 'in', presence: 'optional'}, + onSlave: {width: 1, direction: 'in', presence: 'optional'} + } + }, + WREN: { + description: 'Write enable', + wire: { + onMaster: {width: 1, direction: 'out', presence: 'required'}, + onSlave: {width: 1, direction: 'in', presence: 'required'} + } + }, + BEN: { + description: 'Byte enable', + wire: { + onMaster: {width: 'BEN_WIDTH', direction: 'out', presence: 'optional'}, + onSlave: {width: 'BEN_WIDTH', direction: 'in', presence: 'optional'} + } + }, + ADDR: { + description: 'Read / Write port address', + wire: { + onMaster: {width: 'ADDR_WIDTH', direction: 'out', presence: 'required'}, + onSlave: {width: 'ADDR_WIDTH', direction: 'in', presence: 'required'} + } + }, + WRDATA: { + description: 'Write port data', + wire: { + onMaster: {width: 'DATA_WIDTH', direction: 'out', presence: 'required'}, + onSlave: {width: 'DATA_WIDTH', direction: 'in', presence: 'required'} + } + }, + RDERR: { + description: 'If ECC feature is present, this signals that an undorrectable error was detected on the read data', + wire: { + onMaster: {direction: 'in', presence: 'optional'}, + onSlave: {direction: 'out', presence: 'optional'} + } + } + } + } +}