Generate hardware for an FPGA

dohw.sh

@@ -0,0 +1 @@
+sbt "run --hw true --harnessName OpenSoC_CMeshTester_Random_Packet --numVCs 2 --moduleName OpenSoC_CMesh"

quartus/OpenSoC_CMesh.qsf

@@ -0,0 +1,58 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2019  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and any partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details, at
+# https://fpgasoftware.intel.com/eula.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+# Date created = 15:43:37  August 24, 2021
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		OpenSoC_CMesh_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus Prime software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone IV E"
+set_global_assignment -name DEVICE AUTO
+set_global_assignment -name TOP_LEVEL_ENTITY SimpleVCRouter_0
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 19.1.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:43:37  AUGUST 24, 2021"
+set_global_assignment -name LAST_QUARTUS_VERSION "19.1.0 Lite Edition"
+set_global_assignment -name VERILOG_FILE ../OpenSoC_CMesh.v
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
+set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

quartus/opensoc.qpf

@@ -0,0 +1,31 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2019  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and any partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details, at
+# https://fpgasoftware.intel.com/eula.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
+# Date created = 15:43:37  August 24, 2021
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "19.1"
+DATE = "15:43:37  August 24, 2021"
+
+# Revisions
+
+PROJECT_REVISION = "OpenSoC_CMesh"

src/main/scala/channel.scala

@@ -17,7 +17,7 @@ class HeadFlit(parms: Parameters) extends FlitCommon(parms) {
 	val packetTypeWidth   = parms.get[Int]("packetTypeWidth")
 	val destCordDim       = parms.get[Int]("destCordDim")
 	val destCordWidth     = parms.get[Int]("destCordWidth")
-	val numPriorityLevels = parms.get[Int]("numPriorityLevels") 
+	val numPriorityLevels = parms.get[Int]("numPriorityLevels")
 
 	val packetType        = UInt(width = packetTypeWidth)
 	val destination       = Vec.fill(destCordDim){UInt(width = destCordWidth)}

src/main/scala/main.scala

@@ -308,17 +308,26 @@ object OpenSoC {
 														("numVCs"->Hard(numVCs)),
 														("credThreshold"->Hard(1)),
 
-														("queueDepth"->Soft(16)),
+														// ("queueDepth"->Soft(16)),
+														("queueDepth"->Soft(4)),
 
-														("packetIDWidth"->Hard(16)),
+														// ("packetIDWidth"->Hard(16)),
+														// reduced to not have too many pins
+														("packetIDWidth"->Hard(4)),
 														("packetMaxLength"->Hard(16)),
 														("packetWidth"->Hard(32)),
 
 														("packetTypeWidth"->Hard(4)),
 														("destCordWidth"->Hard(Math.max(log2Up(K.max),log2Up(C)))),
 														("destCordDim"->Hard(Dim + C)),
 
-														("flitIDWidth"->Hard(4)),
+														// MS added
+														("numPriorityLevels"->Hard(8)),
+
+
+														//	("flitIDWidth"->Hard(4)),
+														// reduced to not have too many pins
+														("flitIDWidth"->Hard(2)),
 														("payloadWidth"->Hard(32)),
 														("InputFlitizer"->Soft((parms: Parameters) => new PacketToFlit(parms)))
 														)