Basic question about memory access patterns

[sms821]

Thank you for creating and releasing this tool. It helped me understand systolic array functionality to a large extent.

I have a basic question: after the simulation ends, the tool produces DRAM and SRAM read and write trace files. In each of these files, each line lists the memory addresses where data are read from/written to, for each computation cycle of the systolic array. These addresses are not consecutive in memory. This may be a basic question, but I wanted to understand how data are accessed from multiple distinct memory locations in the same processor clock cycle or how is this implemented in real hardware.

Additionally, the ISPASS paper associated with this work presents a number of energy consumption graphs based on Scale-Sim simulations. It would be great if you could shed some light on how these energy results were obtained.

Hope you can clarify my doubts. Thank you!

[Singhabhisheknitp]

I know it is quite late however while working on the project I jumped to this question so though of answering so that others could get clarity if they come around.

DRAM is suitable for dynamic random access and yes you can access any memory cell from DRAM , not necessarily in accessing block size fashion.

However in Computer architecture, our program exhibits great quotients of temporal/spatial locality and our cache access are made that way to fetch some block size, instead of single memory cell to use this to advantage.
so it is made as general architecture in all the computer system however not all the computer system would follow the same technique. Different custom architectures might have random single acesses and not in block