diff --git a/crates/core_arch/src/aarch64/neon/generated.rs b/crates/core_arch/src/aarch64/neon/generated.rs index 4af66039b8..82e196baad 100644 --- a/crates/core_arch/src/aarch64/neon/generated.rs +++ b/crates/core_arch/src/aarch64/neon/generated.rs @@ -14,14 +14,12 @@ use super::*; #[doc = "CRC32-C single round checksum for quad words (64 bits)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32cd)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "crc")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(crc32cx))] #[stable(feature = "stdarch_aarch64_crc32", since = "1.80.0")] -pub unsafe fn __crc32cd(crc: u32, data: u64) -> u32 { +pub fn __crc32cd(crc: u32, data: u64) -> u32 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -29,18 +27,16 @@ pub unsafe fn __crc32cd(crc: u32, data: u64) -> u32 { )] fn ___crc32cd(crc: u32, data: u64) -> u32; } - ___crc32cd(crc, data) + unsafe { ___crc32cd(crc, data) } } #[doc = "CRC32 single round checksum for quad words (64 bits)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32d)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "crc")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(crc32x))] #[stable(feature = "stdarch_aarch64_crc32", since = "1.80.0")] -pub unsafe fn __crc32d(crc: u32, data: u64) -> u32 { +pub fn __crc32d(crc: u32, data: u64) -> u32 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -48,104 +44,102 @@ pub unsafe fn __crc32d(crc: u32, data: u64) -> u32 { )] fn ___crc32d(crc: u32, data: u64) -> u32; } - ___crc32d(crc, data) + unsafe { ___crc32d(crc, data) } } #[doc = "Signed Absolute difference and Accumulate Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_high_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sabal))] -pub unsafe fn vabal_high_s8(a: int16x8_t, b: int8x16_t, c: int8x16_t) -> int16x8_t { - let d: int8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); - let e: int8x8_t = simd_shuffle!(c, c, [8, 9, 10, 11, 12, 13, 14, 15]); - let f: int8x8_t = vabd_s8(d, e); - let f: uint8x8_t = simd_cast(f); - simd_add(a, simd_cast(f)) +pub fn vabal_high_s8(a: int16x8_t, b: int8x16_t, c: int8x16_t) -> int16x8_t { + unsafe { + let d: int8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); + let e: int8x8_t = simd_shuffle!(c, c, [8, 9, 10, 11, 12, 13, 14, 15]); + let f: int8x8_t = vabd_s8(d, e); + let f: uint8x8_t = simd_cast(f); + simd_add(a, simd_cast(f)) + } } #[doc = "Signed Absolute difference and Accumulate Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_high_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sabal))] -pub unsafe fn vabal_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t { - let d: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); - let e: int16x4_t = simd_shuffle!(c, c, [4, 5, 6, 7]); - let f: int16x4_t = vabd_s16(d, e); - let f: uint16x4_t = simd_cast(f); - simd_add(a, simd_cast(f)) +pub fn vabal_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t { + unsafe { + let d: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); + let e: int16x4_t = simd_shuffle!(c, c, [4, 5, 6, 7]); + let f: int16x4_t = vabd_s16(d, e); + let f: uint16x4_t = simd_cast(f); + simd_add(a, simd_cast(f)) + } } #[doc = "Signed Absolute difference and Accumulate Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_high_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sabal))] -pub unsafe fn vabal_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t { - let d: int32x2_t = simd_shuffle!(b, b, [2, 3]); - let e: int32x2_t = simd_shuffle!(c, c, [2, 3]); - let f: int32x2_t = vabd_s32(d, e); - let f: uint32x2_t = simd_cast(f); - simd_add(a, simd_cast(f)) +pub fn vabal_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t { + unsafe { + let d: int32x2_t = simd_shuffle!(b, b, [2, 3]); + let e: int32x2_t = simd_shuffle!(c, c, [2, 3]); + let f: int32x2_t = vabd_s32(d, e); + let f: uint32x2_t = simd_cast(f); + simd_add(a, simd_cast(f)) + } } #[doc = "Unsigned Absolute difference and Accumulate Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_high_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uabal))] -pub unsafe fn vabal_high_u8(a: uint16x8_t, b: uint8x16_t, c: uint8x16_t) -> uint16x8_t { - let d: uint8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); - let e: uint8x8_t = simd_shuffle!(c, c, [8, 9, 10, 11, 12, 13, 14, 15]); - let f: uint8x8_t = vabd_u8(d, e); - simd_add(a, simd_cast(f)) +pub fn vabal_high_u8(a: uint16x8_t, b: uint8x16_t, c: uint8x16_t) -> uint16x8_t { + unsafe { + let d: uint8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); + let e: uint8x8_t = simd_shuffle!(c, c, [8, 9, 10, 11, 12, 13, 14, 15]); + let f: uint8x8_t = vabd_u8(d, e); + simd_add(a, simd_cast(f)) + } } #[doc = "Unsigned Absolute difference and Accumulate Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_high_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uabal))] -pub unsafe fn vabal_high_u16(a: uint32x4_t, b: uint16x8_t, c: uint16x8_t) -> uint32x4_t { - let d: uint16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); - let e: uint16x4_t = simd_shuffle!(c, c, [4, 5, 6, 7]); - let f: uint16x4_t = vabd_u16(d, e); - simd_add(a, simd_cast(f)) +pub fn vabal_high_u16(a: uint32x4_t, b: uint16x8_t, c: uint16x8_t) -> uint32x4_t { + unsafe { + let d: uint16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); + let e: uint16x4_t = simd_shuffle!(c, c, [4, 5, 6, 7]); + let f: uint16x4_t = vabd_u16(d, e); + simd_add(a, simd_cast(f)) + } } #[doc = "Unsigned Absolute difference and Accumulate Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_high_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uabal))] -pub unsafe fn vabal_high_u32(a: uint64x2_t, b: uint32x4_t, c: uint32x4_t) -> uint64x2_t { - let d: uint32x2_t = simd_shuffle!(b, b, [2, 3]); - let e: uint32x2_t = simd_shuffle!(c, c, [2, 3]); - let f: uint32x2_t = vabd_u32(d, e); - simd_add(a, simd_cast(f)) +pub fn vabal_high_u32(a: uint64x2_t, b: uint32x4_t, c: uint32x4_t) -> uint64x2_t { + unsafe { + let d: uint32x2_t = simd_shuffle!(b, b, [2, 3]); + let e: uint32x2_t = simd_shuffle!(c, c, [2, 3]); + let f: uint32x2_t = vabd_u32(d, e); + simd_add(a, simd_cast(f)) + } } #[doc = "Absolute difference between the arguments of Floating"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fabd))] -pub unsafe fn vabd_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { +pub fn vabd_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -153,17 +147,15 @@ pub unsafe fn vabd_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { )] fn _vabd_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t; } - _vabd_f64(a, b) + unsafe { _vabd_f64(a, b) } } #[doc = "Absolute difference between the arguments of Floating"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fabd))] -pub unsafe fn vabdq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { +pub fn vabdq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -171,153 +163,141 @@ pub unsafe fn vabdq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { )] fn _vabdq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t; } - _vabdq_f64(a, b) + unsafe { _vabdq_f64(a, b) } } #[doc = "Floating-point absolute difference"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdd_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fabd))] -pub unsafe fn vabdd_f64(a: f64, b: f64) -> f64 { - simd_extract!(vabd_f64(vdup_n_f64(a), vdup_n_f64(b)), 0) +pub fn vabdd_f64(a: f64, b: f64) -> f64 { + unsafe { simd_extract!(vabd_f64(vdup_n_f64(a), vdup_n_f64(b)), 0) } } #[doc = "Floating-point absolute difference"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabds_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fabd))] -pub unsafe fn vabds_f32(a: f32, b: f32) -> f32 { - simd_extract!(vabd_f32(vdup_n_f32(a), vdup_n_f32(b)), 0) +pub fn vabds_f32(a: f32, b: f32) -> f32 { + unsafe { simd_extract!(vabd_f32(vdup_n_f32(a), vdup_n_f32(b)), 0) } } #[doc = "Floating-point absolute difference"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdh_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(fabd))] -pub unsafe fn vabdh_f16(a: f16, b: f16) -> f16 { - simd_extract!(vabd_f16(vdup_n_f16(a), vdup_n_f16(b)), 0) +pub fn vabdh_f16(a: f16, b: f16) -> f16 { + unsafe { simd_extract!(vabd_f16(vdup_n_f16(a), vdup_n_f16(b)), 0) } } #[doc = "Signed Absolute difference Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(sabdl))] -pub unsafe fn vabdl_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t { - let c: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); - let d: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); - let e: uint16x4_t = simd_cast(vabd_s16(c, d)); - simd_cast(e) +pub fn vabdl_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t { + unsafe { + let c: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); + let d: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); + let e: uint16x4_t = simd_cast(vabd_s16(c, d)); + simd_cast(e) + } } #[doc = "Signed Absolute difference Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(sabdl))] -pub unsafe fn vabdl_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t { - let c: int32x2_t = simd_shuffle!(a, a, [2, 3]); - let d: int32x2_t = simd_shuffle!(b, b, [2, 3]); - let e: uint32x2_t = simd_cast(vabd_s32(c, d)); - simd_cast(e) +pub fn vabdl_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t { + unsafe { + let c: int32x2_t = simd_shuffle!(a, a, [2, 3]); + let d: int32x2_t = simd_shuffle!(b, b, [2, 3]); + let e: uint32x2_t = simd_cast(vabd_s32(c, d)); + simd_cast(e) + } } #[doc = "Signed Absolute difference Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(sabdl))] -pub unsafe fn vabdl_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t { - let c: int8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); - let d: int8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); - let e: uint8x8_t = simd_cast(vabd_s8(c, d)); - simd_cast(e) +pub fn vabdl_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t { + unsafe { + let c: int8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); + let d: int8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); + let e: uint8x8_t = simd_cast(vabd_s8(c, d)); + simd_cast(e) + } } #[doc = "Unsigned Absolute difference Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(uabdl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vabdl_high_u8(a: uint8x16_t, b: uint8x16_t) -> uint16x8_t { - let c: uint8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); - let d: uint8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); - simd_cast(vabd_u8(c, d)) +pub fn vabdl_high_u8(a: uint8x16_t, b: uint8x16_t) -> uint16x8_t { + unsafe { + let c: uint8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); + let d: uint8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); + simd_cast(vabd_u8(c, d)) + } } #[doc = "Unsigned Absolute difference Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(uabdl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vabdl_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t { - let c: uint16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); - let d: uint16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); - simd_cast(vabd_u16(c, d)) +pub fn vabdl_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t { + unsafe { + let c: uint16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); + let d: uint16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); + simd_cast(vabd_u16(c, d)) + } } #[doc = "Unsigned Absolute difference Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(uabdl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vabdl_high_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t { - let c: uint32x2_t = simd_shuffle!(a, a, [2, 3]); - let d: uint32x2_t = simd_shuffle!(b, b, [2, 3]); - simd_cast(vabd_u32(c, d)) +pub fn vabdl_high_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t { + unsafe { + let c: uint32x2_t = simd_shuffle!(a, a, [2, 3]); + let d: uint32x2_t = simd_shuffle!(b, b, [2, 3]); + simd_cast(vabd_u32(c, d)) + } } #[doc = "Floating-point absolute value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fabs))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vabs_f64(a: float64x1_t) -> float64x1_t { - simd_fabs(a) +pub fn vabs_f64(a: float64x1_t) -> float64x1_t { + unsafe { simd_fabs(a) } } #[doc = "Floating-point absolute value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fabs))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vabsq_f64(a: float64x2_t) -> float64x2_t { - simd_fabs(a) +pub fn vabsq_f64(a: float64x2_t) -> float64x2_t { + unsafe { simd_fabs(a) } } #[doc = "Absolute Value (wrapping)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(abs))] -pub unsafe fn vabs_s64(a: int64x1_t) -> int64x1_t { +pub fn vabs_s64(a: int64x1_t) -> int64x1_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -325,17 +305,15 @@ pub unsafe fn vabs_s64(a: int64x1_t) -> int64x1_t { )] fn _vabs_s64(a: int64x1_t) -> int64x1_t; } - _vabs_s64(a) + unsafe { _vabs_s64(a) } } #[doc = "Absolute Value (wrapping)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsd_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(abs))] -pub unsafe fn vabsd_s64(a: i64) -> i64 { +pub fn vabsd_s64(a: i64) -> i64 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -343,17 +321,15 @@ pub unsafe fn vabsd_s64(a: i64) -> i64 { )] fn _vabsd_s64(a: i64) -> i64; } - _vabsd_s64(a) + unsafe { _vabsd_s64(a) } } #[doc = "Absolute Value (wrapping)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(abs))] -pub unsafe fn vabsq_s64(a: int64x2_t) -> int64x2_t { +pub fn vabsq_s64(a: int64x2_t) -> int64x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -361,39 +337,33 @@ pub unsafe fn vabsq_s64(a: int64x2_t) -> int64x2_t { )] fn _vabsq_s64(a: int64x2_t) -> int64x2_t; } - _vabsq_s64(a) + unsafe { _vabsq_s64(a) } } #[doc = "Add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddd_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vaddd_s64(a: i64, b: i64) -> i64 { +pub fn vaddd_s64(a: i64, b: i64) -> i64 { a.wrapping_add(b) } #[doc = "Add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddd_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vaddd_u64(a: u64, b: u64) -> u64 { +pub fn vaddd_u64(a: u64, b: u64) -> u64 { a.wrapping_add(b) } #[doc = "Signed Add Long across Vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlv_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(saddlv))] -pub unsafe fn vaddlv_s16(a: int16x4_t) -> i32 { +pub fn vaddlv_s16(a: int16x4_t) -> i32 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -401,17 +371,15 @@ pub unsafe fn vaddlv_s16(a: int16x4_t) -> i32 { )] fn _vaddlv_s16(a: int16x4_t) -> i32; } - _vaddlv_s16(a) + unsafe { _vaddlv_s16(a) } } #[doc = "Signed Add Long across Vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlvq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(saddlv))] -pub unsafe fn vaddlvq_s16(a: int16x8_t) -> i32 { +pub fn vaddlvq_s16(a: int16x8_t) -> i32 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -419,17 +387,15 @@ pub unsafe fn vaddlvq_s16(a: int16x8_t) -> i32 { )] fn _vaddlvq_s16(a: int16x8_t) -> i32; } - _vaddlvq_s16(a) + unsafe { _vaddlvq_s16(a) } } #[doc = "Signed Add Long across Vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlvq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(saddlv))] -pub unsafe fn vaddlvq_s32(a: int32x4_t) -> i64 { +pub fn vaddlvq_s32(a: int32x4_t) -> i64 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -437,17 +403,15 @@ pub unsafe fn vaddlvq_s32(a: int32x4_t) -> i64 { )] fn _vaddlvq_s32(a: int32x4_t) -> i64; } - _vaddlvq_s32(a) + unsafe { _vaddlvq_s32(a) } } #[doc = "Signed Add Long across Vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlv_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(saddlp))] -pub unsafe fn vaddlv_s32(a: int32x2_t) -> i64 { +pub fn vaddlv_s32(a: int32x2_t) -> i64 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -455,17 +419,15 @@ pub unsafe fn vaddlv_s32(a: int32x2_t) -> i64 { )] fn _vaddlv_s32(a: int32x2_t) -> i64; } - _vaddlv_s32(a) + unsafe { _vaddlv_s32(a) } } #[doc = "Signed Add Long across Vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlv_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(saddlv))] -pub unsafe fn vaddlv_s8(a: int8x8_t) -> i16 { +pub fn vaddlv_s8(a: int8x8_t) -> i16 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -473,17 +435,15 @@ pub unsafe fn vaddlv_s8(a: int8x8_t) -> i16 { )] fn _vaddlv_s8(a: int8x8_t) -> i32; } - _vaddlv_s8(a) as i16 + unsafe { _vaddlv_s8(a) as i16 } } #[doc = "Signed Add Long across Vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlvq_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(saddlv))] -pub unsafe fn vaddlvq_s8(a: int8x16_t) -> i16 { +pub fn vaddlvq_s8(a: int8x16_t) -> i16 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -491,17 +451,15 @@ pub unsafe fn vaddlvq_s8(a: int8x16_t) -> i16 { )] fn _vaddlvq_s8(a: int8x16_t) -> i32; } - _vaddlvq_s8(a) as i16 + unsafe { _vaddlvq_s8(a) as i16 } } #[doc = "Unsigned Add Long across Vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlv_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(uaddlv))] -pub unsafe fn vaddlv_u16(a: uint16x4_t) -> u32 { +pub fn vaddlv_u16(a: uint16x4_t) -> u32 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -509,17 +467,15 @@ pub unsafe fn vaddlv_u16(a: uint16x4_t) -> u32 { )] fn _vaddlv_u16(a: uint16x4_t) -> u32; } - _vaddlv_u16(a) + unsafe { _vaddlv_u16(a) } } #[doc = "Unsigned Add Long across Vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlvq_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(uaddlv))] -pub unsafe fn vaddlvq_u16(a: uint16x8_t) -> u32 { +pub fn vaddlvq_u16(a: uint16x8_t) -> u32 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -527,17 +483,15 @@ pub unsafe fn vaddlvq_u16(a: uint16x8_t) -> u32 { )] fn _vaddlvq_u16(a: uint16x8_t) -> u32; } - _vaddlvq_u16(a) + unsafe { _vaddlvq_u16(a) } } #[doc = "Unsigned Add Long across Vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlvq_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(uaddlv))] -pub unsafe fn vaddlvq_u32(a: uint32x4_t) -> u64 { +pub fn vaddlvq_u32(a: uint32x4_t) -> u64 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -545,17 +499,15 @@ pub unsafe fn vaddlvq_u32(a: uint32x4_t) -> u64 { )] fn _vaddlvq_u32(a: uint32x4_t) -> u64; } - _vaddlvq_u32(a) + unsafe { _vaddlvq_u32(a) } } #[doc = "Unsigned Add Long across Vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlv_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(uaddlp))] -pub unsafe fn vaddlv_u32(a: uint32x2_t) -> u64 { +pub fn vaddlv_u32(a: uint32x2_t) -> u64 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -563,17 +515,15 @@ pub unsafe fn vaddlv_u32(a: uint32x2_t) -> u64 { )] fn _vaddlv_u32(a: uint32x2_t) -> u64; } - _vaddlv_u32(a) + unsafe { _vaddlv_u32(a) } } #[doc = "Unsigned Add Long across Vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlv_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(uaddlv))] -pub unsafe fn vaddlv_u8(a: uint8x8_t) -> u16 { +pub fn vaddlv_u8(a: uint8x8_t) -> u16 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -581,17 +531,15 @@ pub unsafe fn vaddlv_u8(a: uint8x8_t) -> u16 { )] fn _vaddlv_u8(a: uint8x8_t) -> i32; } - _vaddlv_u8(a) as u16 + unsafe { _vaddlv_u8(a) as u16 } } #[doc = "Unsigned Add Long across Vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlvq_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(uaddlv))] -pub unsafe fn vaddlvq_u8(a: uint8x16_t) -> u16 { +pub fn vaddlvq_u8(a: uint8x16_t) -> u16 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -599,17 +547,15 @@ pub unsafe fn vaddlvq_u8(a: uint8x16_t) -> u16 { )] fn _vaddlvq_u8(a: uint8x16_t) -> i32; } - _vaddlvq_u8(a) as u16 + unsafe { _vaddlvq_u8(a) as u16 } } #[doc = "Floating-point add across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddv_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(faddp))] -pub unsafe fn vaddv_f32(a: float32x2_t) -> f32 { +pub fn vaddv_f32(a: float32x2_t) -> f32 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -617,17 +563,15 @@ pub unsafe fn vaddv_f32(a: float32x2_t) -> f32 { )] fn _vaddv_f32(a: float32x2_t) -> f32; } - _vaddv_f32(a) + unsafe { _vaddv_f32(a) } } #[doc = "Floating-point add across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(faddp))] -pub unsafe fn vaddvq_f32(a: float32x4_t) -> f32 { +pub fn vaddvq_f32(a: float32x4_t) -> f32 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -635,17 +579,15 @@ pub unsafe fn vaddvq_f32(a: float32x4_t) -> f32 { )] fn _vaddvq_f32(a: float32x4_t) -> f32; } - _vaddvq_f32(a) + unsafe { _vaddvq_f32(a) } } #[doc = "Floating-point add across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(faddp))] -pub unsafe fn vaddvq_f64(a: float64x2_t) -> f64 { +pub fn vaddvq_f64(a: float64x2_t) -> f64 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -653,17 +595,15 @@ pub unsafe fn vaddvq_f64(a: float64x2_t) -> f64 { )] fn _vaddvq_f64(a: float64x2_t) -> f64; } - _vaddvq_f64(a) + unsafe { _vaddvq_f64(a) } } #[doc = "Add across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddv_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addp))] -pub unsafe fn vaddv_s32(a: int32x2_t) -> i32 { +pub fn vaddv_s32(a: int32x2_t) -> i32 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -671,17 +611,15 @@ pub unsafe fn vaddv_s32(a: int32x2_t) -> i32 { )] fn _vaddv_s32(a: int32x2_t) -> i32; } - _vaddv_s32(a) + unsafe { _vaddv_s32(a) } } #[doc = "Add across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddv_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addv))] -pub unsafe fn vaddv_s8(a: int8x8_t) -> i8 { +pub fn vaddv_s8(a: int8x8_t) -> i8 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -689,17 +627,15 @@ pub unsafe fn vaddv_s8(a: int8x8_t) -> i8 { )] fn _vaddv_s8(a: int8x8_t) -> i8; } - _vaddv_s8(a) + unsafe { _vaddv_s8(a) } } #[doc = "Add across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addv))] -pub unsafe fn vaddvq_s8(a: int8x16_t) -> i8 { +pub fn vaddvq_s8(a: int8x16_t) -> i8 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -707,17 +643,15 @@ pub unsafe fn vaddvq_s8(a: int8x16_t) -> i8 { )] fn _vaddvq_s8(a: int8x16_t) -> i8; } - _vaddvq_s8(a) + unsafe { _vaddvq_s8(a) } } #[doc = "Add across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddv_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addv))] -pub unsafe fn vaddv_s16(a: int16x4_t) -> i16 { +pub fn vaddv_s16(a: int16x4_t) -> i16 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -725,17 +659,15 @@ pub unsafe fn vaddv_s16(a: int16x4_t) -> i16 { )] fn _vaddv_s16(a: int16x4_t) -> i16; } - _vaddv_s16(a) + unsafe { _vaddv_s16(a) } } #[doc = "Add across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addv))] -pub unsafe fn vaddvq_s16(a: int16x8_t) -> i16 { +pub fn vaddvq_s16(a: int16x8_t) -> i16 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -743,17 +675,15 @@ pub unsafe fn vaddvq_s16(a: int16x8_t) -> i16 { )] fn _vaddvq_s16(a: int16x8_t) -> i16; } - _vaddvq_s16(a) + unsafe { _vaddvq_s16(a) } } #[doc = "Add across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addv))] -pub unsafe fn vaddvq_s32(a: int32x4_t) -> i32 { +pub fn vaddvq_s32(a: int32x4_t) -> i32 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -761,17 +691,15 @@ pub unsafe fn vaddvq_s32(a: int32x4_t) -> i32 { )] fn _vaddvq_s32(a: int32x4_t) -> i32; } - _vaddvq_s32(a) + unsafe { _vaddvq_s32(a) } } #[doc = "Add across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddv_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addp))] -pub unsafe fn vaddv_u32(a: uint32x2_t) -> u32 { +pub fn vaddv_u32(a: uint32x2_t) -> u32 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -779,17 +707,15 @@ pub unsafe fn vaddv_u32(a: uint32x2_t) -> u32 { )] fn _vaddv_u32(a: uint32x2_t) -> u32; } - _vaddv_u32(a) + unsafe { _vaddv_u32(a) } } #[doc = "Add across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddv_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addv))] -pub unsafe fn vaddv_u8(a: uint8x8_t) -> u8 { +pub fn vaddv_u8(a: uint8x8_t) -> u8 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -797,17 +723,15 @@ pub unsafe fn vaddv_u8(a: uint8x8_t) -> u8 { )] fn _vaddv_u8(a: uint8x8_t) -> u8; } - _vaddv_u8(a) + unsafe { _vaddv_u8(a) } } #[doc = "Add across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addv))] -pub unsafe fn vaddvq_u8(a: uint8x16_t) -> u8 { +pub fn vaddvq_u8(a: uint8x16_t) -> u8 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -815,17 +739,15 @@ pub unsafe fn vaddvq_u8(a: uint8x16_t) -> u8 { )] fn _vaddvq_u8(a: uint8x16_t) -> u8; } - _vaddvq_u8(a) + unsafe { _vaddvq_u8(a) } } #[doc = "Add across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddv_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addv))] -pub unsafe fn vaddv_u16(a: uint16x4_t) -> u16 { +pub fn vaddv_u16(a: uint16x4_t) -> u16 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -833,17 +755,15 @@ pub unsafe fn vaddv_u16(a: uint16x4_t) -> u16 { )] fn _vaddv_u16(a: uint16x4_t) -> u16; } - _vaddv_u16(a) + unsafe { _vaddv_u16(a) } } #[doc = "Add across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addv))] -pub unsafe fn vaddvq_u16(a: uint16x8_t) -> u16 { +pub fn vaddvq_u16(a: uint16x8_t) -> u16 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -851,17 +771,15 @@ pub unsafe fn vaddvq_u16(a: uint16x8_t) -> u16 { )] fn _vaddvq_u16(a: uint16x8_t) -> u16; } - _vaddvq_u16(a) + unsafe { _vaddvq_u16(a) } } #[doc = "Add across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addv))] -pub unsafe fn vaddvq_u32(a: uint32x4_t) -> u32 { +pub fn vaddvq_u32(a: uint32x4_t) -> u32 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -869,17 +787,15 @@ pub unsafe fn vaddvq_u32(a: uint32x4_t) -> u32 { )] fn _vaddvq_u32(a: uint32x4_t) -> u32; } - _vaddvq_u32(a) + unsafe { _vaddvq_u32(a) } } #[doc = "Add across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addp))] -pub unsafe fn vaddvq_s64(a: int64x2_t) -> i64 { +pub fn vaddvq_s64(a: int64x2_t) -> i64 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -887,17 +803,15 @@ pub unsafe fn vaddvq_s64(a: int64x2_t) -> i64 { )] fn _vaddvq_s64(a: int64x2_t) -> i64; } - _vaddvq_s64(a) + unsafe { _vaddvq_s64(a) } } #[doc = "Add across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addp))] -pub unsafe fn vaddvq_u64(a: uint64x2_t) -> u64 { +pub fn vaddvq_u64(a: uint64x2_t) -> u64 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -905,17 +819,15 @@ pub unsafe fn vaddvq_u64(a: uint64x2_t) -> u64 { )] fn _vaddvq_u64(a: uint64x2_t) -> u64; } - _vaddvq_u64(a) + unsafe { _vaddvq_u64(a) } } #[doc = "Bit clear and exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbcaxq_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,sha3")] #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] #[cfg_attr(test, assert_instr(bcax))] -pub unsafe fn vbcaxq_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t { +pub fn vbcaxq_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -923,17 +835,15 @@ pub unsafe fn vbcaxq_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t { )] fn _vbcaxq_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t; } - _vbcaxq_s8(a, b, c) + unsafe { _vbcaxq_s8(a, b, c) } } #[doc = "Bit clear and exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbcaxq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,sha3")] #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] #[cfg_attr(test, assert_instr(bcax))] -pub unsafe fn vbcaxq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t { +pub fn vbcaxq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -941,17 +851,15 @@ pub unsafe fn vbcaxq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t )] fn _vbcaxq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t; } - _vbcaxq_s16(a, b, c) + unsafe { _vbcaxq_s16(a, b, c) } } #[doc = "Bit clear and exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbcaxq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,sha3")] #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] #[cfg_attr(test, assert_instr(bcax))] -pub unsafe fn vbcaxq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t { +pub fn vbcaxq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -959,17 +867,15 @@ pub unsafe fn vbcaxq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t )] fn _vbcaxq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t; } - _vbcaxq_s32(a, b, c) + unsafe { _vbcaxq_s32(a, b, c) } } #[doc = "Bit clear and exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbcaxq_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,sha3")] #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] #[cfg_attr(test, assert_instr(bcax))] -pub unsafe fn vbcaxq_s64(a: int64x2_t, b: int64x2_t, c: int64x2_t) -> int64x2_t { +pub fn vbcaxq_s64(a: int64x2_t, b: int64x2_t, c: int64x2_t) -> int64x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -977,17 +883,15 @@ pub unsafe fn vbcaxq_s64(a: int64x2_t, b: int64x2_t, c: int64x2_t) -> int64x2_t )] fn _vbcaxq_s64(a: int64x2_t, b: int64x2_t, c: int64x2_t) -> int64x2_t; } - _vbcaxq_s64(a, b, c) + unsafe { _vbcaxq_s64(a, b, c) } } #[doc = "Bit clear and exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbcaxq_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,sha3")] #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] #[cfg_attr(test, assert_instr(bcax))] -pub unsafe fn vbcaxq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t { +pub fn vbcaxq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -995,17 +899,15 @@ pub unsafe fn vbcaxq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16 )] fn _vbcaxq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t; } - _vbcaxq_u8(a, b, c) + unsafe { _vbcaxq_u8(a, b, c) } } #[doc = "Bit clear and exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbcaxq_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,sha3")] #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] #[cfg_attr(test, assert_instr(bcax))] -pub unsafe fn vbcaxq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t { +pub fn vbcaxq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -1013,17 +915,15 @@ pub unsafe fn vbcaxq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x )] fn _vbcaxq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t; } - _vbcaxq_u16(a, b, c) + unsafe { _vbcaxq_u16(a, b, c) } } #[doc = "Bit clear and exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbcaxq_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,sha3")] #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] #[cfg_attr(test, assert_instr(bcax))] -pub unsafe fn vbcaxq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t { +pub fn vbcaxq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -1031,17 +931,15 @@ pub unsafe fn vbcaxq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x )] fn _vbcaxq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t; } - _vbcaxq_u32(a, b, c) + unsafe { _vbcaxq_u32(a, b, c) } } #[doc = "Bit clear and exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbcaxq_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,sha3")] #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] #[cfg_attr(test, assert_instr(bcax))] -pub unsafe fn vbcaxq_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t { +pub fn vbcaxq_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -1049,18 +947,16 @@ pub unsafe fn vbcaxq_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x )] fn _vbcaxq_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t; } - _vbcaxq_u64(a, b, c) + unsafe { _vbcaxq_u64(a, b, c) } } #[doc = "Floating-point complex add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcadd_rot270_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fcma"))] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(fcadd))] -pub unsafe fn vcadd_rot270_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { +pub fn vcadd_rot270_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -1068,18 +964,16 @@ pub unsafe fn vcadd_rot270_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { )] fn _vcadd_rot270_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t; } - _vcadd_rot270_f16(a, b) + unsafe { _vcadd_rot270_f16(a, b) } } #[doc = "Floating-point complex add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaddq_rot270_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fcma"))] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(fcadd))] -pub unsafe fn vcaddq_rot270_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { +pub fn vcaddq_rot270_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -1087,17 +981,15 @@ pub unsafe fn vcaddq_rot270_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { )] fn _vcaddq_rot270_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t; } - _vcaddq_rot270_f16(a, b) + unsafe { _vcaddq_rot270_f16(a, b) } } #[doc = "Floating-point complex add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcadd_rot270_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fcma")] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] #[cfg_attr(test, assert_instr(fcadd))] -pub unsafe fn vcadd_rot270_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { +pub fn vcadd_rot270_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -1105,17 +997,15 @@ pub unsafe fn vcadd_rot270_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { )] fn _vcadd_rot270_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t; } - _vcadd_rot270_f32(a, b) + unsafe { _vcadd_rot270_f32(a, b) } } #[doc = "Floating-point complex add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaddq_rot270_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fcma")] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] #[cfg_attr(test, assert_instr(fcadd))] -pub unsafe fn vcaddq_rot270_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { +pub fn vcaddq_rot270_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -1123,17 +1013,15 @@ pub unsafe fn vcaddq_rot270_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { )] fn _vcaddq_rot270_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t; } - _vcaddq_rot270_f32(a, b) + unsafe { _vcaddq_rot270_f32(a, b) } } #[doc = "Floating-point complex add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaddq_rot270_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fcma")] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] #[cfg_attr(test, assert_instr(fcadd))] -pub unsafe fn vcaddq_rot270_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { +pub fn vcaddq_rot270_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -1141,18 +1029,16 @@ pub unsafe fn vcaddq_rot270_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { )] fn _vcaddq_rot270_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t; } - _vcaddq_rot270_f64(a, b) + unsafe { _vcaddq_rot270_f64(a, b) } } #[doc = "Floating-point complex add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcadd_rot90_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fcma"))] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(fcadd))] -pub unsafe fn vcadd_rot90_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { +pub fn vcadd_rot90_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -1160,18 +1046,16 @@ pub unsafe fn vcadd_rot90_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { )] fn _vcadd_rot90_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t; } - _vcadd_rot90_f16(a, b) + unsafe { _vcadd_rot90_f16(a, b) } } #[doc = "Floating-point complex add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaddq_rot90_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fcma"))] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(fcadd))] -pub unsafe fn vcaddq_rot90_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { +pub fn vcaddq_rot90_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -1179,17 +1063,15 @@ pub unsafe fn vcaddq_rot90_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { )] fn _vcaddq_rot90_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t; } - _vcaddq_rot90_f16(a, b) + unsafe { _vcaddq_rot90_f16(a, b) } } #[doc = "Floating-point complex add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcadd_rot90_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fcma")] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] #[cfg_attr(test, assert_instr(fcadd))] -pub unsafe fn vcadd_rot90_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { +pub fn vcadd_rot90_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -1197,17 +1079,15 @@ pub unsafe fn vcadd_rot90_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { )] fn _vcadd_rot90_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t; } - _vcadd_rot90_f32(a, b) + unsafe { _vcadd_rot90_f32(a, b) } } #[doc = "Floating-point complex add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaddq_rot90_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fcma")] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] #[cfg_attr(test, assert_instr(fcadd))] -pub unsafe fn vcaddq_rot90_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { +pub fn vcaddq_rot90_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -1215,17 +1095,15 @@ pub unsafe fn vcaddq_rot90_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { )] fn _vcaddq_rot90_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t; } - _vcaddq_rot90_f32(a, b) + unsafe { _vcaddq_rot90_f32(a, b) } } #[doc = "Floating-point complex add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaddq_rot90_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fcma")] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] #[cfg_attr(test, assert_instr(fcadd))] -pub unsafe fn vcaddq_rot90_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { +pub fn vcaddq_rot90_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -1233,17 +1111,15 @@ pub unsafe fn vcaddq_rot90_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { )] fn _vcaddq_rot90_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t; } - _vcaddq_rot90_f64(a, b) + unsafe { _vcaddq_rot90_f64(a, b) } } #[doc = "Floating-point absolute compare greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcage_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(facge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcage_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { +pub fn vcage_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -1251,17 +1127,15 @@ pub unsafe fn vcage_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { )] fn _vcage_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t; } - _vcage_f64(a, b) + unsafe { _vcage_f64(a, b) } } #[doc = "Floating-point absolute compare greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcageq_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(facge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcageq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { +pub fn vcageq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -1269,17 +1143,15 @@ pub unsafe fn vcageq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { )] fn _vcageq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t; } - _vcageq_f64(a, b) + unsafe { _vcageq_f64(a, b) } } #[doc = "Floating-point absolute compare greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaged_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(facge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcaged_f64(a: f64, b: f64) -> u64 { +pub fn vcaged_f64(a: f64, b: f64) -> u64 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -1287,17 +1159,15 @@ pub unsafe fn vcaged_f64(a: f64, b: f64) -> u64 { )] fn _vcaged_f64(a: f64, b: f64) -> u64; } - _vcaged_f64(a, b) + unsafe { _vcaged_f64(a, b) } } #[doc = "Floating-point absolute compare greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcages_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(facge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcages_f32(a: f32, b: f32) -> u32 { +pub fn vcages_f32(a: f32, b: f32) -> u32 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -1305,17 +1175,15 @@ pub unsafe fn vcages_f32(a: f32, b: f32) -> u32 { )] fn _vcages_f32(a: f32, b: f32) -> u32; } - _vcages_f32(a, b) + unsafe { _vcages_f32(a, b) } } #[doc = "Floating-point absolute compare greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcageh_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(facge))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcageh_f16(a: f16, b: f16) -> u16 { +pub fn vcageh_f16(a: f16, b: f16) -> u16 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -1323,17 +1191,15 @@ pub unsafe fn vcageh_f16(a: f16, b: f16) -> u16 { )] fn _vcageh_f16(a: f16, b: f16) -> i32; } - _vcageh_f16(a, b) as u16 + unsafe { _vcageh_f16(a, b) as u16 } } #[doc = "Floating-point absolute compare greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagt_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(facgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcagt_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { +pub fn vcagt_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -1341,17 +1207,15 @@ pub unsafe fn vcagt_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { )] fn _vcagt_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t; } - _vcagt_f64(a, b) + unsafe { _vcagt_f64(a, b) } } #[doc = "Floating-point absolute compare greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagtq_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(facgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcagtq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { +pub fn vcagtq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -1359,17 +1223,15 @@ pub unsafe fn vcagtq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { )] fn _vcagtq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t; } - _vcagtq_f64(a, b) + unsafe { _vcagtq_f64(a, b) } } #[doc = "Floating-point absolute compare greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagtd_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(facgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcagtd_f64(a: f64, b: f64) -> u64 { +pub fn vcagtd_f64(a: f64, b: f64) -> u64 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -1377,17 +1239,15 @@ pub unsafe fn vcagtd_f64(a: f64, b: f64) -> u64 { )] fn _vcagtd_f64(a: f64, b: f64) -> u64; } - _vcagtd_f64(a, b) + unsafe { _vcagtd_f64(a, b) } } #[doc = "Floating-point absolute compare greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagts_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(facgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcagts_f32(a: f32, b: f32) -> u32 { +pub fn vcagts_f32(a: f32, b: f32) -> u32 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -1395,17 +1255,15 @@ pub unsafe fn vcagts_f32(a: f32, b: f32) -> u32 { )] fn _vcagts_f32(a: f32, b: f32) -> u32; } - _vcagts_f32(a, b) + unsafe { _vcagts_f32(a, b) } } #[doc = "Floating-point absolute compare greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagth_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(facgt))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcagth_f16(a: f16, b: f16) -> u16 { +pub fn vcagth_f16(a: f16, b: f16) -> u16 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -1413,1874 +1271,1548 @@ pub unsafe fn vcagth_f16(a: f16, b: f16) -> u16 { )] fn _vcagth_f16(a: f16, b: f16) -> i32; } - _vcagth_f16(a, b) as u16 + unsafe { _vcagth_f16(a, b) as u16 } } #[doc = "Floating-point absolute compare less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcale_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(facge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcale_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { +pub fn vcale_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { vcage_f64(b, a) } #[doc = "Floating-point absolute compare less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaleq_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(facge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcaleq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { +pub fn vcaleq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { vcageq_f64(b, a) } #[doc = "Floating-point absolute compare less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaled_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(facge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcaled_f64(a: f64, b: f64) -> u64 { +pub fn vcaled_f64(a: f64, b: f64) -> u64 { vcaged_f64(b, a) } #[doc = "Floating-point absolute compare less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcales_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(facge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcales_f32(a: f32, b: f32) -> u32 { +pub fn vcales_f32(a: f32, b: f32) -> u32 { vcages_f32(b, a) } #[doc = "Floating-point absolute compare less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaleh_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(facge))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcaleh_f16(a: f16, b: f16) -> u16 { +pub fn vcaleh_f16(a: f16, b: f16) -> u16 { vcageh_f16(b, a) } #[doc = "Floating-point absolute compare less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcalt_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(facgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcalt_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { +pub fn vcalt_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { vcagt_f64(b, a) } #[doc = "Floating-point absolute compare less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaltq_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(facgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcaltq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { +pub fn vcaltq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { vcagtq_f64(b, a) } #[doc = "Floating-point absolute compare less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaltd_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(facgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcaltd_f64(a: f64, b: f64) -> u64 { +pub fn vcaltd_f64(a: f64, b: f64) -> u64 { vcagtd_f64(b, a) } #[doc = "Floating-point absolute compare less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcalts_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(facgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcalts_f32(a: f32, b: f32) -> u32 { +pub fn vcalts_f32(a: f32, b: f32) -> u32 { vcagts_f32(b, a) } #[doc = "Floating-point absolute compare less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcalth_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(facgt))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcalth_f16(a: f16, b: f16) -> u16 { +pub fn vcalth_f16(a: f16, b: f16) -> u16 { vcagth_f16(b, a) } #[doc = "Floating-point compare equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vceq_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { - simd_eq(a, b) +pub fn vceq_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { + unsafe { simd_eq(a, b) } } #[doc = "Floating-point compare equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vceqq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { - simd_eq(a, b) +pub fn vceqq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { + unsafe { simd_eq(a, b) } } #[doc = "Compare bitwise Equal (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vceq_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t { - simd_eq(a, b) +pub fn vceq_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t { + unsafe { simd_eq(a, b) } } #[doc = "Compare bitwise Equal (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vceqq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t { - simd_eq(a, b) +pub fn vceqq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t { + unsafe { simd_eq(a, b) } } #[doc = "Compare bitwise Equal (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vceq_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { - simd_eq(a, b) +pub fn vceq_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { + unsafe { simd_eq(a, b) } } #[doc = "Compare bitwise Equal (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vceqq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { - simd_eq(a, b) +pub fn vceqq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { + unsafe { simd_eq(a, b) } } #[doc = "Compare bitwise Equal (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vceq_p64(a: poly64x1_t, b: poly64x1_t) -> uint64x1_t { - simd_eq(a, b) +pub fn vceq_p64(a: poly64x1_t, b: poly64x1_t) -> uint64x1_t { + unsafe { simd_eq(a, b) } } #[doc = "Compare bitwise Equal (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vceqq_p64(a: poly64x2_t, b: poly64x2_t) -> uint64x2_t { - simd_eq(a, b) +pub fn vceqq_p64(a: poly64x2_t, b: poly64x2_t) -> uint64x2_t { + unsafe { simd_eq(a, b) } } #[doc = "Floating-point compare equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqd_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vceqd_f64(a: f64, b: f64) -> u64 { - simd_extract!(vceq_f64(vdup_n_f64(a), vdup_n_f64(b)), 0) +pub fn vceqd_f64(a: f64, b: f64) -> u64 { + unsafe { simd_extract!(vceq_f64(vdup_n_f64(a), vdup_n_f64(b)), 0) } } #[doc = "Floating-point compare equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqs_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vceqs_f32(a: f32, b: f32) -> u32 { - simd_extract!(vceq_f32(vdup_n_f32(a), vdup_n_f32(b)), 0) +pub fn vceqs_f32(a: f32, b: f32) -> u32 { + unsafe { simd_extract!(vceq_f32(vdup_n_f32(a), vdup_n_f32(b)), 0) } } #[doc = "Compare bitwise equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqd_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vceqd_s64(a: i64, b: i64) -> u64 { - transmute(vceq_s64(transmute(a), transmute(b))) +pub fn vceqd_s64(a: i64, b: i64) -> u64 { + unsafe { transmute(vceq_s64(transmute(a), transmute(b))) } } #[doc = "Compare bitwise equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqd_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vceqd_u64(a: u64, b: u64) -> u64 { - transmute(vceq_u64(transmute(a), transmute(b))) +pub fn vceqd_u64(a: u64, b: u64) -> u64 { + unsafe { transmute(vceq_u64(transmute(a), transmute(b))) } } #[doc = "Floating-point compare equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqh_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fcmp))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vceqh_f16(a: f16, b: f16) -> u16 { - simd_extract!(vceq_f16(vdup_n_f16(a), vdup_n_f16(b)), 0) +pub fn vceqh_f16(a: f16, b: f16) -> u16 { + unsafe { simd_extract!(vceq_f16(vdup_n_f16(a), vdup_n_f16(b)), 0) } } #[doc = "Floating-point compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fcmeq))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vceqz_f16(a: float16x4_t) -> uint16x4_t { +pub fn vceqz_f16(a: float16x4_t) -> uint16x4_t { let b: f16x4 = f16x4::new(0.0, 0.0, 0.0, 0.0); - simd_eq(a, transmute(b)) + unsafe { simd_eq(a, transmute(b)) } } #[doc = "Floating-point compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fcmeq))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vceqzq_f16(a: float16x8_t) -> uint16x8_t { +pub fn vceqzq_f16(a: float16x8_t) -> uint16x8_t { let b: f16x8 = f16x8::new(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0); - simd_eq(a, transmute(b)) + unsafe { simd_eq(a, transmute(b)) } } #[doc = "Floating-point compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vceqz_f32(a: float32x2_t) -> uint32x2_t { +pub fn vceqz_f32(a: float32x2_t) -> uint32x2_t { let b: f32x2 = f32x2::new(0.0, 0.0); - simd_eq(a, transmute(b)) + unsafe { simd_eq(a, transmute(b)) } } #[doc = "Floating-point compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vceqzq_f32(a: float32x4_t) -> uint32x4_t { +pub fn vceqzq_f32(a: float32x4_t) -> uint32x4_t { let b: f32x4 = f32x4::new(0.0, 0.0, 0.0, 0.0); - simd_eq(a, transmute(b)) + unsafe { simd_eq(a, transmute(b)) } } #[doc = "Floating-point compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vceqz_f64(a: float64x1_t) -> uint64x1_t { +pub fn vceqz_f64(a: float64x1_t) -> uint64x1_t { let b: f64 = 0.0; - simd_eq(a, transmute(b)) + unsafe { simd_eq(a, transmute(b)) } } #[doc = "Floating-point compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vceqzq_f64(a: float64x2_t) -> uint64x2_t { +pub fn vceqzq_f64(a: float64x2_t) -> uint64x2_t { let b: f64x2 = f64x2::new(0.0, 0.0); - simd_eq(a, transmute(b)) + unsafe { simd_eq(a, transmute(b)) } } #[doc = "Signed compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vceqz_s8(a: int8x8_t) -> uint8x8_t { +pub fn vceqz_s8(a: int8x8_t) -> uint8x8_t { let b: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); - simd_eq(a, transmute(b)) + unsafe { simd_eq(a, transmute(b)) } } #[doc = "Signed compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vceqzq_s8(a: int8x16_t) -> uint8x16_t { +pub fn vceqzq_s8(a: int8x16_t) -> uint8x16_t { let b: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); - simd_eq(a, transmute(b)) + unsafe { simd_eq(a, transmute(b)) } } #[doc = "Signed compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vceqz_s16(a: int16x4_t) -> uint16x4_t { +pub fn vceqz_s16(a: int16x4_t) -> uint16x4_t { let b: i16x4 = i16x4::new(0, 0, 0, 0); - simd_eq(a, transmute(b)) + unsafe { simd_eq(a, transmute(b)) } } #[doc = "Signed compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vceqzq_s16(a: int16x8_t) -> uint16x8_t { +pub fn vceqzq_s16(a: int16x8_t) -> uint16x8_t { let b: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0); - simd_eq(a, transmute(b)) + unsafe { simd_eq(a, transmute(b)) } } #[doc = "Signed compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vceqz_s32(a: int32x2_t) -> uint32x2_t { +pub fn vceqz_s32(a: int32x2_t) -> uint32x2_t { let b: i32x2 = i32x2::new(0, 0); - simd_eq(a, transmute(b)) + unsafe { simd_eq(a, transmute(b)) } } #[doc = "Signed compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vceqzq_s32(a: int32x4_t) -> uint32x4_t { +pub fn vceqzq_s32(a: int32x4_t) -> uint32x4_t { let b: i32x4 = i32x4::new(0, 0, 0, 0); - simd_eq(a, transmute(b)) + unsafe { simd_eq(a, transmute(b)) } } #[doc = "Signed compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vceqz_s64(a: int64x1_t) -> uint64x1_t { +pub fn vceqz_s64(a: int64x1_t) -> uint64x1_t { let b: i64x1 = i64x1::new(0); - simd_eq(a, transmute(b)) + unsafe { simd_eq(a, transmute(b)) } } #[doc = "Signed compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vceqzq_s64(a: int64x2_t) -> uint64x2_t { +pub fn vceqzq_s64(a: int64x2_t) -> uint64x2_t { let b: i64x2 = i64x2::new(0, 0); - simd_eq(a, transmute(b)) + unsafe { simd_eq(a, transmute(b)) } } #[doc = "Signed compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vceqz_p8(a: poly8x8_t) -> uint8x8_t { +pub fn vceqz_p8(a: poly8x8_t) -> uint8x8_t { let b: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); - simd_eq(a, transmute(b)) + unsafe { simd_eq(a, transmute(b)) } } #[doc = "Signed compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vceqzq_p8(a: poly8x16_t) -> uint8x16_t { +pub fn vceqzq_p8(a: poly8x16_t) -> uint8x16_t { let b: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); - simd_eq(a, transmute(b)) + unsafe { simd_eq(a, transmute(b)) } } #[doc = "Signed compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vceqz_p64(a: poly64x1_t) -> uint64x1_t { +pub fn vceqz_p64(a: poly64x1_t) -> uint64x1_t { let b: i64x1 = i64x1::new(0); - simd_eq(a, transmute(b)) + unsafe { simd_eq(a, transmute(b)) } } #[doc = "Signed compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vceqzq_p64(a: poly64x2_t) -> uint64x2_t { +pub fn vceqzq_p64(a: poly64x2_t) -> uint64x2_t { let b: i64x2 = i64x2::new(0, 0); - simd_eq(a, transmute(b)) + unsafe { simd_eq(a, transmute(b)) } } #[doc = "Unsigned compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vceqz_u8(a: uint8x8_t) -> uint8x8_t { +pub fn vceqz_u8(a: uint8x8_t) -> uint8x8_t { let b: u8x8 = u8x8::new(0, 0, 0, 0, 0, 0, 0, 0); - simd_eq(a, transmute(b)) + unsafe { simd_eq(a, transmute(b)) } } #[doc = "Unsigned compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vceqzq_u8(a: uint8x16_t) -> uint8x16_t { +pub fn vceqzq_u8(a: uint8x16_t) -> uint8x16_t { let b: u8x16 = u8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); - simd_eq(a, transmute(b)) + unsafe { simd_eq(a, transmute(b)) } } #[doc = "Unsigned compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vceqz_u16(a: uint16x4_t) -> uint16x4_t { +pub fn vceqz_u16(a: uint16x4_t) -> uint16x4_t { let b: u16x4 = u16x4::new(0, 0, 0, 0); - simd_eq(a, transmute(b)) + unsafe { simd_eq(a, transmute(b)) } } #[doc = "Unsigned compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vceqzq_u16(a: uint16x8_t) -> uint16x8_t { +pub fn vceqzq_u16(a: uint16x8_t) -> uint16x8_t { let b: u16x8 = u16x8::new(0, 0, 0, 0, 0, 0, 0, 0); - simd_eq(a, transmute(b)) + unsafe { simd_eq(a, transmute(b)) } } #[doc = "Unsigned compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vceqz_u32(a: uint32x2_t) -> uint32x2_t { +pub fn vceqz_u32(a: uint32x2_t) -> uint32x2_t { let b: u32x2 = u32x2::new(0, 0); - simd_eq(a, transmute(b)) + unsafe { simd_eq(a, transmute(b)) } } #[doc = "Unsigned compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vceqzq_u32(a: uint32x4_t) -> uint32x4_t { +pub fn vceqzq_u32(a: uint32x4_t) -> uint32x4_t { let b: u32x4 = u32x4::new(0, 0, 0, 0); - simd_eq(a, transmute(b)) + unsafe { simd_eq(a, transmute(b)) } } #[doc = "Unsigned compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vceqz_u64(a: uint64x1_t) -> uint64x1_t { +pub fn vceqz_u64(a: uint64x1_t) -> uint64x1_t { let b: u64x1 = u64x1::new(0); - simd_eq(a, transmute(b)) + unsafe { simd_eq(a, transmute(b)) } } #[doc = "Unsigned compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vceqzq_u64(a: uint64x2_t) -> uint64x2_t { +pub fn vceqzq_u64(a: uint64x2_t) -> uint64x2_t { let b: u64x2 = u64x2::new(0, 0); - simd_eq(a, transmute(b)) + unsafe { simd_eq(a, transmute(b)) } } #[doc = "Compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzd_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vceqzd_s64(a: i64) -> u64 { - transmute(vceqz_s64(transmute(a))) +pub fn vceqzd_s64(a: i64) -> u64 { + unsafe { transmute(vceqz_s64(transmute(a))) } } #[doc = "Compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzd_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vceqzd_u64(a: u64) -> u64 { - transmute(vceqz_u64(transmute(a))) +pub fn vceqzd_u64(a: u64) -> u64 { + unsafe { transmute(vceqz_u64(transmute(a))) } } #[doc = "Floating-point compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzh_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fcmp))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vceqzh_f16(a: f16) -> u16 { - simd_extract!(vceqz_f16(vdup_n_f16(a)), 0) +pub fn vceqzh_f16(a: f16) -> u16 { + unsafe { simd_extract!(vceqz_f16(vdup_n_f16(a)), 0) } } #[doc = "Floating-point compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzs_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vceqzs_f32(a: f32) -> u32 { - simd_extract!(vceqz_f32(vdup_n_f32(a)), 0) +pub fn vceqzs_f32(a: f32) -> u32 { + unsafe { simd_extract!(vceqz_f32(vdup_n_f32(a)), 0) } } #[doc = "Floating-point compare bitwise equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzd_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vceqzd_f64(a: f64) -> u64 { - simd_extract!(vceqz_f64(vdup_n_f64(a)), 0) +pub fn vceqzd_f64(a: f64) -> u64 { + unsafe { simd_extract!(vceqz_f64(vdup_n_f64(a)), 0) } } #[doc = "Floating-point compare greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcge_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { - simd_ge(a, b) +pub fn vcge_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { + unsafe { simd_ge(a, b) } } #[doc = "Floating-point compare greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcgeq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { - simd_ge(a, b) +pub fn vcgeq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { + unsafe { simd_ge(a, b) } } #[doc = "Compare signed greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcge_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t { - simd_ge(a, b) +pub fn vcge_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t { + unsafe { simd_ge(a, b) } } #[doc = "Compare signed greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcgeq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t { - simd_ge(a, b) +pub fn vcgeq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t { + unsafe { simd_ge(a, b) } } #[doc = "Compare unsigned greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmhs))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcge_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { - simd_ge(a, b) +pub fn vcge_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { + unsafe { simd_ge(a, b) } } #[doc = "Compare unsigned greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmhs))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcgeq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { - simd_ge(a, b) +pub fn vcgeq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { + unsafe { simd_ge(a, b) } } #[doc = "Floating-point compare greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcged_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcged_f64(a: f64, b: f64) -> u64 { - simd_extract!(vcge_f64(vdup_n_f64(a), vdup_n_f64(b)), 0) +pub fn vcged_f64(a: f64, b: f64) -> u64 { + unsafe { simd_extract!(vcge_f64(vdup_n_f64(a), vdup_n_f64(b)), 0) } } #[doc = "Floating-point compare greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcges_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcges_f32(a: f32, b: f32) -> u32 { - simd_extract!(vcge_f32(vdup_n_f32(a), vdup_n_f32(b)), 0) +pub fn vcges_f32(a: f32, b: f32) -> u32 { + unsafe { simd_extract!(vcge_f32(vdup_n_f32(a), vdup_n_f32(b)), 0) } } #[doc = "Compare greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcged_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcged_s64(a: i64, b: i64) -> u64 { - transmute(vcge_s64(transmute(a), transmute(b))) +pub fn vcged_s64(a: i64, b: i64) -> u64 { + unsafe { transmute(vcge_s64(transmute(a), transmute(b))) } } #[doc = "Compare greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcged_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcged_u64(a: u64, b: u64) -> u64 { - transmute(vcge_u64(transmute(a), transmute(b))) +pub fn vcged_u64(a: u64, b: u64) -> u64 { + unsafe { transmute(vcge_u64(transmute(a), transmute(b))) } } #[doc = "Floating-point compare greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeh_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fcmp))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcgeh_f16(a: f16, b: f16) -> u16 { - simd_extract!(vcge_f16(vdup_n_f16(a), vdup_n_f16(b)), 0) +pub fn vcgeh_f16(a: f16, b: f16) -> u16 { + unsafe { simd_extract!(vcge_f16(vdup_n_f16(a), vdup_n_f16(b)), 0) } } #[doc = "Floating-point compare greater than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgez_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcgez_f32(a: float32x2_t) -> uint32x2_t { +pub fn vcgez_f32(a: float32x2_t) -> uint32x2_t { let b: f32x2 = f32x2::new(0.0, 0.0); - simd_ge(a, transmute(b)) + unsafe { simd_ge(a, transmute(b)) } } #[doc = "Floating-point compare greater than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcgezq_f32(a: float32x4_t) -> uint32x4_t { +pub fn vcgezq_f32(a: float32x4_t) -> uint32x4_t { let b: f32x4 = f32x4::new(0.0, 0.0, 0.0, 0.0); - simd_ge(a, transmute(b)) + unsafe { simd_ge(a, transmute(b)) } } #[doc = "Floating-point compare greater than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgez_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcgez_f64(a: float64x1_t) -> uint64x1_t { +pub fn vcgez_f64(a: float64x1_t) -> uint64x1_t { let b: f64 = 0.0; - simd_ge(a, transmute(b)) + unsafe { simd_ge(a, transmute(b)) } } #[doc = "Floating-point compare greater than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezq_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcgezq_f64(a: float64x2_t) -> uint64x2_t { +pub fn vcgezq_f64(a: float64x2_t) -> uint64x2_t { let b: f64x2 = f64x2::new(0.0, 0.0); - simd_ge(a, transmute(b)) + unsafe { simd_ge(a, transmute(b)) } } #[doc = "Compare signed greater than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgez_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcgez_s8(a: int8x8_t) -> uint8x8_t { +pub fn vcgez_s8(a: int8x8_t) -> uint8x8_t { let b: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); - simd_ge(a, transmute(b)) + unsafe { simd_ge(a, transmute(b)) } } #[doc = "Compare signed greater than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezq_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcgezq_s8(a: int8x16_t) -> uint8x16_t { +pub fn vcgezq_s8(a: int8x16_t) -> uint8x16_t { let b: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); - simd_ge(a, transmute(b)) + unsafe { simd_ge(a, transmute(b)) } } #[doc = "Compare signed greater than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgez_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcgez_s16(a: int16x4_t) -> uint16x4_t { +pub fn vcgez_s16(a: int16x4_t) -> uint16x4_t { let b: i16x4 = i16x4::new(0, 0, 0, 0); - simd_ge(a, transmute(b)) + unsafe { simd_ge(a, transmute(b)) } } #[doc = "Compare signed greater than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcgezq_s16(a: int16x8_t) -> uint16x8_t { +pub fn vcgezq_s16(a: int16x8_t) -> uint16x8_t { let b: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0); - simd_ge(a, transmute(b)) + unsafe { simd_ge(a, transmute(b)) } } #[doc = "Compare signed greater than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgez_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcgez_s32(a: int32x2_t) -> uint32x2_t { +pub fn vcgez_s32(a: int32x2_t) -> uint32x2_t { let b: i32x2 = i32x2::new(0, 0); - simd_ge(a, transmute(b)) + unsafe { simd_ge(a, transmute(b)) } } #[doc = "Compare signed greater than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcgezq_s32(a: int32x4_t) -> uint32x4_t { +pub fn vcgezq_s32(a: int32x4_t) -> uint32x4_t { let b: i32x4 = i32x4::new(0, 0, 0, 0); - simd_ge(a, transmute(b)) + unsafe { simd_ge(a, transmute(b)) } } #[doc = "Compare signed greater than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgez_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcgez_s64(a: int64x1_t) -> uint64x1_t { +pub fn vcgez_s64(a: int64x1_t) -> uint64x1_t { let b: i64x1 = i64x1::new(0); - simd_ge(a, transmute(b)) + unsafe { simd_ge(a, transmute(b)) } } #[doc = "Compare signed greater than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezq_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcgezq_s64(a: int64x2_t) -> uint64x2_t { +pub fn vcgezq_s64(a: int64x2_t) -> uint64x2_t { let b: i64x2 = i64x2::new(0, 0); - simd_ge(a, transmute(b)) + unsafe { simd_ge(a, transmute(b)) } } #[doc = "Floating-point compare greater than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezd_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcgezd_f64(a: f64) -> u64 { - simd_extract!(vcgez_f64(vdup_n_f64(a)), 0) +pub fn vcgezd_f64(a: f64) -> u64 { + unsafe { simd_extract!(vcgez_f64(vdup_n_f64(a)), 0) } } #[doc = "Floating-point compare greater than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezs_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcgezs_f32(a: f32) -> u32 { - simd_extract!(vcgez_f32(vdup_n_f32(a)), 0) +pub fn vcgezs_f32(a: f32) -> u32 { + unsafe { simd_extract!(vcgez_f32(vdup_n_f32(a)), 0) } } #[doc = "Compare signed greater than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezd_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcgezd_s64(a: i64) -> u64 { - transmute(vcgez_s64(transmute(a))) +pub fn vcgezd_s64(a: i64) -> u64 { + unsafe { transmute(vcgez_s64(transmute(a))) } } #[doc = "Floating-point compare greater than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezh_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fcmp))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcgezh_f16(a: f16) -> u16 { - simd_extract!(vcgez_f16(vdup_n_f16(a)), 0) +pub fn vcgezh_f16(a: f16) -> u16 { + unsafe { simd_extract!(vcgez_f16(vdup_n_f16(a)), 0) } } #[doc = "Floating-point compare greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcgt_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { - simd_gt(a, b) +pub fn vcgt_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { + unsafe { simd_gt(a, b) } } #[doc = "Floating-point compare greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcgtq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { - simd_gt(a, b) +pub fn vcgtq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { + unsafe { simd_gt(a, b) } } #[doc = "Compare signed greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcgt_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t { - simd_gt(a, b) +pub fn vcgt_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t { + unsafe { simd_gt(a, b) } } #[doc = "Compare signed greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcgtq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t { - simd_gt(a, b) +pub fn vcgtq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t { + unsafe { simd_gt(a, b) } } #[doc = "Compare unsigned greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmhi))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcgt_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { - simd_gt(a, b) +pub fn vcgt_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { + unsafe { simd_gt(a, b) } } #[doc = "Compare unsigned greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmhi))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcgtq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { - simd_gt(a, b) +pub fn vcgtq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { + unsafe { simd_gt(a, b) } } #[doc = "Floating-point compare greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtd_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcgtd_f64(a: f64, b: f64) -> u64 { - simd_extract!(vcgt_f64(vdup_n_f64(a), vdup_n_f64(b)), 0) +pub fn vcgtd_f64(a: f64, b: f64) -> u64 { + unsafe { simd_extract!(vcgt_f64(vdup_n_f64(a), vdup_n_f64(b)), 0) } } #[doc = "Floating-point compare greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgts_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcgts_f32(a: f32, b: f32) -> u32 { - simd_extract!(vcgt_f32(vdup_n_f32(a), vdup_n_f32(b)), 0) +pub fn vcgts_f32(a: f32, b: f32) -> u32 { + unsafe { simd_extract!(vcgt_f32(vdup_n_f32(a), vdup_n_f32(b)), 0) } } #[doc = "Compare greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtd_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcgtd_s64(a: i64, b: i64) -> u64 { - transmute(vcgt_s64(transmute(a), transmute(b))) +pub fn vcgtd_s64(a: i64, b: i64) -> u64 { + unsafe { transmute(vcgt_s64(transmute(a), transmute(b))) } } #[doc = "Compare greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtd_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcgtd_u64(a: u64, b: u64) -> u64 { - transmute(vcgt_u64(transmute(a), transmute(b))) +pub fn vcgtd_u64(a: u64, b: u64) -> u64 { + unsafe { transmute(vcgt_u64(transmute(a), transmute(b))) } } #[doc = "Floating-point compare greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgth_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fcmp))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcgth_f16(a: f16, b: f16) -> u16 { - simd_extract!(vcgt_f16(vdup_n_f16(a), vdup_n_f16(b)), 0) +pub fn vcgth_f16(a: f16, b: f16) -> u16 { + unsafe { simd_extract!(vcgt_f16(vdup_n_f16(a), vdup_n_f16(b)), 0) } } #[doc = "Floating-point compare greater than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtz_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcgtz_f32(a: float32x2_t) -> uint32x2_t { +pub fn vcgtz_f32(a: float32x2_t) -> uint32x2_t { let b: f32x2 = f32x2::new(0.0, 0.0); - simd_gt(a, transmute(b)) + unsafe { simd_gt(a, transmute(b)) } } #[doc = "Floating-point compare greater than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcgtzq_f32(a: float32x4_t) -> uint32x4_t { +pub fn vcgtzq_f32(a: float32x4_t) -> uint32x4_t { let b: f32x4 = f32x4::new(0.0, 0.0, 0.0, 0.0); - simd_gt(a, transmute(b)) + unsafe { simd_gt(a, transmute(b)) } } #[doc = "Floating-point compare greater than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtz_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcgtz_f64(a: float64x1_t) -> uint64x1_t { +pub fn vcgtz_f64(a: float64x1_t) -> uint64x1_t { let b: f64 = 0.0; - simd_gt(a, transmute(b)) + unsafe { simd_gt(a, transmute(b)) } } #[doc = "Floating-point compare greater than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzq_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcgtzq_f64(a: float64x2_t) -> uint64x2_t { +pub fn vcgtzq_f64(a: float64x2_t) -> uint64x2_t { let b: f64x2 = f64x2::new(0.0, 0.0); - simd_gt(a, transmute(b)) + unsafe { simd_gt(a, transmute(b)) } } #[doc = "Compare signed greater than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtz_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcgtz_s8(a: int8x8_t) -> uint8x8_t { +pub fn vcgtz_s8(a: int8x8_t) -> uint8x8_t { let b: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); - simd_gt(a, transmute(b)) + unsafe { simd_gt(a, transmute(b)) } } #[doc = "Compare signed greater than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzq_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcgtzq_s8(a: int8x16_t) -> uint8x16_t { +pub fn vcgtzq_s8(a: int8x16_t) -> uint8x16_t { let b: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); - simd_gt(a, transmute(b)) + unsafe { simd_gt(a, transmute(b)) } } #[doc = "Compare signed greater than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtz_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcgtz_s16(a: int16x4_t) -> uint16x4_t { +pub fn vcgtz_s16(a: int16x4_t) -> uint16x4_t { let b: i16x4 = i16x4::new(0, 0, 0, 0); - simd_gt(a, transmute(b)) + unsafe { simd_gt(a, transmute(b)) } } #[doc = "Compare signed greater than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcgtzq_s16(a: int16x8_t) -> uint16x8_t { +pub fn vcgtzq_s16(a: int16x8_t) -> uint16x8_t { let b: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0); - simd_gt(a, transmute(b)) + unsafe { simd_gt(a, transmute(b)) } } #[doc = "Compare signed greater than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtz_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcgtz_s32(a: int32x2_t) -> uint32x2_t { +pub fn vcgtz_s32(a: int32x2_t) -> uint32x2_t { let b: i32x2 = i32x2::new(0, 0); - simd_gt(a, transmute(b)) + unsafe { simd_gt(a, transmute(b)) } } #[doc = "Compare signed greater than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcgtzq_s32(a: int32x4_t) -> uint32x4_t { +pub fn vcgtzq_s32(a: int32x4_t) -> uint32x4_t { let b: i32x4 = i32x4::new(0, 0, 0, 0); - simd_gt(a, transmute(b)) + unsafe { simd_gt(a, transmute(b)) } } #[doc = "Compare signed greater than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtz_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcgtz_s64(a: int64x1_t) -> uint64x1_t { +pub fn vcgtz_s64(a: int64x1_t) -> uint64x1_t { let b: i64x1 = i64x1::new(0); - simd_gt(a, transmute(b)) + unsafe { simd_gt(a, transmute(b)) } } #[doc = "Compare signed greater than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzq_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcgtzq_s64(a: int64x2_t) -> uint64x2_t { +pub fn vcgtzq_s64(a: int64x2_t) -> uint64x2_t { let b: i64x2 = i64x2::new(0, 0); - simd_gt(a, transmute(b)) + unsafe { simd_gt(a, transmute(b)) } } #[doc = "Floating-point compare greater than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzd_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcgtzd_f64(a: f64) -> u64 { - simd_extract!(vcgtz_f64(vdup_n_f64(a)), 0) +pub fn vcgtzd_f64(a: f64) -> u64 { + unsafe { simd_extract!(vcgtz_f64(vdup_n_f64(a)), 0) } } #[doc = "Floating-point compare greater than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzs_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcgtzs_f32(a: f32) -> u32 { - simd_extract!(vcgtz_f32(vdup_n_f32(a)), 0) +pub fn vcgtzs_f32(a: f32) -> u32 { + unsafe { simd_extract!(vcgtz_f32(vdup_n_f32(a)), 0) } } #[doc = "Compare signed greater than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzd_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcgtzd_s64(a: i64) -> u64 { - transmute(vcgtz_s64(transmute(a))) +pub fn vcgtzd_s64(a: i64) -> u64 { + unsafe { transmute(vcgtz_s64(transmute(a))) } } #[doc = "Floating-point compare greater than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzh_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fcmp))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcgtzh_f16(a: f16) -> u16 { - simd_extract!(vcgtz_f16(vdup_n_f16(a)), 0) +pub fn vcgtzh_f16(a: f16) -> u16 { + unsafe { simd_extract!(vcgtz_f16(vdup_n_f16(a)), 0) } } #[doc = "Floating-point compare less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcle_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { - simd_le(a, b) +pub fn vcle_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { + unsafe { simd_le(a, b) } } #[doc = "Floating-point compare less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcleq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { - simd_le(a, b) +pub fn vcleq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { + unsafe { simd_le(a, b) } } #[doc = "Compare signed less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcle_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t { - simd_le(a, b) +pub fn vcle_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t { + unsafe { simd_le(a, b) } } #[doc = "Compare signed less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcleq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t { - simd_le(a, b) +pub fn vcleq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t { + unsafe { simd_le(a, b) } } #[doc = "Compare unsigned less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmhs))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcle_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { - simd_le(a, b) +pub fn vcle_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { + unsafe { simd_le(a, b) } } #[doc = "Compare unsigned less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmhs))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcleq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { - simd_le(a, b) +pub fn vcleq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { + unsafe { simd_le(a, b) } } #[doc = "Floating-point compare less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcled_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcled_f64(a: f64, b: f64) -> u64 { - simd_extract!(vcle_f64(vdup_n_f64(a), vdup_n_f64(b)), 0) +pub fn vcled_f64(a: f64, b: f64) -> u64 { + unsafe { simd_extract!(vcle_f64(vdup_n_f64(a), vdup_n_f64(b)), 0) } } #[doc = "Floating-point compare less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcles_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcles_f32(a: f32, b: f32) -> u32 { - simd_extract!(vcle_f32(vdup_n_f32(a), vdup_n_f32(b)), 0) +pub fn vcles_f32(a: f32, b: f32) -> u32 { + unsafe { simd_extract!(vcle_f32(vdup_n_f32(a), vdup_n_f32(b)), 0) } } #[doc = "Compare less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcled_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcled_u64(a: u64, b: u64) -> u64 { - transmute(vcle_u64(transmute(a), transmute(b))) +pub fn vcled_u64(a: u64, b: u64) -> u64 { + unsafe { transmute(vcle_u64(transmute(a), transmute(b))) } } #[doc = "Compare less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcled_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcled_s64(a: i64, b: i64) -> u64 { - transmute(vcle_s64(transmute(a), transmute(b))) +pub fn vcled_s64(a: i64, b: i64) -> u64 { + unsafe { transmute(vcle_s64(transmute(a), transmute(b))) } } #[doc = "Floating-point compare less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleh_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fcmp))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcleh_f16(a: f16, b: f16) -> u16 { - simd_extract!(vcle_f16(vdup_n_f16(a), vdup_n_f16(b)), 0) +pub fn vcleh_f16(a: f16, b: f16) -> u16 { + unsafe { simd_extract!(vcle_f16(vdup_n_f16(a), vdup_n_f16(b)), 0) } } #[doc = "Floating-point compare less than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclez_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmle))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vclez_f32(a: float32x2_t) -> uint32x2_t { +pub fn vclez_f32(a: float32x2_t) -> uint32x2_t { let b: f32x2 = f32x2::new(0.0, 0.0); - simd_le(a, transmute(b)) + unsafe { simd_le(a, transmute(b)) } } #[doc = "Floating-point compare less than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmle))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vclezq_f32(a: float32x4_t) -> uint32x4_t { +pub fn vclezq_f32(a: float32x4_t) -> uint32x4_t { let b: f32x4 = f32x4::new(0.0, 0.0, 0.0, 0.0); - simd_le(a, transmute(b)) + unsafe { simd_le(a, transmute(b)) } } #[doc = "Floating-point compare less than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclez_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmle))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vclez_f64(a: float64x1_t) -> uint64x1_t { +pub fn vclez_f64(a: float64x1_t) -> uint64x1_t { let b: f64 = 0.0; - simd_le(a, transmute(b)) + unsafe { simd_le(a, transmute(b)) } } #[doc = "Floating-point compare less than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezq_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmle))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vclezq_f64(a: float64x2_t) -> uint64x2_t { +pub fn vclezq_f64(a: float64x2_t) -> uint64x2_t { let b: f64x2 = f64x2::new(0.0, 0.0); - simd_le(a, transmute(b)) + unsafe { simd_le(a, transmute(b)) } } #[doc = "Compare signed less than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclez_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmle))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vclez_s8(a: int8x8_t) -> uint8x8_t { +pub fn vclez_s8(a: int8x8_t) -> uint8x8_t { let b: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); - simd_le(a, transmute(b)) + unsafe { simd_le(a, transmute(b)) } } #[doc = "Compare signed less than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezq_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmle))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vclezq_s8(a: int8x16_t) -> uint8x16_t { +pub fn vclezq_s8(a: int8x16_t) -> uint8x16_t { let b: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); - simd_le(a, transmute(b)) + unsafe { simd_le(a, transmute(b)) } } #[doc = "Compare signed less than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclez_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmle))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vclez_s16(a: int16x4_t) -> uint16x4_t { +pub fn vclez_s16(a: int16x4_t) -> uint16x4_t { let b: i16x4 = i16x4::new(0, 0, 0, 0); - simd_le(a, transmute(b)) + unsafe { simd_le(a, transmute(b)) } } #[doc = "Compare signed less than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmle))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vclezq_s16(a: int16x8_t) -> uint16x8_t { +pub fn vclezq_s16(a: int16x8_t) -> uint16x8_t { let b: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0); - simd_le(a, transmute(b)) + unsafe { simd_le(a, transmute(b)) } } #[doc = "Compare signed less than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclez_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmle))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vclez_s32(a: int32x2_t) -> uint32x2_t { +pub fn vclez_s32(a: int32x2_t) -> uint32x2_t { let b: i32x2 = i32x2::new(0, 0); - simd_le(a, transmute(b)) + unsafe { simd_le(a, transmute(b)) } } #[doc = "Compare signed less than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmle))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vclezq_s32(a: int32x4_t) -> uint32x4_t { +pub fn vclezq_s32(a: int32x4_t) -> uint32x4_t { let b: i32x4 = i32x4::new(0, 0, 0, 0); - simd_le(a, transmute(b)) + unsafe { simd_le(a, transmute(b)) } } #[doc = "Compare signed less than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclez_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmle))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vclez_s64(a: int64x1_t) -> uint64x1_t { +pub fn vclez_s64(a: int64x1_t) -> uint64x1_t { let b: i64x1 = i64x1::new(0); - simd_le(a, transmute(b)) + unsafe { simd_le(a, transmute(b)) } } #[doc = "Compare signed less than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezq_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmle))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vclezq_s64(a: int64x2_t) -> uint64x2_t { +pub fn vclezq_s64(a: int64x2_t) -> uint64x2_t { let b: i64x2 = i64x2::new(0, 0); - simd_le(a, transmute(b)) + unsafe { simd_le(a, transmute(b)) } } #[doc = "Floating-point compare less than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezd_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vclezd_f64(a: f64) -> u64 { - simd_extract!(vclez_f64(vdup_n_f64(a)), 0) +pub fn vclezd_f64(a: f64) -> u64 { + unsafe { simd_extract!(vclez_f64(vdup_n_f64(a)), 0) } } #[doc = "Floating-point compare less than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezs_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vclezs_f32(a: f32) -> u32 { - simd_extract!(vclez_f32(vdup_n_f32(a)), 0) +pub fn vclezs_f32(a: f32) -> u32 { + unsafe { simd_extract!(vclez_f32(vdup_n_f32(a)), 0) } } #[doc = "Compare less than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezd_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vclezd_s64(a: i64) -> u64 { - transmute(vclez_s64(transmute(a))) +pub fn vclezd_s64(a: i64) -> u64 { + unsafe { transmute(vclez_s64(transmute(a))) } } #[doc = "Floating-point compare less than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezh_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fcmp))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vclezh_f16(a: f16) -> u16 { - simd_extract!(vclez_f16(vdup_n_f16(a)), 0) +pub fn vclezh_f16(a: f16) -> u16 { + unsafe { simd_extract!(vclez_f16(vdup_n_f16(a)), 0) } } #[doc = "Floating-point compare less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vclt_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { - simd_lt(a, b) +pub fn vclt_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { + unsafe { simd_lt(a, b) } } #[doc = "Floating-point compare less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcltq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { - simd_lt(a, b) +pub fn vcltq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { + unsafe { simd_lt(a, b) } } #[doc = "Compare signed less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vclt_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t { - simd_lt(a, b) +pub fn vclt_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t { + unsafe { simd_lt(a, b) } } #[doc = "Compare signed less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcltq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t { - simd_lt(a, b) +pub fn vcltq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t { + unsafe { simd_lt(a, b) } } #[doc = "Compare unsigned less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmhi))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vclt_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { - simd_lt(a, b) +pub fn vclt_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { + unsafe { simd_lt(a, b) } } #[doc = "Compare unsigned less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmhi))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcltq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { - simd_lt(a, b) +pub fn vcltq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { + unsafe { simd_lt(a, b) } } #[doc = "Compare less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltd_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcltd_u64(a: u64, b: u64) -> u64 { - transmute(vclt_u64(transmute(a), transmute(b))) +pub fn vcltd_u64(a: u64, b: u64) -> u64 { + unsafe { transmute(vclt_u64(transmute(a), transmute(b))) } } #[doc = "Compare less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltd_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcltd_s64(a: i64, b: i64) -> u64 { - transmute(vclt_s64(transmute(a), transmute(b))) +pub fn vcltd_s64(a: i64, b: i64) -> u64 { + unsafe { transmute(vclt_s64(transmute(a), transmute(b))) } } #[doc = "Floating-point compare less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclth_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fcmp))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vclth_f16(a: f16, b: f16) -> u16 { - simd_extract!(vclt_f16(vdup_n_f16(a), vdup_n_f16(b)), 0) +pub fn vclth_f16(a: f16, b: f16) -> u16 { + unsafe { simd_extract!(vclt_f16(vdup_n_f16(a), vdup_n_f16(b)), 0) } } #[doc = "Floating-point compare less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclts_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vclts_f32(a: f32, b: f32) -> u32 { - simd_extract!(vclt_f32(vdup_n_f32(a), vdup_n_f32(b)), 0) +pub fn vclts_f32(a: f32, b: f32) -> u32 { + unsafe { simd_extract!(vclt_f32(vdup_n_f32(a), vdup_n_f32(b)), 0) } } #[doc = "Floating-point compare less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltd_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcltd_f64(a: f64, b: f64) -> u64 { - simd_extract!(vclt_f64(vdup_n_f64(a), vdup_n_f64(b)), 0) +pub fn vcltd_f64(a: f64, b: f64) -> u64 { + unsafe { simd_extract!(vclt_f64(vdup_n_f64(a), vdup_n_f64(b)), 0) } } #[doc = "Floating-point compare less than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltz_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmlt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcltz_f32(a: float32x2_t) -> uint32x2_t { +pub fn vcltz_f32(a: float32x2_t) -> uint32x2_t { let b: f32x2 = f32x2::new(0.0, 0.0); - simd_lt(a, transmute(b)) + unsafe { simd_lt(a, transmute(b)) } } #[doc = "Floating-point compare less than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmlt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcltzq_f32(a: float32x4_t) -> uint32x4_t { +pub fn vcltzq_f32(a: float32x4_t) -> uint32x4_t { let b: f32x4 = f32x4::new(0.0, 0.0, 0.0, 0.0); - simd_lt(a, transmute(b)) + unsafe { simd_lt(a, transmute(b)) } } #[doc = "Floating-point compare less than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltz_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmlt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcltz_f64(a: float64x1_t) -> uint64x1_t { +pub fn vcltz_f64(a: float64x1_t) -> uint64x1_t { let b: f64 = 0.0; - simd_lt(a, transmute(b)) + unsafe { simd_lt(a, transmute(b)) } } #[doc = "Floating-point compare less than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzq_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmlt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcltzq_f64(a: float64x2_t) -> uint64x2_t { +pub fn vcltzq_f64(a: float64x2_t) -> uint64x2_t { let b: f64x2 = f64x2::new(0.0, 0.0); - simd_lt(a, transmute(b)) + unsafe { simd_lt(a, transmute(b)) } } #[doc = "Compare signed less than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltz_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmlt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcltz_s8(a: int8x8_t) -> uint8x8_t { +pub fn vcltz_s8(a: int8x8_t) -> uint8x8_t { let b: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); - simd_lt(a, transmute(b)) + unsafe { simd_lt(a, transmute(b)) } } #[doc = "Compare signed less than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzq_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmlt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcltzq_s8(a: int8x16_t) -> uint8x16_t { +pub fn vcltzq_s8(a: int8x16_t) -> uint8x16_t { let b: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); - simd_lt(a, transmute(b)) + unsafe { simd_lt(a, transmute(b)) } } #[doc = "Compare signed less than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltz_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmlt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcltz_s16(a: int16x4_t) -> uint16x4_t { +pub fn vcltz_s16(a: int16x4_t) -> uint16x4_t { let b: i16x4 = i16x4::new(0, 0, 0, 0); - simd_lt(a, transmute(b)) + unsafe { simd_lt(a, transmute(b)) } } #[doc = "Compare signed less than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmlt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcltzq_s16(a: int16x8_t) -> uint16x8_t { +pub fn vcltzq_s16(a: int16x8_t) -> uint16x8_t { let b: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0); - simd_lt(a, transmute(b)) + unsafe { simd_lt(a, transmute(b)) } } #[doc = "Compare signed less than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltz_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmlt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcltz_s32(a: int32x2_t) -> uint32x2_t { +pub fn vcltz_s32(a: int32x2_t) -> uint32x2_t { let b: i32x2 = i32x2::new(0, 0); - simd_lt(a, transmute(b)) + unsafe { simd_lt(a, transmute(b)) } } #[doc = "Compare signed less than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmlt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcltzq_s32(a: int32x4_t) -> uint32x4_t { +pub fn vcltzq_s32(a: int32x4_t) -> uint32x4_t { let b: i32x4 = i32x4::new(0, 0, 0, 0); - simd_lt(a, transmute(b)) + unsafe { simd_lt(a, transmute(b)) } } #[doc = "Compare signed less than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltz_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmlt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcltz_s64(a: int64x1_t) -> uint64x1_t { +pub fn vcltz_s64(a: int64x1_t) -> uint64x1_t { let b: i64x1 = i64x1::new(0); - simd_lt(a, transmute(b)) + unsafe { simd_lt(a, transmute(b)) } } #[doc = "Compare signed less than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzq_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmlt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcltzq_s64(a: int64x2_t) -> uint64x2_t { +pub fn vcltzq_s64(a: int64x2_t) -> uint64x2_t { let b: i64x2 = i64x2::new(0, 0); - simd_lt(a, transmute(b)) + unsafe { simd_lt(a, transmute(b)) } } #[doc = "Floating-point compare less than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzd_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcltzd_f64(a: f64) -> u64 { - simd_extract!(vcltz_f64(vdup_n_f64(a)), 0) +pub fn vcltzd_f64(a: f64) -> u64 { + unsafe { simd_extract!(vcltz_f64(vdup_n_f64(a)), 0) } } #[doc = "Floating-point compare less than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzs_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcltzs_f32(a: f32) -> u32 { - simd_extract!(vcltz_f32(vdup_n_f32(a)), 0) +pub fn vcltzs_f32(a: f32) -> u32 { + unsafe { simd_extract!(vcltz_f32(vdup_n_f32(a)), 0) } } #[doc = "Compare less than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzd_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(asr))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcltzd_s64(a: i64) -> u64 { - transmute(vcltz_s64(transmute(a))) +pub fn vcltzd_s64(a: i64) -> u64 { + unsafe { transmute(vcltz_s64(transmute(a))) } } #[doc = "Floating-point compare less than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzh_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fcmp))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcltzh_f16(a: f16) -> u16 { - simd_extract!(vcltz_f16(vdup_n_f16(a)), 0) +pub fn vcltzh_f16(a: f16) -> u16 { + unsafe { simd_extract!(vcltz_f16(vdup_n_f16(a)), 0) } } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fcma")] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(fcmla))] -pub unsafe fn vcmla_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t { +pub fn vcmla_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -3288,18 +2820,16 @@ pub unsafe fn vcmla_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float )] fn _vcmla_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t; } - _vcmla_f16(a, b, c) + unsafe { _vcmla_f16(a, b, c) } } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fcma")] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(fcmla))] -pub unsafe fn vcmlaq_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t { +pub fn vcmlaq_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -3307,17 +2837,15 @@ pub unsafe fn vcmlaq_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> floa )] fn _vcmlaq_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t; } - _vcmlaq_f16(a, b, c) + unsafe { _vcmlaq_f16(a, b, c) } } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fcma")] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] #[cfg_attr(test, assert_instr(fcmla))] -pub unsafe fn vcmla_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t { +pub fn vcmla_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -3325,17 +2853,15 @@ pub unsafe fn vcmla_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float )] fn _vcmla_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t; } - _vcmla_f32(a, b, c) + unsafe { _vcmla_f32(a, b, c) } } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fcma")] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] #[cfg_attr(test, assert_instr(fcmla))] -pub unsafe fn vcmlaq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t { +pub fn vcmlaq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -3343,17 +2869,15 @@ pub unsafe fn vcmlaq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> floa )] fn _vcmlaq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t; } - _vcmlaq_f32(a, b, c) + unsafe { _vcmlaq_f32(a, b, c) } } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fcma")] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] #[cfg_attr(test, assert_instr(fcmla))] -pub unsafe fn vcmlaq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t { +pub fn vcmlaq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -3361,228 +2885,226 @@ pub unsafe fn vcmlaq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> floa )] fn _vcmlaq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t; } - _vcmlaq_f64(a, b, c) + unsafe { _vcmlaq_f64(a, b, c) } } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_lane_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcmla_lane_f16( +pub fn vcmla_lane_f16( a: float16x4_t, b: float16x4_t, c: float16x4_t, ) -> float16x4_t { static_assert_uimm_bits!(LANE, 1); - let c: float16x4_t = simd_shuffle!( - c, - c, - [ - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1 - ] - ); - vcmla_f16(a, b, c) + unsafe { + let c: float16x4_t = simd_shuffle!( + c, + c, + [ + 2 * LANE as u32, + 2 * LANE as u32 + 1, + 2 * LANE as u32, + 2 * LANE as u32 + 1 + ] + ); + vcmla_f16(a, b, c) + } } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_lane_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcmlaq_lane_f16( +pub fn vcmlaq_lane_f16( a: float16x8_t, b: float16x8_t, c: float16x4_t, ) -> float16x8_t { static_assert_uimm_bits!(LANE, 1); - let c: float16x8_t = simd_shuffle!( - c, - c, - [ - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1 - ] - ); - vcmlaq_f16(a, b, c) + unsafe { + let c: float16x8_t = simd_shuffle!( + c, + c, + [ + 2 * LANE as u32, + 2 * LANE as u32 + 1, + 2 * LANE as u32, + 2 * LANE as u32 + 1, + 2 * LANE as u32, + 2 * LANE as u32 + 1, + 2 * LANE as u32, + 2 * LANE as u32 + 1 + ] + ); + vcmlaq_f16(a, b, c) + } } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_lane_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] -pub unsafe fn vcmla_lane_f32( +pub fn vcmla_lane_f32( a: float32x2_t, b: float32x2_t, c: float32x2_t, ) -> float32x2_t { static_assert!(LANE == 0); - let c: float32x2_t = simd_shuffle!(c, c, [2 * LANE as u32, 2 * LANE as u32 + 1]); - vcmla_f32(a, b, c) + unsafe { + let c: float32x2_t = simd_shuffle!(c, c, [2 * LANE as u32, 2 * LANE as u32 + 1]); + vcmla_f32(a, b, c) + } } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_lane_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] -pub unsafe fn vcmlaq_lane_f32( +pub fn vcmlaq_lane_f32( a: float32x4_t, b: float32x4_t, c: float32x2_t, ) -> float32x4_t { static_assert!(LANE == 0); - let c: float32x4_t = simd_shuffle!( - c, - c, - [ - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1 - ] - ); - vcmlaq_f32(a, b, c) + unsafe { + let c: float32x4_t = simd_shuffle!( + c, + c, + [ + 2 * LANE as u32, + 2 * LANE as u32 + 1, + 2 * LANE as u32, + 2 * LANE as u32 + 1 + ] + ); + vcmlaq_f32(a, b, c) + } } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_laneq_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcmla_laneq_f16( +pub fn vcmla_laneq_f16( a: float16x4_t, b: float16x4_t, c: float16x8_t, ) -> float16x4_t { static_assert_uimm_bits!(LANE, 2); - let c: float16x4_t = simd_shuffle!( - c, - c, - [ - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1 - ] - ); - vcmla_f16(a, b, c) + unsafe { + let c: float16x4_t = simd_shuffle!( + c, + c, + [ + 2 * LANE as u32, + 2 * LANE as u32 + 1, + 2 * LANE as u32, + 2 * LANE as u32 + 1 + ] + ); + vcmla_f16(a, b, c) + } } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_laneq_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcmlaq_laneq_f16( +pub fn vcmlaq_laneq_f16( a: float16x8_t, b: float16x8_t, c: float16x8_t, ) -> float16x8_t { static_assert_uimm_bits!(LANE, 2); - let c: float16x8_t = simd_shuffle!( - c, - c, - [ - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1 - ] - ); - vcmlaq_f16(a, b, c) + unsafe { + let c: float16x8_t = simd_shuffle!( + c, + c, + [ + 2 * LANE as u32, + 2 * LANE as u32 + 1, + 2 * LANE as u32, + 2 * LANE as u32 + 1, + 2 * LANE as u32, + 2 * LANE as u32 + 1, + 2 * LANE as u32, + 2 * LANE as u32 + 1 + ] + ); + vcmlaq_f16(a, b, c) + } } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_laneq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] -pub unsafe fn vcmla_laneq_f32( +pub fn vcmla_laneq_f32( a: float32x2_t, b: float32x2_t, c: float32x4_t, ) -> float32x2_t { static_assert_uimm_bits!(LANE, 1); - let c: float32x2_t = simd_shuffle!(c, c, [2 * LANE as u32, 2 * LANE as u32 + 1]); - vcmla_f32(a, b, c) + unsafe { + let c: float32x2_t = simd_shuffle!(c, c, [2 * LANE as u32, 2 * LANE as u32 + 1]); + vcmla_f32(a, b, c) + } } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_laneq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] -pub unsafe fn vcmlaq_laneq_f32( +pub fn vcmlaq_laneq_f32( a: float32x4_t, b: float32x4_t, c: float32x4_t, ) -> float32x4_t { static_assert_uimm_bits!(LANE, 1); - let c: float32x4_t = simd_shuffle!( - c, - c, - [ - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1 - ] - ); - vcmlaq_f32(a, b, c) + unsafe { + let c: float32x4_t = simd_shuffle!( + c, + c, + [ + 2 * LANE as u32, + 2 * LANE as u32 + 1, + 2 * LANE as u32, + 2 * LANE as u32 + 1 + ] + ); + vcmlaq_f32(a, b, c) + } } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot180_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fcma")] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(fcmla))] -pub unsafe fn vcmla_rot180_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t { +pub fn vcmla_rot180_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -3590,18 +3112,16 @@ pub unsafe fn vcmla_rot180_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) - )] fn _vcmla_rot180_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t; } - _vcmla_rot180_f16(a, b, c) + unsafe { _vcmla_rot180_f16(a, b, c) } } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot180_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fcma")] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(fcmla))] -pub unsafe fn vcmlaq_rot180_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t { +pub fn vcmlaq_rot180_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -3609,17 +3129,15 @@ pub unsafe fn vcmlaq_rot180_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) )] fn _vcmlaq_rot180_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t; } - _vcmlaq_rot180_f16(a, b, c) + unsafe { _vcmlaq_rot180_f16(a, b, c) } } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot180_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fcma")] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] #[cfg_attr(test, assert_instr(fcmla))] -pub unsafe fn vcmla_rot180_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t { +pub fn vcmla_rot180_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -3627,17 +3145,15 @@ pub unsafe fn vcmla_rot180_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) - )] fn _vcmla_rot180_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t; } - _vcmla_rot180_f32(a, b, c) + unsafe { _vcmla_rot180_f32(a, b, c) } } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot180_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fcma")] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] #[cfg_attr(test, assert_instr(fcmla))] -pub unsafe fn vcmlaq_rot180_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t { +pub fn vcmlaq_rot180_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -3645,17 +3161,15 @@ pub unsafe fn vcmlaq_rot180_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) )] fn _vcmlaq_rot180_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t; } - _vcmlaq_rot180_f32(a, b, c) + unsafe { _vcmlaq_rot180_f32(a, b, c) } } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot180_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fcma")] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] #[cfg_attr(test, assert_instr(fcmla))] -pub unsafe fn vcmlaq_rot180_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t { +pub fn vcmlaq_rot180_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -3663,228 +3177,226 @@ pub unsafe fn vcmlaq_rot180_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) )] fn _vcmlaq_rot180_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t; } - _vcmlaq_rot180_f64(a, b, c) + unsafe { _vcmlaq_rot180_f64(a, b, c) } } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot180_lane_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcmla_rot180_lane_f16( +pub fn vcmla_rot180_lane_f16( a: float16x4_t, b: float16x4_t, c: float16x4_t, ) -> float16x4_t { static_assert_uimm_bits!(LANE, 1); - let c: float16x4_t = simd_shuffle!( - c, - c, - [ - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1 - ] - ); - vcmla_rot180_f16(a, b, c) + unsafe { + let c: float16x4_t = simd_shuffle!( + c, + c, + [ + 2 * LANE as u32, + 2 * LANE as u32 + 1, + 2 * LANE as u32, + 2 * LANE as u32 + 1 + ] + ); + vcmla_rot180_f16(a, b, c) + } } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot180_lane_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcmlaq_rot180_lane_f16( +pub fn vcmlaq_rot180_lane_f16( a: float16x8_t, b: float16x8_t, c: float16x4_t, ) -> float16x8_t { static_assert_uimm_bits!(LANE, 1); - let c: float16x8_t = simd_shuffle!( - c, - c, - [ - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1 - ] - ); - vcmlaq_rot180_f16(a, b, c) + unsafe { + let c: float16x8_t = simd_shuffle!( + c, + c, + [ + 2 * LANE as u32, + 2 * LANE as u32 + 1, + 2 * LANE as u32, + 2 * LANE as u32 + 1, + 2 * LANE as u32, + 2 * LANE as u32 + 1, + 2 * LANE as u32, + 2 * LANE as u32 + 1 + ] + ); + vcmlaq_rot180_f16(a, b, c) + } } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot180_lane_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] -pub unsafe fn vcmla_rot180_lane_f32( +pub fn vcmla_rot180_lane_f32( a: float32x2_t, b: float32x2_t, c: float32x2_t, ) -> float32x2_t { static_assert!(LANE == 0); - let c: float32x2_t = simd_shuffle!(c, c, [2 * LANE as u32, 2 * LANE as u32 + 1]); - vcmla_rot180_f32(a, b, c) + unsafe { + let c: float32x2_t = simd_shuffle!(c, c, [2 * LANE as u32, 2 * LANE as u32 + 1]); + vcmla_rot180_f32(a, b, c) + } } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot180_lane_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] -pub unsafe fn vcmlaq_rot180_lane_f32( +pub fn vcmlaq_rot180_lane_f32( a: float32x4_t, b: float32x4_t, c: float32x2_t, ) -> float32x4_t { static_assert!(LANE == 0); - let c: float32x4_t = simd_shuffle!( - c, - c, - [ - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1 - ] - ); - vcmlaq_rot180_f32(a, b, c) + unsafe { + let c: float32x4_t = simd_shuffle!( + c, + c, + [ + 2 * LANE as u32, + 2 * LANE as u32 + 1, + 2 * LANE as u32, + 2 * LANE as u32 + 1 + ] + ); + vcmlaq_rot180_f32(a, b, c) + } } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot180_laneq_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcmla_rot180_laneq_f16( +pub fn vcmla_rot180_laneq_f16( a: float16x4_t, b: float16x4_t, c: float16x8_t, ) -> float16x4_t { static_assert_uimm_bits!(LANE, 2); - let c: float16x4_t = simd_shuffle!( - c, - c, - [ - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1 - ] - ); - vcmla_rot180_f16(a, b, c) + unsafe { + let c: float16x4_t = simd_shuffle!( + c, + c, + [ + 2 * LANE as u32, + 2 * LANE as u32 + 1, + 2 * LANE as u32, + 2 * LANE as u32 + 1 + ] + ); + vcmla_rot180_f16(a, b, c) + } } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot180_laneq_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcmlaq_rot180_laneq_f16( +pub fn vcmlaq_rot180_laneq_f16( a: float16x8_t, b: float16x8_t, c: float16x8_t, ) -> float16x8_t { static_assert_uimm_bits!(LANE, 2); - let c: float16x8_t = simd_shuffle!( - c, - c, - [ - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1 - ] - ); - vcmlaq_rot180_f16(a, b, c) + unsafe { + let c: float16x8_t = simd_shuffle!( + c, + c, + [ + 2 * LANE as u32, + 2 * LANE as u32 + 1, + 2 * LANE as u32, + 2 * LANE as u32 + 1, + 2 * LANE as u32, + 2 * LANE as u32 + 1, + 2 * LANE as u32, + 2 * LANE as u32 + 1 + ] + ); + vcmlaq_rot180_f16(a, b, c) + } } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot180_laneq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] -pub unsafe fn vcmla_rot180_laneq_f32( +pub fn vcmla_rot180_laneq_f32( a: float32x2_t, b: float32x2_t, c: float32x4_t, ) -> float32x2_t { static_assert_uimm_bits!(LANE, 1); - let c: float32x2_t = simd_shuffle!(c, c, [2 * LANE as u32, 2 * LANE as u32 + 1]); - vcmla_rot180_f32(a, b, c) + unsafe { + let c: float32x2_t = simd_shuffle!(c, c, [2 * LANE as u32, 2 * LANE as u32 + 1]); + vcmla_rot180_f32(a, b, c) + } } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot180_laneq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] -pub unsafe fn vcmlaq_rot180_laneq_f32( +pub fn vcmlaq_rot180_laneq_f32( a: float32x4_t, b: float32x4_t, c: float32x4_t, ) -> float32x4_t { static_assert_uimm_bits!(LANE, 1); - let c: float32x4_t = simd_shuffle!( - c, - c, - [ - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1 - ] - ); - vcmlaq_rot180_f32(a, b, c) + unsafe { + let c: float32x4_t = simd_shuffle!( + c, + c, + [ + 2 * LANE as u32, + 2 * LANE as u32 + 1, + 2 * LANE as u32, + 2 * LANE as u32 + 1 + ] + ); + vcmlaq_rot180_f32(a, b, c) + } } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot270_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fcma")] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(fcmla))] -pub unsafe fn vcmla_rot270_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t { +pub fn vcmla_rot270_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -3892,18 +3404,16 @@ pub unsafe fn vcmla_rot270_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) - )] fn _vcmla_rot270_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t; } - _vcmla_rot270_f16(a, b, c) + unsafe { _vcmla_rot270_f16(a, b, c) } } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot270_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fcma")] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(fcmla))] -pub unsafe fn vcmlaq_rot270_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t { +pub fn vcmlaq_rot270_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -3911,17 +3421,15 @@ pub unsafe fn vcmlaq_rot270_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) )] fn _vcmlaq_rot270_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t; } - _vcmlaq_rot270_f16(a, b, c) + unsafe { _vcmlaq_rot270_f16(a, b, c) } } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot270_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fcma")] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] #[cfg_attr(test, assert_instr(fcmla))] -pub unsafe fn vcmla_rot270_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t { +pub fn vcmla_rot270_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -3929,17 +3437,15 @@ pub unsafe fn vcmla_rot270_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) - )] fn _vcmla_rot270_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t; } - _vcmla_rot270_f32(a, b, c) + unsafe { _vcmla_rot270_f32(a, b, c) } } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot270_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fcma")] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] #[cfg_attr(test, assert_instr(fcmla))] -pub unsafe fn vcmlaq_rot270_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t { +pub fn vcmlaq_rot270_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -3947,17 +3453,15 @@ pub unsafe fn vcmlaq_rot270_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) )] fn _vcmlaq_rot270_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t; } - _vcmlaq_rot270_f32(a, b, c) + unsafe { _vcmlaq_rot270_f32(a, b, c) } } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot270_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fcma")] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] #[cfg_attr(test, assert_instr(fcmla))] -pub unsafe fn vcmlaq_rot270_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t { +pub fn vcmlaq_rot270_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -3965,228 +3469,226 @@ pub unsafe fn vcmlaq_rot270_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) )] fn _vcmlaq_rot270_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t; } - _vcmlaq_rot270_f64(a, b, c) + unsafe { _vcmlaq_rot270_f64(a, b, c) } } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot270_lane_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcmla_rot270_lane_f16( +pub fn vcmla_rot270_lane_f16( a: float16x4_t, b: float16x4_t, c: float16x4_t, ) -> float16x4_t { static_assert_uimm_bits!(LANE, 1); - let c: float16x4_t = simd_shuffle!( - c, - c, - [ - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1 - ] - ); - vcmla_rot270_f16(a, b, c) + unsafe { + let c: float16x4_t = simd_shuffle!( + c, + c, + [ + 2 * LANE as u32, + 2 * LANE as u32 + 1, + 2 * LANE as u32, + 2 * LANE as u32 + 1 + ] + ); + vcmla_rot270_f16(a, b, c) + } } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot270_lane_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcmlaq_rot270_lane_f16( +pub fn vcmlaq_rot270_lane_f16( a: float16x8_t, b: float16x8_t, c: float16x4_t, ) -> float16x8_t { static_assert_uimm_bits!(LANE, 1); - let c: float16x8_t = simd_shuffle!( - c, - c, - [ - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1 - ] - ); - vcmlaq_rot270_f16(a, b, c) + unsafe { + let c: float16x8_t = simd_shuffle!( + c, + c, + [ + 2 * LANE as u32, + 2 * LANE as u32 + 1, + 2 * LANE as u32, + 2 * LANE as u32 + 1, + 2 * LANE as u32, + 2 * LANE as u32 + 1, + 2 * LANE as u32, + 2 * LANE as u32 + 1 + ] + ); + vcmlaq_rot270_f16(a, b, c) + } } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot270_lane_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] -pub unsafe fn vcmla_rot270_lane_f32( +pub fn vcmla_rot270_lane_f32( a: float32x2_t, b: float32x2_t, c: float32x2_t, ) -> float32x2_t { static_assert!(LANE == 0); - let c: float32x2_t = simd_shuffle!(c, c, [2 * LANE as u32, 2 * LANE as u32 + 1]); - vcmla_rot270_f32(a, b, c) + unsafe { + let c: float32x2_t = simd_shuffle!(c, c, [2 * LANE as u32, 2 * LANE as u32 + 1]); + vcmla_rot270_f32(a, b, c) + } } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot270_lane_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] -pub unsafe fn vcmlaq_rot270_lane_f32( +pub fn vcmlaq_rot270_lane_f32( a: float32x4_t, b: float32x4_t, c: float32x2_t, ) -> float32x4_t { static_assert!(LANE == 0); - let c: float32x4_t = simd_shuffle!( - c, - c, - [ - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1 - ] - ); - vcmlaq_rot270_f32(a, b, c) + unsafe { + let c: float32x4_t = simd_shuffle!( + c, + c, + [ + 2 * LANE as u32, + 2 * LANE as u32 + 1, + 2 * LANE as u32, + 2 * LANE as u32 + 1 + ] + ); + vcmlaq_rot270_f32(a, b, c) + } } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot270_laneq_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcmla_rot270_laneq_f16( +pub fn vcmla_rot270_laneq_f16( a: float16x4_t, b: float16x4_t, c: float16x8_t, ) -> float16x4_t { static_assert_uimm_bits!(LANE, 2); - let c: float16x4_t = simd_shuffle!( - c, - c, - [ - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1 - ] - ); - vcmla_rot270_f16(a, b, c) + unsafe { + let c: float16x4_t = simd_shuffle!( + c, + c, + [ + 2 * LANE as u32, + 2 * LANE as u32 + 1, + 2 * LANE as u32, + 2 * LANE as u32 + 1 + ] + ); + vcmla_rot270_f16(a, b, c) + } } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot270_laneq_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcmlaq_rot270_laneq_f16( +pub fn vcmlaq_rot270_laneq_f16( a: float16x8_t, b: float16x8_t, c: float16x8_t, ) -> float16x8_t { static_assert_uimm_bits!(LANE, 2); - let c: float16x8_t = simd_shuffle!( - c, - c, - [ - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1 - ] - ); - vcmlaq_rot270_f16(a, b, c) + unsafe { + let c: float16x8_t = simd_shuffle!( + c, + c, + [ + 2 * LANE as u32, + 2 * LANE as u32 + 1, + 2 * LANE as u32, + 2 * LANE as u32 + 1, + 2 * LANE as u32, + 2 * LANE as u32 + 1, + 2 * LANE as u32, + 2 * LANE as u32 + 1 + ] + ); + vcmlaq_rot270_f16(a, b, c) + } } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot270_laneq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] -pub unsafe fn vcmla_rot270_laneq_f32( +pub fn vcmla_rot270_laneq_f32( a: float32x2_t, b: float32x2_t, c: float32x4_t, ) -> float32x2_t { static_assert_uimm_bits!(LANE, 1); - let c: float32x2_t = simd_shuffle!(c, c, [2 * LANE as u32, 2 * LANE as u32 + 1]); - vcmla_rot270_f32(a, b, c) + unsafe { + let c: float32x2_t = simd_shuffle!(c, c, [2 * LANE as u32, 2 * LANE as u32 + 1]); + vcmla_rot270_f32(a, b, c) + } } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot270_laneq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] -pub unsafe fn vcmlaq_rot270_laneq_f32( +pub fn vcmlaq_rot270_laneq_f32( a: float32x4_t, b: float32x4_t, c: float32x4_t, ) -> float32x4_t { static_assert_uimm_bits!(LANE, 1); - let c: float32x4_t = simd_shuffle!( - c, - c, - [ - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1 - ] - ); - vcmlaq_rot270_f32(a, b, c) + unsafe { + let c: float32x4_t = simd_shuffle!( + c, + c, + [ + 2 * LANE as u32, + 2 * LANE as u32 + 1, + 2 * LANE as u32, + 2 * LANE as u32 + 1 + ] + ); + vcmlaq_rot270_f32(a, b, c) + } } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot90_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fcma")] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(fcmla))] -pub unsafe fn vcmla_rot90_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t { +pub fn vcmla_rot90_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -4194,18 +3696,16 @@ pub unsafe fn vcmla_rot90_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> )] fn _vcmla_rot90_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t; } - _vcmla_rot90_f16(a, b, c) + unsafe { _vcmla_rot90_f16(a, b, c) } } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot90_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fcma")] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(fcmla))] -pub unsafe fn vcmlaq_rot90_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t { +pub fn vcmlaq_rot90_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -4213,17 +3713,15 @@ pub unsafe fn vcmlaq_rot90_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) - )] fn _vcmlaq_rot90_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t; } - _vcmlaq_rot90_f16(a, b, c) + unsafe { _vcmlaq_rot90_f16(a, b, c) } } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot90_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fcma")] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] #[cfg_attr(test, assert_instr(fcmla))] -pub unsafe fn vcmla_rot90_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t { +pub fn vcmla_rot90_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -4231,17 +3729,15 @@ pub unsafe fn vcmla_rot90_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> )] fn _vcmla_rot90_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t; } - _vcmla_rot90_f32(a, b, c) + unsafe { _vcmla_rot90_f32(a, b, c) } } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot90_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fcma")] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] #[cfg_attr(test, assert_instr(fcmla))] -pub unsafe fn vcmlaq_rot90_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t { +pub fn vcmlaq_rot90_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -4249,17 +3745,15 @@ pub unsafe fn vcmlaq_rot90_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) - )] fn _vcmlaq_rot90_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t; } - _vcmlaq_rot90_f32(a, b, c) + unsafe { _vcmlaq_rot90_f32(a, b, c) } } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot90_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fcma")] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] #[cfg_attr(test, assert_instr(fcmla))] -pub unsafe fn vcmlaq_rot90_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t { +pub fn vcmlaq_rot90_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -4267,3492 +3761,3455 @@ pub unsafe fn vcmlaq_rot90_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) - )] fn _vcmlaq_rot90_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t; } - _vcmlaq_rot90_f64(a, b, c) + unsafe { _vcmlaq_rot90_f64(a, b, c) } } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot90_lane_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcmla_rot90_lane_f16( +pub fn vcmla_rot90_lane_f16( a: float16x4_t, b: float16x4_t, c: float16x4_t, ) -> float16x4_t { static_assert_uimm_bits!(LANE, 1); - let c: float16x4_t = simd_shuffle!( - c, - c, - [ - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1 - ] - ); - vcmla_rot90_f16(a, b, c) + unsafe { + let c: float16x4_t = simd_shuffle!( + c, + c, + [ + 2 * LANE as u32, + 2 * LANE as u32 + 1, + 2 * LANE as u32, + 2 * LANE as u32 + 1 + ] + ); + vcmla_rot90_f16(a, b, c) + } } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot90_lane_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcmlaq_rot90_lane_f16( +pub fn vcmlaq_rot90_lane_f16( a: float16x8_t, b: float16x8_t, c: float16x4_t, ) -> float16x8_t { static_assert_uimm_bits!(LANE, 1); - let c: float16x8_t = simd_shuffle!( - c, - c, - [ - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1 - ] - ); - vcmlaq_rot90_f16(a, b, c) + unsafe { + let c: float16x8_t = simd_shuffle!( + c, + c, + [ + 2 * LANE as u32, + 2 * LANE as u32 + 1, + 2 * LANE as u32, + 2 * LANE as u32 + 1, + 2 * LANE as u32, + 2 * LANE as u32 + 1, + 2 * LANE as u32, + 2 * LANE as u32 + 1 + ] + ); + vcmlaq_rot90_f16(a, b, c) + } } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot90_lane_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] -pub unsafe fn vcmla_rot90_lane_f32( +pub fn vcmla_rot90_lane_f32( a: float32x2_t, b: float32x2_t, c: float32x2_t, ) -> float32x2_t { static_assert!(LANE == 0); - let c: float32x2_t = simd_shuffle!(c, c, [2 * LANE as u32, 2 * LANE as u32 + 1]); - vcmla_rot90_f32(a, b, c) + unsafe { + let c: float32x2_t = simd_shuffle!(c, c, [2 * LANE as u32, 2 * LANE as u32 + 1]); + vcmla_rot90_f32(a, b, c) + } } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot90_lane_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] -pub unsafe fn vcmlaq_rot90_lane_f32( +pub fn vcmlaq_rot90_lane_f32( a: float32x4_t, b: float32x4_t, c: float32x2_t, ) -> float32x4_t { static_assert!(LANE == 0); - let c: float32x4_t = simd_shuffle!( - c, - c, - [ - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1 - ] - ); - vcmlaq_rot90_f32(a, b, c) + unsafe { + let c: float32x4_t = simd_shuffle!( + c, + c, + [ + 2 * LANE as u32, + 2 * LANE as u32 + 1, + 2 * LANE as u32, + 2 * LANE as u32 + 1 + ] + ); + vcmlaq_rot90_f32(a, b, c) + } } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot90_laneq_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcmla_rot90_laneq_f16( +pub fn vcmla_rot90_laneq_f16( a: float16x4_t, b: float16x4_t, c: float16x8_t, ) -> float16x4_t { static_assert_uimm_bits!(LANE, 2); - let c: float16x4_t = simd_shuffle!( - c, - c, - [ - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1 - ] - ); - vcmla_rot90_f16(a, b, c) + unsafe { + let c: float16x4_t = simd_shuffle!( + c, + c, + [ + 2 * LANE as u32, + 2 * LANE as u32 + 1, + 2 * LANE as u32, + 2 * LANE as u32 + 1 + ] + ); + vcmla_rot90_f16(a, b, c) + } } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot90_laneq_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcmlaq_rot90_laneq_f16( +pub fn vcmlaq_rot90_laneq_f16( a: float16x8_t, b: float16x8_t, c: float16x8_t, ) -> float16x8_t { static_assert_uimm_bits!(LANE, 2); - let c: float16x8_t = simd_shuffle!( - c, - c, - [ - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1 - ] - ); - vcmlaq_rot90_f16(a, b, c) -} -#[doc = "Floating-point complex multiply accumulate"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot90_laneq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] + unsafe { + let c: float16x8_t = simd_shuffle!( + c, + c, + [ + 2 * LANE as u32, + 2 * LANE as u32 + 1, + 2 * LANE as u32, + 2 * LANE as u32 + 1, + 2 * LANE as u32, + 2 * LANE as u32 + 1, + 2 * LANE as u32, + 2 * LANE as u32 + 1 + ] + ); + vcmlaq_rot90_f16(a, b, c) + } +} +#[doc = "Floating-point complex multiply accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot90_laneq_f32)"] #[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] -pub unsafe fn vcmla_rot90_laneq_f32( +pub fn vcmla_rot90_laneq_f32( a: float32x2_t, b: float32x2_t, c: float32x4_t, ) -> float32x2_t { static_assert_uimm_bits!(LANE, 1); - let c: float32x2_t = simd_shuffle!(c, c, [2 * LANE as u32, 2 * LANE as u32 + 1]); - vcmla_rot90_f32(a, b, c) + unsafe { + let c: float32x2_t = simd_shuffle!(c, c, [2 * LANE as u32, 2 * LANE as u32 + 1]); + vcmla_rot90_f32(a, b, c) + } } #[doc = "Floating-point complex multiply accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot90_laneq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fcma")] #[cfg_attr(test, assert_instr(fcmla, LANE = 0))] #[rustc_legacy_const_generics(3)] #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] -pub unsafe fn vcmlaq_rot90_laneq_f32( +pub fn vcmlaq_rot90_laneq_f32( a: float32x4_t, b: float32x4_t, c: float32x4_t, ) -> float32x4_t { static_assert_uimm_bits!(LANE, 1); - let c: float32x4_t = simd_shuffle!( - c, - c, - [ - 2 * LANE as u32, - 2 * LANE as u32 + 1, - 2 * LANE as u32, - 2 * LANE as u32 + 1 - ] - ); - vcmlaq_rot90_f32(a, b, c) + unsafe { + let c: float32x4_t = simd_shuffle!( + c, + c, + [ + 2 * LANE as u32, + 2 * LANE as u32 + 1, + 2 * LANE as u32, + 2 * LANE as u32 + 1 + ] + ); + vcmlaq_rot90_f32(a, b, c) + } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopy_lane_f32( +pub fn vcopy_lane_f32( a: float32x2_t, b: float32x2_t, ) -> float32x2_t { static_assert_uimm_bits!(LANE1, 1); static_assert_uimm_bits!(LANE2, 1); - match LANE1 & 0b1 { - 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), - 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), - _ => unreachable_unchecked(), + unsafe { + match LANE1 & 0b1 { + 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), + 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), + _ => unreachable_unchecked(), + } } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopy_lane_s8( - a: int8x8_t, - b: int8x8_t, -) -> int8x8_t { +pub fn vcopy_lane_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { static_assert_uimm_bits!(LANE1, 3); static_assert_uimm_bits!(LANE2, 3); - match LANE1 & 0b111 { - 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), - 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), - 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), - 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), - 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), - 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), - 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), - _ => unreachable_unchecked(), + unsafe { + match LANE1 & 0b111 { + 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), + 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), + 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), + 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), + 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), + 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), + 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), + 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), + _ => unreachable_unchecked(), + } } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopy_lane_s16( - a: int16x4_t, - b: int16x4_t, -) -> int16x4_t { +pub fn vcopy_lane_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { static_assert_uimm_bits!(LANE1, 2); static_assert_uimm_bits!(LANE2, 2); - match LANE1 & 0b11 { - 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), - 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), - 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), - _ => unreachable_unchecked(), + unsafe { + match LANE1 & 0b11 { + 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), + 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), + 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), + 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), + _ => unreachable_unchecked(), + } } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopy_lane_s32( - a: int32x2_t, - b: int32x2_t, -) -> int32x2_t { +pub fn vcopy_lane_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { static_assert_uimm_bits!(LANE1, 1); static_assert_uimm_bits!(LANE2, 1); - match LANE1 & 0b1 { - 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), - 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), - _ => unreachable_unchecked(), + unsafe { + match LANE1 & 0b1 { + 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), + 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), + _ => unreachable_unchecked(), + } } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopy_lane_u8( - a: uint8x8_t, - b: uint8x8_t, -) -> uint8x8_t { +pub fn vcopy_lane_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { static_assert_uimm_bits!(LANE1, 3); static_assert_uimm_bits!(LANE2, 3); - match LANE1 & 0b111 { - 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), - 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), - 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), - 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), - 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), - 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), - 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), - _ => unreachable_unchecked(), + unsafe { + match LANE1 & 0b111 { + 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), + 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), + 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), + 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), + 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), + 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), + 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), + 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), + _ => unreachable_unchecked(), + } } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopy_lane_u16( +pub fn vcopy_lane_u16( a: uint16x4_t, b: uint16x4_t, ) -> uint16x4_t { static_assert_uimm_bits!(LANE1, 2); static_assert_uimm_bits!(LANE2, 2); - match LANE1 & 0b11 { - 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), - 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), - 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), - _ => unreachable_unchecked(), + unsafe { + match LANE1 & 0b11 { + 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), + 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), + 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), + 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), + _ => unreachable_unchecked(), + } } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopy_lane_u32( +pub fn vcopy_lane_u32( a: uint32x2_t, b: uint32x2_t, ) -> uint32x2_t { static_assert_uimm_bits!(LANE1, 1); static_assert_uimm_bits!(LANE2, 1); - match LANE1 & 0b1 { - 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), - 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), - _ => unreachable_unchecked(), + unsafe { + match LANE1 & 0b1 { + 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), + 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), + _ => unreachable_unchecked(), + } } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopy_lane_p8( - a: poly8x8_t, - b: poly8x8_t, -) -> poly8x8_t { +pub fn vcopy_lane_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { static_assert_uimm_bits!(LANE1, 3); static_assert_uimm_bits!(LANE2, 3); - match LANE1 & 0b111 { - 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), - 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), - 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), - 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), - 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), - 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), - 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), - _ => unreachable_unchecked(), + unsafe { + match LANE1 & 0b111 { + 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), + 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), + 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), + 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), + 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), + 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), + 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), + 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), + _ => unreachable_unchecked(), + } } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopy_lane_p16( +pub fn vcopy_lane_p16( a: poly16x4_t, b: poly16x4_t, ) -> poly16x4_t { static_assert_uimm_bits!(LANE1, 2); static_assert_uimm_bits!(LANE2, 2); - match LANE1 & 0b11 { - 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), - 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), - 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), - _ => unreachable_unchecked(), + unsafe { + match LANE1 & 0b11 { + 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), + 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), + 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), + 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), + _ => unreachable_unchecked(), + } } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopy_laneq_f32( +pub fn vcopy_laneq_f32( a: float32x2_t, b: float32x4_t, ) -> float32x2_t { static_assert_uimm_bits!(LANE1, 1); static_assert_uimm_bits!(LANE2, 2); - let a: float32x4_t = simd_shuffle!(a, a, [0, 1, 2, 3]); - match LANE1 & 0b1 { - 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1]), - 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32]), - _ => unreachable_unchecked(), + let a: float32x4_t = unsafe { simd_shuffle!(a, a, [0, 1, 2, 3]) }; + unsafe { + match LANE1 & 0b1 { + 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1]), + 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32]), + _ => unreachable_unchecked(), + } } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopy_laneq_s8( - a: int8x8_t, - b: int8x16_t, -) -> int8x8_t { +pub fn vcopy_laneq_s8(a: int8x8_t, b: int8x16_t) -> int8x8_t { static_assert_uimm_bits!(LANE1, 3); static_assert_uimm_bits!(LANE2, 4); - let a: int8x16_t = simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]); - match LANE1 & 0b111 { - 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), - 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), - 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7]), - 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7]), - 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7]), - 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7]), - 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32]), - _ => unreachable_unchecked(), + let a: int8x16_t = + unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) }; + unsafe { + match LANE1 & 0b111 { + 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), + 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), + 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7]), + 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7]), + 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7]), + 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7]), + 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7]), + 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32]), + _ => unreachable_unchecked(), + } } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopy_laneq_s16( +pub fn vcopy_laneq_s16( a: int16x4_t, b: int16x8_t, ) -> int16x4_t { static_assert_uimm_bits!(LANE1, 2); static_assert_uimm_bits!(LANE2, 3); - let a: int16x8_t = simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]); - match LANE1 & 0b11 { - 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3]), - 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3]), - 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32]), - _ => unreachable_unchecked(), + let a: int16x8_t = unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]) }; + unsafe { + match LANE1 & 0b11 { + 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3]), + 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3]), + 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3]), + 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32]), + _ => unreachable_unchecked(), + } } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopy_laneq_s32( +pub fn vcopy_laneq_s32( a: int32x2_t, b: int32x4_t, ) -> int32x2_t { static_assert_uimm_bits!(LANE1, 1); static_assert_uimm_bits!(LANE2, 2); - let a: int32x4_t = simd_shuffle!(a, a, [0, 1, 2, 3]); - match LANE1 & 0b1 { - 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1]), - 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32]), - _ => unreachable_unchecked(), + let a: int32x4_t = unsafe { simd_shuffle!(a, a, [0, 1, 2, 3]) }; + unsafe { + match LANE1 & 0b1 { + 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1]), + 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32]), + _ => unreachable_unchecked(), + } } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopy_laneq_u8( +pub fn vcopy_laneq_u8( a: uint8x8_t, b: uint8x16_t, ) -> uint8x8_t { static_assert_uimm_bits!(LANE1, 3); static_assert_uimm_bits!(LANE2, 4); - let a: uint8x16_t = simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]); - match LANE1 & 0b111 { - 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), - 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), - 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7]), - 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7]), - 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7]), - 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7]), - 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32]), - _ => unreachable_unchecked(), + let a: uint8x16_t = + unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) }; + unsafe { + match LANE1 & 0b111 { + 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), + 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), + 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7]), + 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7]), + 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7]), + 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7]), + 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7]), + 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32]), + _ => unreachable_unchecked(), + } } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopy_laneq_u16( +pub fn vcopy_laneq_u16( a: uint16x4_t, b: uint16x8_t, ) -> uint16x4_t { static_assert_uimm_bits!(LANE1, 2); static_assert_uimm_bits!(LANE2, 3); - let a: uint16x8_t = simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]); - match LANE1 & 0b11 { - 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3]), - 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3]), - 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32]), - _ => unreachable_unchecked(), + let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]) }; + unsafe { + match LANE1 & 0b11 { + 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3]), + 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3]), + 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3]), + 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32]), + _ => unreachable_unchecked(), + } } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopy_laneq_u32( +pub fn vcopy_laneq_u32( a: uint32x2_t, b: uint32x4_t, ) -> uint32x2_t { static_assert_uimm_bits!(LANE1, 1); static_assert_uimm_bits!(LANE2, 2); - let a: uint32x4_t = simd_shuffle!(a, a, [0, 1, 2, 3]); - match LANE1 & 0b1 { - 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1]), - 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32]), - _ => unreachable_unchecked(), + let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [0, 1, 2, 3]) }; + unsafe { + match LANE1 & 0b1 { + 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1]), + 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32]), + _ => unreachable_unchecked(), + } } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopy_laneq_p8( +pub fn vcopy_laneq_p8( a: poly8x8_t, b: poly8x16_t, ) -> poly8x8_t { static_assert_uimm_bits!(LANE1, 3); static_assert_uimm_bits!(LANE2, 4); - let a: poly8x16_t = simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]); - match LANE1 & 0b111 { - 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), - 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), - 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7]), - 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7]), - 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7]), - 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7]), - 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32]), - _ => unreachable_unchecked(), + let a: poly8x16_t = + unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) }; + unsafe { + match LANE1 & 0b111 { + 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), + 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), + 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7]), + 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7]), + 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7]), + 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7]), + 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7]), + 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32]), + _ => unreachable_unchecked(), + } } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopy_laneq_p16( +pub fn vcopy_laneq_p16( a: poly16x4_t, b: poly16x8_t, ) -> poly16x4_t { static_assert_uimm_bits!(LANE1, 2); static_assert_uimm_bits!(LANE2, 3); - let a: poly16x8_t = simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]); - match LANE1 & 0b11 { - 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3]), - 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3]), - 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32]), - _ => unreachable_unchecked(), + let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]) }; + unsafe { + match LANE1 & 0b11 { + 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3]), + 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3]), + 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3]), + 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32]), + _ => unreachable_unchecked(), + } } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(mov, LANE1 = 1, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopyq_lane_f32( +pub fn vcopyq_lane_f32( a: float32x4_t, b: float32x2_t, ) -> float32x4_t { static_assert_uimm_bits!(LANE1, 2); static_assert_uimm_bits!(LANE2, 1); - let b: float32x4_t = simd_shuffle!(b, b, [0, 1, 2, 3]); - match LANE1 & 0b11 { - 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), - 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), - 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), - _ => unreachable_unchecked(), + let b: float32x4_t = unsafe { simd_shuffle!(b, b, [0, 1, 2, 3]) }; + unsafe { + match LANE1 & 0b11 { + 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), + 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), + 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), + 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), + _ => unreachable_unchecked(), + } } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(mov, LANE1 = 1, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopyq_lane_f64( +pub fn vcopyq_lane_f64( a: float64x2_t, b: float64x1_t, ) -> float64x2_t { static_assert_uimm_bits!(LANE1, 1); static_assert!(LANE2 == 0); - let b: float64x2_t = simd_shuffle!(b, b, [0, 1]); - match LANE1 & 0b1 { - 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), - 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), - _ => unreachable_unchecked(), + let b: float64x2_t = unsafe { simd_shuffle!(b, b, [0, 1]) }; + unsafe { + match LANE1 & 0b1 { + 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), + 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), + _ => unreachable_unchecked(), + } } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(mov, LANE1 = 1, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopyq_lane_s64( +pub fn vcopyq_lane_s64( a: int64x2_t, b: int64x1_t, ) -> int64x2_t { static_assert_uimm_bits!(LANE1, 1); static_assert!(LANE2 == 0); - let b: int64x2_t = simd_shuffle!(b, b, [0, 1]); - match LANE1 & 0b1 { - 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), - 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), - _ => unreachable_unchecked(), + let b: int64x2_t = unsafe { simd_shuffle!(b, b, [0, 1]) }; + unsafe { + match LANE1 & 0b1 { + 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), + 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), + _ => unreachable_unchecked(), + } } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(mov, LANE1 = 1, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopyq_lane_u64( +pub fn vcopyq_lane_u64( a: uint64x2_t, b: uint64x1_t, ) -> uint64x2_t { static_assert_uimm_bits!(LANE1, 1); static_assert!(LANE2 == 0); - let b: uint64x2_t = simd_shuffle!(b, b, [0, 1]); - match LANE1 & 0b1 { - 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), - 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), - _ => unreachable_unchecked(), + let b: uint64x2_t = unsafe { simd_shuffle!(b, b, [0, 1]) }; + unsafe { + match LANE1 & 0b1 { + 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), + 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), + _ => unreachable_unchecked(), + } } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(mov, LANE1 = 1, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopyq_lane_p64( +pub fn vcopyq_lane_p64( a: poly64x2_t, b: poly64x1_t, ) -> poly64x2_t { static_assert_uimm_bits!(LANE1, 1); static_assert!(LANE2 == 0); - let b: poly64x2_t = simd_shuffle!(b, b, [0, 1]); - match LANE1 & 0b1 { - 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), - 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), - _ => unreachable_unchecked(), + let b: poly64x2_t = unsafe { simd_shuffle!(b, b, [0, 1]) }; + unsafe { + match LANE1 & 0b1 { + 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), + 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), + _ => unreachable_unchecked(), + } } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopyq_lane_s8( - a: int8x16_t, - b: int8x8_t, -) -> int8x16_t { +pub fn vcopyq_lane_s8(a: int8x16_t, b: int8x8_t) -> int8x16_t { static_assert_uimm_bits!(LANE1, 4); static_assert_uimm_bits!(LANE2, 3); - let b: int8x16_t = simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]); - match LANE1 & 0b1111 { - 0 => simd_shuffle!( - a, - b, - [ - 16 + LANE2 as u32, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 1 => simd_shuffle!( - a, - b, - [ - 0, - 16 + LANE2 as u32, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 2 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 16 + LANE2 as u32, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 3 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 16 + LANE2 as u32, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 4 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 16 + LANE2 as u32, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 5 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 16 + LANE2 as u32, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 6 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 16 + LANE2 as u32, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 7 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 16 + LANE2 as u32, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 8 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 16 + LANE2 as u32, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 9 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 16 + LANE2 as u32, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 10 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 16 + LANE2 as u32, - 11, - 12, - 13, - 14, - 15 - ] - ), - 11 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 16 + LANE2 as u32, - 12, - 13, - 14, - 15 - ] - ), - 12 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 16 + LANE2 as u32, - 13, - 14, - 15 - ] - ), - 13 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 16 + LANE2 as u32, - 14, - 15 - ] - ), - 14 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 16 + LANE2 as u32, - 15 - ] - ), - 15 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 16 + LANE2 as u32 - ] - ), - _ => unreachable_unchecked(), + let b: int8x16_t = + unsafe { simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) }; + unsafe { + match LANE1 & 0b1111 { + 0 => simd_shuffle!( + a, + b, + [ + 16 + LANE2 as u32, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 1 => simd_shuffle!( + a, + b, + [ + 0, + 16 + LANE2 as u32, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 2 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 16 + LANE2 as u32, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 3 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 16 + LANE2 as u32, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 4 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 16 + LANE2 as u32, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 5 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 16 + LANE2 as u32, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 6 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 16 + LANE2 as u32, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 7 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 16 + LANE2 as u32, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 8 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 16 + LANE2 as u32, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 9 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 16 + LANE2 as u32, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 10 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 16 + LANE2 as u32, + 11, + 12, + 13, + 14, + 15 + ] + ), + 11 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 16 + LANE2 as u32, + 12, + 13, + 14, + 15 + ] + ), + 12 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 16 + LANE2 as u32, + 13, + 14, + 15 + ] + ), + 13 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 16 + LANE2 as u32, + 14, + 15 + ] + ), + 14 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 16 + LANE2 as u32, + 15 + ] + ), + 15 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 16 + LANE2 as u32 + ] + ), + _ => unreachable_unchecked(), + } } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopyq_lane_s16( +pub fn vcopyq_lane_s16( a: int16x8_t, b: int16x4_t, ) -> int16x8_t { static_assert_uimm_bits!(LANE1, 3); static_assert_uimm_bits!(LANE2, 2); - let b: int16x8_t = simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7]); - match LANE1 & 0b111 { - 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), - 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), - 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), - 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), - 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), - 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), - 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), - _ => unreachable_unchecked(), + let b: int16x8_t = unsafe { simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7]) }; + unsafe { + match LANE1 & 0b111 { + 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), + 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), + 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), + 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), + 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), + 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), + 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), + 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), + _ => unreachable_unchecked(), + } } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopyq_lane_s32( +pub fn vcopyq_lane_s32( a: int32x4_t, b: int32x2_t, ) -> int32x4_t { static_assert_uimm_bits!(LANE1, 2); static_assert_uimm_bits!(LANE2, 1); - let b: int32x4_t = simd_shuffle!(b, b, [0, 1, 2, 3]); - match LANE1 & 0b11 { - 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), - 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), - 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), - _ => unreachable_unchecked(), + let b: int32x4_t = unsafe { simd_shuffle!(b, b, [0, 1, 2, 3]) }; + unsafe { + match LANE1 & 0b11 { + 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), + 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), + 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), + 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), + _ => unreachable_unchecked(), + } } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopyq_lane_u8( +pub fn vcopyq_lane_u8( a: uint8x16_t, b: uint8x8_t, ) -> uint8x16_t { static_assert_uimm_bits!(LANE1, 4); static_assert_uimm_bits!(LANE2, 3); - let b: uint8x16_t = simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]); - match LANE1 & 0b1111 { - 0 => simd_shuffle!( - a, - b, - [ - 16 + LANE2 as u32, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 1 => simd_shuffle!( - a, - b, - [ - 0, - 16 + LANE2 as u32, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 2 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 16 + LANE2 as u32, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 3 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 16 + LANE2 as u32, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 4 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 16 + LANE2 as u32, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 5 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 16 + LANE2 as u32, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 6 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 16 + LANE2 as u32, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 7 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 16 + LANE2 as u32, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 8 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 16 + LANE2 as u32, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 9 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 16 + LANE2 as u32, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 10 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 16 + LANE2 as u32, - 11, - 12, - 13, - 14, - 15 - ] - ), - 11 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 16 + LANE2 as u32, - 12, - 13, - 14, - 15 - ] - ), - 12 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 16 + LANE2 as u32, - 13, - 14, - 15 - ] - ), - 13 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 16 + LANE2 as u32, - 14, - 15 - ] - ), - 14 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 16 + LANE2 as u32, - 15 - ] - ), - 15 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 16 + LANE2 as u32 - ] - ), - _ => unreachable_unchecked(), + let b: uint8x16_t = + unsafe { simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) }; + unsafe { + match LANE1 & 0b1111 { + 0 => simd_shuffle!( + a, + b, + [ + 16 + LANE2 as u32, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 1 => simd_shuffle!( + a, + b, + [ + 0, + 16 + LANE2 as u32, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 2 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 16 + LANE2 as u32, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 3 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 16 + LANE2 as u32, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 4 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 16 + LANE2 as u32, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 5 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 16 + LANE2 as u32, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 6 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 16 + LANE2 as u32, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 7 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 16 + LANE2 as u32, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 8 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 16 + LANE2 as u32, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 9 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 16 + LANE2 as u32, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 10 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 16 + LANE2 as u32, + 11, + 12, + 13, + 14, + 15 + ] + ), + 11 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 16 + LANE2 as u32, + 12, + 13, + 14, + 15 + ] + ), + 12 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 16 + LANE2 as u32, + 13, + 14, + 15 + ] + ), + 13 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 16 + LANE2 as u32, + 14, + 15 + ] + ), + 14 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 16 + LANE2 as u32, + 15 + ] + ), + 15 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 16 + LANE2 as u32 + ] + ), + _ => unreachable_unchecked(), + } } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopyq_lane_u16( +pub fn vcopyq_lane_u16( a: uint16x8_t, b: uint16x4_t, ) -> uint16x8_t { static_assert_uimm_bits!(LANE1, 3); static_assert_uimm_bits!(LANE2, 2); - let b: uint16x8_t = simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7]); - match LANE1 & 0b111 { - 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), - 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), - 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), - 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), - 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), - 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), - 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), - _ => unreachable_unchecked(), + let b: uint16x8_t = unsafe { simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7]) }; + unsafe { + match LANE1 & 0b111 { + 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), + 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), + 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), + 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), + 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), + 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), + 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), + 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), + _ => unreachable_unchecked(), + } } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopyq_lane_u32( +pub fn vcopyq_lane_u32( a: uint32x4_t, b: uint32x2_t, ) -> uint32x4_t { static_assert_uimm_bits!(LANE1, 2); static_assert_uimm_bits!(LANE2, 1); - let b: uint32x4_t = simd_shuffle!(b, b, [0, 1, 2, 3]); - match LANE1 & 0b11 { - 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), - 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), - 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), - _ => unreachable_unchecked(), + let b: uint32x4_t = unsafe { simd_shuffle!(b, b, [0, 1, 2, 3]) }; + unsafe { + match LANE1 & 0b11 { + 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), + 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), + 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), + 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), + _ => unreachable_unchecked(), + } } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopyq_lane_p8( +pub fn vcopyq_lane_p8( a: poly8x16_t, b: poly8x8_t, ) -> poly8x16_t { static_assert_uimm_bits!(LANE1, 4); static_assert_uimm_bits!(LANE2, 3); - let b: poly8x16_t = simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]); - match LANE1 & 0b1111 { - 0 => simd_shuffle!( - a, - b, - [ - 16 + LANE2 as u32, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 1 => simd_shuffle!( - a, - b, - [ - 0, - 16 + LANE2 as u32, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 2 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 16 + LANE2 as u32, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 3 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 16 + LANE2 as u32, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 4 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 16 + LANE2 as u32, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 5 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 16 + LANE2 as u32, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 6 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 16 + LANE2 as u32, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 7 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 16 + LANE2 as u32, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 8 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 16 + LANE2 as u32, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 9 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 16 + LANE2 as u32, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 10 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 16 + LANE2 as u32, - 11, - 12, - 13, - 14, - 15 - ] - ), - 11 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 16 + LANE2 as u32, - 12, - 13, - 14, - 15 - ] - ), - 12 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 16 + LANE2 as u32, - 13, - 14, - 15 - ] - ), - 13 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 16 + LANE2 as u32, - 14, - 15 - ] - ), - 14 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 16 + LANE2 as u32, - 15 - ] - ), - 15 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 16 + LANE2 as u32 - ] - ), - _ => unreachable_unchecked(), + let b: poly8x16_t = + unsafe { simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) }; + unsafe { + match LANE1 & 0b1111 { + 0 => simd_shuffle!( + a, + b, + [ + 16 + LANE2 as u32, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 1 => simd_shuffle!( + a, + b, + [ + 0, + 16 + LANE2 as u32, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 2 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 16 + LANE2 as u32, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 3 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 16 + LANE2 as u32, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 4 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 16 + LANE2 as u32, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 5 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 16 + LANE2 as u32, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 6 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 16 + LANE2 as u32, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 7 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 16 + LANE2 as u32, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 8 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 16 + LANE2 as u32, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 9 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 16 + LANE2 as u32, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 10 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 16 + LANE2 as u32, + 11, + 12, + 13, + 14, + 15 + ] + ), + 11 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 16 + LANE2 as u32, + 12, + 13, + 14, + 15 + ] + ), + 12 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 16 + LANE2 as u32, + 13, + 14, + 15 + ] + ), + 13 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 16 + LANE2 as u32, + 14, + 15 + ] + ), + 14 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 16 + LANE2 as u32, + 15 + ] + ), + 15 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 16 + LANE2 as u32 + ] + ), + _ => unreachable_unchecked(), + } } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopyq_lane_p16( +pub fn vcopyq_lane_p16( a: poly16x8_t, b: poly16x4_t, ) -> poly16x8_t { static_assert_uimm_bits!(LANE1, 3); static_assert_uimm_bits!(LANE2, 2); - let b: poly16x8_t = simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7]); - match LANE1 & 0b111 { - 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), - 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), - 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), - 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), - 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), - 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), - 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), - _ => unreachable_unchecked(), + let b: poly16x8_t = unsafe { simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7]) }; + unsafe { + match LANE1 & 0b111 { + 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), + 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), + 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), + 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), + 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), + 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), + 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), + 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), + _ => unreachable_unchecked(), + } } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopyq_laneq_f32( +pub fn vcopyq_laneq_f32( a: float32x4_t, b: float32x4_t, ) -> float32x4_t { static_assert_uimm_bits!(LANE1, 2); static_assert_uimm_bits!(LANE2, 2); - match LANE1 & 0b11 { - 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), - 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), - 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), - _ => unreachable_unchecked(), + unsafe { + match LANE1 & 0b11 { + 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), + 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), + 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), + 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), + _ => unreachable_unchecked(), + } } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopyq_laneq_f64( +pub fn vcopyq_laneq_f64( a: float64x2_t, b: float64x2_t, ) -> float64x2_t { static_assert_uimm_bits!(LANE1, 1); static_assert_uimm_bits!(LANE2, 1); - match LANE1 & 0b1 { - 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), - 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), - _ => unreachable_unchecked(), + unsafe { + match LANE1 & 0b1 { + 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), + 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), + _ => unreachable_unchecked(), + } } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopyq_laneq_s8( +pub fn vcopyq_laneq_s8( a: int8x16_t, b: int8x16_t, ) -> int8x16_t { - static_assert_uimm_bits!(LANE1, 4); - static_assert_uimm_bits!(LANE2, 4); - match LANE1 & 0b1111 { - 0 => simd_shuffle!( - a, - b, - [ - 16 + LANE2 as u32, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 1 => simd_shuffle!( - a, - b, - [ - 0, - 16 + LANE2 as u32, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 2 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 16 + LANE2 as u32, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 3 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 16 + LANE2 as u32, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 4 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 16 + LANE2 as u32, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 5 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 16 + LANE2 as u32, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 6 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 16 + LANE2 as u32, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 7 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 16 + LANE2 as u32, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 8 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 16 + LANE2 as u32, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 9 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 16 + LANE2 as u32, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 10 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 16 + LANE2 as u32, - 11, - 12, - 13, - 14, - 15 - ] - ), - 11 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 16 + LANE2 as u32, - 12, - 13, - 14, - 15 - ] - ), - 12 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 16 + LANE2 as u32, - 13, - 14, - 15 - ] - ), - 13 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 16 + LANE2 as u32, - 14, - 15 - ] - ), - 14 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 16 + LANE2 as u32, - 15 - ] - ), - 15 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 16 + LANE2 as u32 - ] - ), - _ => unreachable_unchecked(), - } -} -#[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] -#[rustc_legacy_const_generics(1, 3)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopyq_laneq_s16( - a: int16x8_t, - b: int16x8_t, -) -> int16x8_t { - static_assert_uimm_bits!(LANE1, 3); - static_assert_uimm_bits!(LANE2, 3); - match LANE1 & 0b111 { - 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), - 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), - 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), - 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), - 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), - 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), - 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), - _ => unreachable_unchecked(), - } -} -#[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] -#[rustc_legacy_const_generics(1, 3)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopyq_laneq_s32( - a: int32x4_t, - b: int32x4_t, -) -> int32x4_t { - static_assert_uimm_bits!(LANE1, 2); - static_assert_uimm_bits!(LANE2, 2); - match LANE1 & 0b11 { - 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), - 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), - 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), - _ => unreachable_unchecked(), - } -} -#[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] -#[rustc_legacy_const_generics(1, 3)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopyq_laneq_s64( - a: int64x2_t, - b: int64x2_t, -) -> int64x2_t { - static_assert_uimm_bits!(LANE1, 1); - static_assert_uimm_bits!(LANE2, 1); - match LANE1 & 0b1 { - 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), - 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), - _ => unreachable_unchecked(), - } -} -#[doc = "Insert vector element from another vector element"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] -#[rustc_legacy_const_generics(1, 3)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopyq_laneq_u8( - a: uint8x16_t, - b: uint8x16_t, -) -> uint8x16_t { - static_assert_uimm_bits!(LANE1, 4); - static_assert_uimm_bits!(LANE2, 4); - match LANE1 & 0b1111 { - 0 => simd_shuffle!( - a, - b, - [ - 16 + LANE2 as u32, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 1 => simd_shuffle!( - a, - b, - [ - 0, - 16 + LANE2 as u32, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 2 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 16 + LANE2 as u32, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 3 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 16 + LANE2 as u32, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 4 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 16 + LANE2 as u32, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 5 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 16 + LANE2 as u32, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 6 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 16 + LANE2 as u32, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 7 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 16 + LANE2 as u32, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 8 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 16 + LANE2 as u32, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 9 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 16 + LANE2 as u32, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 10 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 16 + LANE2 as u32, - 11, - 12, - 13, - 14, - 15 - ] - ), - 11 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 16 + LANE2 as u32, - 12, - 13, - 14, - 15 - ] - ), - 12 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 16 + LANE2 as u32, - 13, - 14, - 15 - ] - ), - 13 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 16 + LANE2 as u32, - 14, - 15 - ] - ), - 14 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 16 + LANE2 as u32, - 15 - ] - ), - 15 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 16 + LANE2 as u32 - ] - ), - _ => unreachable_unchecked(), + static_assert_uimm_bits!(LANE1, 4); + static_assert_uimm_bits!(LANE2, 4); + unsafe { + match LANE1 & 0b1111 { + 0 => simd_shuffle!( + a, + b, + [ + 16 + LANE2 as u32, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 1 => simd_shuffle!( + a, + b, + [ + 0, + 16 + LANE2 as u32, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 2 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 16 + LANE2 as u32, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 3 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 16 + LANE2 as u32, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 4 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 16 + LANE2 as u32, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 5 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 16 + LANE2 as u32, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 6 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 16 + LANE2 as u32, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 7 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 16 + LANE2 as u32, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 8 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 16 + LANE2 as u32, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 9 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 16 + LANE2 as u32, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 10 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 16 + LANE2 as u32, + 11, + 12, + 13, + 14, + 15 + ] + ), + 11 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 16 + LANE2 as u32, + 12, + 13, + 14, + 15 + ] + ), + 12 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 16 + LANE2 as u32, + 13, + 14, + 15 + ] + ), + 13 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 16 + LANE2 as u32, + 14, + 15 + ] + ), + 14 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 16 + LANE2 as u32, + 15 + ] + ), + 15 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 16 + LANE2 as u32 + ] + ), + _ => unreachable_unchecked(), + } + } +} +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_s16)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[rustc_legacy_const_generics(1, 3)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vcopyq_laneq_s16( + a: int16x8_t, + b: int16x8_t, +) -> int16x8_t { + static_assert_uimm_bits!(LANE1, 3); + static_assert_uimm_bits!(LANE2, 3); + unsafe { + match LANE1 & 0b111 { + 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), + 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), + 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), + 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), + 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), + 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), + 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), + 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), + _ => unreachable_unchecked(), + } + } +} +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_s32)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[rustc_legacy_const_generics(1, 3)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vcopyq_laneq_s32( + a: int32x4_t, + b: int32x4_t, +) -> int32x4_t { + static_assert_uimm_bits!(LANE1, 2); + static_assert_uimm_bits!(LANE2, 2); + unsafe { + match LANE1 & 0b11 { + 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), + 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), + 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), + 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), + _ => unreachable_unchecked(), + } + } +} +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_s64)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[rustc_legacy_const_generics(1, 3)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vcopyq_laneq_s64( + a: int64x2_t, + b: int64x2_t, +) -> int64x2_t { + static_assert_uimm_bits!(LANE1, 1); + static_assert_uimm_bits!(LANE2, 1); + unsafe { + match LANE1 & 0b1 { + 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), + 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), + _ => unreachable_unchecked(), + } + } +} +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_u8)"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[rustc_legacy_const_generics(1, 3)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub fn vcopyq_laneq_u8( + a: uint8x16_t, + b: uint8x16_t, +) -> uint8x16_t { + static_assert_uimm_bits!(LANE1, 4); + static_assert_uimm_bits!(LANE2, 4); + unsafe { + match LANE1 & 0b1111 { + 0 => simd_shuffle!( + a, + b, + [ + 16 + LANE2 as u32, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 1 => simd_shuffle!( + a, + b, + [ + 0, + 16 + LANE2 as u32, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 2 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 16 + LANE2 as u32, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 3 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 16 + LANE2 as u32, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 4 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 16 + LANE2 as u32, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 5 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 16 + LANE2 as u32, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 6 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 16 + LANE2 as u32, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 7 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 16 + LANE2 as u32, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 8 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 16 + LANE2 as u32, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 9 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 16 + LANE2 as u32, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 10 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 16 + LANE2 as u32, + 11, + 12, + 13, + 14, + 15 + ] + ), + 11 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 16 + LANE2 as u32, + 12, + 13, + 14, + 15 + ] + ), + 12 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 16 + LANE2 as u32, + 13, + 14, + 15 + ] + ), + 13 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 16 + LANE2 as u32, + 14, + 15 + ] + ), + 14 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 16 + LANE2 as u32, + 15 + ] + ), + 15 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 16 + LANE2 as u32 + ] + ), + _ => unreachable_unchecked(), + } } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopyq_laneq_u16( +pub fn vcopyq_laneq_u16( a: uint16x8_t, b: uint16x8_t, ) -> uint16x8_t { static_assert_uimm_bits!(LANE1, 3); static_assert_uimm_bits!(LANE2, 3); - match LANE1 & 0b111 { - 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), - 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), - 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), - 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), - 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), - 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), - 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), - _ => unreachable_unchecked(), + unsafe { + match LANE1 & 0b111 { + 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), + 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), + 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), + 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), + 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), + 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), + 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), + 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), + _ => unreachable_unchecked(), + } } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopyq_laneq_u32( +pub fn vcopyq_laneq_u32( a: uint32x4_t, b: uint32x4_t, ) -> uint32x4_t { static_assert_uimm_bits!(LANE1, 2); static_assert_uimm_bits!(LANE2, 2); - match LANE1 & 0b11 { - 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), - 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), - 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), - _ => unreachable_unchecked(), + unsafe { + match LANE1 & 0b11 { + 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), + 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), + 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), + 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), + _ => unreachable_unchecked(), + } } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopyq_laneq_u64( +pub fn vcopyq_laneq_u64( a: uint64x2_t, b: uint64x2_t, ) -> uint64x2_t { static_assert_uimm_bits!(LANE1, 1); static_assert_uimm_bits!(LANE2, 1); - match LANE1 & 0b1 { - 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), - 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), - _ => unreachable_unchecked(), + unsafe { + match LANE1 & 0b1 { + 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), + 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), + _ => unreachable_unchecked(), + } } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopyq_laneq_p8( +pub fn vcopyq_laneq_p8( a: poly8x16_t, b: poly8x16_t, ) -> poly8x16_t { static_assert_uimm_bits!(LANE1, 4); static_assert_uimm_bits!(LANE2, 4); - match LANE1 & 0b1111 { - 0 => simd_shuffle!( - a, - b, - [ - 16 + LANE2 as u32, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 1 => simd_shuffle!( - a, - b, - [ - 0, - 16 + LANE2 as u32, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 2 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 16 + LANE2 as u32, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 3 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 16 + LANE2 as u32, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 4 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 16 + LANE2 as u32, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 5 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 16 + LANE2 as u32, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 6 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 16 + LANE2 as u32, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 7 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 16 + LANE2 as u32, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 8 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 16 + LANE2 as u32, - 9, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 9 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 16 + LANE2 as u32, - 10, - 11, - 12, - 13, - 14, - 15 - ] - ), - 10 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 16 + LANE2 as u32, - 11, - 12, - 13, - 14, - 15 - ] - ), - 11 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 16 + LANE2 as u32, - 12, - 13, - 14, - 15 - ] - ), - 12 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 16 + LANE2 as u32, - 13, - 14, - 15 - ] - ), - 13 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 16 + LANE2 as u32, - 14, - 15 - ] - ), - 14 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 16 + LANE2 as u32, - 15 - ] - ), - 15 => simd_shuffle!( - a, - b, - [ - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 16 + LANE2 as u32 - ] - ), - _ => unreachable_unchecked(), + unsafe { + match LANE1 & 0b1111 { + 0 => simd_shuffle!( + a, + b, + [ + 16 + LANE2 as u32, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 1 => simd_shuffle!( + a, + b, + [ + 0, + 16 + LANE2 as u32, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 2 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 16 + LANE2 as u32, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 3 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 16 + LANE2 as u32, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 4 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 16 + LANE2 as u32, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 5 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 16 + LANE2 as u32, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 6 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 16 + LANE2 as u32, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 7 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 16 + LANE2 as u32, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 8 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 16 + LANE2 as u32, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 9 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 16 + LANE2 as u32, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 10 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 16 + LANE2 as u32, + 11, + 12, + 13, + 14, + 15 + ] + ), + 11 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 16 + LANE2 as u32, + 12, + 13, + 14, + 15 + ] + ), + 12 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 16 + LANE2 as u32, + 13, + 14, + 15 + ] + ), + 13 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 16 + LANE2 as u32, + 14, + 15 + ] + ), + 14 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 16 + LANE2 as u32, + 15 + ] + ), + 15 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 16 + LANE2 as u32 + ] + ), + _ => unreachable_unchecked(), + } } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopyq_laneq_p16( +pub fn vcopyq_laneq_p16( a: poly16x8_t, b: poly16x8_t, ) -> poly16x8_t { static_assert_uimm_bits!(LANE1, 3); static_assert_uimm_bits!(LANE2, 3); - match LANE1 & 0b111 { - 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), - 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), - 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), - 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), - 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), - 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), - 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), - _ => unreachable_unchecked(), + unsafe { + match LANE1 & 0b111 { + 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), + 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), + 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), + 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), + 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), + 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), + 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), + 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), + _ => unreachable_unchecked(), + } } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopyq_laneq_p64( +pub fn vcopyq_laneq_p64( a: poly64x2_t, b: poly64x2_t, ) -> poly64x2_t { static_assert_uimm_bits!(LANE1, 1); static_assert_uimm_bits!(LANE2, 1); - match LANE1 & 0b1 { - 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), - 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), - _ => unreachable_unchecked(), + unsafe { + match LANE1 & 0b1 { + 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), + 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), + _ => unreachable_unchecked(), + } } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcreate_f64(a: u64) -> float64x1_t { - transmute(a) +pub fn vcreate_f64(a: u64) -> float64x1_t { + unsafe { transmute(a) } } #[doc = "Floating-point convert"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f32_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtn))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvt_f32_f64(a: float64x2_t) -> float32x2_t { - simd_cast(a) +pub fn vcvt_f32_f64(a: float64x2_t) -> float32x2_t { + unsafe { simd_cast(a) } } #[doc = "Floating-point convert to higher precision long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f64_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvt_f64_f32(a: float32x2_t) -> float64x2_t { - simd_cast(a) +pub fn vcvt_f64_f32(a: float32x2_t) -> float64x2_t { + unsafe { simd_cast(a) } } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f64_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(scvtf))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvt_f64_s64(a: int64x1_t) -> float64x1_t { - simd_cast(a) +pub fn vcvt_f64_s64(a: int64x1_t) -> float64x1_t { + unsafe { simd_cast(a) } } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_f64_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(scvtf))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtq_f64_s64(a: int64x2_t) -> float64x2_t { - simd_cast(a) +pub fn vcvtq_f64_s64(a: int64x2_t) -> float64x2_t { + unsafe { simd_cast(a) } } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f64_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ucvtf))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvt_f64_u64(a: uint64x1_t) -> float64x1_t { - simd_cast(a) +pub fn vcvt_f64_u64(a: uint64x1_t) -> float64x1_t { + unsafe { simd_cast(a) } } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_f64_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ucvtf))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtq_f64_u64(a: uint64x2_t) -> float64x2_t { - simd_cast(a) +pub fn vcvtq_f64_u64(a: uint64x2_t) -> float64x2_t { + unsafe { simd_cast(a) } } #[doc = "Floating-point convert to lower precision"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_high_f16_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fcvtn2))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvt_high_f16_f32(a: float16x4_t, b: float32x4_t) -> float16x8_t { +pub fn vcvt_high_f16_f32(a: float16x4_t, b: float32x4_t) -> float16x8_t { vcombine_f16(a, vcvt_f16_f32(b)) } #[doc = "Floating-point convert to higher precision"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_high_f32_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fcvtl2))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvt_high_f32_f16(a: float16x8_t) -> float32x4_t { +pub fn vcvt_high_f32_f16(a: float16x8_t) -> float32x4_t { vcvt_f32_f16(vget_high_f16(a)) } #[doc = "Floating-point convert to lower precision narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_high_f32_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtn))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvt_high_f32_f64(a: float32x2_t, b: float64x2_t) -> float32x4_t { - simd_shuffle!(a, simd_cast(b), [0, 1, 2, 3]) +pub fn vcvt_high_f32_f64(a: float32x2_t, b: float64x2_t) -> float32x4_t { + unsafe { simd_shuffle!(a, simd_cast(b), [0, 1, 2, 3]) } } #[doc = "Floating-point convert to higher precision long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_high_f64_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvt_high_f64_f32(a: float32x4_t) -> float64x2_t { - let b: float32x2_t = simd_shuffle!(a, a, [2, 3]); - simd_cast(b) +pub fn vcvt_high_f64_f32(a: float32x4_t) -> float64x2_t { + unsafe { + let b: float32x2_t = simd_shuffle!(a, a, [2, 3]); + simd_cast(b) + } } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f64_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(scvtf, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvt_n_f64_s64(a: int64x1_t) -> float64x1_t { +pub fn vcvt_n_f64_s64(a: int64x1_t) -> float64x1_t { static_assert!(N >= 1 && N <= 64); unsafe extern "unadjusted" { #[cfg_attr( @@ -7761,18 +7218,16 @@ pub unsafe fn vcvt_n_f64_s64(a: int64x1_t) -> float64x1_t { )] fn _vcvt_n_f64_s64(a: int64x1_t, n: i32) -> float64x1_t; } - _vcvt_n_f64_s64(a, N) + unsafe { _vcvt_n_f64_s64(a, N) } } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f64_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(scvtf, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtq_n_f64_s64(a: int64x2_t) -> float64x2_t { +pub fn vcvtq_n_f64_s64(a: int64x2_t) -> float64x2_t { static_assert!(N >= 1 && N <= 64); unsafe extern "unadjusted" { #[cfg_attr( @@ -7781,18 +7236,16 @@ pub unsafe fn vcvtq_n_f64_s64(a: int64x2_t) -> float64x2_t { )] fn _vcvtq_n_f64_s64(a: int64x2_t, n: i32) -> float64x2_t; } - _vcvtq_n_f64_s64(a, N) + unsafe { _vcvtq_n_f64_s64(a, N) } } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f64_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ucvtf, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvt_n_f64_u64(a: uint64x1_t) -> float64x1_t { +pub fn vcvt_n_f64_u64(a: uint64x1_t) -> float64x1_t { static_assert!(N >= 1 && N <= 64); unsafe extern "unadjusted" { #[cfg_attr( @@ -7801,18 +7254,16 @@ pub unsafe fn vcvt_n_f64_u64(a: uint64x1_t) -> float64x1_t { )] fn _vcvt_n_f64_u64(a: uint64x1_t, n: i32) -> float64x1_t; } - _vcvt_n_f64_u64(a, N) + unsafe { _vcvt_n_f64_u64(a, N) } } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f64_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ucvtf, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtq_n_f64_u64(a: uint64x2_t) -> float64x2_t { +pub fn vcvtq_n_f64_u64(a: uint64x2_t) -> float64x2_t { static_assert!(N >= 1 && N <= 64); unsafe extern "unadjusted" { #[cfg_attr( @@ -7821,18 +7272,16 @@ pub unsafe fn vcvtq_n_f64_u64(a: uint64x2_t) -> float64x2_t { )] fn _vcvtq_n_f64_u64(a: uint64x2_t, n: i32) -> float64x2_t; } - _vcvtq_n_f64_u64(a, N) + unsafe { _vcvtq_n_f64_u64(a, N) } } #[doc = "Floating-point convert to fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_s64_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtzs, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvt_n_s64_f64(a: float64x1_t) -> int64x1_t { +pub fn vcvt_n_s64_f64(a: float64x1_t) -> int64x1_t { static_assert!(N >= 1 && N <= 64); unsafe extern "unadjusted" { #[cfg_attr( @@ -7841,18 +7290,16 @@ pub unsafe fn vcvt_n_s64_f64(a: float64x1_t) -> int64x1_t { )] fn _vcvt_n_s64_f64(a: float64x1_t, n: i32) -> int64x1_t; } - _vcvt_n_s64_f64(a, N) + unsafe { _vcvt_n_s64_f64(a, N) } } #[doc = "Floating-point convert to fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_s64_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtzs, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtq_n_s64_f64(a: float64x2_t) -> int64x2_t { +pub fn vcvtq_n_s64_f64(a: float64x2_t) -> int64x2_t { static_assert!(N >= 1 && N <= 64); unsafe extern "unadjusted" { #[cfg_attr( @@ -7861,18 +7308,16 @@ pub unsafe fn vcvtq_n_s64_f64(a: float64x2_t) -> int64x2_t { )] fn _vcvtq_n_s64_f64(a: float64x2_t, n: i32) -> int64x2_t; } - _vcvtq_n_s64_f64(a, N) + unsafe { _vcvtq_n_s64_f64(a, N) } } #[doc = "Floating-point convert to fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_u64_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtzu, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvt_n_u64_f64(a: float64x1_t) -> uint64x1_t { +pub fn vcvt_n_u64_f64(a: float64x1_t) -> uint64x1_t { static_assert!(N >= 1 && N <= 64); unsafe extern "unadjusted" { #[cfg_attr( @@ -7881,18 +7326,16 @@ pub unsafe fn vcvt_n_u64_f64(a: float64x1_t) -> uint64x1_t { )] fn _vcvt_n_u64_f64(a: float64x1_t, n: i32) -> uint64x1_t; } - _vcvt_n_u64_f64(a, N) + unsafe { _vcvt_n_u64_f64(a, N) } } #[doc = "Floating-point convert to fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_u64_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtzu, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtq_n_u64_f64(a: float64x2_t) -> uint64x2_t { +pub fn vcvtq_n_u64_f64(a: float64x2_t) -> uint64x2_t { static_assert!(N >= 1 && N <= 64); unsafe extern "unadjusted" { #[cfg_attr( @@ -7901,17 +7344,15 @@ pub unsafe fn vcvtq_n_u64_f64(a: float64x2_t) -> uint64x2_t { )] fn _vcvtq_n_u64_f64(a: float64x2_t, n: i32) -> uint64x2_t; } - _vcvtq_n_u64_f64(a, N) + unsafe { _vcvtq_n_u64_f64(a, N) } } #[doc = "Floating-point convert to signed fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_s64_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtzs))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvt_s64_f64(a: float64x1_t) -> int64x1_t { +pub fn vcvt_s64_f64(a: float64x1_t) -> int64x1_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -7919,17 +7360,15 @@ pub unsafe fn vcvt_s64_f64(a: float64x1_t) -> int64x1_t { )] fn _vcvt_s64_f64(a: float64x1_t) -> int64x1_t; } - _vcvt_s64_f64(a) + unsafe { _vcvt_s64_f64(a) } } #[doc = "Floating-point convert to signed fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_s64_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtzs))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtq_s64_f64(a: float64x2_t) -> int64x2_t { +pub fn vcvtq_s64_f64(a: float64x2_t) -> int64x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -7937,17 +7376,15 @@ pub unsafe fn vcvtq_s64_f64(a: float64x2_t) -> int64x2_t { )] fn _vcvtq_s64_f64(a: float64x2_t) -> int64x2_t; } - _vcvtq_s64_f64(a) + unsafe { _vcvtq_s64_f64(a) } } #[doc = "Floating-point convert to unsigned fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_u64_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtzu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvt_u64_f64(a: float64x1_t) -> uint64x1_t { +pub fn vcvt_u64_f64(a: float64x1_t) -> uint64x1_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -7955,17 +7392,15 @@ pub unsafe fn vcvt_u64_f64(a: float64x1_t) -> uint64x1_t { )] fn _vcvt_u64_f64(a: float64x1_t) -> uint64x1_t; } - _vcvt_u64_f64(a) + unsafe { _vcvt_u64_f64(a) } } #[doc = "Floating-point convert to unsigned fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_u64_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtzu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtq_u64_f64(a: float64x2_t) -> uint64x2_t { +pub fn vcvtq_u64_f64(a: float64x2_t) -> uint64x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -7973,17 +7408,15 @@ pub unsafe fn vcvtq_u64_f64(a: float64x2_t) -> uint64x2_t { )] fn _vcvtq_u64_f64(a: float64x2_t) -> uint64x2_t; } - _vcvtq_u64_f64(a) + unsafe { _vcvtq_u64_f64(a) } } #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvta_s16_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fcvtas))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvta_s16_f16(a: float16x4_t) -> int16x4_t { +pub fn vcvta_s16_f16(a: float16x4_t) -> int16x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -7991,17 +7424,15 @@ pub unsafe fn vcvta_s16_f16(a: float16x4_t) -> int16x4_t { )] fn _vcvta_s16_f16(a: float16x4_t) -> int16x4_t; } - _vcvta_s16_f16(a) + unsafe { _vcvta_s16_f16(a) } } #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtaq_s16_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fcvtas))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvtaq_s16_f16(a: float16x8_t) -> int16x8_t { +pub fn vcvtaq_s16_f16(a: float16x8_t) -> int16x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -8009,17 +7440,15 @@ pub unsafe fn vcvtaq_s16_f16(a: float16x8_t) -> int16x8_t { )] fn _vcvtaq_s16_f16(a: float16x8_t) -> int16x8_t; } - _vcvtaq_s16_f16(a) + unsafe { _vcvtaq_s16_f16(a) } } #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvta_s32_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtas))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvta_s32_f32(a: float32x2_t) -> int32x2_t { +pub fn vcvta_s32_f32(a: float32x2_t) -> int32x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -8027,17 +7456,15 @@ pub unsafe fn vcvta_s32_f32(a: float32x2_t) -> int32x2_t { )] fn _vcvta_s32_f32(a: float32x2_t) -> int32x2_t; } - _vcvta_s32_f32(a) + unsafe { _vcvta_s32_f32(a) } } #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtaq_s32_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtas))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtaq_s32_f32(a: float32x4_t) -> int32x4_t { +pub fn vcvtaq_s32_f32(a: float32x4_t) -> int32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -8045,17 +7472,15 @@ pub unsafe fn vcvtaq_s32_f32(a: float32x4_t) -> int32x4_t { )] fn _vcvtaq_s32_f32(a: float32x4_t) -> int32x4_t; } - _vcvtaq_s32_f32(a) + unsafe { _vcvtaq_s32_f32(a) } } #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvta_s64_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtas))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvta_s64_f64(a: float64x1_t) -> int64x1_t { +pub fn vcvta_s64_f64(a: float64x1_t) -> int64x1_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -8063,17 +7488,15 @@ pub unsafe fn vcvta_s64_f64(a: float64x1_t) -> int64x1_t { )] fn _vcvta_s64_f64(a: float64x1_t) -> int64x1_t; } - _vcvta_s64_f64(a) + unsafe { _vcvta_s64_f64(a) } } #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtaq_s64_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtas))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtaq_s64_f64(a: float64x2_t) -> int64x2_t { +pub fn vcvtaq_s64_f64(a: float64x2_t) -> int64x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -8081,17 +7504,15 @@ pub unsafe fn vcvtaq_s64_f64(a: float64x2_t) -> int64x2_t { )] fn _vcvtaq_s64_f64(a: float64x2_t) -> int64x2_t; } - _vcvtaq_s64_f64(a) + unsafe { _vcvtaq_s64_f64(a) } } #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvta_u16_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fcvtau))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvta_u16_f16(a: float16x4_t) -> uint16x4_t { +pub fn vcvta_u16_f16(a: float16x4_t) -> uint16x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -8099,17 +7520,15 @@ pub unsafe fn vcvta_u16_f16(a: float16x4_t) -> uint16x4_t { )] fn _vcvta_u16_f16(a: float16x4_t) -> uint16x4_t; } - _vcvta_u16_f16(a) + unsafe { _vcvta_u16_f16(a) } } #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtaq_u16_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fcvtau))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvtaq_u16_f16(a: float16x8_t) -> uint16x8_t { +pub fn vcvtaq_u16_f16(a: float16x8_t) -> uint16x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -8117,17 +7536,15 @@ pub unsafe fn vcvtaq_u16_f16(a: float16x8_t) -> uint16x8_t { )] fn _vcvtaq_u16_f16(a: float16x8_t) -> uint16x8_t; } - _vcvtaq_u16_f16(a) + unsafe { _vcvtaq_u16_f16(a) } } #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvta_u32_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtau))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvta_u32_f32(a: float32x2_t) -> uint32x2_t { +pub fn vcvta_u32_f32(a: float32x2_t) -> uint32x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -8135,17 +7552,15 @@ pub unsafe fn vcvta_u32_f32(a: float32x2_t) -> uint32x2_t { )] fn _vcvta_u32_f32(a: float32x2_t) -> uint32x2_t; } - _vcvta_u32_f32(a) + unsafe { _vcvta_u32_f32(a) } } #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtaq_u32_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtau))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtaq_u32_f32(a: float32x4_t) -> uint32x4_t { +pub fn vcvtaq_u32_f32(a: float32x4_t) -> uint32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -8153,17 +7568,15 @@ pub unsafe fn vcvtaq_u32_f32(a: float32x4_t) -> uint32x4_t { )] fn _vcvtaq_u32_f32(a: float32x4_t) -> uint32x4_t; } - _vcvtaq_u32_f32(a) + unsafe { _vcvtaq_u32_f32(a) } } #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvta_u64_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtau))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvta_u64_f64(a: float64x1_t) -> uint64x1_t { +pub fn vcvta_u64_f64(a: float64x1_t) -> uint64x1_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -8171,17 +7584,15 @@ pub unsafe fn vcvta_u64_f64(a: float64x1_t) -> uint64x1_t { )] fn _vcvta_u64_f64(a: float64x1_t) -> uint64x1_t; } - _vcvta_u64_f64(a) + unsafe { _vcvta_u64_f64(a) } } #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtaq_u64_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtau))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtaq_u64_f64(a: float64x2_t) -> uint64x2_t { +pub fn vcvtaq_u64_f64(a: float64x2_t) -> uint64x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -8189,28 +7600,24 @@ pub unsafe fn vcvtaq_u64_f64(a: float64x2_t) -> uint64x2_t { )] fn _vcvtaq_u64_f64(a: float64x2_t) -> uint64x2_t; } - _vcvtaq_u64_f64(a) + unsafe { _vcvtaq_u64_f64(a) } } #[doc = "Floating-point convert to integer, rounding to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtah_s16_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fcvtas))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvtah_s16_f16(a: f16) -> i16 { +pub fn vcvtah_s16_f16(a: f16) -> i16 { vcvtah_s32_f16(a) as i16 } #[doc = "Floating-point convert to integer, rounding to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtah_s32_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fcvtas))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvtah_s32_f16(a: f16) -> i32 { +pub fn vcvtah_s32_f16(a: f16) -> i32 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -8218,17 +7625,15 @@ pub unsafe fn vcvtah_s32_f16(a: f16) -> i32 { )] fn _vcvtah_s32_f16(a: f16) -> i32; } - _vcvtah_s32_f16(a) + unsafe { _vcvtah_s32_f16(a) } } #[doc = "Floating-point convert to integer, rounding to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtah_s64_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fcvtas))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvtah_s64_f16(a: f16) -> i64 { +pub fn vcvtah_s64_f16(a: f16) -> i64 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -8236,28 +7641,24 @@ pub unsafe fn vcvtah_s64_f16(a: f16) -> i64 { )] fn _vcvtah_s64_f16(a: f16) -> i64; } - _vcvtah_s64_f16(a) + unsafe { _vcvtah_s64_f16(a) } } #[doc = "Floating-point convert to integer, rounding to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtah_u16_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fcvtau))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvtah_u16_f16(a: f16) -> u16 { +pub fn vcvtah_u16_f16(a: f16) -> u16 { vcvtah_u32_f16(a) as u16 } #[doc = "Floating-point convert to integer, rounding to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtah_u32_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fcvtau))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvtah_u32_f16(a: f16) -> u32 { +pub fn vcvtah_u32_f16(a: f16) -> u32 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -8265,17 +7666,15 @@ pub unsafe fn vcvtah_u32_f16(a: f16) -> u32 { )] fn _vcvtah_u32_f16(a: f16) -> u32; } - _vcvtah_u32_f16(a) + unsafe { _vcvtah_u32_f16(a) } } #[doc = "Floating-point convert to integer, rounding to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtah_u64_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fcvtau))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvtah_u64_f16(a: f16) -> u64 { +pub fn vcvtah_u64_f16(a: f16) -> u64 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -8283,17 +7682,15 @@ pub unsafe fn vcvtah_u64_f16(a: f16) -> u64 { )] fn _vcvtah_u64_f16(a: f16) -> u64; } - _vcvtah_u64_f16(a) + unsafe { _vcvtah_u64_f16(a) } } #[doc = "Floating-point convert to integer, rounding to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtas_s32_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtas))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtas_s32_f32(a: f32) -> i32 { +pub fn vcvtas_s32_f32(a: f32) -> i32 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -8301,17 +7698,15 @@ pub unsafe fn vcvtas_s32_f32(a: f32) -> i32 { )] fn _vcvtas_s32_f32(a: f32) -> i32; } - _vcvtas_s32_f32(a) + unsafe { _vcvtas_s32_f32(a) } } #[doc = "Floating-point convert to integer, rounding to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtad_s64_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtas))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtad_s64_f64(a: f64) -> i64 { +pub fn vcvtad_s64_f64(a: f64) -> i64 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -8319,17 +7714,15 @@ pub unsafe fn vcvtad_s64_f64(a: f64) -> i64 { )] fn _vcvtad_s64_f64(a: f64) -> i64; } - _vcvtad_s64_f64(a) + unsafe { _vcvtad_s64_f64(a) } } #[doc = "Floating-point convert to integer, rounding to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtas_u32_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtau))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtas_u32_f32(a: f32) -> u32 { +pub fn vcvtas_u32_f32(a: f32) -> u32 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -8337,17 +7730,15 @@ pub unsafe fn vcvtas_u32_f32(a: f32) -> u32 { )] fn _vcvtas_u32_f32(a: f32) -> u32; } - _vcvtas_u32_f32(a) + unsafe { _vcvtas_u32_f32(a) } } #[doc = "Floating-point convert to integer, rounding to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtad_u64_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtau))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtad_u64_f64(a: f64) -> u64 { +pub fn vcvtad_u64_f64(a: f64) -> u64 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -8355,119 +7746,99 @@ pub unsafe fn vcvtad_u64_f64(a: f64) -> u64 { )] fn _vcvtad_u64_f64(a: f64) -> u64; } - _vcvtad_u64_f64(a) + unsafe { _vcvtad_u64_f64(a) } } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtd_f64_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(scvtf))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtd_f64_s64(a: i64) -> f64 { +pub fn vcvtd_f64_s64(a: i64) -> f64 { a as f64 } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_f32_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(scvtf))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvts_f32_s32(a: i32) -> f32 { +pub fn vcvts_f32_s32(a: i32) -> f32 { a as f32 } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_f16_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(scvtf))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvth_f16_s16(a: i16) -> f16 { +pub fn vcvth_f16_s16(a: i16) -> f16 { a as f16 } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_f16_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(scvtf))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvth_f16_s32(a: i32) -> f16 { +pub fn vcvth_f16_s32(a: i32) -> f16 { a as f16 } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_f16_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(scvtf))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvth_f16_s64(a: i64) -> f16 { +pub fn vcvth_f16_s64(a: i64) -> f16 { a as f16 } #[doc = "Unsigned fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_f16_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(ucvtf))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvth_f16_u16(a: u16) -> f16 { +pub fn vcvth_f16_u16(a: u16) -> f16 { a as f16 } #[doc = "Unsigned fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_f16_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(ucvtf))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvth_f16_u32(a: u32) -> f16 { +pub fn vcvth_f16_u32(a: u32) -> f16 { a as f16 } #[doc = "Unsigned fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_f16_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(ucvtf))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvth_f16_u64(a: u64) -> f16 { +pub fn vcvth_f16_u64(a: u64) -> f16 { a as f16 } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_f16_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(scvtf, N = 2))] #[rustc_legacy_const_generics(1)] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvth_n_f16_s16(a: i16) -> f16 { +pub fn vcvth_n_f16_s16(a: i16) -> f16 { static_assert!(N >= 1 && N <= 16); vcvth_n_f16_s32::(a as i32) as f16 } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_f16_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(scvtf, N = 2))] #[rustc_legacy_const_generics(1)] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvth_n_f16_s32(a: i32) -> f16 { +pub fn vcvth_n_f16_s32(a: i32) -> f16 { static_assert!(N >= 1 && N <= 16); unsafe extern "unadjusted" { #[cfg_attr( @@ -8476,18 +7847,16 @@ pub unsafe fn vcvth_n_f16_s32(a: i32) -> f16 { )] fn _vcvth_n_f16_s32(a: i32, n: i32) -> f16; } - _vcvth_n_f16_s32(a, N) + unsafe { _vcvth_n_f16_s32(a, N) } } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_f16_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(scvtf, N = 2))] #[rustc_legacy_const_generics(1)] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvth_n_f16_s64(a: i64) -> f16 { +pub fn vcvth_n_f16_s64(a: i64) -> f16 { static_assert!(N >= 1 && N <= 16); unsafe extern "unadjusted" { #[cfg_attr( @@ -8496,31 +7865,27 @@ pub unsafe fn vcvth_n_f16_s64(a: i64) -> f16 { )] fn _vcvth_n_f16_s64(a: i64, n: i32) -> f16; } - _vcvth_n_f16_s64(a, N) + unsafe { _vcvth_n_f16_s64(a, N) } } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_f16_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(ucvtf, N = 2))] #[rustc_legacy_const_generics(1)] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvth_n_f16_u16(a: u16) -> f16 { +pub fn vcvth_n_f16_u16(a: u16) -> f16 { static_assert!(N >= 1 && N <= 16); vcvth_n_f16_u32::(a as u32) as f16 } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_f16_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(ucvtf, N = 2))] #[rustc_legacy_const_generics(1)] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvth_n_f16_u32(a: u32) -> f16 { +pub fn vcvth_n_f16_u32(a: u32) -> f16 { static_assert!(N >= 1 && N <= 16); unsafe extern "unadjusted" { #[cfg_attr( @@ -8529,18 +7894,16 @@ pub unsafe fn vcvth_n_f16_u32(a: u32) -> f16 { )] fn _vcvth_n_f16_u32(a: u32, n: i32) -> f16; } - _vcvth_n_f16_u32(a, N) + unsafe { _vcvth_n_f16_u32(a, N) } } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_f16_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(ucvtf, N = 2))] #[rustc_legacy_const_generics(1)] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvth_n_f16_u64(a: u64) -> f16 { +pub fn vcvth_n_f16_u64(a: u64) -> f16 { static_assert!(N >= 1 && N <= 16); unsafe extern "unadjusted" { #[cfg_attr( @@ -8549,31 +7912,27 @@ pub unsafe fn vcvth_n_f16_u64(a: u64) -> f16 { )] fn _vcvth_n_f16_u64(a: u64, n: i32) -> f16; } - _vcvth_n_f16_u64(a, N) + unsafe { _vcvth_n_f16_u64(a, N) } } #[doc = "Floating-point convert to fixed-point, rounding toward zero"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_s16_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_s16_f16)"] #[inline] #[cfg_attr(test, assert_instr(fcvtzs, N = 2))] #[rustc_legacy_const_generics(1)] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvth_n_s16_f16(a: f16) -> i16 { +pub fn vcvth_n_s16_f16(a: f16) -> i16 { static_assert!(N >= 1 && N <= 16); vcvth_n_s32_f16::(a) as i16 } #[doc = "Floating-point convert to fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_s32_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fcvtzs, N = 2))] #[rustc_legacy_const_generics(1)] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvth_n_s32_f16(a: f16) -> i32 { +pub fn vcvth_n_s32_f16(a: f16) -> i32 { static_assert!(N >= 1 && N <= 16); unsafe extern "unadjusted" { #[cfg_attr( @@ -8582,18 +7941,16 @@ pub unsafe fn vcvth_n_s32_f16(a: f16) -> i32 { )] fn _vcvth_n_s32_f16(a: f16, n: i32) -> i32; } - _vcvth_n_s32_f16(a, N) + unsafe { _vcvth_n_s32_f16(a, N) } } #[doc = "Floating-point convert to fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_s64_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fcvtzs, N = 2))] #[rustc_legacy_const_generics(1)] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvth_n_s64_f16(a: f16) -> i64 { +pub fn vcvth_n_s64_f16(a: f16) -> i64 { static_assert!(N >= 1 && N <= 16); unsafe extern "unadjusted" { #[cfg_attr( @@ -8602,31 +7959,27 @@ pub unsafe fn vcvth_n_s64_f16(a: f16) -> i64 { )] fn _vcvth_n_s64_f16(a: f16, n: i32) -> i64; } - _vcvth_n_s64_f16(a, N) + unsafe { _vcvth_n_s64_f16(a, N) } } #[doc = "Floating-point convert to fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_u16_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fcvtzu, N = 2))] #[rustc_legacy_const_generics(1)] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvth_n_u16_f16(a: f16) -> u16 { +pub fn vcvth_n_u16_f16(a: f16) -> u16 { static_assert!(N >= 1 && N <= 16); vcvth_n_u32_f16::(a) as u16 } #[doc = "Floating-point convert to fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_u32_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fcvtzu, N = 2))] #[rustc_legacy_const_generics(1)] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvth_n_u32_f16(a: f16) -> u32 { +pub fn vcvth_n_u32_f16(a: f16) -> u32 { static_assert!(N >= 1 && N <= 16); unsafe extern "unadjusted" { #[cfg_attr( @@ -8635,18 +7988,16 @@ pub unsafe fn vcvth_n_u32_f16(a: f16) -> u32 { )] fn _vcvth_n_u32_f16(a: f16, n: i32) -> u32; } - _vcvth_n_u32_f16(a, N) + unsafe { _vcvth_n_u32_f16(a, N) } } #[doc = "Floating-point convert to fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_u64_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fcvtzu, N = 2))] #[rustc_legacy_const_generics(1)] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvth_n_u64_f16(a: f16) -> u64 { +pub fn vcvth_n_u64_f16(a: f16) -> u64 { static_assert!(N >= 1 && N <= 16); unsafe extern "unadjusted" { #[cfg_attr( @@ -8655,83 +8006,69 @@ pub unsafe fn vcvth_n_u64_f16(a: f16) -> u64 { )] fn _vcvth_n_u64_f16(a: f16, n: i32) -> u64; } - _vcvth_n_u64_f16(a, N) + unsafe { _vcvth_n_u64_f16(a, N) } } #[doc = "Floating-point convert to signed fixed-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_s16_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fcvtzs))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvth_s16_f16(a: f16) -> i16 { +pub fn vcvth_s16_f16(a: f16) -> i16 { a as i16 } #[doc = "Floating-point convert to signed fixed-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_s32_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fcvtzs))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvth_s32_f16(a: f16) -> i32 { +pub fn vcvth_s32_f16(a: f16) -> i32 { a as i32 } #[doc = "Floating-point convert to signed fixed-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_s64_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fcvtzs))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvth_s64_f16(a: f16) -> i64 { +pub fn vcvth_s64_f16(a: f16) -> i64 { a as i64 } #[doc = "Floating-point convert to unsigned fixed-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_u16_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fcvtzu))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvth_u16_f16(a: f16) -> u16 { +pub fn vcvth_u16_f16(a: f16) -> u16 { a as u16 } #[doc = "Floating-point convert to unsigned fixed-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_u32_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fcvtzu))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvth_u32_f16(a: f16) -> u32 { +pub fn vcvth_u32_f16(a: f16) -> u32 { a as u32 } #[doc = "Floating-point convert to unsigned fixed-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_u64_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fcvtzu))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvth_u64_f16(a: f16) -> u64 { +pub fn vcvth_u64_f16(a: f16) -> u64 { a as u64 } #[doc = "Floating-point convert to signed integer, rounding toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtm_s16_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fcvtms))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvtm_s16_f16(a: float16x4_t) -> int16x4_t { +pub fn vcvtm_s16_f16(a: float16x4_t) -> int16x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -8739,17 +8076,15 @@ pub unsafe fn vcvtm_s16_f16(a: float16x4_t) -> int16x4_t { )] fn _vcvtm_s16_f16(a: float16x4_t) -> int16x4_t; } - _vcvtm_s16_f16(a) + unsafe { _vcvtm_s16_f16(a) } } #[doc = "Floating-point convert to signed integer, rounding toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmq_s16_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fcvtms))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvtmq_s16_f16(a: float16x8_t) -> int16x8_t { +pub fn vcvtmq_s16_f16(a: float16x8_t) -> int16x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -8757,17 +8092,15 @@ pub unsafe fn vcvtmq_s16_f16(a: float16x8_t) -> int16x8_t { )] fn _vcvtmq_s16_f16(a: float16x8_t) -> int16x8_t; } - _vcvtmq_s16_f16(a) + unsafe { _vcvtmq_s16_f16(a) } } #[doc = "Floating-point convert to signed integer, rounding toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtm_s32_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtms))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtm_s32_f32(a: float32x2_t) -> int32x2_t { +pub fn vcvtm_s32_f32(a: float32x2_t) -> int32x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -8775,17 +8108,15 @@ pub unsafe fn vcvtm_s32_f32(a: float32x2_t) -> int32x2_t { )] fn _vcvtm_s32_f32(a: float32x2_t) -> int32x2_t; } - _vcvtm_s32_f32(a) + unsafe { _vcvtm_s32_f32(a) } } #[doc = "Floating-point convert to signed integer, rounding toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmq_s32_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtms))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtmq_s32_f32(a: float32x4_t) -> int32x4_t { +pub fn vcvtmq_s32_f32(a: float32x4_t) -> int32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -8793,17 +8124,15 @@ pub unsafe fn vcvtmq_s32_f32(a: float32x4_t) -> int32x4_t { )] fn _vcvtmq_s32_f32(a: float32x4_t) -> int32x4_t; } - _vcvtmq_s32_f32(a) + unsafe { _vcvtmq_s32_f32(a) } } #[doc = "Floating-point convert to signed integer, rounding toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtm_s64_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtms))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtm_s64_f64(a: float64x1_t) -> int64x1_t { +pub fn vcvtm_s64_f64(a: float64x1_t) -> int64x1_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -8811,17 +8140,15 @@ pub unsafe fn vcvtm_s64_f64(a: float64x1_t) -> int64x1_t { )] fn _vcvtm_s64_f64(a: float64x1_t) -> int64x1_t; } - _vcvtm_s64_f64(a) + unsafe { _vcvtm_s64_f64(a) } } #[doc = "Floating-point convert to signed integer, rounding toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmq_s64_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtms))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtmq_s64_f64(a: float64x2_t) -> int64x2_t { +pub fn vcvtmq_s64_f64(a: float64x2_t) -> int64x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -8829,17 +8156,15 @@ pub unsafe fn vcvtmq_s64_f64(a: float64x2_t) -> int64x2_t { )] fn _vcvtmq_s64_f64(a: float64x2_t) -> int64x2_t; } - _vcvtmq_s64_f64(a) + unsafe { _vcvtmq_s64_f64(a) } } #[doc = "Floating-point convert to unsigned integer, rounding toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtm_u16_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fcvtmu))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvtm_u16_f16(a: float16x4_t) -> uint16x4_t { +pub fn vcvtm_u16_f16(a: float16x4_t) -> uint16x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -8847,17 +8172,15 @@ pub unsafe fn vcvtm_u16_f16(a: float16x4_t) -> uint16x4_t { )] fn _vcvtm_u16_f16(a: float16x4_t) -> uint16x4_t; } - _vcvtm_u16_f16(a) + unsafe { _vcvtm_u16_f16(a) } } #[doc = "Floating-point convert to unsigned integer, rounding toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmq_u16_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fcvtmu))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvtmq_u16_f16(a: float16x8_t) -> uint16x8_t { +pub fn vcvtmq_u16_f16(a: float16x8_t) -> uint16x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -8865,17 +8188,15 @@ pub unsafe fn vcvtmq_u16_f16(a: float16x8_t) -> uint16x8_t { )] fn _vcvtmq_u16_f16(a: float16x8_t) -> uint16x8_t; } - _vcvtmq_u16_f16(a) + unsafe { _vcvtmq_u16_f16(a) } } #[doc = "Floating-point convert to unsigned integer, rounding toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtm_u32_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtmu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtm_u32_f32(a: float32x2_t) -> uint32x2_t { +pub fn vcvtm_u32_f32(a: float32x2_t) -> uint32x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -8883,17 +8204,15 @@ pub unsafe fn vcvtm_u32_f32(a: float32x2_t) -> uint32x2_t { )] fn _vcvtm_u32_f32(a: float32x2_t) -> uint32x2_t; } - _vcvtm_u32_f32(a) + unsafe { _vcvtm_u32_f32(a) } } #[doc = "Floating-point convert to unsigned integer, rounding toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmq_u32_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtmu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtmq_u32_f32(a: float32x4_t) -> uint32x4_t { +pub fn vcvtmq_u32_f32(a: float32x4_t) -> uint32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -8901,17 +8220,15 @@ pub unsafe fn vcvtmq_u32_f32(a: float32x4_t) -> uint32x4_t { )] fn _vcvtmq_u32_f32(a: float32x4_t) -> uint32x4_t; } - _vcvtmq_u32_f32(a) + unsafe { _vcvtmq_u32_f32(a) } } #[doc = "Floating-point convert to unsigned integer, rounding toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtm_u64_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtmu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtm_u64_f64(a: float64x1_t) -> uint64x1_t { +pub fn vcvtm_u64_f64(a: float64x1_t) -> uint64x1_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -8919,17 +8236,15 @@ pub unsafe fn vcvtm_u64_f64(a: float64x1_t) -> uint64x1_t { )] fn _vcvtm_u64_f64(a: float64x1_t) -> uint64x1_t; } - _vcvtm_u64_f64(a) + unsafe { _vcvtm_u64_f64(a) } } #[doc = "Floating-point convert to unsigned integer, rounding toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmq_u64_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtmu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtmq_u64_f64(a: float64x2_t) -> uint64x2_t { +pub fn vcvtmq_u64_f64(a: float64x2_t) -> uint64x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -8937,28 +8252,24 @@ pub unsafe fn vcvtmq_u64_f64(a: float64x2_t) -> uint64x2_t { )] fn _vcvtmq_u64_f64(a: float64x2_t) -> uint64x2_t; } - _vcvtmq_u64_f64(a) + unsafe { _vcvtmq_u64_f64(a) } } #[doc = "Floating-point convert to integer, rounding towards minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmh_s16_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fcvtms))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvtmh_s16_f16(a: f16) -> i16 { +pub fn vcvtmh_s16_f16(a: f16) -> i16 { vcvtmh_s32_f16(a) as i16 } #[doc = "Floating-point convert to integer, rounding towards minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmh_s32_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fcvtms))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvtmh_s32_f16(a: f16) -> i32 { +pub fn vcvtmh_s32_f16(a: f16) -> i32 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -8966,17 +8277,15 @@ pub unsafe fn vcvtmh_s32_f16(a: f16) -> i32 { )] fn _vcvtmh_s32_f16(a: f16) -> i32; } - _vcvtmh_s32_f16(a) + unsafe { _vcvtmh_s32_f16(a) } } #[doc = "Floating-point convert to integer, rounding towards minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmh_s64_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fcvtms))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvtmh_s64_f16(a: f16) -> i64 { +pub fn vcvtmh_s64_f16(a: f16) -> i64 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -8984,28 +8293,24 @@ pub unsafe fn vcvtmh_s64_f16(a: f16) -> i64 { )] fn _vcvtmh_s64_f16(a: f16) -> i64; } - _vcvtmh_s64_f16(a) + unsafe { _vcvtmh_s64_f16(a) } } #[doc = "Floating-point convert to integer, rounding towards minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmh_u16_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fcvtmu))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvtmh_u16_f16(a: f16) -> u16 { +pub fn vcvtmh_u16_f16(a: f16) -> u16 { vcvtmh_u32_f16(a) as u16 } #[doc = "Floating-point convert to unsigned integer, rounding towards minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmh_u32_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fcvtmu))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvtmh_u32_f16(a: f16) -> u32 { +pub fn vcvtmh_u32_f16(a: f16) -> u32 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -9013,17 +8318,15 @@ pub unsafe fn vcvtmh_u32_f16(a: f16) -> u32 { )] fn _vcvtmh_u32_f16(a: f16) -> u32; } - _vcvtmh_u32_f16(a) + unsafe { _vcvtmh_u32_f16(a) } } #[doc = "Floating-point convert to unsigned integer, rounding towards minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmh_u64_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fcvtmu))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvtmh_u64_f16(a: f16) -> u64 { +pub fn vcvtmh_u64_f16(a: f16) -> u64 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -9031,17 +8334,15 @@ pub unsafe fn vcvtmh_u64_f16(a: f16) -> u64 { )] fn _vcvtmh_u64_f16(a: f16) -> u64; } - _vcvtmh_u64_f16(a) + unsafe { _vcvtmh_u64_f16(a) } } #[doc = "Floating-point convert to signed integer, rounding toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtms_s32_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtms))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtms_s32_f32(a: f32) -> i32 { +pub fn vcvtms_s32_f32(a: f32) -> i32 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -9049,17 +8350,15 @@ pub unsafe fn vcvtms_s32_f32(a: f32) -> i32 { )] fn _vcvtms_s32_f32(a: f32) -> i32; } - _vcvtms_s32_f32(a) + unsafe { _vcvtms_s32_f32(a) } } #[doc = "Floating-point convert to signed integer, rounding toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmd_s64_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtms))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtmd_s64_f64(a: f64) -> i64 { +pub fn vcvtmd_s64_f64(a: f64) -> i64 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -9067,17 +8366,15 @@ pub unsafe fn vcvtmd_s64_f64(a: f64) -> i64 { )] fn _vcvtmd_s64_f64(a: f64) -> i64; } - _vcvtmd_s64_f64(a) + unsafe { _vcvtmd_s64_f64(a) } } #[doc = "Floating-point convert to unsigned integer, rounding toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtms_u32_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtmu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtms_u32_f32(a: f32) -> u32 { +pub fn vcvtms_u32_f32(a: f32) -> u32 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -9085,17 +8382,15 @@ pub unsafe fn vcvtms_u32_f32(a: f32) -> u32 { )] fn _vcvtms_u32_f32(a: f32) -> u32; } - _vcvtms_u32_f32(a) + unsafe { _vcvtms_u32_f32(a) } } #[doc = "Floating-point convert to unsigned integer, rounding toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmd_u64_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtmu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtmd_u64_f64(a: f64) -> u64 { +pub fn vcvtmd_u64_f64(a: f64) -> u64 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -9103,17 +8398,15 @@ pub unsafe fn vcvtmd_u64_f64(a: f64) -> u64 { )] fn _vcvtmd_u64_f64(a: f64) -> u64; } - _vcvtmd_u64_f64(a) + unsafe { _vcvtmd_u64_f64(a) } } #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtn_s16_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fcvtns))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvtn_s16_f16(a: float16x4_t) -> int16x4_t { +pub fn vcvtn_s16_f16(a: float16x4_t) -> int16x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -9121,17 +8414,15 @@ pub unsafe fn vcvtn_s16_f16(a: float16x4_t) -> int16x4_t { )] fn _vcvtn_s16_f16(a: float16x4_t) -> int16x4_t; } - _vcvtn_s16_f16(a) + unsafe { _vcvtn_s16_f16(a) } } #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnq_s16_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fcvtns))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvtnq_s16_f16(a: float16x8_t) -> int16x8_t { +pub fn vcvtnq_s16_f16(a: float16x8_t) -> int16x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -9139,17 +8430,15 @@ pub unsafe fn vcvtnq_s16_f16(a: float16x8_t) -> int16x8_t { )] fn _vcvtnq_s16_f16(a: float16x8_t) -> int16x8_t; } - _vcvtnq_s16_f16(a) + unsafe { _vcvtnq_s16_f16(a) } } #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtn_s32_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtns))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtn_s32_f32(a: float32x2_t) -> int32x2_t { +pub fn vcvtn_s32_f32(a: float32x2_t) -> int32x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -9157,17 +8446,15 @@ pub unsafe fn vcvtn_s32_f32(a: float32x2_t) -> int32x2_t { )] fn _vcvtn_s32_f32(a: float32x2_t) -> int32x2_t; } - _vcvtn_s32_f32(a) + unsafe { _vcvtn_s32_f32(a) } } #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnq_s32_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtns))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtnq_s32_f32(a: float32x4_t) -> int32x4_t { +pub fn vcvtnq_s32_f32(a: float32x4_t) -> int32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -9175,17 +8462,15 @@ pub unsafe fn vcvtnq_s32_f32(a: float32x4_t) -> int32x4_t { )] fn _vcvtnq_s32_f32(a: float32x4_t) -> int32x4_t; } - _vcvtnq_s32_f32(a) + unsafe { _vcvtnq_s32_f32(a) } } #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtn_s64_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtns))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtn_s64_f64(a: float64x1_t) -> int64x1_t { +pub fn vcvtn_s64_f64(a: float64x1_t) -> int64x1_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -9193,17 +8478,15 @@ pub unsafe fn vcvtn_s64_f64(a: float64x1_t) -> int64x1_t { )] fn _vcvtn_s64_f64(a: float64x1_t) -> int64x1_t; } - _vcvtn_s64_f64(a) + unsafe { _vcvtn_s64_f64(a) } } #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnq_s64_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtns))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtnq_s64_f64(a: float64x2_t) -> int64x2_t { +pub fn vcvtnq_s64_f64(a: float64x2_t) -> int64x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -9211,17 +8494,15 @@ pub unsafe fn vcvtnq_s64_f64(a: float64x2_t) -> int64x2_t { )] fn _vcvtnq_s64_f64(a: float64x2_t) -> int64x2_t; } - _vcvtnq_s64_f64(a) + unsafe { _vcvtnq_s64_f64(a) } } #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtn_u16_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fcvtnu))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvtn_u16_f16(a: float16x4_t) -> uint16x4_t { +pub fn vcvtn_u16_f16(a: float16x4_t) -> uint16x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -9229,17 +8510,15 @@ pub unsafe fn vcvtn_u16_f16(a: float16x4_t) -> uint16x4_t { )] fn _vcvtn_u16_f16(a: float16x4_t) -> uint16x4_t; } - _vcvtn_u16_f16(a) + unsafe { _vcvtn_u16_f16(a) } } #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnq_u16_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fcvtnu))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvtnq_u16_f16(a: float16x8_t) -> uint16x8_t { +pub fn vcvtnq_u16_f16(a: float16x8_t) -> uint16x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -9247,17 +8526,15 @@ pub unsafe fn vcvtnq_u16_f16(a: float16x8_t) -> uint16x8_t { )] fn _vcvtnq_u16_f16(a: float16x8_t) -> uint16x8_t; } - _vcvtnq_u16_f16(a) + unsafe { _vcvtnq_u16_f16(a) } } #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtn_u32_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtnu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtn_u32_f32(a: float32x2_t) -> uint32x2_t { +pub fn vcvtn_u32_f32(a: float32x2_t) -> uint32x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -9265,17 +8542,15 @@ pub unsafe fn vcvtn_u32_f32(a: float32x2_t) -> uint32x2_t { )] fn _vcvtn_u32_f32(a: float32x2_t) -> uint32x2_t; } - _vcvtn_u32_f32(a) + unsafe { _vcvtn_u32_f32(a) } } #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnq_u32_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtnu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtnq_u32_f32(a: float32x4_t) -> uint32x4_t { +pub fn vcvtnq_u32_f32(a: float32x4_t) -> uint32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -9283,17 +8558,15 @@ pub unsafe fn vcvtnq_u32_f32(a: float32x4_t) -> uint32x4_t { )] fn _vcvtnq_u32_f32(a: float32x4_t) -> uint32x4_t; } - _vcvtnq_u32_f32(a) + unsafe { _vcvtnq_u32_f32(a) } } #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtn_u64_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtnu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtn_u64_f64(a: float64x1_t) -> uint64x1_t { +pub fn vcvtn_u64_f64(a: float64x1_t) -> uint64x1_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -9301,17 +8574,15 @@ pub unsafe fn vcvtn_u64_f64(a: float64x1_t) -> uint64x1_t { )] fn _vcvtn_u64_f64(a: float64x1_t) -> uint64x1_t; } - _vcvtn_u64_f64(a) + unsafe { _vcvtn_u64_f64(a) } } #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnq_u64_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtnu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtnq_u64_f64(a: float64x2_t) -> uint64x2_t { +pub fn vcvtnq_u64_f64(a: float64x2_t) -> uint64x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -9319,28 +8590,24 @@ pub unsafe fn vcvtnq_u64_f64(a: float64x2_t) -> uint64x2_t { )] fn _vcvtnq_u64_f64(a: float64x2_t) -> uint64x2_t; } - _vcvtnq_u64_f64(a) + unsafe { _vcvtnq_u64_f64(a) } } #[doc = "Floating-point convert to integer, rounding to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnh_s16_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fcvtns))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvtnh_s16_f16(a: f16) -> i16 { +pub fn vcvtnh_s16_f16(a: f16) -> i16 { vcvtnh_s32_f16(a) as i16 } #[doc = "Floating-point convert to integer, rounding to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnh_s32_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fcvtns))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvtnh_s32_f16(a: f16) -> i32 { +pub fn vcvtnh_s32_f16(a: f16) -> i32 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -9348,17 +8615,15 @@ pub unsafe fn vcvtnh_s32_f16(a: f16) -> i32 { )] fn _vcvtnh_s32_f16(a: f16) -> i32; } - _vcvtnh_s32_f16(a) + unsafe { _vcvtnh_s32_f16(a) } } #[doc = "Floating-point convert to integer, rounding to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnh_s64_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fcvtns))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvtnh_s64_f16(a: f16) -> i64 { +pub fn vcvtnh_s64_f16(a: f16) -> i64 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -9366,28 +8631,24 @@ pub unsafe fn vcvtnh_s64_f16(a: f16) -> i64 { )] fn _vcvtnh_s64_f16(a: f16) -> i64; } - _vcvtnh_s64_f16(a) + unsafe { _vcvtnh_s64_f16(a) } } #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnh_u16_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fcvtnu))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvtnh_u16_f16(a: f16) -> u16 { +pub fn vcvtnh_u16_f16(a: f16) -> u16 { vcvtnh_u32_f16(a) as u16 } #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnh_u32_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fcvtnu))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvtnh_u32_f16(a: f16) -> u32 { +pub fn vcvtnh_u32_f16(a: f16) -> u32 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -9395,17 +8656,15 @@ pub unsafe fn vcvtnh_u32_f16(a: f16) -> u32 { )] fn _vcvtnh_u32_f16(a: f16) -> u32; } - _vcvtnh_u32_f16(a) + unsafe { _vcvtnh_u32_f16(a) } } #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnh_u64_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fcvtnu))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvtnh_u64_f16(a: f16) -> u64 { +pub fn vcvtnh_u64_f16(a: f16) -> u64 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -9413,17 +8672,15 @@ pub unsafe fn vcvtnh_u64_f16(a: f16) -> u64 { )] fn _vcvtnh_u64_f16(a: f16) -> u64; } - _vcvtnh_u64_f16(a) + unsafe { _vcvtnh_u64_f16(a) } } #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtns_s32_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtns))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtns_s32_f32(a: f32) -> i32 { +pub fn vcvtns_s32_f32(a: f32) -> i32 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -9431,17 +8688,15 @@ pub unsafe fn vcvtns_s32_f32(a: f32) -> i32 { )] fn _vcvtns_s32_f32(a: f32) -> i32; } - _vcvtns_s32_f32(a) + unsafe { _vcvtns_s32_f32(a) } } #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnd_s64_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtns))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtnd_s64_f64(a: f64) -> i64 { +pub fn vcvtnd_s64_f64(a: f64) -> i64 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -9449,17 +8704,15 @@ pub unsafe fn vcvtnd_s64_f64(a: f64) -> i64 { )] fn _vcvtnd_s64_f64(a: f64) -> i64; } - _vcvtnd_s64_f64(a) + unsafe { _vcvtnd_s64_f64(a) } } #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtns_u32_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtnu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtns_u32_f32(a: f32) -> u32 { +pub fn vcvtns_u32_f32(a: f32) -> u32 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -9467,17 +8720,15 @@ pub unsafe fn vcvtns_u32_f32(a: f32) -> u32 { )] fn _vcvtns_u32_f32(a: f32) -> u32; } - _vcvtns_u32_f32(a) + unsafe { _vcvtns_u32_f32(a) } } #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnd_u64_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtnu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtnd_u64_f64(a: f64) -> u64 { +pub fn vcvtnd_u64_f64(a: f64) -> u64 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -9485,17 +8736,15 @@ pub unsafe fn vcvtnd_u64_f64(a: f64) -> u64 { )] fn _vcvtnd_u64_f64(a: f64) -> u64; } - _vcvtnd_u64_f64(a) + unsafe { _vcvtnd_u64_f64(a) } } #[doc = "Floating-point convert to signed integer, rounding to plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtp_s16_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fcvtps))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvtp_s16_f16(a: float16x4_t) -> int16x4_t { +pub fn vcvtp_s16_f16(a: float16x4_t) -> int16x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -9503,17 +8752,15 @@ pub unsafe fn vcvtp_s16_f16(a: float16x4_t) -> int16x4_t { )] fn _vcvtp_s16_f16(a: float16x4_t) -> int16x4_t; } - _vcvtp_s16_f16(a) + unsafe { _vcvtp_s16_f16(a) } } #[doc = "Floating-point convert to signed integer, rounding to plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtpq_s16_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fcvtps))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvtpq_s16_f16(a: float16x8_t) -> int16x8_t { +pub fn vcvtpq_s16_f16(a: float16x8_t) -> int16x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -9521,17 +8768,15 @@ pub unsafe fn vcvtpq_s16_f16(a: float16x8_t) -> int16x8_t { )] fn _vcvtpq_s16_f16(a: float16x8_t) -> int16x8_t; } - _vcvtpq_s16_f16(a) + unsafe { _vcvtpq_s16_f16(a) } } #[doc = "Floating-point convert to signed integer, rounding toward plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtp_s32_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtps))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtp_s32_f32(a: float32x2_t) -> int32x2_t { +pub fn vcvtp_s32_f32(a: float32x2_t) -> int32x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -9539,17 +8784,15 @@ pub unsafe fn vcvtp_s32_f32(a: float32x2_t) -> int32x2_t { )] fn _vcvtp_s32_f32(a: float32x2_t) -> int32x2_t; } - _vcvtp_s32_f32(a) + unsafe { _vcvtp_s32_f32(a) } } #[doc = "Floating-point convert to signed integer, rounding toward plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtpq_s32_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtps))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtpq_s32_f32(a: float32x4_t) -> int32x4_t { +pub fn vcvtpq_s32_f32(a: float32x4_t) -> int32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -9557,17 +8800,15 @@ pub unsafe fn vcvtpq_s32_f32(a: float32x4_t) -> int32x4_t { )] fn _vcvtpq_s32_f32(a: float32x4_t) -> int32x4_t; } - _vcvtpq_s32_f32(a) + unsafe { _vcvtpq_s32_f32(a) } } #[doc = "Floating-point convert to signed integer, rounding toward plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtp_s64_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtps))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtp_s64_f64(a: float64x1_t) -> int64x1_t { +pub fn vcvtp_s64_f64(a: float64x1_t) -> int64x1_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -9575,17 +8816,15 @@ pub unsafe fn vcvtp_s64_f64(a: float64x1_t) -> int64x1_t { )] fn _vcvtp_s64_f64(a: float64x1_t) -> int64x1_t; } - _vcvtp_s64_f64(a) + unsafe { _vcvtp_s64_f64(a) } } #[doc = "Floating-point convert to signed integer, rounding toward plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtpq_s64_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtps))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtpq_s64_f64(a: float64x2_t) -> int64x2_t { +pub fn vcvtpq_s64_f64(a: float64x2_t) -> int64x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -9593,17 +8832,15 @@ pub unsafe fn vcvtpq_s64_f64(a: float64x2_t) -> int64x2_t { )] fn _vcvtpq_s64_f64(a: float64x2_t) -> int64x2_t; } - _vcvtpq_s64_f64(a) + unsafe { _vcvtpq_s64_f64(a) } } #[doc = "Floating-point convert to unsigned integer, rounding to plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtp_u16_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fcvtpu))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvtp_u16_f16(a: float16x4_t) -> uint16x4_t { +pub fn vcvtp_u16_f16(a: float16x4_t) -> uint16x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -9611,17 +8848,15 @@ pub unsafe fn vcvtp_u16_f16(a: float16x4_t) -> uint16x4_t { )] fn _vcvtp_u16_f16(a: float16x4_t) -> uint16x4_t; } - _vcvtp_u16_f16(a) + unsafe { _vcvtp_u16_f16(a) } } #[doc = "Floating-point convert to unsigned integer, rounding to plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtpq_u16_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fcvtpu))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvtpq_u16_f16(a: float16x8_t) -> uint16x8_t { +pub fn vcvtpq_u16_f16(a: float16x8_t) -> uint16x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -9629,17 +8864,15 @@ pub unsafe fn vcvtpq_u16_f16(a: float16x8_t) -> uint16x8_t { )] fn _vcvtpq_u16_f16(a: float16x8_t) -> uint16x8_t; } - _vcvtpq_u16_f16(a) + unsafe { _vcvtpq_u16_f16(a) } } #[doc = "Floating-point convert to unsigned integer, rounding toward plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtp_u32_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtpu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtp_u32_f32(a: float32x2_t) -> uint32x2_t { +pub fn vcvtp_u32_f32(a: float32x2_t) -> uint32x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -9647,17 +8880,15 @@ pub unsafe fn vcvtp_u32_f32(a: float32x2_t) -> uint32x2_t { )] fn _vcvtp_u32_f32(a: float32x2_t) -> uint32x2_t; } - _vcvtp_u32_f32(a) + unsafe { _vcvtp_u32_f32(a) } } #[doc = "Floating-point convert to unsigned integer, rounding toward plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtpq_u32_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtpu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtpq_u32_f32(a: float32x4_t) -> uint32x4_t { +pub fn vcvtpq_u32_f32(a: float32x4_t) -> uint32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -9665,17 +8896,15 @@ pub unsafe fn vcvtpq_u32_f32(a: float32x4_t) -> uint32x4_t { )] fn _vcvtpq_u32_f32(a: float32x4_t) -> uint32x4_t; } - _vcvtpq_u32_f32(a) + unsafe { _vcvtpq_u32_f32(a) } } #[doc = "Floating-point convert to unsigned integer, rounding toward plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtp_u64_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtpu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtp_u64_f64(a: float64x1_t) -> uint64x1_t { +pub fn vcvtp_u64_f64(a: float64x1_t) -> uint64x1_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -9683,17 +8912,15 @@ pub unsafe fn vcvtp_u64_f64(a: float64x1_t) -> uint64x1_t { )] fn _vcvtp_u64_f64(a: float64x1_t) -> uint64x1_t; } - _vcvtp_u64_f64(a) + unsafe { _vcvtp_u64_f64(a) } } #[doc = "Floating-point convert to unsigned integer, rounding toward plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtpq_u64_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtpu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtpq_u64_f64(a: float64x2_t) -> uint64x2_t { +pub fn vcvtpq_u64_f64(a: float64x2_t) -> uint64x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -9701,28 +8928,24 @@ pub unsafe fn vcvtpq_u64_f64(a: float64x2_t) -> uint64x2_t { )] fn _vcvtpq_u64_f64(a: float64x2_t) -> uint64x2_t; } - _vcvtpq_u64_f64(a) + unsafe { _vcvtpq_u64_f64(a) } } #[doc = "Floating-point convert to integer, rounding to plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtph_s16_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fcvtps))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvtph_s16_f16(a: f16) -> i16 { +pub fn vcvtph_s16_f16(a: f16) -> i16 { vcvtph_s32_f16(a) as i16 } #[doc = "Floating-point convert to integer, rounding to plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtph_s32_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fcvtps))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvtph_s32_f16(a: f16) -> i32 { +pub fn vcvtph_s32_f16(a: f16) -> i32 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -9730,17 +8953,15 @@ pub unsafe fn vcvtph_s32_f16(a: f16) -> i32 { )] fn _vcvtph_s32_f16(a: f16) -> i32; } - _vcvtph_s32_f16(a) + unsafe { _vcvtph_s32_f16(a) } } #[doc = "Floating-point convert to integer, rounding to plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtph_s64_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fcvtps))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvtph_s64_f16(a: f16) -> i64 { +pub fn vcvtph_s64_f16(a: f16) -> i64 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -9748,28 +8969,24 @@ pub unsafe fn vcvtph_s64_f16(a: f16) -> i64 { )] fn _vcvtph_s64_f16(a: f16) -> i64; } - _vcvtph_s64_f16(a) + unsafe { _vcvtph_s64_f16(a) } } #[doc = "Floating-point convert to unsigned integer, rounding to plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtph_u16_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fcvtpu))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvtph_u16_f16(a: f16) -> u16 { +pub fn vcvtph_u16_f16(a: f16) -> u16 { vcvtph_u32_f16(a) as u16 } #[doc = "Floating-point convert to unsigned integer, rounding to plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtph_u32_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fcvtpu))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvtph_u32_f16(a: f16) -> u32 { +pub fn vcvtph_u32_f16(a: f16) -> u32 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -9777,17 +8994,15 @@ pub unsafe fn vcvtph_u32_f16(a: f16) -> u32 { )] fn _vcvtph_u32_f16(a: f16) -> u32; } - _vcvtph_u32_f16(a) + unsafe { _vcvtph_u32_f16(a) } } #[doc = "Floating-point convert to unsigned integer, rounding to plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtph_u64_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fcvtpu))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvtph_u64_f16(a: f16) -> u64 { +pub fn vcvtph_u64_f16(a: f16) -> u64 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -9795,17 +9010,15 @@ pub unsafe fn vcvtph_u64_f16(a: f16) -> u64 { )] fn _vcvtph_u64_f16(a: f16) -> u64; } - _vcvtph_u64_f16(a) + unsafe { _vcvtph_u64_f16(a) } } #[doc = "Floating-point convert to signed integer, rounding toward plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtps_s32_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtps))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtps_s32_f32(a: f32) -> i32 { +pub fn vcvtps_s32_f32(a: f32) -> i32 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -9813,17 +9026,15 @@ pub unsafe fn vcvtps_s32_f32(a: f32) -> i32 { )] fn _vcvtps_s32_f32(a: f32) -> i32; } - _vcvtps_s32_f32(a) + unsafe { _vcvtps_s32_f32(a) } } #[doc = "Floating-point convert to signed integer, rounding toward plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtpd_s64_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtps))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtpd_s64_f64(a: f64) -> i64 { +pub fn vcvtpd_s64_f64(a: f64) -> i64 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -9831,17 +9042,15 @@ pub unsafe fn vcvtpd_s64_f64(a: f64) -> i64 { )] fn _vcvtpd_s64_f64(a: f64) -> i64; } - _vcvtpd_s64_f64(a) + unsafe { _vcvtpd_s64_f64(a) } } #[doc = "Floating-point convert to unsigned integer, rounding toward plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtps_u32_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtpu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtps_u32_f32(a: f32) -> u32 { +pub fn vcvtps_u32_f32(a: f32) -> u32 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -9849,17 +9058,15 @@ pub unsafe fn vcvtps_u32_f32(a: f32) -> u32 { )] fn _vcvtps_u32_f32(a: f32) -> u32; } - _vcvtps_u32_f32(a) + unsafe { _vcvtps_u32_f32(a) } } #[doc = "Floating-point convert to unsigned integer, rounding toward plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtpd_u64_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtpu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtpd_u64_f64(a: f64) -> u64 { +pub fn vcvtpd_u64_f64(a: f64) -> u64 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -9867,40 +9074,34 @@ pub unsafe fn vcvtpd_u64_f64(a: f64) -> u64 { )] fn _vcvtpd_u64_f64(a: f64) -> u64; } - _vcvtpd_u64_f64(a) + unsafe { _vcvtpd_u64_f64(a) } } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_f32_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ucvtf))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvts_f32_u32(a: u32) -> f32 { +pub fn vcvts_f32_u32(a: u32) -> f32 { a as f32 } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtd_f64_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ucvtf))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtd_f64_u64(a: u64) -> f64 { +pub fn vcvtd_f64_u64(a: u64) -> f64 { a as f64 } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_n_f32_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(scvtf, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvts_n_f32_s32(a: i32) -> f32 { +pub fn vcvts_n_f32_s32(a: i32) -> f32 { static_assert!(N >= 1 && N <= 64); unsafe extern "unadjusted" { #[cfg_attr( @@ -9909,18 +9110,16 @@ pub unsafe fn vcvts_n_f32_s32(a: i32) -> f32 { )] fn _vcvts_n_f32_s32(a: i32, n: i32) -> f32; } - _vcvts_n_f32_s32(a, N) + unsafe { _vcvts_n_f32_s32(a, N) } } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtd_n_f64_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(scvtf, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtd_n_f64_s64(a: i64) -> f64 { +pub fn vcvtd_n_f64_s64(a: i64) -> f64 { static_assert!(N >= 1 && N <= 64); unsafe extern "unadjusted" { #[cfg_attr( @@ -9929,18 +9128,16 @@ pub unsafe fn vcvtd_n_f64_s64(a: i64) -> f64 { )] fn _vcvtd_n_f64_s64(a: i64, n: i32) -> f64; } - _vcvtd_n_f64_s64(a, N) + unsafe { _vcvtd_n_f64_s64(a, N) } } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_n_f32_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ucvtf, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvts_n_f32_u32(a: u32) -> f32 { +pub fn vcvts_n_f32_u32(a: u32) -> f32 { static_assert!(N >= 1 && N <= 32); unsafe extern "unadjusted" { #[cfg_attr( @@ -9949,18 +9146,16 @@ pub unsafe fn vcvts_n_f32_u32(a: u32) -> f32 { )] fn _vcvts_n_f32_u32(a: u32, n: i32) -> f32; } - _vcvts_n_f32_u32(a, N) + unsafe { _vcvts_n_f32_u32(a, N) } } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtd_n_f64_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ucvtf, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtd_n_f64_u64(a: u64) -> f64 { +pub fn vcvtd_n_f64_u64(a: u64) -> f64 { static_assert!(N >= 1 && N <= 64); unsafe extern "unadjusted" { #[cfg_attr( @@ -9969,18 +9164,16 @@ pub unsafe fn vcvtd_n_f64_u64(a: u64) -> f64 { )] fn _vcvtd_n_f64_u64(a: u64, n: i32) -> f64; } - _vcvtd_n_f64_u64(a, N) + unsafe { _vcvtd_n_f64_u64(a, N) } } #[doc = "Floating-point convert to fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_n_s32_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtzs, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvts_n_s32_f32(a: f32) -> i32 { +pub fn vcvts_n_s32_f32(a: f32) -> i32 { static_assert!(N >= 1 && N <= 32); unsafe extern "unadjusted" { #[cfg_attr( @@ -9989,18 +9182,16 @@ pub unsafe fn vcvts_n_s32_f32(a: f32) -> i32 { )] fn _vcvts_n_s32_f32(a: f32, n: i32) -> i32; } - _vcvts_n_s32_f32(a, N) + unsafe { _vcvts_n_s32_f32(a, N) } } #[doc = "Floating-point convert to fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtd_n_s64_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtzs, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtd_n_s64_f64(a: f64) -> i64 { +pub fn vcvtd_n_s64_f64(a: f64) -> i64 { static_assert!(N >= 1 && N <= 64); unsafe extern "unadjusted" { #[cfg_attr( @@ -10009,18 +9200,16 @@ pub unsafe fn vcvtd_n_s64_f64(a: f64) -> i64 { )] fn _vcvtd_n_s64_f64(a: f64, n: i32) -> i64; } - _vcvtd_n_s64_f64(a, N) + unsafe { _vcvtd_n_s64_f64(a, N) } } #[doc = "Floating-point convert to fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_n_u32_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtzu, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvts_n_u32_f32(a: f32) -> u32 { +pub fn vcvts_n_u32_f32(a: f32) -> u32 { static_assert!(N >= 1 && N <= 32); unsafe extern "unadjusted" { #[cfg_attr( @@ -10029,18 +9218,16 @@ pub unsafe fn vcvts_n_u32_f32(a: f32) -> u32 { )] fn _vcvts_n_u32_f32(a: f32, n: i32) -> u32; } - _vcvts_n_u32_f32(a, N) + unsafe { _vcvts_n_u32_f32(a, N) } } #[doc = "Floating-point convert to fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtd_n_u64_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtzu, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtd_n_u64_f64(a: f64) -> u64 { +pub fn vcvtd_n_u64_f64(a: f64) -> u64 { static_assert!(N >= 1 && N <= 64); unsafe extern "unadjusted" { #[cfg_attr( @@ -10049,61 +9236,51 @@ pub unsafe fn vcvtd_n_u64_f64(a: f64) -> u64 { )] fn _vcvtd_n_u64_f64(a: f64, n: i32) -> u64; } - _vcvtd_n_u64_f64(a, N) + unsafe { _vcvtd_n_u64_f64(a, N) } } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_s32_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtzs))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvts_s32_f32(a: f32) -> i32 { +pub fn vcvts_s32_f32(a: f32) -> i32 { a as i32 } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtd_s64_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtzs))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtd_s64_f64(a: f64) -> i64 { +pub fn vcvtd_s64_f64(a: f64) -> i64 { a as i64 } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_u32_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtzu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvts_u32_f32(a: f32) -> u32 { +pub fn vcvts_u32_f32(a: f32) -> u32 { a as u32 } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtd_u64_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtzu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtd_u64_f64(a: f64) -> u64 { +pub fn vcvtd_u64_f64(a: f64) -> u64 { a as u64 } #[doc = "Floating-point convert to lower precision narrow, rounding to odd"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtx_f32_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtxn))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtx_f32_f64(a: float64x2_t) -> float32x2_t { +pub fn vcvtx_f32_f64(a: float64x2_t) -> float32x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -10111,634 +9288,532 @@ pub unsafe fn vcvtx_f32_f64(a: float64x2_t) -> float32x2_t { )] fn _vcvtx_f32_f64(a: float64x2_t) -> float32x2_t; } - _vcvtx_f32_f64(a) + unsafe { _vcvtx_f32_f64(a) } } #[doc = "Floating-point convert to lower precision narrow, rounding to odd"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtx_high_f32_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtxn))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtx_high_f32_f64(a: float32x2_t, b: float64x2_t) -> float32x4_t { - simd_shuffle!(a, vcvtx_f32_f64(b), [0, 1, 2, 3]) +pub fn vcvtx_high_f32_f64(a: float32x2_t, b: float64x2_t) -> float32x4_t { + unsafe { simd_shuffle!(a, vcvtx_f32_f64(b), [0, 1, 2, 3]) } } #[doc = "Floating-point convert to lower precision narrow, rounding to odd"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtxd_f32_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtxn))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtxd_f32_f64(a: f64) -> f32 { - simd_extract!(vcvtx_f32_f64(vdupq_n_f64(a)), 0) +pub fn vcvtxd_f32_f64(a: f64) -> f32 { + unsafe { simd_extract!(vcvtx_f32_f64(vdupq_n_f64(a)), 0) } } #[doc = "Divide"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdiv_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(fdiv))] -pub unsafe fn vdiv_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { - simd_div(a, b) +pub fn vdiv_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { + unsafe { simd_div(a, b) } } #[doc = "Divide"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdivq_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(fdiv))] -pub unsafe fn vdivq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { - simd_div(a, b) +pub fn vdivq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { + unsafe { simd_div(a, b) } } #[doc = "Divide"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdiv_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fdiv))] -pub unsafe fn vdiv_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { - simd_div(a, b) +pub fn vdiv_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { + unsafe { simd_div(a, b) } } #[doc = "Divide"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdivq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fdiv))] -pub unsafe fn vdivq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { - simd_div(a, b) +pub fn vdivq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { + unsafe { simd_div(a, b) } } #[doc = "Divide"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdiv_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fdiv))] -pub unsafe fn vdiv_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { - simd_div(a, b) +pub fn vdiv_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { + unsafe { simd_div(a, b) } } #[doc = "Divide"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdivq_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fdiv))] -pub unsafe fn vdivq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { - simd_div(a, b) +pub fn vdivq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { + unsafe { simd_div(a, b) } } #[doc = "Divide"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdivh_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vdivh_f16(a: f16, b: f16) -> f16 { +pub fn vdivh_f16(a: f16, b: f16) -> f16 { a / b } #[doc = "Dot product arithmetic (indexed)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_laneq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,dotprod")] #[cfg_attr(test, assert_instr(sdot, LANE = 0))] #[rustc_legacy_const_generics(3)] #[unstable(feature = "stdarch_neon_dotprod", issue = "117224")] -pub unsafe fn vdot_laneq_s32( - a: int32x2_t, - b: int8x8_t, - c: int8x16_t, -) -> int32x2_t { +pub fn vdot_laneq_s32(a: int32x2_t, b: int8x8_t, c: int8x16_t) -> int32x2_t { static_assert_uimm_bits!(LANE, 2); - let c: int32x4_t = transmute(c); - let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); - vdot_s32(a, b, transmute(c)) + unsafe { + let c: int32x4_t = transmute(c); + let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); + vdot_s32(a, b, transmute(c)) + } } #[doc = "Dot product arithmetic (indexed)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_laneq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,dotprod")] #[cfg_attr(test, assert_instr(sdot, LANE = 0))] #[rustc_legacy_const_generics(3)] #[unstable(feature = "stdarch_neon_dotprod", issue = "117224")] -pub unsafe fn vdotq_laneq_s32( - a: int32x4_t, - b: int8x16_t, - c: int8x16_t, -) -> int32x4_t { +pub fn vdotq_laneq_s32(a: int32x4_t, b: int8x16_t, c: int8x16_t) -> int32x4_t { static_assert_uimm_bits!(LANE, 2); - let c: int32x4_t = transmute(c); - let c: int32x4_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vdotq_s32(a, b, transmute(c)) + unsafe { + let c: int32x4_t = transmute(c); + let c: int32x4_t = + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); + vdotq_s32(a, b, transmute(c)) + } } #[doc = "Dot product arithmetic (indexed)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_laneq_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,dotprod")] #[cfg_attr(test, assert_instr(udot, LANE = 0))] #[rustc_legacy_const_generics(3)] #[unstable(feature = "stdarch_neon_dotprod", issue = "117224")] -pub unsafe fn vdot_laneq_u32( - a: uint32x2_t, - b: uint8x8_t, - c: uint8x16_t, -) -> uint32x2_t { +pub fn vdot_laneq_u32(a: uint32x2_t, b: uint8x8_t, c: uint8x16_t) -> uint32x2_t { static_assert_uimm_bits!(LANE, 2); - let c: uint32x4_t = transmute(c); - let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); - vdot_u32(a, b, transmute(c)) + unsafe { + let c: uint32x4_t = transmute(c); + let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); + vdot_u32(a, b, transmute(c)) + } } #[doc = "Dot product arithmetic (indexed)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_laneq_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,dotprod")] #[cfg_attr(test, assert_instr(udot, LANE = 0))] #[rustc_legacy_const_generics(3)] #[unstable(feature = "stdarch_neon_dotprod", issue = "117224")] -pub unsafe fn vdotq_laneq_u32( - a: uint32x4_t, - b: uint8x16_t, - c: uint8x16_t, -) -> uint32x4_t { +pub fn vdotq_laneq_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4_t { static_assert_uimm_bits!(LANE, 2); - let c: uint32x4_t = transmute(c); - let c: uint32x4_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vdotq_u32(a, b, transmute(c)) + unsafe { + let c: uint32x4_t = transmute(c); + let c: uint32x4_t = + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); + vdotq_u32(a, b, transmute(c)) + } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 0))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vdup_lane_f64(a: float64x1_t) -> float64x1_t { +pub fn vdup_lane_f64(a: float64x1_t) -> float64x1_t { static_assert!(N == 0); a } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 0))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vdup_lane_p64(a: poly64x1_t) -> poly64x1_t { +pub fn vdup_lane_p64(a: poly64x1_t) -> poly64x1_t { static_assert!(N == 0); a } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 1))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vdup_laneq_f64(a: float64x2_t) -> float64x1_t { +pub fn vdup_laneq_f64(a: float64x2_t) -> float64x1_t { static_assert_uimm_bits!(N, 1); - transmute::(simd_extract!(a, N as u32)) + unsafe { transmute::(simd_extract!(a, N as u32)) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 1))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vdup_laneq_p64(a: poly64x2_t) -> poly64x1_t { +pub fn vdup_laneq_p64(a: poly64x2_t) -> poly64x1_t { static_assert_uimm_bits!(N, 1); - transmute::(simd_extract!(a, N as u32)) + unsafe { transmute::(simd_extract!(a, N as u32)) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupb_lane_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 4))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vdupb_lane_s8(a: int8x8_t) -> i8 { +pub fn vdupb_lane_s8(a: int8x8_t) -> i8 { static_assert_uimm_bits!(N, 3); - simd_extract!(a, N as u32) + unsafe { simd_extract!(a, N as u32) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vduph_laneq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 4))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vduph_laneq_s16(a: int16x8_t) -> i16 { +pub fn vduph_laneq_s16(a: int16x8_t) -> i16 { static_assert_uimm_bits!(N, 3); - simd_extract!(a, N as u32) + unsafe { simd_extract!(a, N as u32) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupb_lane_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 4))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vdupb_lane_u8(a: uint8x8_t) -> u8 { +pub fn vdupb_lane_u8(a: uint8x8_t) -> u8 { static_assert_uimm_bits!(N, 3); - simd_extract!(a, N as u32) + unsafe { simd_extract!(a, N as u32) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vduph_laneq_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 4))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vduph_laneq_u16(a: uint16x8_t) -> u16 { +pub fn vduph_laneq_u16(a: uint16x8_t) -> u16 { static_assert_uimm_bits!(N, 3); - simd_extract!(a, N as u32) + unsafe { simd_extract!(a, N as u32) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupb_lane_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 4))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vdupb_lane_p8(a: poly8x8_t) -> p8 { +pub fn vdupb_lane_p8(a: poly8x8_t) -> p8 { static_assert_uimm_bits!(N, 3); - simd_extract!(a, N as u32) + unsafe { simd_extract!(a, N as u32) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vduph_laneq_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 4))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vduph_laneq_p16(a: poly16x8_t) -> p16 { +pub fn vduph_laneq_p16(a: poly16x8_t) -> p16 { static_assert_uimm_bits!(N, 3); - simd_extract!(a, N as u32) + unsafe { simd_extract!(a, N as u32) } } #[doc = "Extract an element from a vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupb_laneq_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 8))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vdupb_laneq_s8(a: int8x16_t) -> i8 { +pub fn vdupb_laneq_s8(a: int8x16_t) -> i8 { static_assert_uimm_bits!(N, 4); - simd_extract!(a, N as u32) + unsafe { simd_extract!(a, N as u32) } } #[doc = "Extract an element from a vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupb_laneq_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 8))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vdupb_laneq_u8(a: uint8x16_t) -> u8 { +pub fn vdupb_laneq_u8(a: uint8x16_t) -> u8 { static_assert_uimm_bits!(N, 4); - simd_extract!(a, N as u32) + unsafe { simd_extract!(a, N as u32) } } #[doc = "Extract an element from a vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupb_laneq_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 8))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vdupb_laneq_p8(a: poly8x16_t) -> p8 { +pub fn vdupb_laneq_p8(a: poly8x16_t) -> p8 { static_assert_uimm_bits!(N, 4); - simd_extract!(a, N as u32) + unsafe { simd_extract!(a, N as u32) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupd_lane_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 0))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vdupd_lane_f64(a: float64x1_t) -> f64 { +pub fn vdupd_lane_f64(a: float64x1_t) -> f64 { static_assert!(N == 0); - simd_extract!(a, N as u32) + unsafe { simd_extract!(a, N as u32) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupd_lane_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 0))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vdupd_lane_s64(a: int64x1_t) -> i64 { +pub fn vdupd_lane_s64(a: int64x1_t) -> i64 { static_assert!(N == 0); - simd_extract!(a, N as u32) + unsafe { simd_extract!(a, N as u32) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupd_lane_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 0))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vdupd_lane_u64(a: uint64x1_t) -> u64 { +pub fn vdupd_lane_u64(a: uint64x1_t) -> u64 { static_assert!(N == 0); - simd_extract!(a, N as u32) + unsafe { simd_extract!(a, N as u32) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vduph_lane_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(nop, N = 2))] #[rustc_legacy_const_generics(1)] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vduph_lane_f16(a: float16x4_t) -> f16 { +pub fn vduph_lane_f16(a: float16x4_t) -> f16 { static_assert_uimm_bits!(N, 2); - simd_extract!(a, N as u32) + unsafe { simd_extract!(a, N as u32) } } #[doc = "Extract an element from a vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vduph_laneq_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(nop, N = 4))] #[rustc_legacy_const_generics(1)] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vduph_laneq_f16(a: float16x8_t) -> f16 { +pub fn vduph_laneq_f16(a: float16x8_t) -> f16 { static_assert_uimm_bits!(N, 4); - simd_extract!(a, N as u32) + unsafe { simd_extract!(a, N as u32) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(dup, N = 0))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vdupq_lane_f64(a: float64x1_t) -> float64x2_t { +pub fn vdupq_lane_f64(a: float64x1_t) -> float64x2_t { static_assert!(N == 0); - simd_shuffle!(a, a, [N as u32, N as u32]) + unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(dup, N = 0))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vdupq_lane_p64(a: poly64x1_t) -> poly64x2_t { +pub fn vdupq_lane_p64(a: poly64x1_t) -> poly64x2_t { static_assert!(N == 0); - simd_shuffle!(a, a, [N as u32, N as u32]) + unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(dup, N = 1))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vdupq_laneq_f64(a: float64x2_t) -> float64x2_t { +pub fn vdupq_laneq_f64(a: float64x2_t) -> float64x2_t { static_assert_uimm_bits!(N, 1); - simd_shuffle!(a, a, [N as u32, N as u32]) + unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(dup, N = 1))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vdupq_laneq_p64(a: poly64x2_t) -> poly64x2_t { +pub fn vdupq_laneq_p64(a: poly64x2_t) -> poly64x2_t { static_assert_uimm_bits!(N, 1); - simd_shuffle!(a, a, [N as u32, N as u32]) + unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdups_lane_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 1))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vdups_lane_f32(a: float32x2_t) -> f32 { +pub fn vdups_lane_f32(a: float32x2_t) -> f32 { static_assert_uimm_bits!(N, 1); - simd_extract!(a, N as u32) + unsafe { simd_extract!(a, N as u32) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupd_laneq_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 1))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vdupd_laneq_f64(a: float64x2_t) -> f64 { +pub fn vdupd_laneq_f64(a: float64x2_t) -> f64 { static_assert_uimm_bits!(N, 1); - simd_extract!(a, N as u32) + unsafe { simd_extract!(a, N as u32) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdups_lane_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 1))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vdups_lane_s32(a: int32x2_t) -> i32 { +pub fn vdups_lane_s32(a: int32x2_t) -> i32 { static_assert_uimm_bits!(N, 1); - simd_extract!(a, N as u32) + unsafe { simd_extract!(a, N as u32) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupd_laneq_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 1))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vdupd_laneq_s64(a: int64x2_t) -> i64 { +pub fn vdupd_laneq_s64(a: int64x2_t) -> i64 { static_assert_uimm_bits!(N, 1); - simd_extract!(a, N as u32) + unsafe { simd_extract!(a, N as u32) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdups_lane_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 1))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vdups_lane_u32(a: uint32x2_t) -> u32 { +pub fn vdups_lane_u32(a: uint32x2_t) -> u32 { static_assert_uimm_bits!(N, 1); - simd_extract!(a, N as u32) + unsafe { simd_extract!(a, N as u32) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupd_laneq_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 1))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vdupd_laneq_u64(a: uint64x2_t) -> u64 { +pub fn vdupd_laneq_u64(a: uint64x2_t) -> u64 { static_assert_uimm_bits!(N, 1); - simd_extract!(a, N as u32) + unsafe { simd_extract!(a, N as u32) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdups_laneq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vdups_laneq_f32(a: float32x4_t) -> f32 { +pub fn vdups_laneq_f32(a: float32x4_t) -> f32 { static_assert_uimm_bits!(N, 2); - simd_extract!(a, N as u32) + unsafe { simd_extract!(a, N as u32) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vduph_lane_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vduph_lane_s16(a: int16x4_t) -> i16 { +pub fn vduph_lane_s16(a: int16x4_t) -> i16 { static_assert_uimm_bits!(N, 2); - simd_extract!(a, N as u32) + unsafe { simd_extract!(a, N as u32) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdups_laneq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vdups_laneq_s32(a: int32x4_t) -> i32 { +pub fn vdups_laneq_s32(a: int32x4_t) -> i32 { static_assert_uimm_bits!(N, 2); - simd_extract!(a, N as u32) + unsafe { simd_extract!(a, N as u32) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vduph_lane_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vduph_lane_u16(a: uint16x4_t) -> u16 { +pub fn vduph_lane_u16(a: uint16x4_t) -> u16 { static_assert_uimm_bits!(N, 2); - simd_extract!(a, N as u32) + unsafe { simd_extract!(a, N as u32) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdups_laneq_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vdups_laneq_u32(a: uint32x4_t) -> u32 { +pub fn vdups_laneq_u32(a: uint32x4_t) -> u32 { static_assert_uimm_bits!(N, 2); - simd_extract!(a, N as u32) + unsafe { simd_extract!(a, N as u32) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vduph_lane_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vduph_lane_p16(a: poly16x4_t) -> p16 { +pub fn vduph_lane_p16(a: poly16x4_t) -> p16 { static_assert_uimm_bits!(N, 2); - simd_extract!(a, N as u32) + unsafe { simd_extract!(a, N as u32) } } #[doc = "Three-way exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor3q_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,sha3")] #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] #[cfg_attr(test, assert_instr(eor3))] -pub unsafe fn veor3q_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t { +pub fn veor3q_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -10746,17 +9821,15 @@ pub unsafe fn veor3q_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t { )] fn _veor3q_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t; } - _veor3q_s8(a, b, c) + unsafe { _veor3q_s8(a, b, c) } } #[doc = "Three-way exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor3q_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,sha3")] #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] #[cfg_attr(test, assert_instr(eor3))] -pub unsafe fn veor3q_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t { +pub fn veor3q_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -10764,17 +9837,15 @@ pub unsafe fn veor3q_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t )] fn _veor3q_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t; } - _veor3q_s16(a, b, c) + unsafe { _veor3q_s16(a, b, c) } } #[doc = "Three-way exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor3q_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,sha3")] #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] #[cfg_attr(test, assert_instr(eor3))] -pub unsafe fn veor3q_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t { +pub fn veor3q_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -10782,17 +9853,15 @@ pub unsafe fn veor3q_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t )] fn _veor3q_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t; } - _veor3q_s32(a, b, c) + unsafe { _veor3q_s32(a, b, c) } } #[doc = "Three-way exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor3q_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,sha3")] #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] #[cfg_attr(test, assert_instr(eor3))] -pub unsafe fn veor3q_s64(a: int64x2_t, b: int64x2_t, c: int64x2_t) -> int64x2_t { +pub fn veor3q_s64(a: int64x2_t, b: int64x2_t, c: int64x2_t) -> int64x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -10800,17 +9869,15 @@ pub unsafe fn veor3q_s64(a: int64x2_t, b: int64x2_t, c: int64x2_t) -> int64x2_t )] fn _veor3q_s64(a: int64x2_t, b: int64x2_t, c: int64x2_t) -> int64x2_t; } - _veor3q_s64(a, b, c) + unsafe { _veor3q_s64(a, b, c) } } #[doc = "Three-way exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor3q_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,sha3")] #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] #[cfg_attr(test, assert_instr(eor3))] -pub unsafe fn veor3q_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t { +pub fn veor3q_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -10818,17 +9885,15 @@ pub unsafe fn veor3q_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16 )] fn _veor3q_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t; } - _veor3q_u8(a, b, c) + unsafe { _veor3q_u8(a, b, c) } } #[doc = "Three-way exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor3q_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,sha3")] #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] #[cfg_attr(test, assert_instr(eor3))] -pub unsafe fn veor3q_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t { +pub fn veor3q_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -10836,17 +9901,15 @@ pub unsafe fn veor3q_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x )] fn _veor3q_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t; } - _veor3q_u16(a, b, c) + unsafe { _veor3q_u16(a, b, c) } } #[doc = "Three-way exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor3q_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,sha3")] #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] #[cfg_attr(test, assert_instr(eor3))] -pub unsafe fn veor3q_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t { +pub fn veor3q_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -10854,17 +9917,15 @@ pub unsafe fn veor3q_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x )] fn _veor3q_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t; } - _veor3q_u32(a, b, c) + unsafe { _veor3q_u32(a, b, c) } } #[doc = "Three-way exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor3q_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,sha3")] #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] #[cfg_attr(test, assert_instr(eor3))] -pub unsafe fn veor3q_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t { +pub fn veor3q_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -10872,51 +9933,49 @@ pub unsafe fn veor3q_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x )] fn _veor3q_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t; } - _veor3q_u64(a, b, c) + unsafe { _veor3q_u64(a, b, c) } } #[doc = "Extract vector from pair of vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ext, N = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vextq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { +pub fn vextq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { static_assert_uimm_bits!(N, 1); - match N & 0b1 { - 0 => simd_shuffle!(a, b, [0, 1]), - 1 => simd_shuffle!(a, b, [1, 2]), - _ => unreachable_unchecked(), + unsafe { + match N & 0b1 { + 0 => simd_shuffle!(a, b, [0, 1]), + 1 => simd_shuffle!(a, b, [1, 2]), + _ => unreachable_unchecked(), + } } } #[doc = "Extract vector from pair of vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ext, N = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vextq_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { +pub fn vextq_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { static_assert_uimm_bits!(N, 1); - match N & 0b1 { - 0 => simd_shuffle!(a, b, [0, 1]), - 1 => simd_shuffle!(a, b, [1, 2]), - _ => unreachable_unchecked(), + unsafe { + match N & 0b1 { + 0 => simd_shuffle!(a, b, [0, 1]), + 1 => simd_shuffle!(a, b, [1, 2]), + _ => unreachable_unchecked(), + } } } #[doc = "Floating-point fused Multiply-Add to accumulator(vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmadd))] -pub unsafe fn vfma_f64(a: float64x1_t, b: float64x1_t, c: float64x1_t) -> float64x1_t { +pub fn vfma_f64(a: float64x1_t, b: float64x1_t, c: float64x1_t) -> float64x1_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -10924,238 +9983,208 @@ pub unsafe fn vfma_f64(a: float64x1_t, b: float64x1_t, c: float64x1_t) -> float6 )] fn _vfma_f64(a: float64x1_t, b: float64x1_t, c: float64x1_t) -> float64x1_t; } - _vfma_f64(b, c, a) + unsafe { _vfma_f64(b, c, a) } } #[doc = "Floating-point fused multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_lane_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fmla, LANE = 0))] #[rustc_legacy_const_generics(3)] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vfma_lane_f16( +pub fn vfma_lane_f16( a: float16x4_t, b: float16x4_t, c: float16x4_t, ) -> float16x4_t { static_assert_uimm_bits!(LANE, 2); - vfma_f16(a, b, vdup_n_f16(simd_extract!(c, LANE as u32))) + unsafe { vfma_f16(a, b, vdup_n_f16(simd_extract!(c, LANE as u32))) } } #[doc = "Floating-point fused multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_laneq_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fmla, LANE = 0))] #[rustc_legacy_const_generics(3)] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vfma_laneq_f16( +pub fn vfma_laneq_f16( a: float16x4_t, b: float16x4_t, c: float16x8_t, ) -> float16x4_t { static_assert_uimm_bits!(LANE, 3); - vfma_f16(a, b, vdup_n_f16(simd_extract!(c, LANE as u32))) + unsafe { vfma_f16(a, b, vdup_n_f16(simd_extract!(c, LANE as u32))) } } #[doc = "Floating-point fused multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_lane_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fmla, LANE = 0))] #[rustc_legacy_const_generics(3)] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vfmaq_lane_f16( +pub fn vfmaq_lane_f16( a: float16x8_t, b: float16x8_t, c: float16x4_t, ) -> float16x8_t { static_assert_uimm_bits!(LANE, 2); - vfmaq_f16(a, b, vdupq_n_f16(simd_extract!(c, LANE as u32))) + unsafe { vfmaq_f16(a, b, vdupq_n_f16(simd_extract!(c, LANE as u32))) } } #[doc = "Floating-point fused multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_laneq_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fmla, LANE = 0))] #[rustc_legacy_const_generics(3)] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vfmaq_laneq_f16( +pub fn vfmaq_laneq_f16( a: float16x8_t, b: float16x8_t, c: float16x8_t, ) -> float16x8_t { static_assert_uimm_bits!(LANE, 3); - vfmaq_f16(a, b, vdupq_n_f16(simd_extract!(c, LANE as u32))) + unsafe { vfmaq_f16(a, b, vdupq_n_f16(simd_extract!(c, LANE as u32))) } } #[doc = "Floating-point fused multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_lane_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmla, LANE = 0))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vfma_lane_f32( +pub fn vfma_lane_f32( a: float32x2_t, b: float32x2_t, c: float32x2_t, ) -> float32x2_t { static_assert_uimm_bits!(LANE, 1); - vfma_f32(a, b, vdup_n_f32(simd_extract!(c, LANE as u32))) + unsafe { vfma_f32(a, b, vdup_n_f32(simd_extract!(c, LANE as u32))) } } #[doc = "Floating-point fused multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_laneq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmla, LANE = 0))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vfma_laneq_f32( +pub fn vfma_laneq_f32( a: float32x2_t, b: float32x2_t, c: float32x4_t, ) -> float32x2_t { static_assert_uimm_bits!(LANE, 2); - vfma_f32(a, b, vdup_n_f32(simd_extract!(c, LANE as u32))) + unsafe { vfma_f32(a, b, vdup_n_f32(simd_extract!(c, LANE as u32))) } } #[doc = "Floating-point fused multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_lane_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmla, LANE = 0))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vfmaq_lane_f32( +pub fn vfmaq_lane_f32( a: float32x4_t, b: float32x4_t, c: float32x2_t, ) -> float32x4_t { static_assert_uimm_bits!(LANE, 1); - vfmaq_f32(a, b, vdupq_n_f32(simd_extract!(c, LANE as u32))) + unsafe { vfmaq_f32(a, b, vdupq_n_f32(simd_extract!(c, LANE as u32))) } } #[doc = "Floating-point fused multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_laneq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmla, LANE = 0))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vfmaq_laneq_f32( +pub fn vfmaq_laneq_f32( a: float32x4_t, b: float32x4_t, c: float32x4_t, ) -> float32x4_t { static_assert_uimm_bits!(LANE, 2); - vfmaq_f32(a, b, vdupq_n_f32(simd_extract!(c, LANE as u32))) + unsafe { vfmaq_f32(a, b, vdupq_n_f32(simd_extract!(c, LANE as u32))) } } #[doc = "Floating-point fused multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_laneq_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmla, LANE = 0))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vfmaq_laneq_f64( +pub fn vfmaq_laneq_f64( a: float64x2_t, b: float64x2_t, c: float64x2_t, ) -> float64x2_t { static_assert_uimm_bits!(LANE, 1); - vfmaq_f64(a, b, vdupq_n_f64(simd_extract!(c, LANE as u32))) + unsafe { vfmaq_f64(a, b, vdupq_n_f64(simd_extract!(c, LANE as u32))) } } #[doc = "Floating-point fused multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_lane_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmadd, LANE = 0))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vfma_lane_f64( +pub fn vfma_lane_f64( a: float64x1_t, b: float64x1_t, c: float64x1_t, ) -> float64x1_t { static_assert!(LANE == 0); - vfma_f64(a, b, vdup_n_f64(simd_extract!(c, LANE as u32))) + unsafe { vfma_f64(a, b, vdup_n_f64(simd_extract!(c, LANE as u32))) } } #[doc = "Floating-point fused multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_laneq_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmadd, LANE = 0))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vfma_laneq_f64( +pub fn vfma_laneq_f64( a: float64x1_t, b: float64x1_t, c: float64x2_t, ) -> float64x1_t { static_assert_uimm_bits!(LANE, 1); - vfma_f64(a, b, vdup_n_f64(simd_extract!(c, LANE as u32))) + unsafe { vfma_f64(a, b, vdup_n_f64(simd_extract!(c, LANE as u32))) } } #[doc = "Floating-point fused Multiply-Subtract from accumulator."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_n_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(fmla))] -pub unsafe fn vfma_n_f16(a: float16x4_t, b: float16x4_t, c: f16) -> float16x4_t { +pub fn vfma_n_f16(a: float16x4_t, b: float16x4_t, c: f16) -> float16x4_t { vfma_f16(a, b, vdup_n_f16(c)) } #[doc = "Floating-point fused Multiply-Subtract from accumulator."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_n_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(fmla))] -pub unsafe fn vfmaq_n_f16(a: float16x8_t, b: float16x8_t, c: f16) -> float16x8_t { +pub fn vfmaq_n_f16(a: float16x8_t, b: float16x8_t, c: f16) -> float16x8_t { vfmaq_f16(a, b, vdupq_n_f16(c)) } #[doc = "Floating-point fused Multiply-Add to accumulator(vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_n_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmadd))] -pub unsafe fn vfma_n_f64(a: float64x1_t, b: float64x1_t, c: f64) -> float64x1_t { +pub fn vfma_n_f64(a: float64x1_t, b: float64x1_t, c: f64) -> float64x1_t { vfma_f64(a, b, vdup_n_f64(c)) } #[doc = "Floating-point fused multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmad_lane_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmadd, LANE = 0))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vfmad_lane_f64(a: f64, b: f64, c: float64x1_t) -> f64 { +pub fn vfmad_lane_f64(a: f64, b: f64, c: float64x1_t) -> f64 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -11164,18 +10193,18 @@ pub unsafe fn vfmad_lane_f64(a: f64, b: f64, c: float64x1_t) -> fn _vfmad_lane_f64(a: f64, b: f64, c: f64) -> f64; } static_assert!(LANE == 0); - let c: f64 = simd_extract!(c, LANE as u32); - _vfmad_lane_f64(b, c, a) + unsafe { + let c: f64 = simd_extract!(c, LANE as u32); + _vfmad_lane_f64(b, c, a) + } } #[doc = "Floating-point fused multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmah_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fmadd))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vfmah_f16(a: f16, b: f16, c: f16) -> f16 { +pub fn vfmah_f16(a: f16, b: f16, c: f16) -> f16 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -11183,45 +10212,43 @@ pub unsafe fn vfmah_f16(a: f16, b: f16, c: f16) -> f16 { )] fn _vfmah_f16(a: f16, b: f16, c: f16) -> f16; } - _vfmah_f16(b, c, a) + unsafe { _vfmah_f16(b, c, a) } } #[doc = "Floating-point fused multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmah_lane_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fmadd, LANE = 0))] #[rustc_legacy_const_generics(3)] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vfmah_lane_f16(a: f16, b: f16, v: float16x4_t) -> f16 { +pub fn vfmah_lane_f16(a: f16, b: f16, v: float16x4_t) -> f16 { static_assert_uimm_bits!(LANE, 2); - let c: f16 = simd_extract!(v, LANE as u32); - vfmah_f16(a, b, c) + unsafe { + let c: f16 = simd_extract!(v, LANE as u32); + vfmah_f16(a, b, c) + } } #[doc = "Floating-point fused multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmah_laneq_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fmadd, LANE = 0))] #[rustc_legacy_const_generics(3)] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vfmah_laneq_f16(a: f16, b: f16, v: float16x8_t) -> f16 { +pub fn vfmah_laneq_f16(a: f16, b: f16, v: float16x8_t) -> f16 { static_assert_uimm_bits!(LANE, 3); - let c: f16 = simd_extract!(v, LANE as u32); - vfmah_f16(a, b, c) + unsafe { + let c: f16 = simd_extract!(v, LANE as u32); + vfmah_f16(a, b, c) + } } #[doc = "Floating-point fused Multiply-Add to accumulator(vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmla))] -pub unsafe fn vfmaq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t { +pub fn vfmaq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -11229,46 +10256,40 @@ pub unsafe fn vfmaq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float )] fn _vfmaq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t; } - _vfmaq_f64(b, c, a) + unsafe { _vfmaq_f64(b, c, a) } } #[doc = "Floating-point fused multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_lane_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmla, LANE = 0))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vfmaq_lane_f64( +pub fn vfmaq_lane_f64( a: float64x2_t, b: float64x2_t, c: float64x1_t, ) -> float64x2_t { static_assert!(LANE == 0); - vfmaq_f64(a, b, vdupq_n_f64(simd_extract!(c, LANE as u32))) + unsafe { vfmaq_f64(a, b, vdupq_n_f64(simd_extract!(c, LANE as u32))) } } #[doc = "Floating-point fused Multiply-Add to accumulator(vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_n_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmla))] -pub unsafe fn vfmaq_n_f64(a: float64x2_t, b: float64x2_t, c: f64) -> float64x2_t { +pub fn vfmaq_n_f64(a: float64x2_t, b: float64x2_t, c: f64) -> float64x2_t { vfmaq_f64(a, b, vdupq_n_f64(c)) } #[doc = "Floating-point fused multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmas_lane_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmadd, LANE = 0))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vfmas_lane_f32(a: f32, b: f32, c: float32x2_t) -> f32 { +pub fn vfmas_lane_f32(a: f32, b: f32, c: float32x2_t) -> f32 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -11277,19 +10298,19 @@ pub unsafe fn vfmas_lane_f32(a: f32, b: f32, c: float32x2_t) -> fn _vfmas_lane_f32(a: f32, b: f32, c: f32) -> f32; } static_assert_uimm_bits!(LANE, 1); - let c: f32 = simd_extract!(c, LANE as u32); - _vfmas_lane_f32(b, c, a) + unsafe { + let c: f32 = simd_extract!(c, LANE as u32); + _vfmas_lane_f32(b, c, a) + } } #[doc = "Floating-point fused multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmas_laneq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmadd, LANE = 0))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vfmas_laneq_f32(a: f32, b: f32, c: float32x4_t) -> f32 { +pub fn vfmas_laneq_f32(a: f32, b: f32, c: float32x4_t) -> f32 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -11298,19 +10319,19 @@ pub unsafe fn vfmas_laneq_f32(a: f32, b: f32, c: float32x4_t) - fn _vfmas_laneq_f32(a: f32, b: f32, c: f32) -> f32; } static_assert_uimm_bits!(LANE, 2); - let c: f32 = simd_extract!(c, LANE as u32); - _vfmas_laneq_f32(b, c, a) + unsafe { + let c: f32 = simd_extract!(c, LANE as u32); + _vfmas_laneq_f32(b, c, a) + } } #[doc = "Floating-point fused multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmad_laneq_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmadd, LANE = 0))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vfmad_laneq_f64(a: f64, b: f64, c: float64x2_t) -> f64 { +pub fn vfmad_laneq_f64(a: f64, b: f64, c: float64x2_t) -> f64 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -11319,19 +10340,19 @@ pub unsafe fn vfmad_laneq_f64(a: f64, b: f64, c: float64x2_t) - fn _vfmad_laneq_f64(a: f64, b: f64, c: f64) -> f64; } static_assert_uimm_bits!(LANE, 1); - let c: f64 = simd_extract!(c, LANE as u32); - _vfmad_laneq_f64(b, c, a) + unsafe { + let c: f64 = simd_extract!(c, LANE as u32); + _vfmad_laneq_f64(b, c, a) + } } #[doc = "Floating-point fused Multiply-Add Long to accumulator (vector)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlal_high_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(fmlal2))] -pub unsafe fn vfmlal_high_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float32x2_t { +pub fn vfmlal_high_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float32x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -11339,18 +10360,16 @@ pub unsafe fn vfmlal_high_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> )] fn _vfmlal_high_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float32x2_t; } - _vfmlal_high_f16(r, a, b) + unsafe { _vfmlal_high_f16(r, a, b) } } #[doc = "Floating-point fused Multiply-Add Long to accumulator (vector)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlalq_high_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(fmlal2))] -pub unsafe fn vfmlalq_high_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float32x4_t { +pub fn vfmlalq_high_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -11358,162 +10377,144 @@ pub unsafe fn vfmlalq_high_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) - )] fn _vfmlalq_high_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float32x4_t; } - _vfmlalq_high_f16(r, a, b) + unsafe { _vfmlalq_high_f16(r, a, b) } } #[doc = "Floating-point fused Multiply-Add Long to accumulator (by element)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlal_lane_high_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fmlal2, LANE = 0))] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] #[rustc_legacy_const_generics(3)] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vfmlal_lane_high_f16( +pub fn vfmlal_lane_high_f16( r: float32x2_t, a: float16x4_t, b: float16x4_t, ) -> float32x2_t { static_assert_uimm_bits!(LANE, 2); - vfmlal_high_f16(r, a, vdup_n_f16(simd_extract!(b, LANE as u32))) + unsafe { vfmlal_high_f16(r, a, vdup_n_f16(simd_extract!(b, LANE as u32))) } } #[doc = "Floating-point fused Multiply-Add Long to accumulator (by element)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlal_laneq_high_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fmlal2, LANE = 0))] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] #[rustc_legacy_const_generics(3)] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vfmlal_laneq_high_f16( +pub fn vfmlal_laneq_high_f16( r: float32x2_t, a: float16x4_t, b: float16x8_t, ) -> float32x2_t { static_assert_uimm_bits!(LANE, 3); - vfmlal_high_f16(r, a, vdup_n_f16(simd_extract!(b, LANE as u32))) + unsafe { vfmlal_high_f16(r, a, vdup_n_f16(simd_extract!(b, LANE as u32))) } } #[doc = "Floating-point fused Multiply-Add Long to accumulator (by element)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlalq_lane_high_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fmlal2, LANE = 0))] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] #[rustc_legacy_const_generics(3)] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vfmlalq_lane_high_f16( +pub fn vfmlalq_lane_high_f16( r: float32x4_t, a: float16x8_t, b: float16x4_t, ) -> float32x4_t { static_assert_uimm_bits!(LANE, 2); - vfmlalq_high_f16(r, a, vdupq_n_f16(simd_extract!(b, LANE as u32))) + unsafe { vfmlalq_high_f16(r, a, vdupq_n_f16(simd_extract!(b, LANE as u32))) } } #[doc = "Floating-point fused Multiply-Add Long to accumulator (by element)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlalq_laneq_high_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fmlal2, LANE = 0))] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] #[rustc_legacy_const_generics(3)] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vfmlalq_laneq_high_f16( +pub fn vfmlalq_laneq_high_f16( r: float32x4_t, a: float16x8_t, b: float16x8_t, ) -> float32x4_t { static_assert_uimm_bits!(LANE, 3); - vfmlalq_high_f16(r, a, vdupq_n_f16(simd_extract!(b, LANE as u32))) + unsafe { vfmlalq_high_f16(r, a, vdupq_n_f16(simd_extract!(b, LANE as u32))) } } #[doc = "Floating-point fused Multiply-Add Long to accumulator (by element)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlal_lane_low_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fmlal, LANE = 0))] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] #[rustc_legacy_const_generics(3)] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vfmlal_lane_low_f16( +pub fn vfmlal_lane_low_f16( r: float32x2_t, a: float16x4_t, b: float16x4_t, ) -> float32x2_t { static_assert_uimm_bits!(LANE, 2); - vfmlal_low_f16(r, a, vdup_n_f16(simd_extract!(b, LANE as u32))) + unsafe { vfmlal_low_f16(r, a, vdup_n_f16(simd_extract!(b, LANE as u32))) } } #[doc = "Floating-point fused Multiply-Add Long to accumulator (by element)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlal_laneq_low_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fmlal, LANE = 0))] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] #[rustc_legacy_const_generics(3)] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vfmlal_laneq_low_f16( +pub fn vfmlal_laneq_low_f16( r: float32x2_t, a: float16x4_t, b: float16x8_t, ) -> float32x2_t { static_assert_uimm_bits!(LANE, 3); - vfmlal_low_f16(r, a, vdup_n_f16(simd_extract!(b, LANE as u32))) + unsafe { vfmlal_low_f16(r, a, vdup_n_f16(simd_extract!(b, LANE as u32))) } } #[doc = "Floating-point fused Multiply-Add Long to accumulator (by element)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlalq_lane_low_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fmlal, LANE = 0))] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] #[rustc_legacy_const_generics(3)] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vfmlalq_lane_low_f16( +pub fn vfmlalq_lane_low_f16( r: float32x4_t, a: float16x8_t, b: float16x4_t, ) -> float32x4_t { static_assert_uimm_bits!(LANE, 2); - vfmlalq_low_f16(r, a, vdupq_n_f16(simd_extract!(b, LANE as u32))) + unsafe { vfmlalq_low_f16(r, a, vdupq_n_f16(simd_extract!(b, LANE as u32))) } } #[doc = "Floating-point fused Multiply-Add Long to accumulator (by element)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlalq_laneq_low_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fmlal, LANE = 0))] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] #[rustc_legacy_const_generics(3)] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vfmlalq_laneq_low_f16( +pub fn vfmlalq_laneq_low_f16( r: float32x4_t, a: float16x8_t, b: float16x8_t, ) -> float32x4_t { static_assert_uimm_bits!(LANE, 3); - vfmlalq_low_f16(r, a, vdupq_n_f16(simd_extract!(b, LANE as u32))) + unsafe { vfmlalq_low_f16(r, a, vdupq_n_f16(simd_extract!(b, LANE as u32))) } } #[doc = "Floating-point fused Multiply-Add Long to accumulator (vector)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlal_low_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(fmlal))] -pub unsafe fn vfmlal_low_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float32x2_t { +pub fn vfmlal_low_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float32x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -11521,18 +10522,16 @@ pub unsafe fn vfmlal_low_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> )] fn _vfmlal_low_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float32x2_t; } - _vfmlal_low_f16(r, a, b) + unsafe { _vfmlal_low_f16(r, a, b) } } #[doc = "Floating-point fused Multiply-Add Long to accumulator (vector)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlalq_low_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(fmlal))] -pub unsafe fn vfmlalq_low_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float32x4_t { +pub fn vfmlalq_low_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -11540,18 +10539,16 @@ pub unsafe fn vfmlalq_low_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> )] fn _vfmlalq_low_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float32x4_t; } - _vfmlalq_low_f16(r, a, b) + unsafe { _vfmlalq_low_f16(r, a, b) } } #[doc = "Floating-point fused Multiply-Subtract Long from accumulator (vector)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlsl_high_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(fmlsl2))] -pub unsafe fn vfmlsl_high_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float32x2_t { +pub fn vfmlsl_high_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float32x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -11559,18 +10556,16 @@ pub unsafe fn vfmlsl_high_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> )] fn _vfmlsl_high_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float32x2_t; } - _vfmlsl_high_f16(r, a, b) + unsafe { _vfmlsl_high_f16(r, a, b) } } #[doc = "Floating-point fused Multiply-Subtract Long from accumulator (vector)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlslq_high_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(fmlsl2))] -pub unsafe fn vfmlslq_high_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float32x4_t { +pub fn vfmlslq_high_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -11578,162 +10573,144 @@ pub unsafe fn vfmlslq_high_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) - )] fn _vfmlslq_high_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float32x4_t; } - _vfmlslq_high_f16(r, a, b) + unsafe { _vfmlslq_high_f16(r, a, b) } } #[doc = "Floating-point fused Multiply-Subtract Long from accumulator (by element)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlsl_lane_high_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fmlsl2, LANE = 0))] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] #[rustc_legacy_const_generics(3)] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vfmlsl_lane_high_f16( +pub fn vfmlsl_lane_high_f16( r: float32x2_t, a: float16x4_t, b: float16x4_t, ) -> float32x2_t { static_assert_uimm_bits!(LANE, 2); - vfmlsl_high_f16(r, a, vdup_n_f16(simd_extract!(b, LANE as u32))) + unsafe { vfmlsl_high_f16(r, a, vdup_n_f16(simd_extract!(b, LANE as u32))) } } #[doc = "Floating-point fused Multiply-Subtract Long from accumulator (by element)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlsl_laneq_high_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fmlsl2, LANE = 0))] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] #[rustc_legacy_const_generics(3)] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vfmlsl_laneq_high_f16( +pub fn vfmlsl_laneq_high_f16( r: float32x2_t, a: float16x4_t, b: float16x8_t, ) -> float32x2_t { static_assert_uimm_bits!(LANE, 3); - vfmlsl_high_f16(r, a, vdup_n_f16(simd_extract!(b, LANE as u32))) + unsafe { vfmlsl_high_f16(r, a, vdup_n_f16(simd_extract!(b, LANE as u32))) } } #[doc = "Floating-point fused Multiply-Subtract Long from accumulator (by element)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlslq_lane_high_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fmlsl2, LANE = 0))] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] #[rustc_legacy_const_generics(3)] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vfmlslq_lane_high_f16( +pub fn vfmlslq_lane_high_f16( r: float32x4_t, a: float16x8_t, b: float16x4_t, ) -> float32x4_t { static_assert_uimm_bits!(LANE, 2); - vfmlslq_high_f16(r, a, vdupq_n_f16(simd_extract!(b, LANE as u32))) + unsafe { vfmlslq_high_f16(r, a, vdupq_n_f16(simd_extract!(b, LANE as u32))) } } #[doc = "Floating-point fused Multiply-Subtract Long from accumulator (by element)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlslq_laneq_high_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fmlsl2, LANE = 0))] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] #[rustc_legacy_const_generics(3)] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vfmlslq_laneq_high_f16( +pub fn vfmlslq_laneq_high_f16( r: float32x4_t, a: float16x8_t, b: float16x8_t, ) -> float32x4_t { static_assert_uimm_bits!(LANE, 3); - vfmlslq_high_f16(r, a, vdupq_n_f16(simd_extract!(b, LANE as u32))) + unsafe { vfmlslq_high_f16(r, a, vdupq_n_f16(simd_extract!(b, LANE as u32))) } } #[doc = "Floating-point fused Multiply-Subtract Long from accumulator (by element)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlsl_lane_low_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fmlsl, LANE = 0))] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] #[rustc_legacy_const_generics(3)] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vfmlsl_lane_low_f16( +pub fn vfmlsl_lane_low_f16( r: float32x2_t, a: float16x4_t, b: float16x4_t, ) -> float32x2_t { static_assert_uimm_bits!(LANE, 2); - vfmlsl_low_f16(r, a, vdup_n_f16(simd_extract!(b, LANE as u32))) + unsafe { vfmlsl_low_f16(r, a, vdup_n_f16(simd_extract!(b, LANE as u32))) } } #[doc = "Floating-point fused Multiply-Subtract Long from accumulator (by element)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlsl_laneq_low_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fmlsl, LANE = 0))] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] #[rustc_legacy_const_generics(3)] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vfmlsl_laneq_low_f16( +pub fn vfmlsl_laneq_low_f16( r: float32x2_t, a: float16x4_t, b: float16x8_t, ) -> float32x2_t { static_assert_uimm_bits!(LANE, 3); - vfmlsl_low_f16(r, a, vdup_n_f16(simd_extract!(b, LANE as u32))) + unsafe { vfmlsl_low_f16(r, a, vdup_n_f16(simd_extract!(b, LANE as u32))) } } #[doc = "Floating-point fused Multiply-Subtract Long from accumulator (by element)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlslq_lane_low_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fmlsl, LANE = 0))] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] #[rustc_legacy_const_generics(3)] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vfmlslq_lane_low_f16( +pub fn vfmlslq_lane_low_f16( r: float32x4_t, a: float16x8_t, b: float16x4_t, ) -> float32x4_t { static_assert_uimm_bits!(LANE, 2); - vfmlslq_low_f16(r, a, vdupq_n_f16(simd_extract!(b, LANE as u32))) + unsafe { vfmlslq_low_f16(r, a, vdupq_n_f16(simd_extract!(b, LANE as u32))) } } #[doc = "Floating-point fused Multiply-Subtract Long from accumulator (by element)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlslq_laneq_low_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fmlsl, LANE = 0))] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] #[rustc_legacy_const_generics(3)] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vfmlslq_laneq_low_f16( +pub fn vfmlslq_laneq_low_f16( r: float32x4_t, a: float16x8_t, b: float16x8_t, ) -> float32x4_t { static_assert_uimm_bits!(LANE, 3); - vfmlslq_low_f16(r, a, vdupq_n_f16(simd_extract!(b, LANE as u32))) + unsafe { vfmlslq_low_f16(r, a, vdupq_n_f16(simd_extract!(b, LANE as u32))) } } #[doc = "Floating-point fused Multiply-Subtract Long from accumulator (vector)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlsl_low_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(fmlsl))] -pub unsafe fn vfmlsl_low_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float32x2_t { +pub fn vfmlsl_low_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float32x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -11741,18 +10718,16 @@ pub unsafe fn vfmlsl_low_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> )] fn _vfmlsl_low_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float32x2_t; } - _vfmlsl_low_f16(r, a, b) + unsafe { _vfmlsl_low_f16(r, a, b) } } #[doc = "Floating-point fused Multiply-Subtract Long from accumulator (vector)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlslq_low_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(fmlsl))] -pub unsafe fn vfmlslq_low_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float32x4_t { +pub fn vfmlslq_low_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -11760,365 +10735,323 @@ pub unsafe fn vfmlslq_low_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> )] fn _vfmlslq_low_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float32x4_t; } - _vfmlslq_low_f16(r, a, b) + unsafe { _vfmlslq_low_f16(r, a, b) } } #[doc = "Floating-point fused multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmsub))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vfms_f64(a: float64x1_t, b: float64x1_t, c: float64x1_t) -> float64x1_t { - let b: float64x1_t = simd_neg(b); - vfma_f64(a, b, c) +pub fn vfms_f64(a: float64x1_t, b: float64x1_t, c: float64x1_t) -> float64x1_t { + unsafe { + let b: float64x1_t = simd_neg(b); + vfma_f64(a, b, c) + } } #[doc = "Floating-point fused multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_lane_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fmls, LANE = 0))] #[rustc_legacy_const_generics(3)] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vfms_lane_f16( +pub fn vfms_lane_f16( a: float16x4_t, b: float16x4_t, c: float16x4_t, ) -> float16x4_t { static_assert_uimm_bits!(LANE, 2); - vfms_f16(a, b, vdup_n_f16(simd_extract!(c, LANE as u32))) + unsafe { vfms_f16(a, b, vdup_n_f16(simd_extract!(c, LANE as u32))) } } #[doc = "Floating-point fused multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_laneq_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fmls, LANE = 0))] #[rustc_legacy_const_generics(3)] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vfms_laneq_f16( +pub fn vfms_laneq_f16( a: float16x4_t, b: float16x4_t, c: float16x8_t, ) -> float16x4_t { static_assert_uimm_bits!(LANE, 3); - vfms_f16(a, b, vdup_n_f16(simd_extract!(c, LANE as u32))) + unsafe { vfms_f16(a, b, vdup_n_f16(simd_extract!(c, LANE as u32))) } } #[doc = "Floating-point fused multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_lane_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fmls, LANE = 0))] #[rustc_legacy_const_generics(3)] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vfmsq_lane_f16( +pub fn vfmsq_lane_f16( a: float16x8_t, b: float16x8_t, c: float16x4_t, ) -> float16x8_t { static_assert_uimm_bits!(LANE, 2); - vfmsq_f16(a, b, vdupq_n_f16(simd_extract!(c, LANE as u32))) + unsafe { vfmsq_f16(a, b, vdupq_n_f16(simd_extract!(c, LANE as u32))) } } #[doc = "Floating-point fused multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_laneq_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fmls, LANE = 0))] #[rustc_legacy_const_generics(3)] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vfmsq_laneq_f16( +pub fn vfmsq_laneq_f16( a: float16x8_t, b: float16x8_t, c: float16x8_t, ) -> float16x8_t { static_assert_uimm_bits!(LANE, 3); - vfmsq_f16(a, b, vdupq_n_f16(simd_extract!(c, LANE as u32))) + unsafe { vfmsq_f16(a, b, vdupq_n_f16(simd_extract!(c, LANE as u32))) } } #[doc = "Floating-point fused multiply-subtract to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_lane_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmls, LANE = 0))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vfms_lane_f32( +pub fn vfms_lane_f32( a: float32x2_t, b: float32x2_t, c: float32x2_t, ) -> float32x2_t { static_assert_uimm_bits!(LANE, 1); - vfms_f32(a, b, vdup_n_f32(simd_extract!(c, LANE as u32))) + unsafe { vfms_f32(a, b, vdup_n_f32(simd_extract!(c, LANE as u32))) } } #[doc = "Floating-point fused multiply-subtract to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_laneq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmls, LANE = 0))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vfms_laneq_f32( +pub fn vfms_laneq_f32( a: float32x2_t, b: float32x2_t, c: float32x4_t, ) -> float32x2_t { static_assert_uimm_bits!(LANE, 2); - vfms_f32(a, b, vdup_n_f32(simd_extract!(c, LANE as u32))) + unsafe { vfms_f32(a, b, vdup_n_f32(simd_extract!(c, LANE as u32))) } } #[doc = "Floating-point fused multiply-subtract to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_lane_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmls, LANE = 0))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vfmsq_lane_f32( +pub fn vfmsq_lane_f32( a: float32x4_t, b: float32x4_t, c: float32x2_t, ) -> float32x4_t { static_assert_uimm_bits!(LANE, 1); - vfmsq_f32(a, b, vdupq_n_f32(simd_extract!(c, LANE as u32))) + unsafe { vfmsq_f32(a, b, vdupq_n_f32(simd_extract!(c, LANE as u32))) } } #[doc = "Floating-point fused multiply-subtract to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_laneq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmls, LANE = 0))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vfmsq_laneq_f32( +pub fn vfmsq_laneq_f32( a: float32x4_t, b: float32x4_t, c: float32x4_t, ) -> float32x4_t { static_assert_uimm_bits!(LANE, 2); - vfmsq_f32(a, b, vdupq_n_f32(simd_extract!(c, LANE as u32))) + unsafe { vfmsq_f32(a, b, vdupq_n_f32(simd_extract!(c, LANE as u32))) } } #[doc = "Floating-point fused multiply-subtract to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_laneq_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmls, LANE = 0))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vfmsq_laneq_f64( +pub fn vfmsq_laneq_f64( a: float64x2_t, b: float64x2_t, c: float64x2_t, ) -> float64x2_t { static_assert_uimm_bits!(LANE, 1); - vfmsq_f64(a, b, vdupq_n_f64(simd_extract!(c, LANE as u32))) + unsafe { vfmsq_f64(a, b, vdupq_n_f64(simd_extract!(c, LANE as u32))) } } #[doc = "Floating-point fused multiply-subtract to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_lane_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmsub, LANE = 0))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vfms_lane_f64( +pub fn vfms_lane_f64( a: float64x1_t, b: float64x1_t, c: float64x1_t, ) -> float64x1_t { static_assert!(LANE == 0); - vfms_f64(a, b, vdup_n_f64(simd_extract!(c, LANE as u32))) + unsafe { vfms_f64(a, b, vdup_n_f64(simd_extract!(c, LANE as u32))) } } #[doc = "Floating-point fused multiply-subtract to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_laneq_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmsub, LANE = 0))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vfms_laneq_f64( +pub fn vfms_laneq_f64( a: float64x1_t, b: float64x1_t, c: float64x2_t, ) -> float64x1_t { static_assert_uimm_bits!(LANE, 1); - vfms_f64(a, b, vdup_n_f64(simd_extract!(c, LANE as u32))) + unsafe { vfms_f64(a, b, vdup_n_f64(simd_extract!(c, LANE as u32))) } } #[doc = "Floating-point fused Multiply-Subtract from accumulator."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_n_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(fmls))] -pub unsafe fn vfms_n_f16(a: float16x4_t, b: float16x4_t, c: f16) -> float16x4_t { +pub fn vfms_n_f16(a: float16x4_t, b: float16x4_t, c: f16) -> float16x4_t { vfms_f16(a, b, vdup_n_f16(c)) } #[doc = "Floating-point fused Multiply-Subtract from accumulator."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_n_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(fmls))] -pub unsafe fn vfmsq_n_f16(a: float16x8_t, b: float16x8_t, c: f16) -> float16x8_t { +pub fn vfmsq_n_f16(a: float16x8_t, b: float16x8_t, c: f16) -> float16x8_t { vfmsq_f16(a, b, vdupq_n_f16(c)) } #[doc = "Floating-point fused Multiply-subtract to accumulator(vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_n_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmsub))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vfms_n_f64(a: float64x1_t, b: float64x1_t, c: f64) -> float64x1_t { +pub fn vfms_n_f64(a: float64x1_t, b: float64x1_t, c: f64) -> float64x1_t { vfms_f64(a, b, vdup_n_f64(c)) } #[doc = "Floating-point fused multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsh_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fmsub))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vfmsh_f16(a: f16, b: f16, c: f16) -> f16 { +pub fn vfmsh_f16(a: f16, b: f16, c: f16) -> f16 { vfmah_f16(a, -b, c) } #[doc = "Floating-point fused multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsh_lane_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fmsub, LANE = 0))] #[rustc_legacy_const_generics(3)] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vfmsh_lane_f16(a: f16, b: f16, v: float16x4_t) -> f16 { +pub fn vfmsh_lane_f16(a: f16, b: f16, v: float16x4_t) -> f16 { static_assert_uimm_bits!(LANE, 2); - let c: f16 = simd_extract!(v, LANE as u32); - vfmsh_f16(a, b, c) + unsafe { + let c: f16 = simd_extract!(v, LANE as u32); + vfmsh_f16(a, b, c) + } } #[doc = "Floating-point fused multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsh_laneq_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fmsub, LANE = 0))] #[rustc_legacy_const_generics(3)] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vfmsh_laneq_f16(a: f16, b: f16, v: float16x8_t) -> f16 { +pub fn vfmsh_laneq_f16(a: f16, b: f16, v: float16x8_t) -> f16 { static_assert_uimm_bits!(LANE, 3); - let c: f16 = simd_extract!(v, LANE as u32); - vfmsh_f16(a, b, c) + unsafe { + let c: f16 = simd_extract!(v, LANE as u32); + vfmsh_f16(a, b, c) + } } #[doc = "Floating-point fused multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmls))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vfmsq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t { - let b: float64x2_t = simd_neg(b); - vfmaq_f64(a, b, c) +pub fn vfmsq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t { + unsafe { + let b: float64x2_t = simd_neg(b); + vfmaq_f64(a, b, c) + } } #[doc = "Floating-point fused multiply-subtract to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_lane_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmls, LANE = 0))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vfmsq_lane_f64( +pub fn vfmsq_lane_f64( a: float64x2_t, b: float64x2_t, c: float64x1_t, ) -> float64x2_t { static_assert!(LANE == 0); - vfmsq_f64(a, b, vdupq_n_f64(simd_extract!(c, LANE as u32))) + unsafe { vfmsq_f64(a, b, vdupq_n_f64(simd_extract!(c, LANE as u32))) } } #[doc = "Floating-point fused Multiply-subtract to accumulator(vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_n_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmls))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vfmsq_n_f64(a: float64x2_t, b: float64x2_t, c: f64) -> float64x2_t { +pub fn vfmsq_n_f64(a: float64x2_t, b: float64x2_t, c: f64) -> float64x2_t { vfmsq_f64(a, b, vdupq_n_f64(c)) } #[doc = "Floating-point fused multiply-subtract to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmss_lane_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmsub, LANE = 0))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vfmss_lane_f32(a: f32, b: f32, c: float32x2_t) -> f32 { +pub fn vfmss_lane_f32(a: f32, b: f32, c: float32x2_t) -> f32 { vfmas_lane_f32::(a, -b, c) } #[doc = "Floating-point fused multiply-subtract to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmss_laneq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmsub, LANE = 0))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vfmss_laneq_f32(a: f32, b: f32, c: float32x4_t) -> f32 { +pub fn vfmss_laneq_f32(a: f32, b: f32, c: float32x4_t) -> f32 { vfmas_laneq_f32::(a, -b, c) } #[doc = "Floating-point fused multiply-subtract to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsd_lane_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmsub, LANE = 0))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vfmsd_lane_f64(a: f64, b: f64, c: float64x1_t) -> f64 { +pub fn vfmsd_lane_f64(a: f64, b: f64, c: float64x1_t) -> f64 { vfmad_lane_f64::(a, -b, c) } #[doc = "Floating-point fused multiply-subtract to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsd_laneq_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmsub, LANE = 0))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vfmsd_laneq_f64(a: f64, b: f64, c: float64x2_t) -> f64 { +pub fn vfmsd_laneq_f64(a: f64, b: f64, c: float64x2_t) -> f64 { vfmad_laneq_f64::(a, -b, c) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] @@ -13799,13 +12732,11 @@ pub unsafe fn vld4q_u64(a: *const u64) -> uint64x2x4_t { } #[doc = "Maximum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmax))] -pub unsafe fn vmax_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { +pub fn vmax_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -13813,17 +12744,15 @@ pub unsafe fn vmax_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { )] fn _vmax_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t; } - _vmax_f64(a, b) + unsafe { _vmax_f64(a, b) } } #[doc = "Maximum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmax))] -pub unsafe fn vmaxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { +pub fn vmaxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -13831,17 +12760,15 @@ pub unsafe fn vmaxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { )] fn _vmaxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t; } - _vmaxq_f64(a, b) + unsafe { _vmaxq_f64(a, b) } } #[doc = "Maximum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxh_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(fmax))] -pub unsafe fn vmaxh_f16(a: f16, b: f16) -> f16 { +pub fn vmaxh_f16(a: f16, b: f16) -> f16 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -13849,17 +12776,15 @@ pub unsafe fn vmaxh_f16(a: f16, b: f16) -> f16 { )] fn _vmaxh_f16(a: f16, b: f16) -> f16; } - _vmaxh_f16(a, b) + unsafe { _vmaxh_f16(a, b) } } #[doc = "Floating-point Maximum Number (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnm_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmaxnm))] -pub unsafe fn vmaxnm_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { +pub fn vmaxnm_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -13867,17 +12792,15 @@ pub unsafe fn vmaxnm_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { )] fn _vmaxnm_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t; } - _vmaxnm_f64(a, b) + unsafe { _vmaxnm_f64(a, b) } } #[doc = "Floating-point Maximum Number (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmq_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmaxnm))] -pub unsafe fn vmaxnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { +pub fn vmaxnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -13885,17 +12808,15 @@ pub unsafe fn vmaxnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { )] fn _vmaxnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t; } - _vmaxnmq_f64(a, b) + unsafe { _vmaxnmq_f64(a, b) } } #[doc = "Floating-point Maximum Number"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmh_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(fmaxnm))] -pub unsafe fn vmaxnmh_f16(a: f16, b: f16) -> f16 { +pub fn vmaxnmh_f16(a: f16, b: f16) -> f16 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -13903,17 +12824,15 @@ pub unsafe fn vmaxnmh_f16(a: f16, b: f16) -> f16 { )] fn _vmaxnmh_f16(a: f16, b: f16) -> f16; } - _vmaxnmh_f16(a, b) + unsafe { _vmaxnmh_f16(a, b) } } #[doc = "Floating-point maximum number across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmv_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(fmaxnmv))] -pub unsafe fn vmaxnmv_f16(a: float16x4_t) -> f16 { +pub fn vmaxnmv_f16(a: float16x4_t) -> f16 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -13921,17 +12840,15 @@ pub unsafe fn vmaxnmv_f16(a: float16x4_t) -> f16 { )] fn _vmaxnmv_f16(a: float16x4_t) -> f16; } - _vmaxnmv_f16(a) + unsafe { _vmaxnmv_f16(a) } } #[doc = "Floating-point maximum number across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmvq_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(fmaxnmv))] -pub unsafe fn vmaxnmvq_f16(a: float16x8_t) -> f16 { +pub fn vmaxnmvq_f16(a: float16x8_t) -> f16 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -13939,17 +12856,15 @@ pub unsafe fn vmaxnmvq_f16(a: float16x8_t) -> f16 { )] fn _vmaxnmvq_f16(a: float16x8_t) -> f16; } - _vmaxnmvq_f16(a) + unsafe { _vmaxnmvq_f16(a) } } #[doc = "Floating-point maximum number across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmv_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmaxnmp))] -pub unsafe fn vmaxnmv_f32(a: float32x2_t) -> f32 { +pub fn vmaxnmv_f32(a: float32x2_t) -> f32 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -13957,17 +12872,15 @@ pub unsafe fn vmaxnmv_f32(a: float32x2_t) -> f32 { )] fn _vmaxnmv_f32(a: float32x2_t) -> f32; } - _vmaxnmv_f32(a) + unsafe { _vmaxnmv_f32(a) } } #[doc = "Floating-point maximum number across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmvq_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmaxnmp))] -pub unsafe fn vmaxnmvq_f64(a: float64x2_t) -> f64 { +pub fn vmaxnmvq_f64(a: float64x2_t) -> f64 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -13975,17 +12888,15 @@ pub unsafe fn vmaxnmvq_f64(a: float64x2_t) -> f64 { )] fn _vmaxnmvq_f64(a: float64x2_t) -> f64; } - _vmaxnmvq_f64(a) + unsafe { _vmaxnmvq_f64(a) } } #[doc = "Floating-point maximum number across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmvq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmaxnmv))] -pub unsafe fn vmaxnmvq_f32(a: float32x4_t) -> f32 { +pub fn vmaxnmvq_f32(a: float32x4_t) -> f32 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -13993,17 +12904,15 @@ pub unsafe fn vmaxnmvq_f32(a: float32x4_t) -> f32 { )] fn _vmaxnmvq_f32(a: float32x4_t) -> f32; } - _vmaxnmvq_f32(a) + unsafe { _vmaxnmvq_f32(a) } } #[doc = "Floating-point maximum number across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(fmaxv))] -pub unsafe fn vmaxv_f16(a: float16x4_t) -> f16 { +pub fn vmaxv_f16(a: float16x4_t) -> f16 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -14011,17 +12920,15 @@ pub unsafe fn vmaxv_f16(a: float16x4_t) -> f16 { )] fn _vmaxv_f16(a: float16x4_t) -> f16; } - _vmaxv_f16(a) + unsafe { _vmaxv_f16(a) } } #[doc = "Floating-point maximum number across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(fmaxv))] -pub unsafe fn vmaxvq_f16(a: float16x8_t) -> f16 { +pub fn vmaxvq_f16(a: float16x8_t) -> f16 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -14029,17 +12936,15 @@ pub unsafe fn vmaxvq_f16(a: float16x8_t) -> f16 { )] fn _vmaxvq_f16(a: float16x8_t) -> f16; } - _vmaxvq_f16(a) + unsafe { _vmaxvq_f16(a) } } #[doc = "Horizontal vector max."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmaxp))] -pub unsafe fn vmaxv_f32(a: float32x2_t) -> f32 { +pub fn vmaxv_f32(a: float32x2_t) -> f32 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -14047,17 +12952,15 @@ pub unsafe fn vmaxv_f32(a: float32x2_t) -> f32 { )] fn _vmaxv_f32(a: float32x2_t) -> f32; } - _vmaxv_f32(a) + unsafe { _vmaxv_f32(a) } } #[doc = "Horizontal vector max."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmaxv))] -pub unsafe fn vmaxvq_f32(a: float32x4_t) -> f32 { +pub fn vmaxvq_f32(a: float32x4_t) -> f32 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -14065,17 +12968,15 @@ pub unsafe fn vmaxvq_f32(a: float32x4_t) -> f32 { )] fn _vmaxvq_f32(a: float32x4_t) -> f32; } - _vmaxvq_f32(a) + unsafe { _vmaxvq_f32(a) } } #[doc = "Horizontal vector max."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmaxp))] -pub unsafe fn vmaxvq_f64(a: float64x2_t) -> f64 { +pub fn vmaxvq_f64(a: float64x2_t) -> f64 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -14083,17 +12984,15 @@ pub unsafe fn vmaxvq_f64(a: float64x2_t) -> f64 { )] fn _vmaxvq_f64(a: float64x2_t) -> f64; } - _vmaxvq_f64(a) + unsafe { _vmaxvq_f64(a) } } #[doc = "Horizontal vector max."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(smaxv))] -pub unsafe fn vmaxv_s8(a: int8x8_t) -> i8 { +pub fn vmaxv_s8(a: int8x8_t) -> i8 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -14101,17 +13000,15 @@ pub unsafe fn vmaxv_s8(a: int8x8_t) -> i8 { )] fn _vmaxv_s8(a: int8x8_t) -> i8; } - _vmaxv_s8(a) + unsafe { _vmaxv_s8(a) } } #[doc = "Horizontal vector max."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(smaxv))] -pub unsafe fn vmaxvq_s8(a: int8x16_t) -> i8 { +pub fn vmaxvq_s8(a: int8x16_t) -> i8 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -14119,17 +13016,15 @@ pub unsafe fn vmaxvq_s8(a: int8x16_t) -> i8 { )] fn _vmaxvq_s8(a: int8x16_t) -> i8; } - _vmaxvq_s8(a) + unsafe { _vmaxvq_s8(a) } } #[doc = "Horizontal vector max."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(smaxv))] -pub unsafe fn vmaxv_s16(a: int16x4_t) -> i16 { +pub fn vmaxv_s16(a: int16x4_t) -> i16 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -14137,17 +13032,15 @@ pub unsafe fn vmaxv_s16(a: int16x4_t) -> i16 { )] fn _vmaxv_s16(a: int16x4_t) -> i16; } - _vmaxv_s16(a) + unsafe { _vmaxv_s16(a) } } #[doc = "Horizontal vector max."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(smaxv))] -pub unsafe fn vmaxvq_s16(a: int16x8_t) -> i16 { +pub fn vmaxvq_s16(a: int16x8_t) -> i16 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -14155,17 +13048,15 @@ pub unsafe fn vmaxvq_s16(a: int16x8_t) -> i16 { )] fn _vmaxvq_s16(a: int16x8_t) -> i16; } - _vmaxvq_s16(a) + unsafe { _vmaxvq_s16(a) } } #[doc = "Horizontal vector max."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(smaxp))] -pub unsafe fn vmaxv_s32(a: int32x2_t) -> i32 { +pub fn vmaxv_s32(a: int32x2_t) -> i32 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -14173,17 +13064,15 @@ pub unsafe fn vmaxv_s32(a: int32x2_t) -> i32 { )] fn _vmaxv_s32(a: int32x2_t) -> i32; } - _vmaxv_s32(a) + unsafe { _vmaxv_s32(a) } } #[doc = "Horizontal vector max."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(smaxv))] -pub unsafe fn vmaxvq_s32(a: int32x4_t) -> i32 { +pub fn vmaxvq_s32(a: int32x4_t) -> i32 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -14191,17 +13080,15 @@ pub unsafe fn vmaxvq_s32(a: int32x4_t) -> i32 { )] fn _vmaxvq_s32(a: int32x4_t) -> i32; } - _vmaxvq_s32(a) + unsafe { _vmaxvq_s32(a) } } #[doc = "Horizontal vector max."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(umaxv))] -pub unsafe fn vmaxv_u8(a: uint8x8_t) -> u8 { +pub fn vmaxv_u8(a: uint8x8_t) -> u8 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -14209,17 +13096,15 @@ pub unsafe fn vmaxv_u8(a: uint8x8_t) -> u8 { )] fn _vmaxv_u8(a: uint8x8_t) -> u8; } - _vmaxv_u8(a) + unsafe { _vmaxv_u8(a) } } #[doc = "Horizontal vector max."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(umaxv))] -pub unsafe fn vmaxvq_u8(a: uint8x16_t) -> u8 { +pub fn vmaxvq_u8(a: uint8x16_t) -> u8 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -14227,17 +13112,15 @@ pub unsafe fn vmaxvq_u8(a: uint8x16_t) -> u8 { )] fn _vmaxvq_u8(a: uint8x16_t) -> u8; } - _vmaxvq_u8(a) + unsafe { _vmaxvq_u8(a) } } #[doc = "Horizontal vector max."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(umaxv))] -pub unsafe fn vmaxv_u16(a: uint16x4_t) -> u16 { +pub fn vmaxv_u16(a: uint16x4_t) -> u16 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -14245,17 +13128,15 @@ pub unsafe fn vmaxv_u16(a: uint16x4_t) -> u16 { )] fn _vmaxv_u16(a: uint16x4_t) -> u16; } - _vmaxv_u16(a) + unsafe { _vmaxv_u16(a) } } #[doc = "Horizontal vector max."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(umaxv))] -pub unsafe fn vmaxvq_u16(a: uint16x8_t) -> u16 { +pub fn vmaxvq_u16(a: uint16x8_t) -> u16 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -14263,17 +13144,15 @@ pub unsafe fn vmaxvq_u16(a: uint16x8_t) -> u16 { )] fn _vmaxvq_u16(a: uint16x8_t) -> u16; } - _vmaxvq_u16(a) + unsafe { _vmaxvq_u16(a) } } #[doc = "Horizontal vector max."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(umaxp))] -pub unsafe fn vmaxv_u32(a: uint32x2_t) -> u32 { +pub fn vmaxv_u32(a: uint32x2_t) -> u32 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -14281,17 +13160,15 @@ pub unsafe fn vmaxv_u32(a: uint32x2_t) -> u32 { )] fn _vmaxv_u32(a: uint32x2_t) -> u32; } - _vmaxv_u32(a) + unsafe { _vmaxv_u32(a) } } #[doc = "Horizontal vector max."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(umaxv))] -pub unsafe fn vmaxvq_u32(a: uint32x4_t) -> u32 { +pub fn vmaxvq_u32(a: uint32x4_t) -> u32 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -14299,17 +13176,15 @@ pub unsafe fn vmaxvq_u32(a: uint32x4_t) -> u32 { )] fn _vmaxvq_u32(a: uint32x4_t) -> u32; } - _vmaxvq_u32(a) + unsafe { _vmaxvq_u32(a) } } #[doc = "Minimum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmin))] -pub unsafe fn vmin_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { +pub fn vmin_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -14317,17 +13192,15 @@ pub unsafe fn vmin_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { )] fn _vmin_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t; } - _vmin_f64(a, b) + unsafe { _vmin_f64(a, b) } } #[doc = "Minimum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmin))] -pub unsafe fn vminq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { +pub fn vminq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -14335,17 +13208,15 @@ pub unsafe fn vminq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { )] fn _vminq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t; } - _vminq_f64(a, b) + unsafe { _vminq_f64(a, b) } } #[doc = "Minimum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminh_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(fmin))] -pub unsafe fn vminh_f16(a: f16, b: f16) -> f16 { +pub fn vminh_f16(a: f16, b: f16) -> f16 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -14353,17 +13224,15 @@ pub unsafe fn vminh_f16(a: f16, b: f16) -> f16 { )] fn _vminh_f16(a: f16, b: f16) -> f16; } - _vminh_f16(a, b) + unsafe { _vminh_f16(a, b) } } #[doc = "Floating-point Minimum Number (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnm_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fminnm))] -pub unsafe fn vminnm_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { +pub fn vminnm_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -14371,17 +13240,15 @@ pub unsafe fn vminnm_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { )] fn _vminnm_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t; } - _vminnm_f64(a, b) + unsafe { _vminnm_f64(a, b) } } #[doc = "Floating-point Minimum Number (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmq_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fminnm))] -pub unsafe fn vminnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { +pub fn vminnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -14389,17 +13256,15 @@ pub unsafe fn vminnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { )] fn _vminnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t; } - _vminnmq_f64(a, b) + unsafe { _vminnmq_f64(a, b) } } #[doc = "Floating-point Minimum Number"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmh_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(fminnm))] -pub unsafe fn vminnmh_f16(a: f16, b: f16) -> f16 { +pub fn vminnmh_f16(a: f16, b: f16) -> f16 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -14407,17 +13272,15 @@ pub unsafe fn vminnmh_f16(a: f16, b: f16) -> f16 { )] fn _vminnmh_f16(a: f16, b: f16) -> f16; } - _vminnmh_f16(a, b) + unsafe { _vminnmh_f16(a, b) } } #[doc = "Floating-point minimum number across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmv_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(fminnmv))] -pub unsafe fn vminnmv_f16(a: float16x4_t) -> f16 { +pub fn vminnmv_f16(a: float16x4_t) -> f16 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -14425,17 +13288,15 @@ pub unsafe fn vminnmv_f16(a: float16x4_t) -> f16 { )] fn _vminnmv_f16(a: float16x4_t) -> f16; } - _vminnmv_f16(a) + unsafe { _vminnmv_f16(a) } } #[doc = "Floating-point minimum number across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmvq_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(fminnmv))] -pub unsafe fn vminnmvq_f16(a: float16x8_t) -> f16 { +pub fn vminnmvq_f16(a: float16x8_t) -> f16 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -14443,17 +13304,15 @@ pub unsafe fn vminnmvq_f16(a: float16x8_t) -> f16 { )] fn _vminnmvq_f16(a: float16x8_t) -> f16; } - _vminnmvq_f16(a) + unsafe { _vminnmvq_f16(a) } } #[doc = "Floating-point minimum number across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmv_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fminnmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vminnmv_f32(a: float32x2_t) -> f32 { +pub fn vminnmv_f32(a: float32x2_t) -> f32 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -14461,17 +13320,15 @@ pub unsafe fn vminnmv_f32(a: float32x2_t) -> f32 { )] fn _vminnmv_f32(a: float32x2_t) -> f32; } - _vminnmv_f32(a) + unsafe { _vminnmv_f32(a) } } #[doc = "Floating-point minimum number across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmvq_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fminnmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vminnmvq_f64(a: float64x2_t) -> f64 { +pub fn vminnmvq_f64(a: float64x2_t) -> f64 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -14479,17 +13336,15 @@ pub unsafe fn vminnmvq_f64(a: float64x2_t) -> f64 { )] fn _vminnmvq_f64(a: float64x2_t) -> f64; } - _vminnmvq_f64(a) + unsafe { _vminnmvq_f64(a) } } #[doc = "Floating-point minimum number across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmvq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fminnmv))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vminnmvq_f32(a: float32x4_t) -> f32 { +pub fn vminnmvq_f32(a: float32x4_t) -> f32 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -14497,17 +13352,15 @@ pub unsafe fn vminnmvq_f32(a: float32x4_t) -> f32 { )] fn _vminnmvq_f32(a: float32x4_t) -> f32; } - _vminnmvq_f32(a) + unsafe { _vminnmvq_f32(a) } } #[doc = "Floating-point minimum number across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(fminv))] -pub unsafe fn vminv_f16(a: float16x4_t) -> f16 { +pub fn vminv_f16(a: float16x4_t) -> f16 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -14515,17 +13368,15 @@ pub unsafe fn vminv_f16(a: float16x4_t) -> f16 { )] fn _vminv_f16(a: float16x4_t) -> f16; } - _vminv_f16(a) + unsafe { _vminv_f16(a) } } #[doc = "Floating-point minimum number across vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(fminv))] -pub unsafe fn vminvq_f16(a: float16x8_t) -> f16 { +pub fn vminvq_f16(a: float16x8_t) -> f16 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -14533,17 +13384,15 @@ pub unsafe fn vminvq_f16(a: float16x8_t) -> f16 { )] fn _vminvq_f16(a: float16x8_t) -> f16; } - _vminvq_f16(a) + unsafe { _vminvq_f16(a) } } #[doc = "Horizontal vector min."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fminp))] -pub unsafe fn vminv_f32(a: float32x2_t) -> f32 { +pub fn vminv_f32(a: float32x2_t) -> f32 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -14551,17 +13400,15 @@ pub unsafe fn vminv_f32(a: float32x2_t) -> f32 { )] fn _vminv_f32(a: float32x2_t) -> f32; } - _vminv_f32(a) + unsafe { _vminv_f32(a) } } #[doc = "Horizontal vector min."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fminv))] -pub unsafe fn vminvq_f32(a: float32x4_t) -> f32 { +pub fn vminvq_f32(a: float32x4_t) -> f32 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -14569,17 +13416,15 @@ pub unsafe fn vminvq_f32(a: float32x4_t) -> f32 { )] fn _vminvq_f32(a: float32x4_t) -> f32; } - _vminvq_f32(a) + unsafe { _vminvq_f32(a) } } #[doc = "Horizontal vector min."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fminp))] -pub unsafe fn vminvq_f64(a: float64x2_t) -> f64 { +pub fn vminvq_f64(a: float64x2_t) -> f64 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -14587,17 +13432,15 @@ pub unsafe fn vminvq_f64(a: float64x2_t) -> f64 { )] fn _vminvq_f64(a: float64x2_t) -> f64; } - _vminvq_f64(a) + unsafe { _vminvq_f64(a) } } #[doc = "Horizontal vector min."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(sminv))] -pub unsafe fn vminv_s8(a: int8x8_t) -> i8 { +pub fn vminv_s8(a: int8x8_t) -> i8 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -14605,17 +13448,15 @@ pub unsafe fn vminv_s8(a: int8x8_t) -> i8 { )] fn _vminv_s8(a: int8x8_t) -> i8; } - _vminv_s8(a) + unsafe { _vminv_s8(a) } } #[doc = "Horizontal vector min."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(sminv))] -pub unsafe fn vminvq_s8(a: int8x16_t) -> i8 { +pub fn vminvq_s8(a: int8x16_t) -> i8 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -14623,17 +13464,15 @@ pub unsafe fn vminvq_s8(a: int8x16_t) -> i8 { )] fn _vminvq_s8(a: int8x16_t) -> i8; } - _vminvq_s8(a) + unsafe { _vminvq_s8(a) } } #[doc = "Horizontal vector min."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(sminv))] -pub unsafe fn vminv_s16(a: int16x4_t) -> i16 { +pub fn vminv_s16(a: int16x4_t) -> i16 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -14641,17 +13480,15 @@ pub unsafe fn vminv_s16(a: int16x4_t) -> i16 { )] fn _vminv_s16(a: int16x4_t) -> i16; } - _vminv_s16(a) + unsafe { _vminv_s16(a) } } #[doc = "Horizontal vector min."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(sminv))] -pub unsafe fn vminvq_s16(a: int16x8_t) -> i16 { +pub fn vminvq_s16(a: int16x8_t) -> i16 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -14659,17 +13496,15 @@ pub unsafe fn vminvq_s16(a: int16x8_t) -> i16 { )] fn _vminvq_s16(a: int16x8_t) -> i16; } - _vminvq_s16(a) + unsafe { _vminvq_s16(a) } } #[doc = "Horizontal vector min."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(sminp))] -pub unsafe fn vminv_s32(a: int32x2_t) -> i32 { +pub fn vminv_s32(a: int32x2_t) -> i32 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -14677,17 +13512,15 @@ pub unsafe fn vminv_s32(a: int32x2_t) -> i32 { )] fn _vminv_s32(a: int32x2_t) -> i32; } - _vminv_s32(a) + unsafe { _vminv_s32(a) } } #[doc = "Horizontal vector min."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(sminv))] -pub unsafe fn vminvq_s32(a: int32x4_t) -> i32 { +pub fn vminvq_s32(a: int32x4_t) -> i32 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -14695,17 +13528,15 @@ pub unsafe fn vminvq_s32(a: int32x4_t) -> i32 { )] fn _vminvq_s32(a: int32x4_t) -> i32; } - _vminvq_s32(a) + unsafe { _vminvq_s32(a) } } #[doc = "Horizontal vector min."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(uminv))] -pub unsafe fn vminv_u8(a: uint8x8_t) -> u8 { +pub fn vminv_u8(a: uint8x8_t) -> u8 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -14713,17 +13544,15 @@ pub unsafe fn vminv_u8(a: uint8x8_t) -> u8 { )] fn _vminv_u8(a: uint8x8_t) -> u8; } - _vminv_u8(a) + unsafe { _vminv_u8(a) } } #[doc = "Horizontal vector min."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(uminv))] -pub unsafe fn vminvq_u8(a: uint8x16_t) -> u8 { +pub fn vminvq_u8(a: uint8x16_t) -> u8 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -14731,17 +13560,15 @@ pub unsafe fn vminvq_u8(a: uint8x16_t) -> u8 { )] fn _vminvq_u8(a: uint8x16_t) -> u8; } - _vminvq_u8(a) + unsafe { _vminvq_u8(a) } } #[doc = "Horizontal vector min."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(uminv))] -pub unsafe fn vminv_u16(a: uint16x4_t) -> u16 { +pub fn vminv_u16(a: uint16x4_t) -> u16 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -14749,17 +13576,15 @@ pub unsafe fn vminv_u16(a: uint16x4_t) -> u16 { )] fn _vminv_u16(a: uint16x4_t) -> u16; } - _vminv_u16(a) + unsafe { _vminv_u16(a) } } #[doc = "Horizontal vector min."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(uminv))] -pub unsafe fn vminvq_u16(a: uint16x8_t) -> u16 { +pub fn vminvq_u16(a: uint16x8_t) -> u16 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -14767,17 +13592,15 @@ pub unsafe fn vminvq_u16(a: uint16x8_t) -> u16 { )] fn _vminvq_u16(a: uint16x8_t) -> u16; } - _vminvq_u16(a) + unsafe { _vminvq_u16(a) } } #[doc = "Horizontal vector min."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(uminp))] -pub unsafe fn vminv_u32(a: uint32x2_t) -> u32 { +pub fn vminv_u32(a: uint32x2_t) -> u32 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -14785,17 +13608,15 @@ pub unsafe fn vminv_u32(a: uint32x2_t) -> u32 { )] fn _vminv_u32(a: uint32x2_t) -> u32; } - _vminv_u32(a) + unsafe { _vminv_u32(a) } } #[doc = "Horizontal vector min."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(uminv))] -pub unsafe fn vminvq_u32(a: uint32x4_t) -> u32 { +pub fn vminvq_u32(a: uint32x4_t) -> u32 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -14803,1383 +13624,1317 @@ pub unsafe fn vminvq_u32(a: uint32x4_t) -> u32 { )] fn _vminvq_u32(a: uint32x4_t) -> u32; } - _vminvq_u32(a) + unsafe { _vminvq_u32(a) } } #[doc = "Floating-point multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmul))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmla_f64(a: float64x1_t, b: float64x1_t, c: float64x1_t) -> float64x1_t { - simd_add(a, simd_mul(b, c)) +pub fn vmla_f64(a: float64x1_t, b: float64x1_t, c: float64x1_t) -> float64x1_t { + unsafe { simd_add(a, simd_mul(b, c)) } } #[doc = "Floating-point multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmul))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmlaq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t { - simd_add(a, simd_mul(b, c)) +pub fn vmlaq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t { + unsafe { simd_add(a, simd_mul(b, c)) } } #[doc = "Multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_lane_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(smlal2, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmlal_high_lane_s16( - a: int32x4_t, - b: int16x8_t, - c: int16x4_t, -) -> int32x4_t { +pub fn vmlal_high_lane_s16(a: int32x4_t, b: int16x8_t, c: int16x4_t) -> int32x4_t { static_assert_uimm_bits!(LANE, 2); - vmlal_high_s16( - a, - b, - simd_shuffle!( - c, - c, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) + unsafe { + vmlal_high_s16( + a, + b, + simd_shuffle!( + c, + c, + [ + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32 + ] + ), + ) + } } #[doc = "Multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_laneq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(smlal2, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmlal_high_laneq_s16( +pub fn vmlal_high_laneq_s16( a: int32x4_t, b: int16x8_t, c: int16x8_t, ) -> int32x4_t { static_assert_uimm_bits!(LANE, 3); - vmlal_high_s16( - a, - b, - simd_shuffle!( - c, - c, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) + unsafe { + vmlal_high_s16( + a, + b, + simd_shuffle!( + c, + c, + [ + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32 + ] + ), + ) + } } #[doc = "Multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_lane_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(smlal2, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmlal_high_lane_s32( - a: int64x2_t, - b: int32x4_t, - c: int32x2_t, -) -> int64x2_t { +pub fn vmlal_high_lane_s32(a: int64x2_t, b: int32x4_t, c: int32x2_t) -> int64x2_t { static_assert_uimm_bits!(LANE, 1); - vmlal_high_s32( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) + unsafe { + vmlal_high_s32( + a, + b, + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) + } } #[doc = "Multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_laneq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(smlal2, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmlal_high_laneq_s32( +pub fn vmlal_high_laneq_s32( a: int64x2_t, b: int32x4_t, c: int32x4_t, ) -> int64x2_t { static_assert_uimm_bits!(LANE, 2); - vmlal_high_s32( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) + unsafe { + vmlal_high_s32( + a, + b, + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) + } } #[doc = "Multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_lane_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(umlal2, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmlal_high_lane_u16( +pub fn vmlal_high_lane_u16( a: uint32x4_t, b: uint16x8_t, c: uint16x4_t, ) -> uint32x4_t { static_assert_uimm_bits!(LANE, 2); - vmlal_high_u16( - a, - b, - simd_shuffle!( - c, - c, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) + unsafe { + vmlal_high_u16( + a, + b, + simd_shuffle!( + c, + c, + [ + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32 + ] + ), + ) + } } #[doc = "Multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_laneq_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(umlal2, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmlal_high_laneq_u16( +pub fn vmlal_high_laneq_u16( a: uint32x4_t, b: uint16x8_t, c: uint16x8_t, ) -> uint32x4_t { static_assert_uimm_bits!(LANE, 3); - vmlal_high_u16( - a, - b, - simd_shuffle!( - c, - c, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) + unsafe { + vmlal_high_u16( + a, + b, + simd_shuffle!( + c, + c, + [ + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32 + ] + ), + ) + } } #[doc = "Multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_lane_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(umlal2, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmlal_high_lane_u32( +pub fn vmlal_high_lane_u32( a: uint64x2_t, b: uint32x4_t, c: uint32x2_t, ) -> uint64x2_t { static_assert_uimm_bits!(LANE, 1); - vmlal_high_u32( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) + unsafe { + vmlal_high_u32( + a, + b, + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) + } } #[doc = "Multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_laneq_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(umlal2, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmlal_high_laneq_u32( +pub fn vmlal_high_laneq_u32( a: uint64x2_t, b: uint32x4_t, c: uint32x4_t, ) -> uint64x2_t { static_assert_uimm_bits!(LANE, 2); - vmlal_high_u32( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) + unsafe { + vmlal_high_u32( + a, + b, + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) + } } #[doc = "Multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_n_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(smlal2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmlal_high_n_s16(a: int32x4_t, b: int16x8_t, c: i16) -> int32x4_t { +pub fn vmlal_high_n_s16(a: int32x4_t, b: int16x8_t, c: i16) -> int32x4_t { vmlal_high_s16(a, b, vdupq_n_s16(c)) } #[doc = "Multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_n_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(smlal2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmlal_high_n_s32(a: int64x2_t, b: int32x4_t, c: i32) -> int64x2_t { +pub fn vmlal_high_n_s32(a: int64x2_t, b: int32x4_t, c: i32) -> int64x2_t { vmlal_high_s32(a, b, vdupq_n_s32(c)) } #[doc = "Multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_n_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(umlal2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmlal_high_n_u16(a: uint32x4_t, b: uint16x8_t, c: u16) -> uint32x4_t { +pub fn vmlal_high_n_u16(a: uint32x4_t, b: uint16x8_t, c: u16) -> uint32x4_t { vmlal_high_u16(a, b, vdupq_n_u16(c)) } #[doc = "Multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_n_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(umlal2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmlal_high_n_u32(a: uint64x2_t, b: uint32x4_t, c: u32) -> uint64x2_t { +pub fn vmlal_high_n_u32(a: uint64x2_t, b: uint32x4_t, c: u32) -> uint64x2_t { vmlal_high_u32(a, b, vdupq_n_u32(c)) } #[doc = "Signed multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(smlal2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmlal_high_s8(a: int16x8_t, b: int8x16_t, c: int8x16_t) -> int16x8_t { - let b: int8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); - let c: int8x8_t = simd_shuffle!(c, c, [8, 9, 10, 11, 12, 13, 14, 15]); - vmlal_s8(a, b, c) +pub fn vmlal_high_s8(a: int16x8_t, b: int8x16_t, c: int8x16_t) -> int16x8_t { + unsafe { + let b: int8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); + let c: int8x8_t = simd_shuffle!(c, c, [8, 9, 10, 11, 12, 13, 14, 15]); + vmlal_s8(a, b, c) + } } #[doc = "Signed multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(smlal2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmlal_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t { - let b: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); - let c: int16x4_t = simd_shuffle!(c, c, [4, 5, 6, 7]); - vmlal_s16(a, b, c) +pub fn vmlal_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t { + unsafe { + let b: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); + let c: int16x4_t = simd_shuffle!(c, c, [4, 5, 6, 7]); + vmlal_s16(a, b, c) + } } #[doc = "Signed multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(smlal2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmlal_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t { - let b: int32x2_t = simd_shuffle!(b, b, [2, 3]); - let c: int32x2_t = simd_shuffle!(c, c, [2, 3]); - vmlal_s32(a, b, c) +pub fn vmlal_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t { + unsafe { + let b: int32x2_t = simd_shuffle!(b, b, [2, 3]); + let c: int32x2_t = simd_shuffle!(c, c, [2, 3]); + vmlal_s32(a, b, c) + } } #[doc = "Unsigned multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(umlal2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmlal_high_u8(a: uint16x8_t, b: uint8x16_t, c: uint8x16_t) -> uint16x8_t { - let b: uint8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); - let c: uint8x8_t = simd_shuffle!(c, c, [8, 9, 10, 11, 12, 13, 14, 15]); - vmlal_u8(a, b, c) +pub fn vmlal_high_u8(a: uint16x8_t, b: uint8x16_t, c: uint8x16_t) -> uint16x8_t { + unsafe { + let b: uint8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); + let c: uint8x8_t = simd_shuffle!(c, c, [8, 9, 10, 11, 12, 13, 14, 15]); + vmlal_u8(a, b, c) + } } #[doc = "Unsigned multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(umlal2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmlal_high_u16(a: uint32x4_t, b: uint16x8_t, c: uint16x8_t) -> uint32x4_t { - let b: uint16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); - let c: uint16x4_t = simd_shuffle!(c, c, [4, 5, 6, 7]); - vmlal_u16(a, b, c) +pub fn vmlal_high_u16(a: uint32x4_t, b: uint16x8_t, c: uint16x8_t) -> uint32x4_t { + unsafe { + let b: uint16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); + let c: uint16x4_t = simd_shuffle!(c, c, [4, 5, 6, 7]); + vmlal_u16(a, b, c) + } } #[doc = "Unsigned multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(umlal2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmlal_high_u32(a: uint64x2_t, b: uint32x4_t, c: uint32x4_t) -> uint64x2_t { - let b: uint32x2_t = simd_shuffle!(b, b, [2, 3]); - let c: uint32x2_t = simd_shuffle!(c, c, [2, 3]); - vmlal_u32(a, b, c) +pub fn vmlal_high_u32(a: uint64x2_t, b: uint32x4_t, c: uint32x4_t) -> uint64x2_t { + unsafe { + let b: uint32x2_t = simd_shuffle!(b, b, [2, 3]); + let c: uint32x2_t = simd_shuffle!(c, c, [2, 3]); + vmlal_u32(a, b, c) + } } #[doc = "Floating-point multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmul))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmls_f64(a: float64x1_t, b: float64x1_t, c: float64x1_t) -> float64x1_t { - simd_sub(a, simd_mul(b, c)) +pub fn vmls_f64(a: float64x1_t, b: float64x1_t, c: float64x1_t) -> float64x1_t { + unsafe { simd_sub(a, simd_mul(b, c)) } } #[doc = "Floating-point multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmul))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmlsq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t { - simd_sub(a, simd_mul(b, c)) +pub fn vmlsq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t { + unsafe { simd_sub(a, simd_mul(b, c)) } } #[doc = "Multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_lane_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(smlsl2, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmlsl_high_lane_s16( - a: int32x4_t, - b: int16x8_t, - c: int16x4_t, -) -> int32x4_t { +pub fn vmlsl_high_lane_s16(a: int32x4_t, b: int16x8_t, c: int16x4_t) -> int32x4_t { static_assert_uimm_bits!(LANE, 2); - vmlsl_high_s16( - a, - b, - simd_shuffle!( - c, - c, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) + unsafe { + vmlsl_high_s16( + a, + b, + simd_shuffle!( + c, + c, + [ + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32 + ] + ), + ) + } } #[doc = "Multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_laneq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(smlsl2, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmlsl_high_laneq_s16( +pub fn vmlsl_high_laneq_s16( a: int32x4_t, b: int16x8_t, c: int16x8_t, ) -> int32x4_t { static_assert_uimm_bits!(LANE, 3); - vmlsl_high_s16( - a, - b, - simd_shuffle!( - c, - c, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) + unsafe { + vmlsl_high_s16( + a, + b, + simd_shuffle!( + c, + c, + [ + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32 + ] + ), + ) + } } #[doc = "Multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_lane_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(smlsl2, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmlsl_high_lane_s32( - a: int64x2_t, - b: int32x4_t, - c: int32x2_t, -) -> int64x2_t { +pub fn vmlsl_high_lane_s32(a: int64x2_t, b: int32x4_t, c: int32x2_t) -> int64x2_t { static_assert_uimm_bits!(LANE, 1); - vmlsl_high_s32( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) + unsafe { + vmlsl_high_s32( + a, + b, + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) + } } #[doc = "Multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_laneq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(smlsl2, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmlsl_high_laneq_s32( +pub fn vmlsl_high_laneq_s32( a: int64x2_t, b: int32x4_t, c: int32x4_t, ) -> int64x2_t { static_assert_uimm_bits!(LANE, 2); - vmlsl_high_s32( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) + unsafe { + vmlsl_high_s32( + a, + b, + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) + } } #[doc = "Multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_lane_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(umlsl2, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmlsl_high_lane_u16( +pub fn vmlsl_high_lane_u16( a: uint32x4_t, b: uint16x8_t, c: uint16x4_t, ) -> uint32x4_t { static_assert_uimm_bits!(LANE, 2); - vmlsl_high_u16( - a, - b, - simd_shuffle!( - c, - c, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) + unsafe { + vmlsl_high_u16( + a, + b, + simd_shuffle!( + c, + c, + [ + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32 + ] + ), + ) + } } #[doc = "Multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_laneq_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(umlsl2, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmlsl_high_laneq_u16( +pub fn vmlsl_high_laneq_u16( a: uint32x4_t, b: uint16x8_t, c: uint16x8_t, ) -> uint32x4_t { static_assert_uimm_bits!(LANE, 3); - vmlsl_high_u16( - a, - b, - simd_shuffle!( - c, - c, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) + unsafe { + vmlsl_high_u16( + a, + b, + simd_shuffle!( + c, + c, + [ + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32 + ] + ), + ) + } } #[doc = "Multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_lane_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(umlsl2, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmlsl_high_lane_u32( +pub fn vmlsl_high_lane_u32( a: uint64x2_t, b: uint32x4_t, c: uint32x2_t, ) -> uint64x2_t { static_assert_uimm_bits!(LANE, 1); - vmlsl_high_u32( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) + unsafe { + vmlsl_high_u32( + a, + b, + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) + } } #[doc = "Multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_laneq_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(umlsl2, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmlsl_high_laneq_u32( +pub fn vmlsl_high_laneq_u32( a: uint64x2_t, b: uint32x4_t, c: uint32x4_t, ) -> uint64x2_t { static_assert_uimm_bits!(LANE, 2); - vmlsl_high_u32( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) + unsafe { + vmlsl_high_u32( + a, + b, + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) + } } #[doc = "Multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_n_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(smlsl2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmlsl_high_n_s16(a: int32x4_t, b: int16x8_t, c: i16) -> int32x4_t { +pub fn vmlsl_high_n_s16(a: int32x4_t, b: int16x8_t, c: i16) -> int32x4_t { vmlsl_high_s16(a, b, vdupq_n_s16(c)) } #[doc = "Multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_n_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(smlsl2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmlsl_high_n_s32(a: int64x2_t, b: int32x4_t, c: i32) -> int64x2_t { +pub fn vmlsl_high_n_s32(a: int64x2_t, b: int32x4_t, c: i32) -> int64x2_t { vmlsl_high_s32(a, b, vdupq_n_s32(c)) } #[doc = "Multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_n_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(umlsl2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmlsl_high_n_u16(a: uint32x4_t, b: uint16x8_t, c: u16) -> uint32x4_t { +pub fn vmlsl_high_n_u16(a: uint32x4_t, b: uint16x8_t, c: u16) -> uint32x4_t { vmlsl_high_u16(a, b, vdupq_n_u16(c)) } #[doc = "Multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_n_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(umlsl2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmlsl_high_n_u32(a: uint64x2_t, b: uint32x4_t, c: u32) -> uint64x2_t { +pub fn vmlsl_high_n_u32(a: uint64x2_t, b: uint32x4_t, c: u32) -> uint64x2_t { vmlsl_high_u32(a, b, vdupq_n_u32(c)) } #[doc = "Signed multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(smlsl2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmlsl_high_s8(a: int16x8_t, b: int8x16_t, c: int8x16_t) -> int16x8_t { - let b: int8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); - let c: int8x8_t = simd_shuffle!(c, c, [8, 9, 10, 11, 12, 13, 14, 15]); - vmlsl_s8(a, b, c) +pub fn vmlsl_high_s8(a: int16x8_t, b: int8x16_t, c: int8x16_t) -> int16x8_t { + unsafe { + let b: int8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); + let c: int8x8_t = simd_shuffle!(c, c, [8, 9, 10, 11, 12, 13, 14, 15]); + vmlsl_s8(a, b, c) + } } #[doc = "Signed multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(smlsl2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmlsl_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t { - let b: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); - let c: int16x4_t = simd_shuffle!(c, c, [4, 5, 6, 7]); - vmlsl_s16(a, b, c) +pub fn vmlsl_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t { + unsafe { + let b: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); + let c: int16x4_t = simd_shuffle!(c, c, [4, 5, 6, 7]); + vmlsl_s16(a, b, c) + } } #[doc = "Signed multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(smlsl2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmlsl_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t { - let b: int32x2_t = simd_shuffle!(b, b, [2, 3]); - let c: int32x2_t = simd_shuffle!(c, c, [2, 3]); - vmlsl_s32(a, b, c) +pub fn vmlsl_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t { + unsafe { + let b: int32x2_t = simd_shuffle!(b, b, [2, 3]); + let c: int32x2_t = simd_shuffle!(c, c, [2, 3]); + vmlsl_s32(a, b, c) + } } #[doc = "Unsigned multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(umlsl2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmlsl_high_u8(a: uint16x8_t, b: uint8x16_t, c: uint8x16_t) -> uint16x8_t { - let b: uint8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); - let c: uint8x8_t = simd_shuffle!(c, c, [8, 9, 10, 11, 12, 13, 14, 15]); - vmlsl_u8(a, b, c) +pub fn vmlsl_high_u8(a: uint16x8_t, b: uint8x16_t, c: uint8x16_t) -> uint16x8_t { + unsafe { + let b: uint8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); + let c: uint8x8_t = simd_shuffle!(c, c, [8, 9, 10, 11, 12, 13, 14, 15]); + vmlsl_u8(a, b, c) + } } #[doc = "Unsigned multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(umlsl2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmlsl_high_u16(a: uint32x4_t, b: uint16x8_t, c: uint16x8_t) -> uint32x4_t { - let b: uint16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); - let c: uint16x4_t = simd_shuffle!(c, c, [4, 5, 6, 7]); - vmlsl_u16(a, b, c) +pub fn vmlsl_high_u16(a: uint32x4_t, b: uint16x8_t, c: uint16x8_t) -> uint32x4_t { + unsafe { + let b: uint16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); + let c: uint16x4_t = simd_shuffle!(c, c, [4, 5, 6, 7]); + vmlsl_u16(a, b, c) + } } #[doc = "Unsigned multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(umlsl2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmlsl_high_u32(a: uint64x2_t, b: uint32x4_t, c: uint32x4_t) -> uint64x2_t { - let b: uint32x2_t = simd_shuffle!(b, b, [2, 3]); - let c: uint32x2_t = simd_shuffle!(c, c, [2, 3]); - vmlsl_u32(a, b, c) +pub fn vmlsl_high_u32(a: uint64x2_t, b: uint32x4_t, c: uint32x4_t) -> uint64x2_t { + unsafe { + let b: uint32x2_t = simd_shuffle!(b, b, [2, 3]); + let c: uint32x2_t = simd_shuffle!(c, c, [2, 3]); + vmlsl_u32(a, b, c) + } } #[doc = "Vector move"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_high_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(sxtl2))] -pub unsafe fn vmovl_high_s8(a: int8x16_t) -> int16x8_t { - let a: int8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); - vmovl_s8(a) +pub fn vmovl_high_s8(a: int8x16_t) -> int16x8_t { + unsafe { + let a: int8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); + vmovl_s8(a) + } } #[doc = "Vector move"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_high_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(sxtl2))] -pub unsafe fn vmovl_high_s16(a: int16x8_t) -> int32x4_t { - let a: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); - vmovl_s16(a) +pub fn vmovl_high_s16(a: int16x8_t) -> int32x4_t { + unsafe { + let a: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); + vmovl_s16(a) + } } #[doc = "Vector move"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_high_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(sxtl2))] -pub unsafe fn vmovl_high_s32(a: int32x4_t) -> int64x2_t { - let a: int32x2_t = simd_shuffle!(a, a, [2, 3]); - vmovl_s32(a) +pub fn vmovl_high_s32(a: int32x4_t) -> int64x2_t { + unsafe { + let a: int32x2_t = simd_shuffle!(a, a, [2, 3]); + vmovl_s32(a) + } } #[doc = "Vector move"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_high_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(uxtl2))] -pub unsafe fn vmovl_high_u8(a: uint8x16_t) -> uint16x8_t { - let a: uint8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); - vmovl_u8(a) +pub fn vmovl_high_u8(a: uint8x16_t) -> uint16x8_t { + unsafe { + let a: uint8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); + vmovl_u8(a) + } } #[doc = "Vector move"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_high_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(uxtl2))] -pub unsafe fn vmovl_high_u16(a: uint16x8_t) -> uint32x4_t { - let a: uint16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); - vmovl_u16(a) +pub fn vmovl_high_u16(a: uint16x8_t) -> uint32x4_t { + unsafe { + let a: uint16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); + vmovl_u16(a) + } } #[doc = "Vector move"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_high_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(uxtl2))] -pub unsafe fn vmovl_high_u32(a: uint32x4_t) -> uint64x2_t { - let a: uint32x2_t = simd_shuffle!(a, a, [2, 3]); - vmovl_u32(a) +pub fn vmovl_high_u32(a: uint32x4_t) -> uint64x2_t { + unsafe { + let a: uint32x2_t = simd_shuffle!(a, a, [2, 3]); + vmovl_u32(a) + } } #[doc = "Extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_high_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(xtn2))] -pub unsafe fn vmovn_high_s16(a: int8x8_t, b: int16x8_t) -> int8x16_t { - let c: int8x8_t = simd_cast(b); - simd_shuffle!(a, c, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) +pub fn vmovn_high_s16(a: int8x8_t, b: int16x8_t) -> int8x16_t { + unsafe { + let c: int8x8_t = simd_cast(b); + simd_shuffle!(a, c, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) + } } #[doc = "Extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_high_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(xtn2))] -pub unsafe fn vmovn_high_s32(a: int16x4_t, b: int32x4_t) -> int16x8_t { - let c: int16x4_t = simd_cast(b); - simd_shuffle!(a, c, [0, 1, 2, 3, 4, 5, 6, 7]) +pub fn vmovn_high_s32(a: int16x4_t, b: int32x4_t) -> int16x8_t { + unsafe { + let c: int16x4_t = simd_cast(b); + simd_shuffle!(a, c, [0, 1, 2, 3, 4, 5, 6, 7]) + } } #[doc = "Extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_high_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(xtn2))] -pub unsafe fn vmovn_high_s64(a: int32x2_t, b: int64x2_t) -> int32x4_t { - let c: int32x2_t = simd_cast(b); - simd_shuffle!(a, c, [0, 1, 2, 3]) +pub fn vmovn_high_s64(a: int32x2_t, b: int64x2_t) -> int32x4_t { + unsafe { + let c: int32x2_t = simd_cast(b); + simd_shuffle!(a, c, [0, 1, 2, 3]) + } } #[doc = "Extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_high_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(xtn2))] -pub unsafe fn vmovn_high_u16(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t { - let c: uint8x8_t = simd_cast(b); - simd_shuffle!(a, c, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) +pub fn vmovn_high_u16(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t { + unsafe { + let c: uint8x8_t = simd_cast(b); + simd_shuffle!(a, c, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) + } } #[doc = "Extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_high_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(xtn2))] -pub unsafe fn vmovn_high_u32(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t { - let c: uint16x4_t = simd_cast(b); - simd_shuffle!(a, c, [0, 1, 2, 3, 4, 5, 6, 7]) +pub fn vmovn_high_u32(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t { + unsafe { + let c: uint16x4_t = simd_cast(b); + simd_shuffle!(a, c, [0, 1, 2, 3, 4, 5, 6, 7]) + } } #[doc = "Extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_high_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(xtn2))] -pub unsafe fn vmovn_high_u64(a: uint32x2_t, b: uint64x2_t) -> uint32x4_t { - let c: uint32x2_t = simd_cast(b); - simd_shuffle!(a, c, [0, 1, 2, 3]) +pub fn vmovn_high_u64(a: uint32x2_t, b: uint64x2_t) -> uint32x4_t { + unsafe { + let c: uint32x2_t = simd_cast(b); + simd_shuffle!(a, c, [0, 1, 2, 3]) + } } #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmul))] -pub unsafe fn vmul_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { - simd_mul(a, b) +pub fn vmul_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { + unsafe { simd_mul(a, b) } } #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmul))] -pub unsafe fn vmulq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { - simd_mul(a, b) +pub fn vmulq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { + unsafe { simd_mul(a, b) } } #[doc = "Floating-point multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmul, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmul_lane_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { +pub fn vmul_lane_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { static_assert!(LANE == 0); - simd_mul(a, transmute::(simd_extract!(b, LANE as u32))) + unsafe { simd_mul(a, transmute::(simd_extract!(b, LANE as u32))) } } #[doc = "Floating-point multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fmul, LANE = 0))] #[rustc_legacy_const_generics(2)] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vmul_laneq_f16(a: float16x4_t, b: float16x8_t) -> float16x4_t { +pub fn vmul_laneq_f16(a: float16x4_t, b: float16x8_t) -> float16x4_t { static_assert_uimm_bits!(LANE, 3); - simd_mul( - a, - simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) + unsafe { + simd_mul( + a, + simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) + } } #[doc = "Floating-point multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fmul, LANE = 0))] #[rustc_legacy_const_generics(2)] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vmulq_laneq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { +pub fn vmulq_laneq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { static_assert_uimm_bits!(LANE, 3); - simd_mul( - a, - simd_shuffle!( - b, - b, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) + unsafe { + simd_mul( + a, + simd_shuffle!( + b, + b, + [ + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32 + ] + ), + ) + } } #[doc = "Floating-point multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmul, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmul_laneq_f64(a: float64x1_t, b: float64x2_t) -> float64x1_t { +pub fn vmul_laneq_f64(a: float64x1_t, b: float64x2_t) -> float64x1_t { static_assert_uimm_bits!(LANE, 1); - simd_mul(a, transmute::(simd_extract!(b, LANE as u32))) + unsafe { simd_mul(a, transmute::(simd_extract!(b, LANE as u32))) } } #[doc = "Vector multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmul))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmul_n_f64(a: float64x1_t, b: f64) -> float64x1_t { - simd_mul(a, vdup_n_f64(b)) +pub fn vmul_n_f64(a: float64x1_t, b: f64) -> float64x1_t { + unsafe { simd_mul(a, vdup_n_f64(b)) } } #[doc = "Vector multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmul))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmulq_n_f64(a: float64x2_t, b: f64) -> float64x2_t { - simd_mul(a, vdupq_n_f64(b)) +pub fn vmulq_n_f64(a: float64x2_t, b: f64) -> float64x2_t { + unsafe { simd_mul(a, vdupq_n_f64(b)) } } #[doc = "Floating-point multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmuld_lane_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmul, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmuld_lane_f64(a: f64, b: float64x1_t) -> f64 { +pub fn vmuld_lane_f64(a: f64, b: float64x1_t) -> f64 { static_assert!(LANE == 0); - let b: f64 = simd_extract!(b, LANE as u32); - a * b + unsafe { + let b: f64 = simd_extract!(b, LANE as u32); + a * b + } } #[doc = "Add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulh_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vmulh_f16(a: f16, b: f16) -> f16 { +pub fn vmulh_f16(a: f16, b: f16) -> f16 { a * b } #[doc = "Floating-point multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulh_lane_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fmul, LANE = 0))] #[rustc_legacy_const_generics(2)] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vmulh_lane_f16(a: f16, b: float16x4_t) -> f16 { +pub fn vmulh_lane_f16(a: f16, b: float16x4_t) -> f16 { static_assert_uimm_bits!(LANE, 2); - let b: f16 = simd_extract!(b, LANE as u32); - a * b + unsafe { + let b: f16 = simd_extract!(b, LANE as u32); + a * b + } } #[doc = "Floating-point multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulh_laneq_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fmul, LANE = 0))] #[rustc_legacy_const_generics(2)] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vmulh_laneq_f16(a: f16, b: float16x8_t) -> f16 { +pub fn vmulh_laneq_f16(a: f16, b: float16x8_t) -> f16 { static_assert_uimm_bits!(LANE, 3); - let b: f16 = simd_extract!(b, LANE as u32); - a * b + unsafe { + let b: f16 = simd_extract!(b, LANE as u32); + a * b + } } #[doc = "Multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_lane_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(smull2, LANE = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmull_high_lane_s16(a: int16x8_t, b: int16x4_t) -> int32x4_t { +pub fn vmull_high_lane_s16(a: int16x8_t, b: int16x4_t) -> int32x4_t { static_assert_uimm_bits!(LANE, 2); - vmull_high_s16( - a, - simd_shuffle!( - b, - b, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) + unsafe { + vmull_high_s16( + a, + simd_shuffle!( + b, + b, + [ + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32 + ] + ), + ) + } } #[doc = "Multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_laneq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(smull2, LANE = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmull_high_laneq_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t { +pub fn vmull_high_laneq_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t { static_assert_uimm_bits!(LANE, 3); - vmull_high_s16( - a, - simd_shuffle!( - b, - b, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) + unsafe { + vmull_high_s16( + a, + simd_shuffle!( + b, + b, + [ + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32 + ] + ), + ) + } } #[doc = "Multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_lane_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(smull2, LANE = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmull_high_lane_s32(a: int32x4_t, b: int32x2_t) -> int64x2_t { +pub fn vmull_high_lane_s32(a: int32x4_t, b: int32x2_t) -> int64x2_t { static_assert_uimm_bits!(LANE, 1); - vmull_high_s32( - a, - simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) + unsafe { + vmull_high_s32( + a, + simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) + } } #[doc = "Multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_laneq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(smull2, LANE = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmull_high_laneq_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t { +pub fn vmull_high_laneq_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t { static_assert_uimm_bits!(LANE, 2); - vmull_high_s32( - a, - simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) + unsafe { + vmull_high_s32( + a, + simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) + } } #[doc = "Multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_lane_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(umull2, LANE = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmull_high_lane_u16(a: uint16x8_t, b: uint16x4_t) -> uint32x4_t { +pub fn vmull_high_lane_u16(a: uint16x8_t, b: uint16x4_t) -> uint32x4_t { static_assert_uimm_bits!(LANE, 2); - vmull_high_u16( - a, - simd_shuffle!( - b, - b, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) + unsafe { + vmull_high_u16( + a, + simd_shuffle!( + b, + b, + [ + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32 + ] + ), + ) + } } #[doc = "Multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_laneq_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(umull2, LANE = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmull_high_laneq_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t { +pub fn vmull_high_laneq_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t { static_assert_uimm_bits!(LANE, 3); - vmull_high_u16( - a, - simd_shuffle!( - b, - b, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) + unsafe { + vmull_high_u16( + a, + simd_shuffle!( + b, + b, + [ + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32 + ] + ), + ) + } } #[doc = "Multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_lane_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(umull2, LANE = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmull_high_lane_u32(a: uint32x4_t, b: uint32x2_t) -> uint64x2_t { +pub fn vmull_high_lane_u32(a: uint32x4_t, b: uint32x2_t) -> uint64x2_t { static_assert_uimm_bits!(LANE, 1); - vmull_high_u32( - a, - simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) + unsafe { + vmull_high_u32( + a, + simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) + } } #[doc = "Multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_laneq_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(umull2, LANE = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmull_high_laneq_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t { +pub fn vmull_high_laneq_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t { static_assert_uimm_bits!(LANE, 2); - vmull_high_u32( - a, - simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) + unsafe { + vmull_high_u32( + a, + simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) + } } #[doc = "Multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_n_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(smull2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmull_high_n_s16(a: int16x8_t, b: i16) -> int32x4_t { +pub fn vmull_high_n_s16(a: int16x8_t, b: i16) -> int32x4_t { vmull_high_s16(a, vdupq_n_s16(b)) } #[doc = "Multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_n_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(smull2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmull_high_n_s32(a: int32x4_t, b: i32) -> int64x2_t { +pub fn vmull_high_n_s32(a: int32x4_t, b: i32) -> int64x2_t { vmull_high_s32(a, vdupq_n_s32(b)) } #[doc = "Multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_n_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(umull2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmull_high_n_u16(a: uint16x8_t, b: u16) -> uint32x4_t { +pub fn vmull_high_n_u16(a: uint16x8_t, b: u16) -> uint32x4_t { vmull_high_u16(a, vdupq_n_u16(b)) } #[doc = "Multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_n_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(umull2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmull_high_n_u32(a: uint32x4_t, b: u32) -> uint64x2_t { +pub fn vmull_high_n_u32(a: uint32x4_t, b: u32) -> uint64x2_t { vmull_high_u32(a, vdupq_n_u32(b)) } #[doc = "Polynomial multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,aes")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(pmull))] -pub unsafe fn vmull_high_p64(a: poly64x2_t, b: poly64x2_t) -> p128 { - vmull_p64(simd_extract!(a, 1), simd_extract!(b, 1)) +pub fn vmull_high_p64(a: poly64x2_t, b: poly64x2_t) -> p128 { + unsafe { vmull_p64(simd_extract!(a, 1), simd_extract!(b, 1)) } } #[doc = "Polynomial multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(pmull))] -pub unsafe fn vmull_high_p8(a: poly8x16_t, b: poly8x16_t) -> poly16x8_t { - let a: poly8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); - let b: poly8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); - vmull_p8(a, b) +pub fn vmull_high_p8(a: poly8x16_t, b: poly8x16_t) -> poly16x8_t { + unsafe { + let a: poly8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); + let b: poly8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); + vmull_p8(a, b) + } } #[doc = "Signed multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(smull2))] -pub unsafe fn vmull_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t { - let a: int8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); - let b: int8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); - vmull_s8(a, b) +pub fn vmull_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t { + unsafe { + let a: int8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); + let b: int8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); + vmull_s8(a, b) + } } #[doc = "Signed multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(smull2))] -pub unsafe fn vmull_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t { - let a: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); - let b: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); - vmull_s16(a, b) +pub fn vmull_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t { + unsafe { + let a: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); + let b: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); + vmull_s16(a, b) + } } #[doc = "Signed multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(smull2))] -pub unsafe fn vmull_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t { - let a: int32x2_t = simd_shuffle!(a, a, [2, 3]); - let b: int32x2_t = simd_shuffle!(b, b, [2, 3]); - vmull_s32(a, b) +pub fn vmull_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t { + unsafe { + let a: int32x2_t = simd_shuffle!(a, a, [2, 3]); + let b: int32x2_t = simd_shuffle!(b, b, [2, 3]); + vmull_s32(a, b) + } } #[doc = "Unsigned multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(umull2))] -pub unsafe fn vmull_high_u8(a: uint8x16_t, b: uint8x16_t) -> uint16x8_t { - let a: uint8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); - let b: uint8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); - vmull_u8(a, b) +pub fn vmull_high_u8(a: uint8x16_t, b: uint8x16_t) -> uint16x8_t { + unsafe { + let a: uint8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); + let b: uint8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); + vmull_u8(a, b) + } } #[doc = "Unsigned multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(umull2))] -pub unsafe fn vmull_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t { - let a: uint16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); - let b: uint16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); - vmull_u16(a, b) +pub fn vmull_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t { + unsafe { + let a: uint16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); + let b: uint16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); + vmull_u16(a, b) + } } #[doc = "Unsigned multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(umull2))] -pub unsafe fn vmull_high_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t { - let a: uint32x2_t = simd_shuffle!(a, a, [2, 3]); - let b: uint32x2_t = simd_shuffle!(b, b, [2, 3]); - vmull_u32(a, b) +pub fn vmull_high_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t { + unsafe { + let a: uint32x2_t = simd_shuffle!(a, a, [2, 3]); + let b: uint32x2_t = simd_shuffle!(b, b, [2, 3]); + vmull_u32(a, b) + } } #[doc = "Polynomial multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,aes")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(pmull))] -pub unsafe fn vmull_p64(a: p64, b: p64) -> p128 { +pub fn vmull_p64(a: p64, b: p64) -> p128 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -16187,85 +14942,79 @@ pub unsafe fn vmull_p64(a: p64, b: p64) -> p128 { )] fn _vmull_p64(a: p64, b: p64) -> int8x16_t; } - transmute(_vmull_p64(a, b)) + unsafe { transmute(_vmull_p64(a, b)) } } #[doc = "Floating-point multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmul, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmulq_lane_f64(a: float64x2_t, b: float64x1_t) -> float64x2_t { +pub fn vmulq_lane_f64(a: float64x2_t, b: float64x1_t) -> float64x2_t { static_assert!(LANE == 0); - simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) + unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) } } #[doc = "Floating-point multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmul, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmulq_laneq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { +pub fn vmulq_laneq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { static_assert_uimm_bits!(LANE, 1); - simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) + unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) } } #[doc = "Floating-point multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmuls_lane_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmul, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmuls_lane_f32(a: f32, b: float32x2_t) -> f32 { +pub fn vmuls_lane_f32(a: f32, b: float32x2_t) -> f32 { static_assert_uimm_bits!(LANE, 1); - let b: f32 = simd_extract!(b, LANE as u32); - a * b + unsafe { + let b: f32 = simd_extract!(b, LANE as u32); + a * b + } } #[doc = "Floating-point multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmuls_laneq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmul, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmuls_laneq_f32(a: f32, b: float32x4_t) -> f32 { +pub fn vmuls_laneq_f32(a: f32, b: float32x4_t) -> f32 { static_assert_uimm_bits!(LANE, 2); - let b: f32 = simd_extract!(b, LANE as u32); - a * b + unsafe { + let b: f32 = simd_extract!(b, LANE as u32); + a * b + } } #[doc = "Floating-point multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmuld_laneq_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmul, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmuld_laneq_f64(a: f64, b: float64x2_t) -> f64 { +pub fn vmuld_laneq_f64(a: f64, b: float64x2_t) -> f64 { static_assert_uimm_bits!(LANE, 1); - let b: f64 = simd_extract!(b, LANE as u32); - a * b + unsafe { + let b: f64 = simd_extract!(b, LANE as u32); + a * b + } } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(fmulx))] -pub unsafe fn vmulx_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { +pub fn vmulx_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -16273,17 +15022,15 @@ pub unsafe fn vmulx_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { )] fn _vmulx_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t; } - _vmulx_f16(a, b) + unsafe { _vmulx_f16(a, b) } } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(fmulx))] -pub unsafe fn vmulxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { +pub fn vmulxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -16291,17 +15038,15 @@ pub unsafe fn vmulxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { )] fn _vmulxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t; } - _vmulxq_f16(a, b) + unsafe { _vmulxq_f16(a, b) } } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmulx))] -pub unsafe fn vmulx_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { +pub fn vmulx_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -16309,17 +15054,15 @@ pub unsafe fn vmulx_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { )] fn _vmulx_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t; } - _vmulx_f32(a, b) + unsafe { _vmulx_f32(a, b) } } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmulx))] -pub unsafe fn vmulxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { +pub fn vmulxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -16327,17 +15070,15 @@ pub unsafe fn vmulxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { )] fn _vmulxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t; } - _vmulxq_f32(a, b) + unsafe { _vmulxq_f32(a, b) } } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmulx))] -pub unsafe fn vmulx_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { +pub fn vmulx_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -16345,17 +15086,15 @@ pub unsafe fn vmulx_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { )] fn _vmulx_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t; } - _vmulx_f64(a, b) + unsafe { _vmulx_f64(a, b) } } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmulx))] -pub unsafe fn vmulxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { +pub fn vmulxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -16363,226 +15102,210 @@ pub unsafe fn vmulxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { )] fn _vmulxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t; } - _vmulxq_f64(a, b) + unsafe { _vmulxq_f64(a, b) } } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_lane_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] #[rustc_legacy_const_generics(2)] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vmulx_lane_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { +pub fn vmulx_lane_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { static_assert_uimm_bits!(LANE, 2); - vmulx_f16( - a, - simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) + unsafe { + vmulx_f16( + a, + simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) + } } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_laneq_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] #[rustc_legacy_const_generics(2)] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vmulx_laneq_f16(a: float16x4_t, b: float16x8_t) -> float16x4_t { +pub fn vmulx_laneq_f16(a: float16x4_t, b: float16x8_t) -> float16x4_t { static_assert_uimm_bits!(LANE, 3); - vmulx_f16( - a, - simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) + unsafe { + vmulx_f16( + a, + simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) + } } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_lane_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] #[rustc_legacy_const_generics(2)] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vmulxq_lane_f16(a: float16x8_t, b: float16x4_t) -> float16x8_t { +pub fn vmulxq_lane_f16(a: float16x8_t, b: float16x4_t) -> float16x8_t { static_assert_uimm_bits!(LANE, 2); - vmulxq_f16( - a, - simd_shuffle!( - b, - b, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) + unsafe { + vmulxq_f16( + a, + simd_shuffle!( + b, + b, + [ + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32 + ] + ), + ) + } } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_laneq_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] #[rustc_legacy_const_generics(2)] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vmulxq_laneq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { +pub fn vmulxq_laneq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { static_assert_uimm_bits!(LANE, 3); - vmulxq_f16( - a, - simd_shuffle!( - b, - b, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) + unsafe { + vmulxq_f16( + a, + simd_shuffle!( + b, + b, + [ + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32 + ] + ), + ) + } } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_lane_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmulx_lane_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { +pub fn vmulx_lane_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { static_assert_uimm_bits!(LANE, 1); - vmulx_f32(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) + unsafe { vmulx_f32(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) } } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_laneq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmulx_laneq_f32(a: float32x2_t, b: float32x4_t) -> float32x2_t { +pub fn vmulx_laneq_f32(a: float32x2_t, b: float32x4_t) -> float32x2_t { static_assert_uimm_bits!(LANE, 2); - vmulx_f32(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) + unsafe { vmulx_f32(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) } } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_lane_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmulxq_lane_f32(a: float32x4_t, b: float32x2_t) -> float32x4_t { +pub fn vmulxq_lane_f32(a: float32x4_t, b: float32x2_t) -> float32x4_t { static_assert_uimm_bits!(LANE, 1); - vmulxq_f32( - a, - simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) + unsafe { + vmulxq_f32( + a, + simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) + } } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_laneq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmulxq_laneq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { +pub fn vmulxq_laneq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { static_assert_uimm_bits!(LANE, 2); - vmulxq_f32( - a, - simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) + unsafe { + vmulxq_f32( + a, + simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) + } } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_laneq_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmulxq_laneq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { +pub fn vmulxq_laneq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { static_assert_uimm_bits!(LANE, 1); - vmulxq_f64(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) + unsafe { vmulxq_f64(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) } } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_lane_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmulx_lane_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { +pub fn vmulx_lane_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { static_assert!(LANE == 0); - vmulx_f64(a, transmute::(simd_extract!(b, LANE as u32))) + unsafe { vmulx_f64(a, transmute::(simd_extract!(b, LANE as u32))) } } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_laneq_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmulx_laneq_f64(a: float64x1_t, b: float64x2_t) -> float64x1_t { +pub fn vmulx_laneq_f64(a: float64x1_t, b: float64x2_t) -> float64x1_t { static_assert_uimm_bits!(LANE, 1); - vmulx_f64(a, transmute::(simd_extract!(b, LANE as u32))) + unsafe { vmulx_f64(a, transmute::(simd_extract!(b, LANE as u32))) } } #[doc = "Vector multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_n_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fmulx))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vmulx_n_f16(a: float16x4_t, b: f16) -> float16x4_t { +pub fn vmulx_n_f16(a: float16x4_t, b: f16) -> float16x4_t { vmulx_f16(a, vdup_n_f16(b)) } #[doc = "Vector multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_n_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fmulx))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vmulxq_n_f16(a: float16x8_t, b: f16) -> float16x8_t { +pub fn vmulxq_n_f16(a: float16x8_t, b: f16) -> float16x8_t { vmulxq_f16(a, vdupq_n_f16(b)) } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxd_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmulx))] -pub unsafe fn vmulxd_f64(a: f64, b: f64) -> f64 { +pub fn vmulxd_f64(a: f64, b: f64) -> f64 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -16590,17 +15313,15 @@ pub unsafe fn vmulxd_f64(a: f64, b: f64) -> f64 { )] fn _vmulxd_f64(a: f64, b: f64) -> f64; } - _vmulxd_f64(a, b) + unsafe { _vmulxd_f64(a, b) } } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxs_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmulx))] -pub unsafe fn vmulxs_f32(a: f32, b: f32) -> f32 { +pub fn vmulxs_f32(a: f32, b: f32) -> f32 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -16608,69 +15329,59 @@ pub unsafe fn vmulxs_f32(a: f32, b: f32) -> f32 { )] fn _vmulxs_f32(a: f32, b: f32) -> f32; } - _vmulxs_f32(a, b) + unsafe { _vmulxs_f32(a, b) } } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxd_lane_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmulxd_lane_f64(a: f64, b: float64x1_t) -> f64 { +pub fn vmulxd_lane_f64(a: f64, b: float64x1_t) -> f64 { static_assert!(LANE == 0); - vmulxd_f64(a, simd_extract!(b, LANE as u32)) + unsafe { vmulxd_f64(a, simd_extract!(b, LANE as u32)) } } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxd_laneq_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmulxd_laneq_f64(a: f64, b: float64x2_t) -> f64 { +pub fn vmulxd_laneq_f64(a: f64, b: float64x2_t) -> f64 { static_assert_uimm_bits!(LANE, 1); - vmulxd_f64(a, simd_extract!(b, LANE as u32)) + unsafe { vmulxd_f64(a, simd_extract!(b, LANE as u32)) } } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxs_lane_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmulxs_lane_f32(a: f32, b: float32x2_t) -> f32 { +pub fn vmulxs_lane_f32(a: f32, b: float32x2_t) -> f32 { static_assert_uimm_bits!(LANE, 1); - vmulxs_f32(a, simd_extract!(b, LANE as u32)) + unsafe { vmulxs_f32(a, simd_extract!(b, LANE as u32)) } } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxs_laneq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmulxs_laneq_f32(a: f32, b: float32x4_t) -> f32 { +pub fn vmulxs_laneq_f32(a: f32, b: float32x4_t) -> f32 { static_assert_uimm_bits!(LANE, 2); - vmulxs_f32(a, simd_extract!(b, LANE as u32)) + unsafe { vmulxs_f32(a, simd_extract!(b, LANE as u32)) } } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxh_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(fmulx))] -pub unsafe fn vmulxh_f16(a: f16, b: f16) -> f16 { +pub fn vmulxh_f16(a: f16, b: f16) -> f16 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -16678,184 +15389,158 @@ pub unsafe fn vmulxh_f16(a: f16, b: f16) -> f16 { )] fn _vmulxh_f16(a: f16, b: f16) -> f16; } - _vmulxh_f16(a, b) + unsafe { _vmulxh_f16(a, b) } } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxh_lane_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] #[rustc_legacy_const_generics(2)] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vmulxh_lane_f16(a: f16, b: float16x4_t) -> f16 { +pub fn vmulxh_lane_f16(a: f16, b: float16x4_t) -> f16 { static_assert_uimm_bits!(LANE, 2); - vmulxh_f16(a, simd_extract!(b, LANE as u32)) + unsafe { vmulxh_f16(a, simd_extract!(b, LANE as u32)) } } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxh_laneq_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] #[rustc_legacy_const_generics(2)] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vmulxh_laneq_f16(a: f16, b: float16x8_t) -> f16 { +pub fn vmulxh_laneq_f16(a: f16, b: float16x8_t) -> f16 { static_assert_uimm_bits!(LANE, 3); - vmulxh_f16(a, simd_extract!(b, LANE as u32)) + unsafe { vmulxh_f16(a, simd_extract!(b, LANE as u32)) } } #[doc = "Floating-point multiply extended"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_lane_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmulxq_lane_f64(a: float64x2_t, b: float64x1_t) -> float64x2_t { +pub fn vmulxq_lane_f64(a: float64x2_t, b: float64x1_t) -> float64x2_t { static_assert!(LANE == 0); - vmulxq_f64(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) + unsafe { vmulxq_f64(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) } } #[doc = "Negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fneg))] -pub unsafe fn vneg_f64(a: float64x1_t) -> float64x1_t { - simd_neg(a) +pub fn vneg_f64(a: float64x1_t) -> float64x1_t { + unsafe { simd_neg(a) } } #[doc = "Negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fneg))] -pub unsafe fn vnegq_f64(a: float64x2_t) -> float64x2_t { - simd_neg(a) +pub fn vnegq_f64(a: float64x2_t) -> float64x2_t { + unsafe { simd_neg(a) } } #[doc = "Negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(neg))] -pub unsafe fn vneg_s64(a: int64x1_t) -> int64x1_t { - simd_neg(a) +pub fn vneg_s64(a: int64x1_t) -> int64x1_t { + unsafe { simd_neg(a) } } #[doc = "Negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(neg))] -pub unsafe fn vnegq_s64(a: int64x2_t) -> int64x2_t { - simd_neg(a) +pub fn vnegq_s64(a: int64x2_t) -> int64x2_t { + unsafe { simd_neg(a) } } #[doc = "Negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegd_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(neg))] -pub unsafe fn vnegd_s64(a: i64) -> i64 { +pub fn vnegd_s64(a: i64) -> i64 { a.wrapping_neg() } #[doc = "Negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegh_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(fneg))] -pub unsafe fn vnegh_f16(a: f16) -> f16 { +pub fn vnegh_f16(a: f16) -> f16 { -a } #[doc = "Floating-point add pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddd_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vpaddd_f64(a: float64x2_t) -> f64 { - let a1: f64 = simd_extract!(a, 0); - let a2: f64 = simd_extract!(a, 1); - a1 + a2 +pub fn vpaddd_f64(a: float64x2_t) -> f64 { + unsafe { + let a1: f64 = simd_extract!(a, 0); + let a2: f64 = simd_extract!(a, 1); + a1 + a2 + } } #[doc = "Floating-point add pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadds_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vpadds_f32(a: float32x2_t) -> f32 { - let a1: f32 = simd_extract!(a, 0); - let a2: f32 = simd_extract!(a, 1); - a1 + a2 +pub fn vpadds_f32(a: float32x2_t) -> f32 { + unsafe { + let a1: f32 = simd_extract!(a, 0); + let a2: f32 = simd_extract!(a, 1); + a1 + a2 + } } #[doc = "Add pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddd_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addp))] -pub unsafe fn vpaddd_s64(a: int64x2_t) -> i64 { - transmute(vaddvq_u64(transmute(a))) +pub fn vpaddd_s64(a: int64x2_t) -> i64 { + unsafe { transmute(vaddvq_u64(transmute(a))) } } #[doc = "Add pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddd_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addp))] -pub unsafe fn vpaddd_s64(a: int64x2_t) -> i64 { +pub fn vpaddd_s64(a: int64x2_t) -> i64 { let a: int64x2_t = simd_shuffle!(a, a, [1, 0]); - transmute(vaddvq_u64(transmute(a))) + unsafe { transmute(vaddvq_u64(transmute(a))) } } #[doc = "Add pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddd_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addp))] -pub unsafe fn vpaddd_u64(a: uint64x2_t) -> u64 { +pub fn vpaddd_u64(a: uint64x2_t) -> u64 { vaddvq_u64(a) } #[doc = "Floating-point add pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(faddp))] -pub unsafe fn vpaddq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { +pub fn vpaddq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -16863,17 +15548,15 @@ pub unsafe fn vpaddq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { )] fn _vpaddq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t; } - _vpaddq_f16(a, b) + unsafe { _vpaddq_f16(a, b) } } #[doc = "Floating-point add pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(faddp))] -pub unsafe fn vpaddq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { +pub fn vpaddq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -16881,17 +15564,15 @@ pub unsafe fn vpaddq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { )] fn _vpaddq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t; } - _vpaddq_f32(a, b) + unsafe { _vpaddq_f32(a, b) } } #[doc = "Floating-point add pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(faddp))] -pub unsafe fn vpaddq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { +pub fn vpaddq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -16899,17 +15580,15 @@ pub unsafe fn vpaddq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { )] fn _vpaddq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t; } - _vpaddq_f64(a, b) + unsafe { _vpaddq_f64(a, b) } } #[doc = "Add Pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addp))] -pub unsafe fn vpaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { +pub fn vpaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -16917,17 +15596,15 @@ pub unsafe fn vpaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { )] fn _vpaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t; } - _vpaddq_s8(a, b) + unsafe { _vpaddq_s8(a, b) } } #[doc = "Add Pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addp))] -pub unsafe fn vpaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { +pub fn vpaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -16935,17 +15612,15 @@ pub unsafe fn vpaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { )] fn _vpaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t; } - _vpaddq_s16(a, b) + unsafe { _vpaddq_s16(a, b) } } #[doc = "Add Pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addp))] -pub unsafe fn vpaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { +pub fn vpaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -16953,17 +15628,15 @@ pub unsafe fn vpaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { )] fn _vpaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t; } - _vpaddq_s32(a, b) + unsafe { _vpaddq_s32(a, b) } } #[doc = "Add Pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addp))] -pub unsafe fn vpaddq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { +pub fn vpaddq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -16971,129 +15644,119 @@ pub unsafe fn vpaddq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { )] fn _vpaddq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t; } - _vpaddq_s64(a, b) + unsafe { _vpaddq_s64(a, b) } } #[doc = "Add Pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addp))] -pub unsafe fn vpaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { - transmute(vpaddq_s8(transmute(a), transmute(b))) +pub fn vpaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + unsafe { transmute(vpaddq_s8(transmute(a), transmute(b))) } } #[doc = "Add Pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addp))] -pub unsafe fn vpaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { +pub fn vpaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { let a: uint8x16_t = simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); let b: uint8x16_t = simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: uint8x16_t = transmute(vpaddq_s8(transmute(a), transmute(b))); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) + unsafe { + let ret_val: uint8x16_t = transmute(vpaddq_s8(transmute(a), transmute(b))); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } #[doc = "Add Pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addp))] -pub unsafe fn vpaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { - transmute(vpaddq_s16(transmute(a), transmute(b))) +pub fn vpaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + unsafe { transmute(vpaddq_s16(transmute(a), transmute(b))) } } #[doc = "Add Pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addp))] -pub unsafe fn vpaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { +pub fn vpaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); let b: uint16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: uint16x8_t = transmute(vpaddq_s16(transmute(a), transmute(b))); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: uint16x8_t = transmute(vpaddq_s16(transmute(a), transmute(b))); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Add Pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addp))] -pub unsafe fn vpaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { - transmute(vpaddq_s32(transmute(a), transmute(b))) +pub fn vpaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + unsafe { transmute(vpaddq_s32(transmute(a), transmute(b))) } } #[doc = "Add Pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addp))] -pub unsafe fn vpaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { +pub fn vpaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); let b: uint32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); - let ret_val: uint32x4_t = transmute(vpaddq_s32(transmute(a), transmute(b))); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + unsafe { + let ret_val: uint32x4_t = transmute(vpaddq_s32(transmute(a), transmute(b))); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Add Pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addp))] -pub unsafe fn vpaddq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { - transmute(vpaddq_s64(transmute(a), transmute(b))) +pub fn vpaddq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { + unsafe { transmute(vpaddq_s64(transmute(a), transmute(b))) } } #[doc = "Add Pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addp))] -pub unsafe fn vpaddq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { +pub fn vpaddq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]); let b: uint64x2_t = simd_shuffle!(b, b, [1, 0]); - let ret_val: uint64x2_t = transmute(vpaddq_s64(transmute(a), transmute(b))); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: uint64x2_t = transmute(vpaddq_s64(transmute(a), transmute(b))); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Floating-point add pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(fmaxp))] -pub unsafe fn vpmax_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { +pub fn vpmax_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -17101,17 +15764,15 @@ pub unsafe fn vpmax_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { )] fn _vpmax_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t; } - _vpmax_f16(a, b) + unsafe { _vpmax_f16(a, b) } } #[doc = "Floating-point add pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(fmaxp))] -pub unsafe fn vpmaxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { +pub fn vpmaxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -17119,17 +15780,15 @@ pub unsafe fn vpmaxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { )] fn _vpmaxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t; } - _vpmaxq_f16(a, b) + unsafe { _vpmaxq_f16(a, b) } } #[doc = "Floating-point add pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnm_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(fmaxnmp))] -pub unsafe fn vpmaxnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { +pub fn vpmaxnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -17137,17 +15796,15 @@ pub unsafe fn vpmaxnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { )] fn _vpmaxnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t; } - _vpmaxnm_f16(a, b) + unsafe { _vpmaxnm_f16(a, b) } } #[doc = "Floating-point add pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnmq_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(fmaxnmp))] -pub unsafe fn vpmaxnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { +pub fn vpmaxnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -17155,17 +15812,15 @@ pub unsafe fn vpmaxnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { )] fn _vpmaxnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t; } - _vpmaxnmq_f16(a, b) + unsafe { _vpmaxnmq_f16(a, b) } } #[doc = "Floating-point Maximum Number Pairwise (vector)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnm_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmaxnmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vpmaxnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { +pub fn vpmaxnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -17173,17 +15828,15 @@ pub unsafe fn vpmaxnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { )] fn _vpmaxnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t; } - _vpmaxnm_f32(a, b) + unsafe { _vpmaxnm_f32(a, b) } } #[doc = "Floating-point Maximum Number Pairwise (vector)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnmq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmaxnmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vpmaxnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { +pub fn vpmaxnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -17191,17 +15844,15 @@ pub unsafe fn vpmaxnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { )] fn _vpmaxnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t; } - _vpmaxnmq_f32(a, b) + unsafe { _vpmaxnmq_f32(a, b) } } #[doc = "Floating-point Maximum Number Pairwise (vector)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnmq_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmaxnmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vpmaxnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { +pub fn vpmaxnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -17209,17 +15860,15 @@ pub unsafe fn vpmaxnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { )] fn _vpmaxnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t; } - _vpmaxnmq_f64(a, b) + unsafe { _vpmaxnmq_f64(a, b) } } #[doc = "Floating-point maximum number pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnmqd_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmaxnmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vpmaxnmqd_f64(a: float64x2_t) -> f64 { +pub fn vpmaxnmqd_f64(a: float64x2_t) -> f64 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -17227,17 +15876,15 @@ pub unsafe fn vpmaxnmqd_f64(a: float64x2_t) -> f64 { )] fn _vpmaxnmqd_f64(a: float64x2_t) -> f64; } - _vpmaxnmqd_f64(a) + unsafe { _vpmaxnmqd_f64(a) } } #[doc = "Floating-point maximum number pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnms_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmaxnmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vpmaxnms_f32(a: float32x2_t) -> f32 { +pub fn vpmaxnms_f32(a: float32x2_t) -> f32 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -17245,17 +15892,15 @@ pub unsafe fn vpmaxnms_f32(a: float32x2_t) -> f32 { )] fn _vpmaxnms_f32(a: float32x2_t) -> f32; } - _vpmaxnms_f32(a) + unsafe { _vpmaxnms_f32(a) } } #[doc = "Folding maximum of adjacent pairs"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmaxp))] -pub unsafe fn vpmaxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { +pub fn vpmaxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -17263,17 +15908,15 @@ pub unsafe fn vpmaxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { )] fn _vpmaxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t; } - _vpmaxq_f32(a, b) + unsafe { _vpmaxq_f32(a, b) } } #[doc = "Folding maximum of adjacent pairs"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmaxp))] -pub unsafe fn vpmaxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { +pub fn vpmaxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -17281,17 +15924,15 @@ pub unsafe fn vpmaxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { )] fn _vpmaxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t; } - _vpmaxq_f64(a, b) + unsafe { _vpmaxq_f64(a, b) } } #[doc = "Folding maximum of adjacent pairs"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(smaxp))] -pub unsafe fn vpmaxq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { +pub fn vpmaxq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -17299,17 +15940,15 @@ pub unsafe fn vpmaxq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { )] fn _vpmaxq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t; } - _vpmaxq_s8(a, b) + unsafe { _vpmaxq_s8(a, b) } } #[doc = "Folding maximum of adjacent pairs"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(smaxp))] -pub unsafe fn vpmaxq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { +pub fn vpmaxq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -17317,17 +15956,15 @@ pub unsafe fn vpmaxq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { )] fn _vpmaxq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t; } - _vpmaxq_s16(a, b) + unsafe { _vpmaxq_s16(a, b) } } #[doc = "Folding maximum of adjacent pairs"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(smaxp))] -pub unsafe fn vpmaxq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { +pub fn vpmaxq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -17335,17 +15972,15 @@ pub unsafe fn vpmaxq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { )] fn _vpmaxq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t; } - _vpmaxq_s32(a, b) + unsafe { _vpmaxq_s32(a, b) } } #[doc = "Folding maximum of adjacent pairs"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(umaxp))] -pub unsafe fn vpmaxq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { +pub fn vpmaxq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -17353,17 +15988,15 @@ pub unsafe fn vpmaxq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { )] fn _vpmaxq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t; } - _vpmaxq_u8(a, b) + unsafe { _vpmaxq_u8(a, b) } } #[doc = "Folding maximum of adjacent pairs"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(umaxp))] -pub unsafe fn vpmaxq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { +pub fn vpmaxq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -17371,17 +16004,15 @@ pub unsafe fn vpmaxq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { )] fn _vpmaxq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t; } - _vpmaxq_u16(a, b) + unsafe { _vpmaxq_u16(a, b) } } #[doc = "Folding maximum of adjacent pairs"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(umaxp))] -pub unsafe fn vpmaxq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { +pub fn vpmaxq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -17389,17 +16020,15 @@ pub unsafe fn vpmaxq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { )] fn _vpmaxq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t; } - _vpmaxq_u32(a, b) + unsafe { _vpmaxq_u32(a, b) } } #[doc = "Floating-point maximum pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxqd_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmaxp))] -pub unsafe fn vpmaxqd_f64(a: float64x2_t) -> f64 { +pub fn vpmaxqd_f64(a: float64x2_t) -> f64 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -17407,17 +16036,15 @@ pub unsafe fn vpmaxqd_f64(a: float64x2_t) -> f64 { )] fn _vpmaxqd_f64(a: float64x2_t) -> f64; } - _vpmaxqd_f64(a) + unsafe { _vpmaxqd_f64(a) } } #[doc = "Floating-point maximum pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxs_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fmaxp))] -pub unsafe fn vpmaxs_f32(a: float32x2_t) -> f32 { +pub fn vpmaxs_f32(a: float32x2_t) -> f32 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -17425,17 +16052,15 @@ pub unsafe fn vpmaxs_f32(a: float32x2_t) -> f32 { )] fn _vpmaxs_f32(a: float32x2_t) -> f32; } - _vpmaxs_f32(a) + unsafe { _vpmaxs_f32(a) } } #[doc = "Floating-point add pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(fminp))] -pub unsafe fn vpmin_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { +pub fn vpmin_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -17443,17 +16068,15 @@ pub unsafe fn vpmin_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { )] fn _vpmin_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t; } - _vpmin_f16(a, b) + unsafe { _vpmin_f16(a, b) } } #[doc = "Floating-point add pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(fminp))] -pub unsafe fn vpminq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { +pub fn vpminq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -17461,17 +16084,15 @@ pub unsafe fn vpminq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { )] fn _vpminq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t; } - _vpminq_f16(a, b) + unsafe { _vpminq_f16(a, b) } } #[doc = "Floating-point add pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnm_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(fminnmp))] -pub unsafe fn vpminnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { +pub fn vpminnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -17479,17 +16100,15 @@ pub unsafe fn vpminnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { )] fn _vpminnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t; } - _vpminnm_f16(a, b) + unsafe { _vpminnm_f16(a, b) } } #[doc = "Floating-point add pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnmq_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(fminnmp))] -pub unsafe fn vpminnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { +pub fn vpminnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -17497,17 +16116,15 @@ pub unsafe fn vpminnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { )] fn _vpminnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t; } - _vpminnmq_f16(a, b) + unsafe { _vpminnmq_f16(a, b) } } #[doc = "Floating-point Minimum Number Pairwise (vector)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnm_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fminnmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vpminnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { +pub fn vpminnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -17515,17 +16132,15 @@ pub unsafe fn vpminnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { )] fn _vpminnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t; } - _vpminnm_f32(a, b) + unsafe { _vpminnm_f32(a, b) } } #[doc = "Floating-point Minimum Number Pairwise (vector)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnmq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fminnmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vpminnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { +pub fn vpminnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -17533,17 +16148,15 @@ pub unsafe fn vpminnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { )] fn _vpminnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t; } - _vpminnmq_f32(a, b) + unsafe { _vpminnmq_f32(a, b) } } #[doc = "Floating-point Minimum Number Pairwise (vector)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnmq_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fminnmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vpminnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { +pub fn vpminnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -17551,17 +16164,15 @@ pub unsafe fn vpminnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { )] fn _vpminnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t; } - _vpminnmq_f64(a, b) + unsafe { _vpminnmq_f64(a, b) } } #[doc = "Floating-point minimum number pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnmqd_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fminnmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vpminnmqd_f64(a: float64x2_t) -> f64 { +pub fn vpminnmqd_f64(a: float64x2_t) -> f64 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -17569,17 +16180,15 @@ pub unsafe fn vpminnmqd_f64(a: float64x2_t) -> f64 { )] fn _vpminnmqd_f64(a: float64x2_t) -> f64; } - _vpminnmqd_f64(a) + unsafe { _vpminnmqd_f64(a) } } #[doc = "Floating-point minimum number pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnms_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fminnmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vpminnms_f32(a: float32x2_t) -> f32 { +pub fn vpminnms_f32(a: float32x2_t) -> f32 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -17587,17 +16196,15 @@ pub unsafe fn vpminnms_f32(a: float32x2_t) -> f32 { )] fn _vpminnms_f32(a: float32x2_t) -> f32; } - _vpminnms_f32(a) + unsafe { _vpminnms_f32(a) } } #[doc = "Folding minimum of adjacent pairs"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fminp))] -pub unsafe fn vpminq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { +pub fn vpminq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -17605,17 +16212,15 @@ pub unsafe fn vpminq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { )] fn _vpminq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t; } - _vpminq_f32(a, b) + unsafe { _vpminq_f32(a, b) } } #[doc = "Folding minimum of adjacent pairs"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fminp))] -pub unsafe fn vpminq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { +pub fn vpminq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -17623,17 +16228,15 @@ pub unsafe fn vpminq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { )] fn _vpminq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t; } - _vpminq_f64(a, b) + unsafe { _vpminq_f64(a, b) } } #[doc = "Folding minimum of adjacent pairs"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(sminp))] -pub unsafe fn vpminq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { +pub fn vpminq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -17641,17 +16244,15 @@ pub unsafe fn vpminq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { )] fn _vpminq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t; } - _vpminq_s8(a, b) + unsafe { _vpminq_s8(a, b) } } #[doc = "Folding minimum of adjacent pairs"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(sminp))] -pub unsafe fn vpminq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { +pub fn vpminq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -17659,17 +16260,15 @@ pub unsafe fn vpminq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { )] fn _vpminq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t; } - _vpminq_s16(a, b) + unsafe { _vpminq_s16(a, b) } } #[doc = "Folding minimum of adjacent pairs"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(sminp))] -pub unsafe fn vpminq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { +pub fn vpminq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -17677,17 +16276,15 @@ pub unsafe fn vpminq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { )] fn _vpminq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t; } - _vpminq_s32(a, b) + unsafe { _vpminq_s32(a, b) } } #[doc = "Folding minimum of adjacent pairs"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(uminp))] -pub unsafe fn vpminq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { +pub fn vpminq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -17695,17 +16292,15 @@ pub unsafe fn vpminq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { )] fn _vpminq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t; } - _vpminq_u8(a, b) + unsafe { _vpminq_u8(a, b) } } #[doc = "Folding minimum of adjacent pairs"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(uminp))] -pub unsafe fn vpminq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { +pub fn vpminq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -17713,17 +16308,15 @@ pub unsafe fn vpminq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { )] fn _vpminq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t; } - _vpminq_u16(a, b) + unsafe { _vpminq_u16(a, b) } } #[doc = "Folding minimum of adjacent pairs"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(uminp))] -pub unsafe fn vpminq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { +pub fn vpminq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -17731,17 +16324,15 @@ pub unsafe fn vpminq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { )] fn _vpminq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t; } - _vpminq_u32(a, b) + unsafe { _vpminq_u32(a, b) } } #[doc = "Floating-point minimum pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminqd_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fminp))] -pub unsafe fn vpminqd_f64(a: float64x2_t) -> f64 { +pub fn vpminqd_f64(a: float64x2_t) -> f64 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -17749,17 +16340,15 @@ pub unsafe fn vpminqd_f64(a: float64x2_t) -> f64 { )] fn _vpminqd_f64(a: float64x2_t) -> f64; } - _vpminqd_f64(a) + unsafe { _vpminqd_f64(a) } } #[doc = "Floating-point minimum pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmins_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fminp))] -pub unsafe fn vpmins_f32(a: float32x2_t) -> f32 { +pub fn vpmins_f32(a: float32x2_t) -> f32 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -17767,17 +16356,15 @@ pub unsafe fn vpmins_f32(a: float32x2_t) -> f32 { )] fn _vpmins_f32(a: float32x2_t) -> f32; } - _vpmins_f32(a) + unsafe { _vpmins_f32(a) } } #[doc = "Signed saturating Absolute value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabs_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sqabs))] -pub unsafe fn vqabs_s64(a: int64x1_t) -> int64x1_t { +pub fn vqabs_s64(a: int64x1_t) -> int64x1_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -17785,17 +16372,15 @@ pub unsafe fn vqabs_s64(a: int64x1_t) -> int64x1_t { )] fn _vqabs_s64(a: int64x1_t) -> int64x1_t; } - _vqabs_s64(a) + unsafe { _vqabs_s64(a) } } #[doc = "Signed saturating Absolute value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsq_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sqabs))] -pub unsafe fn vqabsq_s64(a: int64x2_t) -> int64x2_t { +pub fn vqabsq_s64(a: int64x2_t) -> int64x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -17803,39 +16388,33 @@ pub unsafe fn vqabsq_s64(a: int64x2_t) -> int64x2_t { )] fn _vqabsq_s64(a: int64x2_t) -> int64x2_t; } - _vqabsq_s64(a) + unsafe { _vqabsq_s64(a) } } #[doc = "Signed saturating absolute value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsb_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sqabs))] -pub unsafe fn vqabsb_s8(a: i8) -> i8 { - simd_extract!(vqabs_s8(vdup_n_s8(a)), 0) +pub fn vqabsb_s8(a: i8) -> i8 { + unsafe { simd_extract!(vqabs_s8(vdup_n_s8(a)), 0) } } #[doc = "Signed saturating absolute value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsh_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sqabs))] -pub unsafe fn vqabsh_s16(a: i16) -> i16 { - simd_extract!(vqabs_s16(vdup_n_s16(a)), 0) +pub fn vqabsh_s16(a: i16) -> i16 { + unsafe { simd_extract!(vqabs_s16(vdup_n_s16(a)), 0) } } #[doc = "Signed saturating absolute value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabss_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sqabs))] -pub unsafe fn vqabss_s32(a: i32) -> i32 { +pub fn vqabss_s32(a: i32) -> i32 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -17843,17 +16422,15 @@ pub unsafe fn vqabss_s32(a: i32) -> i32 { )] fn _vqabss_s32(a: i32) -> i32; } - _vqabss_s32(a) + unsafe { _vqabss_s32(a) } } #[doc = "Signed saturating absolute value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsd_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sqabs))] -pub unsafe fn vqabsd_s64(a: i64) -> i64 { +pub fn vqabsd_s64(a: i64) -> i64 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -17861,69 +16438,59 @@ pub unsafe fn vqabsd_s64(a: i64) -> i64 { )] fn _vqabsd_s64(a: i64) -> i64; } - _vqabsd_s64(a) + unsafe { _vqabsd_s64(a) } } #[doc = "Saturating add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddb_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(sqadd))] -pub unsafe fn vqaddb_s8(a: i8, b: i8) -> i8 { +pub fn vqaddb_s8(a: i8, b: i8) -> i8 { let a: int8x8_t = vdup_n_s8(a); let b: int8x8_t = vdup_n_s8(b); - simd_extract!(vqadd_s8(a, b), 0) + unsafe { simd_extract!(vqadd_s8(a, b), 0) } } #[doc = "Saturating add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddh_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(sqadd))] -pub unsafe fn vqaddh_s16(a: i16, b: i16) -> i16 { +pub fn vqaddh_s16(a: i16, b: i16) -> i16 { let a: int16x4_t = vdup_n_s16(a); let b: int16x4_t = vdup_n_s16(b); - simd_extract!(vqadd_s16(a, b), 0) + unsafe { simd_extract!(vqadd_s16(a, b), 0) } } #[doc = "Saturating add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddb_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(uqadd))] -pub unsafe fn vqaddb_u8(a: u8, b: u8) -> u8 { +pub fn vqaddb_u8(a: u8, b: u8) -> u8 { let a: uint8x8_t = vdup_n_u8(a); let b: uint8x8_t = vdup_n_u8(b); - simd_extract!(vqadd_u8(a, b), 0) + unsafe { simd_extract!(vqadd_u8(a, b), 0) } } #[doc = "Saturating add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddh_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(uqadd))] -pub unsafe fn vqaddh_u16(a: u16, b: u16) -> u16 { +pub fn vqaddh_u16(a: u16, b: u16) -> u16 { let a: uint16x4_t = vdup_n_u16(a); let b: uint16x4_t = vdup_n_u16(b); - simd_extract!(vqadd_u16(a, b), 0) + unsafe { simd_extract!(vqadd_u16(a, b), 0) } } #[doc = "Saturating add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadds_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(sqadd))] -pub unsafe fn vqadds_s32(a: i32, b: i32) -> i32 { +pub fn vqadds_s32(a: i32, b: i32) -> i32 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -17931,17 +16498,15 @@ pub unsafe fn vqadds_s32(a: i32, b: i32) -> i32 { )] fn _vqadds_s32(a: i32, b: i32) -> i32; } - _vqadds_s32(a, b) + unsafe { _vqadds_s32(a, b) } } #[doc = "Saturating add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddd_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(sqadd))] -pub unsafe fn vqaddd_s64(a: i64, b: i64) -> i64 { +pub fn vqaddd_s64(a: i64, b: i64) -> i64 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -17949,17 +16514,15 @@ pub unsafe fn vqaddd_s64(a: i64, b: i64) -> i64 { )] fn _vqaddd_s64(a: i64, b: i64) -> i64; } - _vqaddd_s64(a, b) + unsafe { _vqaddd_s64(a, b) } } #[doc = "Saturating add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadds_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(uqadd))] -pub unsafe fn vqadds_u32(a: u32, b: u32) -> u32 { +pub fn vqadds_u32(a: u32, b: u32) -> u32 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -17967,17 +16530,15 @@ pub unsafe fn vqadds_u32(a: u32, b: u32) -> u32 { )] fn _vqadds_u32(a: u32, b: u32) -> u32; } - _vqadds_u32(a, b) + unsafe { _vqadds_u32(a, b) } } #[doc = "Saturating add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddd_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(uqadd))] -pub unsafe fn vqaddd_u64(a: u64, b: u64) -> u64 { +pub fn vqaddd_u64(a: u64, b: u64) -> u64 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -17985,804 +16546,676 @@ pub unsafe fn vqaddd_u64(a: u64, b: u64) -> u64 { )] fn _vqaddd_u64(a: u64, b: u64) -> u64; } - _vqaddd_u64(a, b) + unsafe { _vqaddd_u64(a, b) } } #[doc = "Signed saturating doubling multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_lane_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmlal2, N = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmlal_high_lane_s16( - a: int32x4_t, - b: int16x8_t, - c: int16x4_t, -) -> int32x4_t { +pub fn vqdmlal_high_lane_s16(a: int32x4_t, b: int16x8_t, c: int16x4_t) -> int32x4_t { static_assert_uimm_bits!(N, 2); vqaddq_s32(a, vqdmull_high_lane_s16::(b, c)) } #[doc = "Signed saturating doubling multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_laneq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmlal2, N = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmlal_high_laneq_s16( - a: int32x4_t, - b: int16x8_t, - c: int16x8_t, -) -> int32x4_t { +pub fn vqdmlal_high_laneq_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t { static_assert_uimm_bits!(N, 3); vqaddq_s32(a, vqdmull_high_laneq_s16::(b, c)) } #[doc = "Signed saturating doubling multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_lane_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmlal2, N = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmlal_high_lane_s32( - a: int64x2_t, - b: int32x4_t, - c: int32x2_t, -) -> int64x2_t { +pub fn vqdmlal_high_lane_s32(a: int64x2_t, b: int32x4_t, c: int32x2_t) -> int64x2_t { static_assert_uimm_bits!(N, 1); vqaddq_s64(a, vqdmull_high_lane_s32::(b, c)) } #[doc = "Signed saturating doubling multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_laneq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmlal2, N = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmlal_high_laneq_s32( - a: int64x2_t, - b: int32x4_t, - c: int32x4_t, -) -> int64x2_t { +pub fn vqdmlal_high_laneq_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t { static_assert_uimm_bits!(N, 2); vqaddq_s64(a, vqdmull_high_laneq_s32::(b, c)) } #[doc = "Signed saturating doubling multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_n_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmlal2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmlal_high_n_s16(a: int32x4_t, b: int16x8_t, c: i16) -> int32x4_t { +pub fn vqdmlal_high_n_s16(a: int32x4_t, b: int16x8_t, c: i16) -> int32x4_t { vqaddq_s32(a, vqdmull_high_n_s16(b, c)) } #[doc = "Signed saturating doubling multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmlal2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmlal_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t { +pub fn vqdmlal_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t { vqaddq_s32(a, vqdmull_high_s16(b, c)) } #[doc = "Signed saturating doubling multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_n_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmlal2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmlal_high_n_s32(a: int64x2_t, b: int32x4_t, c: i32) -> int64x2_t { +pub fn vqdmlal_high_n_s32(a: int64x2_t, b: int32x4_t, c: i32) -> int64x2_t { vqaddq_s64(a, vqdmull_high_n_s32(b, c)) } #[doc = "Signed saturating doubling multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmlal2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmlal_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t { +pub fn vqdmlal_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t { vqaddq_s64(a, vqdmull_high_s32(b, c)) } #[doc = "Vector widening saturating doubling multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_laneq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmlal, N = 2))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmlal_laneq_s16( - a: int32x4_t, - b: int16x4_t, - c: int16x8_t, -) -> int32x4_t { +pub fn vqdmlal_laneq_s16(a: int32x4_t, b: int16x4_t, c: int16x8_t) -> int32x4_t { static_assert_uimm_bits!(N, 3); vqaddq_s32(a, vqdmull_laneq_s16::(b, c)) } #[doc = "Vector widening saturating doubling multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_laneq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmlal, N = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmlal_laneq_s32( - a: int64x2_t, - b: int32x2_t, - c: int32x4_t, -) -> int64x2_t { +pub fn vqdmlal_laneq_s32(a: int64x2_t, b: int32x2_t, c: int32x4_t) -> int64x2_t { static_assert_uimm_bits!(N, 2); vqaddq_s64(a, vqdmull_laneq_s32::(b, c)) } #[doc = "Signed saturating doubling multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlalh_lane_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmlal, LANE = 0))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmlalh_lane_s16(a: i32, b: i16, c: int16x4_t) -> i32 { +pub fn vqdmlalh_lane_s16(a: i32, b: i16, c: int16x4_t) -> i32 { static_assert_uimm_bits!(LANE, 2); - vqdmlalh_s16(a, b, simd_extract!(c, LANE as u32)) + unsafe { vqdmlalh_s16(a, b, simd_extract!(c, LANE as u32)) } } #[doc = "Signed saturating doubling multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlalh_laneq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmlal, LANE = 0))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmlalh_laneq_s16(a: i32, b: i16, c: int16x8_t) -> i32 { +pub fn vqdmlalh_laneq_s16(a: i32, b: i16, c: int16x8_t) -> i32 { static_assert_uimm_bits!(LANE, 3); - vqdmlalh_s16(a, b, simd_extract!(c, LANE as u32)) + unsafe { vqdmlalh_s16(a, b, simd_extract!(c, LANE as u32)) } } #[doc = "Signed saturating doubling multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlals_lane_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmlal, LANE = 0))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmlals_lane_s32(a: i64, b: i32, c: int32x2_t) -> i64 { +pub fn vqdmlals_lane_s32(a: i64, b: i32, c: int32x2_t) -> i64 { static_assert_uimm_bits!(LANE, 1); - vqdmlals_s32(a, b, simd_extract!(c, LANE as u32)) + unsafe { vqdmlals_s32(a, b, simd_extract!(c, LANE as u32)) } } #[doc = "Signed saturating doubling multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlals_laneq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmlal, LANE = 0))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmlals_laneq_s32(a: i64, b: i32, c: int32x4_t) -> i64 { +pub fn vqdmlals_laneq_s32(a: i64, b: i32, c: int32x4_t) -> i64 { static_assert_uimm_bits!(LANE, 2); - vqdmlals_s32(a, b, simd_extract!(c, LANE as u32)) + unsafe { vqdmlals_s32(a, b, simd_extract!(c, LANE as u32)) } } #[doc = "Signed saturating doubling multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlalh_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmlal))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmlalh_s16(a: i32, b: i16, c: i16) -> i32 { +pub fn vqdmlalh_s16(a: i32, b: i16, c: i16) -> i32 { let x: int32x4_t = vqdmull_s16(vdup_n_s16(b), vdup_n_s16(c)); - vqadds_s32(a, simd_extract!(x, 0)) + unsafe { vqadds_s32(a, simd_extract!(x, 0)) } } #[doc = "Signed saturating doubling multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlals_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmlal))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmlals_s32(a: i64, b: i32, c: i32) -> i64 { +pub fn vqdmlals_s32(a: i64, b: i32, c: i32) -> i64 { let x: i64 = vqaddd_s64(a, vqdmulls_s32(b, c)); x as i64 } #[doc = "Signed saturating doubling multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_lane_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmlsl2, N = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmlsl_high_lane_s16( - a: int32x4_t, - b: int16x8_t, - c: int16x4_t, -) -> int32x4_t { +pub fn vqdmlsl_high_lane_s16(a: int32x4_t, b: int16x8_t, c: int16x4_t) -> int32x4_t { static_assert_uimm_bits!(N, 2); vqsubq_s32(a, vqdmull_high_lane_s16::(b, c)) } #[doc = "Signed saturating doubling multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_laneq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmlsl2, N = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmlsl_high_laneq_s16( - a: int32x4_t, - b: int16x8_t, - c: int16x8_t, -) -> int32x4_t { +pub fn vqdmlsl_high_laneq_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t { static_assert_uimm_bits!(N, 3); vqsubq_s32(a, vqdmull_high_laneq_s16::(b, c)) } #[doc = "Signed saturating doubling multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_lane_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmlsl2, N = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmlsl_high_lane_s32( - a: int64x2_t, - b: int32x4_t, - c: int32x2_t, -) -> int64x2_t { +pub fn vqdmlsl_high_lane_s32(a: int64x2_t, b: int32x4_t, c: int32x2_t) -> int64x2_t { static_assert_uimm_bits!(N, 1); vqsubq_s64(a, vqdmull_high_lane_s32::(b, c)) } #[doc = "Signed saturating doubling multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_laneq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmlsl2, N = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmlsl_high_laneq_s32( - a: int64x2_t, - b: int32x4_t, - c: int32x4_t, -) -> int64x2_t { +pub fn vqdmlsl_high_laneq_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t { static_assert_uimm_bits!(N, 2); vqsubq_s64(a, vqdmull_high_laneq_s32::(b, c)) } #[doc = "Signed saturating doubling multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_n_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmlsl2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmlsl_high_n_s16(a: int32x4_t, b: int16x8_t, c: i16) -> int32x4_t { +pub fn vqdmlsl_high_n_s16(a: int32x4_t, b: int16x8_t, c: i16) -> int32x4_t { vqsubq_s32(a, vqdmull_high_n_s16(b, c)) } #[doc = "Signed saturating doubling multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmlsl2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmlsl_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t { +pub fn vqdmlsl_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t { vqsubq_s32(a, vqdmull_high_s16(b, c)) } #[doc = "Signed saturating doubling multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_n_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmlsl2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmlsl_high_n_s32(a: int64x2_t, b: int32x4_t, c: i32) -> int64x2_t { +pub fn vqdmlsl_high_n_s32(a: int64x2_t, b: int32x4_t, c: i32) -> int64x2_t { vqsubq_s64(a, vqdmull_high_n_s32(b, c)) } #[doc = "Signed saturating doubling multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmlsl2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmlsl_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t { +pub fn vqdmlsl_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t { vqsubq_s64(a, vqdmull_high_s32(b, c)) } #[doc = "Vector widening saturating doubling multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_laneq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmlsl, N = 2))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmlsl_laneq_s16( - a: int32x4_t, - b: int16x4_t, - c: int16x8_t, -) -> int32x4_t { +pub fn vqdmlsl_laneq_s16(a: int32x4_t, b: int16x4_t, c: int16x8_t) -> int32x4_t { static_assert_uimm_bits!(N, 3); vqsubq_s32(a, vqdmull_laneq_s16::(b, c)) } #[doc = "Vector widening saturating doubling multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_laneq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmlsl, N = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmlsl_laneq_s32( - a: int64x2_t, - b: int32x2_t, - c: int32x4_t, -) -> int64x2_t { +pub fn vqdmlsl_laneq_s32(a: int64x2_t, b: int32x2_t, c: int32x4_t) -> int64x2_t { static_assert_uimm_bits!(N, 2); vqsubq_s64(a, vqdmull_laneq_s32::(b, c)) } #[doc = "Signed saturating doubling multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlslh_lane_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmlsl, LANE = 0))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmlslh_lane_s16(a: i32, b: i16, c: int16x4_t) -> i32 { +pub fn vqdmlslh_lane_s16(a: i32, b: i16, c: int16x4_t) -> i32 { static_assert_uimm_bits!(LANE, 2); - vqdmlslh_s16(a, b, simd_extract!(c, LANE as u32)) + unsafe { vqdmlslh_s16(a, b, simd_extract!(c, LANE as u32)) } } #[doc = "Signed saturating doubling multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlslh_laneq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmlsl, LANE = 0))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmlslh_laneq_s16(a: i32, b: i16, c: int16x8_t) -> i32 { +pub fn vqdmlslh_laneq_s16(a: i32, b: i16, c: int16x8_t) -> i32 { static_assert_uimm_bits!(LANE, 3); - vqdmlslh_s16(a, b, simd_extract!(c, LANE as u32)) + unsafe { vqdmlslh_s16(a, b, simd_extract!(c, LANE as u32)) } } #[doc = "Signed saturating doubling multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsls_lane_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmlsl, LANE = 0))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmlsls_lane_s32(a: i64, b: i32, c: int32x2_t) -> i64 { +pub fn vqdmlsls_lane_s32(a: i64, b: i32, c: int32x2_t) -> i64 { static_assert_uimm_bits!(LANE, 1); - vqdmlsls_s32(a, b, simd_extract!(c, LANE as u32)) + unsafe { vqdmlsls_s32(a, b, simd_extract!(c, LANE as u32)) } } #[doc = "Signed saturating doubling multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsls_laneq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmlsl, LANE = 0))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmlsls_laneq_s32(a: i64, b: i32, c: int32x4_t) -> i64 { +pub fn vqdmlsls_laneq_s32(a: i64, b: i32, c: int32x4_t) -> i64 { static_assert_uimm_bits!(LANE, 2); - vqdmlsls_s32(a, b, simd_extract!(c, LANE as u32)) + unsafe { vqdmlsls_s32(a, b, simd_extract!(c, LANE as u32)) } } #[doc = "Signed saturating doubling multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlslh_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmlsl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmlslh_s16(a: i32, b: i16, c: i16) -> i32 { +pub fn vqdmlslh_s16(a: i32, b: i16, c: i16) -> i32 { let x: int32x4_t = vqdmull_s16(vdup_n_s16(b), vdup_n_s16(c)); - vqsubs_s32(a, simd_extract!(x, 0)) + unsafe { vqsubs_s32(a, simd_extract!(x, 0)) } } #[doc = "Signed saturating doubling multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsls_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmlsl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmlsls_s32(a: i64, b: i32, c: i32) -> i64 { +pub fn vqdmlsls_s32(a: i64, b: i32, c: i32) -> i64 { let x: i64 = vqsubd_s64(a, vqdmulls_s32(b, c)); x as i64 } #[doc = "Vector saturating doubling multiply high by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_lane_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmulh, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmulh_lane_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { +pub fn vqdmulh_lane_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { static_assert_uimm_bits!(LANE, 2); - vqdmulh_s16(a, vdup_n_s16(simd_extract!(b, LANE as u32))) + unsafe { vqdmulh_s16(a, vdup_n_s16(simd_extract!(b, LANE as u32))) } } #[doc = "Vector saturating doubling multiply high by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_lane_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmulh, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmulhq_lane_s16(a: int16x8_t, b: int16x4_t) -> int16x8_t { +pub fn vqdmulhq_lane_s16(a: int16x8_t, b: int16x4_t) -> int16x8_t { static_assert_uimm_bits!(LANE, 2); - vqdmulhq_s16(a, vdupq_n_s16(simd_extract!(b, LANE as u32))) + unsafe { vqdmulhq_s16(a, vdupq_n_s16(simd_extract!(b, LANE as u32))) } } #[doc = "Vector saturating doubling multiply high by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_lane_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmulh, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmulh_lane_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { +pub fn vqdmulh_lane_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { static_assert_uimm_bits!(LANE, 1); - vqdmulh_s32(a, vdup_n_s32(simd_extract!(b, LANE as u32))) + unsafe { vqdmulh_s32(a, vdup_n_s32(simd_extract!(b, LANE as u32))) } } #[doc = "Vector saturating doubling multiply high by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_lane_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmulh, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmulhq_lane_s32(a: int32x4_t, b: int32x2_t) -> int32x4_t { +pub fn vqdmulhq_lane_s32(a: int32x4_t, b: int32x2_t) -> int32x4_t { static_assert_uimm_bits!(LANE, 1); - vqdmulhq_s32(a, vdupq_n_s32(simd_extract!(b, LANE as u32))) + unsafe { vqdmulhq_s32(a, vdupq_n_s32(simd_extract!(b, LANE as u32))) } } #[doc = "Signed saturating doubling multiply returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhh_lane_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmulh, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmulhh_lane_s16(a: i16, b: int16x4_t) -> i16 { +pub fn vqdmulhh_lane_s16(a: i16, b: int16x4_t) -> i16 { static_assert_uimm_bits!(N, 2); - let b: i16 = simd_extract!(b, N as u32); - vqdmulhh_s16(a, b) + unsafe { + let b: i16 = simd_extract!(b, N as u32); + vqdmulhh_s16(a, b) + } } #[doc = "Signed saturating doubling multiply returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhh_laneq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmulh, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmulhh_laneq_s16(a: i16, b: int16x8_t) -> i16 { +pub fn vqdmulhh_laneq_s16(a: i16, b: int16x8_t) -> i16 { static_assert_uimm_bits!(N, 3); - let b: i16 = simd_extract!(b, N as u32); - vqdmulhh_s16(a, b) + unsafe { + let b: i16 = simd_extract!(b, N as u32); + vqdmulhh_s16(a, b) + } } #[doc = "Signed saturating doubling multiply returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhh_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmulh))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmulhh_s16(a: i16, b: i16) -> i16 { +pub fn vqdmulhh_s16(a: i16, b: i16) -> i16 { let a: int16x4_t = vdup_n_s16(a); let b: int16x4_t = vdup_n_s16(b); - simd_extract!(vqdmulh_s16(a, b), 0) + unsafe { simd_extract!(vqdmulh_s16(a, b), 0) } } #[doc = "Signed saturating doubling multiply returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhs_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmulh))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmulhs_s32(a: i32, b: i32) -> i32 { +pub fn vqdmulhs_s32(a: i32, b: i32) -> i32 { let a: int32x2_t = vdup_n_s32(a); let b: int32x2_t = vdup_n_s32(b); - simd_extract!(vqdmulh_s32(a, b), 0) + unsafe { simd_extract!(vqdmulh_s32(a, b), 0) } } #[doc = "Signed saturating doubling multiply returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhs_lane_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmulh, N = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmulhs_lane_s32(a: i32, b: int32x2_t) -> i32 { +pub fn vqdmulhs_lane_s32(a: i32, b: int32x2_t) -> i32 { static_assert_uimm_bits!(N, 1); - let b: i32 = simd_extract!(b, N as u32); - vqdmulhs_s32(a, b) + unsafe { + let b: i32 = simd_extract!(b, N as u32); + vqdmulhs_s32(a, b) + } } #[doc = "Signed saturating doubling multiply returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhs_laneq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmulh, N = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmulhs_laneq_s32(a: i32, b: int32x4_t) -> i32 { +pub fn vqdmulhs_laneq_s32(a: i32, b: int32x4_t) -> i32 { static_assert_uimm_bits!(N, 2); - let b: i32 = simd_extract!(b, N as u32); - vqdmulhs_s32(a, b) + unsafe { + let b: i32 = simd_extract!(b, N as u32); + vqdmulhs_s32(a, b) + } } #[doc = "Signed saturating doubling multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_lane_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmull2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmull_high_lane_s16(a: int16x8_t, b: int16x4_t) -> int32x4_t { +pub fn vqdmull_high_lane_s16(a: int16x8_t, b: int16x4_t) -> int32x4_t { static_assert_uimm_bits!(N, 2); - let a: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); - let b: int16x4_t = simd_shuffle!(b, b, [N as u32, N as u32, N as u32, N as u32]); - vqdmull_s16(a, b) + unsafe { + let a: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); + let b: int16x4_t = simd_shuffle!(b, b, [N as u32, N as u32, N as u32, N as u32]); + vqdmull_s16(a, b) + } } #[doc = "Signed saturating doubling multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_laneq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmull2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmull_high_laneq_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t { +pub fn vqdmull_high_laneq_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t { static_assert_uimm_bits!(N, 2); - let a: int32x2_t = simd_shuffle!(a, a, [2, 3]); - let b: int32x2_t = simd_shuffle!(b, b, [N as u32, N as u32]); - vqdmull_s32(a, b) + unsafe { + let a: int32x2_t = simd_shuffle!(a, a, [2, 3]); + let b: int32x2_t = simd_shuffle!(b, b, [N as u32, N as u32]); + vqdmull_s32(a, b) + } } #[doc = "Signed saturating doubling multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_lane_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmull2, N = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmull_high_lane_s32(a: int32x4_t, b: int32x2_t) -> int64x2_t { +pub fn vqdmull_high_lane_s32(a: int32x4_t, b: int32x2_t) -> int64x2_t { static_assert_uimm_bits!(N, 1); - let a: int32x2_t = simd_shuffle!(a, a, [2, 3]); - let b: int32x2_t = simd_shuffle!(b, b, [N as u32, N as u32]); - vqdmull_s32(a, b) + unsafe { + let a: int32x2_t = simd_shuffle!(a, a, [2, 3]); + let b: int32x2_t = simd_shuffle!(b, b, [N as u32, N as u32]); + vqdmull_s32(a, b) + } } #[doc = "Signed saturating doubling multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_laneq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmull2, N = 4))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmull_high_laneq_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t { +pub fn vqdmull_high_laneq_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t { static_assert_uimm_bits!(N, 3); - let a: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); - let b: int16x4_t = simd_shuffle!(b, b, [N as u32, N as u32, N as u32, N as u32]); - vqdmull_s16(a, b) + unsafe { + let a: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); + let b: int16x4_t = simd_shuffle!(b, b, [N as u32, N as u32, N as u32, N as u32]); + vqdmull_s16(a, b) + } } #[doc = "Signed saturating doubling multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_n_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmull2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmull_high_n_s16(a: int16x8_t, b: i16) -> int32x4_t { - let a: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); - let b: int16x4_t = vdup_n_s16(b); - vqdmull_s16(a, b) +pub fn vqdmull_high_n_s16(a: int16x8_t, b: i16) -> int32x4_t { + unsafe { + let a: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); + let b: int16x4_t = vdup_n_s16(b); + vqdmull_s16(a, b) + } } #[doc = "Signed saturating doubling multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_n_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmull2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmull_high_n_s32(a: int32x4_t, b: i32) -> int64x2_t { - let a: int32x2_t = simd_shuffle!(a, a, [2, 3]); - let b: int32x2_t = vdup_n_s32(b); - vqdmull_s32(a, b) +pub fn vqdmull_high_n_s32(a: int32x4_t, b: i32) -> int64x2_t { + unsafe { + let a: int32x2_t = simd_shuffle!(a, a, [2, 3]); + let b: int32x2_t = vdup_n_s32(b); + vqdmull_s32(a, b) + } } #[doc = "Signed saturating doubling multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmull2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmull_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t { - let a: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); - let b: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); - vqdmull_s16(a, b) +pub fn vqdmull_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t { + unsafe { + let a: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); + let b: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); + vqdmull_s16(a, b) + } } #[doc = "Signed saturating doubling multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmull2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmull_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t { - let a: int32x2_t = simd_shuffle!(a, a, [2, 3]); - let b: int32x2_t = simd_shuffle!(b, b, [2, 3]); - vqdmull_s32(a, b) +pub fn vqdmull_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t { + unsafe { + let a: int32x2_t = simd_shuffle!(a, a, [2, 3]); + let b: int32x2_t = simd_shuffle!(b, b, [2, 3]); + vqdmull_s32(a, b) + } } #[doc = "Vector saturating doubling long multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_laneq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmull, N = 4))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmull_laneq_s16(a: int16x4_t, b: int16x8_t) -> int32x4_t { +pub fn vqdmull_laneq_s16(a: int16x4_t, b: int16x8_t) -> int32x4_t { static_assert_uimm_bits!(N, 3); - let b: int16x4_t = simd_shuffle!(b, b, [N as u32, N as u32, N as u32, N as u32]); - vqdmull_s16(a, b) + unsafe { + let b: int16x4_t = simd_shuffle!(b, b, [N as u32, N as u32, N as u32, N as u32]); + vqdmull_s16(a, b) + } } #[doc = "Vector saturating doubling long multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_laneq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmull, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmull_laneq_s32(a: int32x2_t, b: int32x4_t) -> int64x2_t { +pub fn vqdmull_laneq_s32(a: int32x2_t, b: int32x4_t) -> int64x2_t { static_assert_uimm_bits!(N, 2); - let b: int32x2_t = simd_shuffle!(b, b, [N as u32, N as u32]); - vqdmull_s32(a, b) + unsafe { + let b: int32x2_t = simd_shuffle!(b, b, [N as u32, N as u32]); + vqdmull_s32(a, b) + } } #[doc = "Signed saturating doubling multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmullh_lane_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmull, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmullh_lane_s16(a: i16, b: int16x4_t) -> i32 { +pub fn vqdmullh_lane_s16(a: i16, b: int16x4_t) -> i32 { static_assert_uimm_bits!(N, 2); - let b: i16 = simd_extract!(b, N as u32); - vqdmullh_s16(a, b) + unsafe { + let b: i16 = simd_extract!(b, N as u32); + vqdmullh_s16(a, b) + } } #[doc = "Signed saturating doubling multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulls_laneq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmull, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmulls_laneq_s32(a: i32, b: int32x4_t) -> i64 { +pub fn vqdmulls_laneq_s32(a: i32, b: int32x4_t) -> i64 { static_assert_uimm_bits!(N, 2); - let b: i32 = simd_extract!(b, N as u32); - vqdmulls_s32(a, b) + unsafe { + let b: i32 = simd_extract!(b, N as u32); + vqdmulls_s32(a, b) + } } #[doc = "Signed saturating doubling multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmullh_laneq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmull, N = 4))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmullh_laneq_s16(a: i16, b: int16x8_t) -> i32 { +pub fn vqdmullh_laneq_s16(a: i16, b: int16x8_t) -> i32 { static_assert_uimm_bits!(N, 3); - let b: i16 = simd_extract!(b, N as u32); - vqdmullh_s16(a, b) + unsafe { + let b: i16 = simd_extract!(b, N as u32); + vqdmullh_s16(a, b) + } } #[doc = "Signed saturating doubling multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmullh_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmull))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmullh_s16(a: i16, b: i16) -> i32 { +pub fn vqdmullh_s16(a: i16, b: i16) -> i32 { let a: int16x4_t = vdup_n_s16(a); let b: int16x4_t = vdup_n_s16(b); - simd_extract!(vqdmull_s16(a, b), 0) + unsafe { simd_extract!(vqdmull_s16(a, b), 0) } } #[doc = "Signed saturating doubling multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulls_lane_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmull, N = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmulls_lane_s32(a: i32, b: int32x2_t) -> i64 { +pub fn vqdmulls_lane_s32(a: i32, b: int32x2_t) -> i64 { static_assert_uimm_bits!(N, 1); - let b: i32 = simd_extract!(b, N as u32); - vqdmulls_s32(a, b) + unsafe { + let b: i32 = simd_extract!(b, N as u32); + vqdmulls_s32(a, b) + } } #[doc = "Signed saturating doubling multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulls_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqdmull))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmulls_s32(a: i32, b: i32) -> i64 { +pub fn vqdmulls_s32(a: i32, b: i32) -> i64 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -18790,91 +17223,81 @@ pub unsafe fn vqdmulls_s32(a: i32, b: i32) -> i64 { )] fn _vqdmulls_s32(a: i32, b: i32) -> i64; } - _vqdmulls_s32(a, b) + unsafe { _vqdmulls_s32(a, b) } } #[doc = "Signed saturating extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_high_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqxtn2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqmovn_high_s16(a: int8x8_t, b: int16x8_t) -> int8x16_t { - simd_shuffle!( - a, - vqmovn_s16(b), - [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] - ) +pub fn vqmovn_high_s16(a: int8x8_t, b: int16x8_t) -> int8x16_t { + unsafe { + simd_shuffle!( + a, + vqmovn_s16(b), + [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] + ) + } } #[doc = "Signed saturating extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_high_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqxtn2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqmovn_high_s32(a: int16x4_t, b: int32x4_t) -> int16x8_t { - simd_shuffle!(a, vqmovn_s32(b), [0, 1, 2, 3, 4, 5, 6, 7]) +pub fn vqmovn_high_s32(a: int16x4_t, b: int32x4_t) -> int16x8_t { + unsafe { simd_shuffle!(a, vqmovn_s32(b), [0, 1, 2, 3, 4, 5, 6, 7]) } } #[doc = "Signed saturating extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_high_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqxtn2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqmovn_high_s64(a: int32x2_t, b: int64x2_t) -> int32x4_t { - simd_shuffle!(a, vqmovn_s64(b), [0, 1, 2, 3]) +pub fn vqmovn_high_s64(a: int32x2_t, b: int64x2_t) -> int32x4_t { + unsafe { simd_shuffle!(a, vqmovn_s64(b), [0, 1, 2, 3]) } } #[doc = "Signed saturating extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_high_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(uqxtn2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqmovn_high_u16(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t { - simd_shuffle!( - a, - vqmovn_u16(b), - [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] - ) +pub fn vqmovn_high_u16(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t { + unsafe { + simd_shuffle!( + a, + vqmovn_u16(b), + [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] + ) + } } #[doc = "Signed saturating extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_high_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(uqxtn2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqmovn_high_u32(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t { - simd_shuffle!(a, vqmovn_u32(b), [0, 1, 2, 3, 4, 5, 6, 7]) +pub fn vqmovn_high_u32(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t { + unsafe { simd_shuffle!(a, vqmovn_u32(b), [0, 1, 2, 3, 4, 5, 6, 7]) } } #[doc = "Signed saturating extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_high_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(uqxtn2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqmovn_high_u64(a: uint32x2_t, b: uint64x2_t) -> uint32x4_t { - simd_shuffle!(a, vqmovn_u64(b), [0, 1, 2, 3]) +pub fn vqmovn_high_u64(a: uint32x2_t, b: uint64x2_t) -> uint32x4_t { + unsafe { simd_shuffle!(a, vqmovn_u64(b), [0, 1, 2, 3]) } } #[doc = "Saturating extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovnd_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqxtn))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqmovnd_s64(a: i64) -> i32 { +pub fn vqmovnd_s64(a: i64) -> i32 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -18882,17 +17305,15 @@ pub unsafe fn vqmovnd_s64(a: i64) -> i32 { )] fn _vqmovnd_s64(a: i64) -> i32; } - _vqmovnd_s64(a) + unsafe { _vqmovnd_s64(a) } } #[doc = "Saturating extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovnd_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(uqxtn))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqmovnd_u64(a: u64) -> u32 { +pub fn vqmovnd_u64(a: u64) -> u32 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -18900,131 +17321,111 @@ pub unsafe fn vqmovnd_u64(a: u64) -> u32 { )] fn _vqmovnd_u64(a: u64) -> u32; } - _vqmovnd_u64(a) + unsafe { _vqmovnd_u64(a) } } #[doc = "Saturating extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovnh_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqxtn))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqmovnh_s16(a: i16) -> i8 { - simd_extract!(vqmovn_s16(vdupq_n_s16(a)), 0) +pub fn vqmovnh_s16(a: i16) -> i8 { + unsafe { simd_extract!(vqmovn_s16(vdupq_n_s16(a)), 0) } } #[doc = "Saturating extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovns_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqxtn))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqmovns_s32(a: i32) -> i16 { - simd_extract!(vqmovn_s32(vdupq_n_s32(a)), 0) +pub fn vqmovns_s32(a: i32) -> i16 { + unsafe { simd_extract!(vqmovn_s32(vdupq_n_s32(a)), 0) } } #[doc = "Saturating extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovnh_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(uqxtn))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqmovnh_u16(a: u16) -> u8 { - simd_extract!(vqmovn_u16(vdupq_n_u16(a)), 0) +pub fn vqmovnh_u16(a: u16) -> u8 { + unsafe { simd_extract!(vqmovn_u16(vdupq_n_u16(a)), 0) } } #[doc = "Saturating extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovns_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(uqxtn))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqmovns_u32(a: u32) -> u16 { - simd_extract!(vqmovn_u32(vdupq_n_u32(a)), 0) +pub fn vqmovns_u32(a: u32) -> u16 { + unsafe { simd_extract!(vqmovn_u32(vdupq_n_u32(a)), 0) } } #[doc = "Signed saturating extract unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_high_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqxtun2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqmovun_high_s16(a: uint8x8_t, b: int16x8_t) -> uint8x16_t { - simd_shuffle!( - a, - vqmovun_s16(b), - [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] - ) +pub fn vqmovun_high_s16(a: uint8x8_t, b: int16x8_t) -> uint8x16_t { + unsafe { + simd_shuffle!( + a, + vqmovun_s16(b), + [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] + ) + } } #[doc = "Signed saturating extract unsigned narrow"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_high_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_high_s32)"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqxtun2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqmovun_high_s32(a: uint16x4_t, b: int32x4_t) -> uint16x8_t { - simd_shuffle!(a, vqmovun_s32(b), [0, 1, 2, 3, 4, 5, 6, 7]) +pub fn vqmovun_high_s32(a: uint16x4_t, b: int32x4_t) -> uint16x8_t { + unsafe { simd_shuffle!(a, vqmovun_s32(b), [0, 1, 2, 3, 4, 5, 6, 7]) } } #[doc = "Signed saturating extract unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_high_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqxtun2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqmovun_high_s64(a: uint32x2_t, b: int64x2_t) -> uint32x4_t { - simd_shuffle!(a, vqmovun_s64(b), [0, 1, 2, 3]) +pub fn vqmovun_high_s64(a: uint32x2_t, b: int64x2_t) -> uint32x4_t { + unsafe { simd_shuffle!(a, vqmovun_s64(b), [0, 1, 2, 3]) } } #[doc = "Signed saturating extract unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovunh_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqxtun))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqmovunh_s16(a: i16) -> u8 { - simd_extract!(vqmovun_s16(vdupq_n_s16(a)), 0) +pub fn vqmovunh_s16(a: i16) -> u8 { + unsafe { simd_extract!(vqmovun_s16(vdupq_n_s16(a)), 0) } } #[doc = "Signed saturating extract unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovuns_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqxtun))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqmovuns_s32(a: i32) -> u16 { - simd_extract!(vqmovun_s32(vdupq_n_s32(a)), 0) +pub fn vqmovuns_s32(a: i32) -> u16 { + unsafe { simd_extract!(vqmovun_s32(vdupq_n_s32(a)), 0) } } #[doc = "Signed saturating extract unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovund_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqxtun))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqmovund_s64(a: i64) -> u32 { - simd_extract!(vqmovun_s64(vdupq_n_s64(a)), 0) +pub fn vqmovund_s64(a: i64) -> u32 { + unsafe { simd_extract!(vqmovun_s64(vdupq_n_s64(a)), 0) } } #[doc = "Signed saturating negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqneg_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(sqneg))] -pub unsafe fn vqneg_s64(a: int64x1_t) -> int64x1_t { +pub fn vqneg_s64(a: int64x1_t) -> int64x1_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -19032,17 +17433,15 @@ pub unsafe fn vqneg_s64(a: int64x1_t) -> int64x1_t { )] fn _vqneg_s64(a: int64x1_t) -> int64x1_t; } - _vqneg_s64(a) + unsafe { _vqneg_s64(a) } } #[doc = "Signed saturating negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegq_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(sqneg))] -pub unsafe fn vqnegq_s64(a: int64x2_t) -> int64x2_t { +pub fn vqnegq_s64(a: int64x2_t) -> int64x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -19050,231 +17449,193 @@ pub unsafe fn vqnegq_s64(a: int64x2_t) -> int64x2_t { )] fn _vqnegq_s64(a: int64x2_t) -> int64x2_t; } - _vqnegq_s64(a) + unsafe { _vqnegq_s64(a) } } #[doc = "Signed saturating negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegb_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(sqneg))] -pub unsafe fn vqnegb_s8(a: i8) -> i8 { - simd_extract!(vqneg_s8(vdup_n_s8(a)), 0) +pub fn vqnegb_s8(a: i8) -> i8 { + unsafe { simd_extract!(vqneg_s8(vdup_n_s8(a)), 0) } } #[doc = "Signed saturating negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegh_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(sqneg))] -pub unsafe fn vqnegh_s16(a: i16) -> i16 { - simd_extract!(vqneg_s16(vdup_n_s16(a)), 0) +pub fn vqnegh_s16(a: i16) -> i16 { + unsafe { simd_extract!(vqneg_s16(vdup_n_s16(a)), 0) } } #[doc = "Signed saturating negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegs_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(sqneg))] -pub unsafe fn vqnegs_s32(a: i32) -> i32 { - simd_extract!(vqneg_s32(vdup_n_s32(a)), 0) +pub fn vqnegs_s32(a: i32) -> i32 { + unsafe { simd_extract!(vqneg_s32(vdup_n_s32(a)), 0) } } #[doc = "Signed saturating negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegd_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(sqneg))] -pub unsafe fn vqnegd_s64(a: i64) -> i64 { - simd_extract!(vqneg_s64(vdup_n_s64(a)), 0) +pub fn vqnegd_s64(a: i64) -> i64 { + unsafe { simd_extract!(vqneg_s64(vdup_n_s64(a)), 0) } } #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlah_lane_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] -pub unsafe fn vqrdmlah_lane_s16( - a: int16x4_t, - b: int16x4_t, - c: int16x4_t, -) -> int16x4_t { +pub fn vqrdmlah_lane_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t { static_assert_uimm_bits!(LANE, 2); - let c: int16x4_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vqrdmlah_s16(a, b, c) + unsafe { + let c: int16x4_t = + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); + vqrdmlah_s16(a, b, c) + } } #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlah_lane_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] -pub unsafe fn vqrdmlah_lane_s32( - a: int32x2_t, - b: int32x2_t, - c: int32x2_t, -) -> int32x2_t { +pub fn vqrdmlah_lane_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t { static_assert_uimm_bits!(LANE, 1); - let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); - vqrdmlah_s32(a, b, c) + unsafe { + let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); + vqrdmlah_s32(a, b, c) + } } #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlah_laneq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] -pub unsafe fn vqrdmlah_laneq_s16( - a: int16x4_t, - b: int16x4_t, - c: int16x8_t, -) -> int16x4_t { +pub fn vqrdmlah_laneq_s16(a: int16x4_t, b: int16x4_t, c: int16x8_t) -> int16x4_t { static_assert_uimm_bits!(LANE, 3); - let c: int16x4_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vqrdmlah_s16(a, b, c) + unsafe { + let c: int16x4_t = + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); + vqrdmlah_s16(a, b, c) + } } #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlah_laneq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] -pub unsafe fn vqrdmlah_laneq_s32( - a: int32x2_t, - b: int32x2_t, - c: int32x4_t, -) -> int32x2_t { +pub fn vqrdmlah_laneq_s32(a: int32x2_t, b: int32x2_t, c: int32x4_t) -> int32x2_t { static_assert_uimm_bits!(LANE, 2); - let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); - vqrdmlah_s32(a, b, c) + unsafe { + let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); + vqrdmlah_s32(a, b, c) + } } #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahq_lane_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] -pub unsafe fn vqrdmlahq_lane_s16( - a: int16x8_t, - b: int16x8_t, - c: int16x4_t, -) -> int16x8_t { +pub fn vqrdmlahq_lane_s16(a: int16x8_t, b: int16x8_t, c: int16x4_t) -> int16x8_t { static_assert_uimm_bits!(LANE, 2); - let c: int16x8_t = simd_shuffle!( - c, - c, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ); - vqrdmlahq_s16(a, b, c) + unsafe { + let c: int16x8_t = simd_shuffle!( + c, + c, + [ + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32 + ] + ); + vqrdmlahq_s16(a, b, c) + } } #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahq_lane_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] -pub unsafe fn vqrdmlahq_lane_s32( - a: int32x4_t, - b: int32x4_t, - c: int32x2_t, -) -> int32x4_t { +pub fn vqrdmlahq_lane_s32(a: int32x4_t, b: int32x4_t, c: int32x2_t) -> int32x4_t { static_assert_uimm_bits!(LANE, 1); - let c: int32x4_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vqrdmlahq_s32(a, b, c) + unsafe { + let c: int32x4_t = + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); + vqrdmlahq_s32(a, b, c) + } } #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahq_laneq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] -pub unsafe fn vqrdmlahq_laneq_s16( - a: int16x8_t, - b: int16x8_t, - c: int16x8_t, -) -> int16x8_t { +pub fn vqrdmlahq_laneq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t { static_assert_uimm_bits!(LANE, 3); - let c: int16x8_t = simd_shuffle!( - c, - c, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ); - vqrdmlahq_s16(a, b, c) + unsafe { + let c: int16x8_t = simd_shuffle!( + c, + c, + [ + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32 + ] + ); + vqrdmlahq_s16(a, b, c) + } } #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahq_laneq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] -pub unsafe fn vqrdmlahq_laneq_s32( - a: int32x4_t, - b: int32x4_t, - c: int32x4_t, -) -> int32x4_t { +pub fn vqrdmlahq_laneq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t { static_assert_uimm_bits!(LANE, 2); - let c: int32x4_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vqrdmlahq_s32(a, b, c) + unsafe { + let c: int32x4_t = + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); + vqrdmlahq_s32(a, b, c) + } } #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlah_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlah))] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] -pub unsafe fn vqrdmlah_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t { +pub fn vqrdmlah_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -19282,17 +17643,15 @@ pub unsafe fn vqrdmlah_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_ )] fn _vqrdmlah_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t; } - _vqrdmlah_s16(a, b, c) + unsafe { _vqrdmlah_s16(a, b, c) } } #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlah))] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] -pub unsafe fn vqrdmlahq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t { +pub fn vqrdmlahq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -19300,17 +17659,15 @@ pub unsafe fn vqrdmlahq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8 )] fn _vqrdmlahq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t; } - _vqrdmlahq_s16(a, b, c) + unsafe { _vqrdmlahq_s16(a, b, c) } } #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlah_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlah))] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] -pub unsafe fn vqrdmlah_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t { +pub fn vqrdmlah_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -19318,17 +17675,15 @@ pub unsafe fn vqrdmlah_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_ )] fn _vqrdmlah_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t; } - _vqrdmlah_s32(a, b, c) + unsafe { _vqrdmlah_s32(a, b, c) } } #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlah))] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] -pub unsafe fn vqrdmlahq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t { +pub fn vqrdmlahq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -19336,267 +17691,225 @@ pub unsafe fn vqrdmlahq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4 )] fn _vqrdmlahq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t; } - _vqrdmlahq_s32(a, b, c) + unsafe { _vqrdmlahq_s32(a, b, c) } } #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahh_lane_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] -pub unsafe fn vqrdmlahh_lane_s16(a: i16, b: i16, c: int16x4_t) -> i16 { +pub fn vqrdmlahh_lane_s16(a: i16, b: i16, c: int16x4_t) -> i16 { static_assert_uimm_bits!(LANE, 2); - vqrdmlahh_s16(a, b, simd_extract!(c, LANE as u32)) + unsafe { vqrdmlahh_s16(a, b, simd_extract!(c, LANE as u32)) } } #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahh_laneq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] -pub unsafe fn vqrdmlahh_laneq_s16(a: i16, b: i16, c: int16x8_t) -> i16 { +pub fn vqrdmlahh_laneq_s16(a: i16, b: i16, c: int16x8_t) -> i16 { static_assert_uimm_bits!(LANE, 3); - vqrdmlahh_s16(a, b, simd_extract!(c, LANE as u32)) + unsafe { vqrdmlahh_s16(a, b, simd_extract!(c, LANE as u32)) } } #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahs_lane_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] -pub unsafe fn vqrdmlahs_lane_s32(a: i32, b: i32, c: int32x2_t) -> i32 { +pub fn vqrdmlahs_lane_s32(a: i32, b: i32, c: int32x2_t) -> i32 { static_assert_uimm_bits!(LANE, 1); - vqrdmlahs_s32(a, b, simd_extract!(c, LANE as u32)) + unsafe { vqrdmlahs_s32(a, b, simd_extract!(c, LANE as u32)) } } #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahs_laneq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] -pub unsafe fn vqrdmlahs_laneq_s32(a: i32, b: i32, c: int32x4_t) -> i32 { +pub fn vqrdmlahs_laneq_s32(a: i32, b: i32, c: int32x4_t) -> i32 { static_assert_uimm_bits!(LANE, 2); - vqrdmlahs_s32(a, b, simd_extract!(c, LANE as u32)) + unsafe { vqrdmlahs_s32(a, b, simd_extract!(c, LANE as u32)) } } #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahh_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlah))] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] -pub unsafe fn vqrdmlahh_s16(a: i16, b: i16, c: i16) -> i16 { +pub fn vqrdmlahh_s16(a: i16, b: i16, c: i16) -> i16 { let a: int16x4_t = vdup_n_s16(a); let b: int16x4_t = vdup_n_s16(b); let c: int16x4_t = vdup_n_s16(c); - simd_extract!(vqrdmlah_s16(a, b, c), 0) + unsafe { simd_extract!(vqrdmlah_s16(a, b, c), 0) } } #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahs_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlah))] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] -pub unsafe fn vqrdmlahs_s32(a: i32, b: i32, c: i32) -> i32 { +pub fn vqrdmlahs_s32(a: i32, b: i32, c: i32) -> i32 { let a: int32x2_t = vdup_n_s32(a); let b: int32x2_t = vdup_n_s32(b); let c: int32x2_t = vdup_n_s32(c); - simd_extract!(vqrdmlah_s32(a, b, c), 0) + unsafe { simd_extract!(vqrdmlah_s32(a, b, c), 0) } } #[doc = "Signed saturating rounding doubling multiply subtract returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlsh_lane_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] -pub unsafe fn vqrdmlsh_lane_s16( - a: int16x4_t, - b: int16x4_t, - c: int16x4_t, -) -> int16x4_t { +pub fn vqrdmlsh_lane_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t { static_assert_uimm_bits!(LANE, 2); - let c: int16x4_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vqrdmlsh_s16(a, b, c) + unsafe { + let c: int16x4_t = + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); + vqrdmlsh_s16(a, b, c) + } } #[doc = "Signed saturating rounding doubling multiply subtract returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlsh_lane_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] -pub unsafe fn vqrdmlsh_lane_s32( - a: int32x2_t, - b: int32x2_t, - c: int32x2_t, -) -> int32x2_t { +pub fn vqrdmlsh_lane_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t { static_assert_uimm_bits!(LANE, 1); - let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); - vqrdmlsh_s32(a, b, c) + unsafe { + let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); + vqrdmlsh_s32(a, b, c) + } } #[doc = "Signed saturating rounding doubling multiply subtract returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlsh_laneq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] -pub unsafe fn vqrdmlsh_laneq_s16( - a: int16x4_t, - b: int16x4_t, - c: int16x8_t, -) -> int16x4_t { +pub fn vqrdmlsh_laneq_s16(a: int16x4_t, b: int16x4_t, c: int16x8_t) -> int16x4_t { static_assert_uimm_bits!(LANE, 3); - let c: int16x4_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vqrdmlsh_s16(a, b, c) + unsafe { + let c: int16x4_t = + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); + vqrdmlsh_s16(a, b, c) + } } #[doc = "Signed saturating rounding doubling multiply subtract returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlsh_laneq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] -pub unsafe fn vqrdmlsh_laneq_s32( - a: int32x2_t, - b: int32x2_t, - c: int32x4_t, -) -> int32x2_t { +pub fn vqrdmlsh_laneq_s32(a: int32x2_t, b: int32x2_t, c: int32x4_t) -> int32x2_t { static_assert_uimm_bits!(LANE, 2); - let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); - vqrdmlsh_s32(a, b, c) + unsafe { + let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); + vqrdmlsh_s32(a, b, c) + } } #[doc = "Signed saturating rounding doubling multiply subtract returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshq_lane_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] -pub unsafe fn vqrdmlshq_lane_s16( - a: int16x8_t, - b: int16x8_t, - c: int16x4_t, -) -> int16x8_t { +pub fn vqrdmlshq_lane_s16(a: int16x8_t, b: int16x8_t, c: int16x4_t) -> int16x8_t { static_assert_uimm_bits!(LANE, 2); - let c: int16x8_t = simd_shuffle!( - c, - c, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ); - vqrdmlshq_s16(a, b, c) + unsafe { + let c: int16x8_t = simd_shuffle!( + c, + c, + [ + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32 + ] + ); + vqrdmlshq_s16(a, b, c) + } } #[doc = "Signed saturating rounding doubling multiply subtract returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshq_lane_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] -pub unsafe fn vqrdmlshq_lane_s32( - a: int32x4_t, - b: int32x4_t, - c: int32x2_t, -) -> int32x4_t { +pub fn vqrdmlshq_lane_s32(a: int32x4_t, b: int32x4_t, c: int32x2_t) -> int32x4_t { static_assert_uimm_bits!(LANE, 1); - let c: int32x4_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vqrdmlshq_s32(a, b, c) + unsafe { + let c: int32x4_t = + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); + vqrdmlshq_s32(a, b, c) + } } #[doc = "Signed saturating rounding doubling multiply subtract returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshq_laneq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] -pub unsafe fn vqrdmlshq_laneq_s16( - a: int16x8_t, - b: int16x8_t, - c: int16x8_t, -) -> int16x8_t { +pub fn vqrdmlshq_laneq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t { static_assert_uimm_bits!(LANE, 3); - let c: int16x8_t = simd_shuffle!( - c, - c, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ); - vqrdmlshq_s16(a, b, c) + unsafe { + let c: int16x8_t = simd_shuffle!( + c, + c, + [ + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32 + ] + ); + vqrdmlshq_s16(a, b, c) + } } #[doc = "Signed saturating rounding doubling multiply subtract returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshq_laneq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] -pub unsafe fn vqrdmlshq_laneq_s32( - a: int32x4_t, - b: int32x4_t, - c: int32x4_t, -) -> int32x4_t { +pub fn vqrdmlshq_laneq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t { static_assert_uimm_bits!(LANE, 2); - let c: int32x4_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vqrdmlshq_s32(a, b, c) + unsafe { + let c: int32x4_t = + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); + vqrdmlshq_s32(a, b, c) + } } #[doc = "Signed saturating rounding doubling multiply subtract returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlsh_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlsh))] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] -pub unsafe fn vqrdmlsh_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t { +pub fn vqrdmlsh_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -19604,17 +17917,15 @@ pub unsafe fn vqrdmlsh_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_ )] fn _vqrdmlsh_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t; } - _vqrdmlsh_s16(a, b, c) + unsafe { _vqrdmlsh_s16(a, b, c) } } #[doc = "Signed saturating rounding doubling multiply subtract returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlsh))] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] -pub unsafe fn vqrdmlshq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t { +pub fn vqrdmlshq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -19622,17 +17933,15 @@ pub unsafe fn vqrdmlshq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8 )] fn _vqrdmlshq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t; } - _vqrdmlshq_s16(a, b, c) + unsafe { _vqrdmlshq_s16(a, b, c) } } #[doc = "Signed saturating rounding doubling multiply subtract returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlsh_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlsh))] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] -pub unsafe fn vqrdmlsh_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t { +pub fn vqrdmlsh_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -19640,17 +17949,15 @@ pub unsafe fn vqrdmlsh_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_ )] fn _vqrdmlsh_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t; } - _vqrdmlsh_s32(a, b, c) + unsafe { _vqrdmlsh_s32(a, b, c) } } #[doc = "Signed saturating rounding doubling multiply subtract returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlsh))] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] -pub unsafe fn vqrdmlshq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t { +pub fn vqrdmlshq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -19658,223 +17965,189 @@ pub unsafe fn vqrdmlshq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4 )] fn _vqrdmlshq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t; } - _vqrdmlshq_s32(a, b, c) + unsafe { _vqrdmlshq_s32(a, b, c) } } #[doc = "Signed saturating rounding doubling multiply subtract returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshh_lane_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] -pub unsafe fn vqrdmlshh_lane_s16(a: i16, b: i16, c: int16x4_t) -> i16 { +pub fn vqrdmlshh_lane_s16(a: i16, b: i16, c: int16x4_t) -> i16 { static_assert_uimm_bits!(LANE, 2); - vqrdmlshh_s16(a, b, simd_extract!(c, LANE as u32)) + unsafe { vqrdmlshh_s16(a, b, simd_extract!(c, LANE as u32)) } } #[doc = "Signed saturating rounding doubling multiply subtract returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshh_laneq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] -pub unsafe fn vqrdmlshh_laneq_s16(a: i16, b: i16, c: int16x8_t) -> i16 { +pub fn vqrdmlshh_laneq_s16(a: i16, b: i16, c: int16x8_t) -> i16 { static_assert_uimm_bits!(LANE, 3); - vqrdmlshh_s16(a, b, simd_extract!(c, LANE as u32)) + unsafe { vqrdmlshh_s16(a, b, simd_extract!(c, LANE as u32)) } } #[doc = "Signed saturating rounding doubling multiply subtract returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshs_lane_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] -pub unsafe fn vqrdmlshs_lane_s32(a: i32, b: i32, c: int32x2_t) -> i32 { +pub fn vqrdmlshs_lane_s32(a: i32, b: i32, c: int32x2_t) -> i32 { static_assert_uimm_bits!(LANE, 1); - vqrdmlshs_s32(a, b, simd_extract!(c, LANE as u32)) + unsafe { vqrdmlshs_s32(a, b, simd_extract!(c, LANE as u32)) } } #[doc = "Signed saturating rounding doubling multiply subtract returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshs_laneq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] -pub unsafe fn vqrdmlshs_laneq_s32(a: i32, b: i32, c: int32x4_t) -> i32 { +pub fn vqrdmlshs_laneq_s32(a: i32, b: i32, c: int32x4_t) -> i32 { static_assert_uimm_bits!(LANE, 2); - vqrdmlshs_s32(a, b, simd_extract!(c, LANE as u32)) + unsafe { vqrdmlshs_s32(a, b, simd_extract!(c, LANE as u32)) } } #[doc = "Signed saturating rounding doubling multiply subtract returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshh_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlsh))] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] -pub unsafe fn vqrdmlshh_s16(a: i16, b: i16, c: i16) -> i16 { +pub fn vqrdmlshh_s16(a: i16, b: i16, c: i16) -> i16 { let a: int16x4_t = vdup_n_s16(a); let b: int16x4_t = vdup_n_s16(b); let c: int16x4_t = vdup_n_s16(c); - simd_extract!(vqrdmlsh_s16(a, b, c), 0) + unsafe { simd_extract!(vqrdmlsh_s16(a, b, c), 0) } } #[doc = "Signed saturating rounding doubling multiply subtract returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshs_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "rdm")] #[cfg_attr(test, assert_instr(sqrdmlsh))] #[stable(feature = "rdm_intrinsics", since = "1.62.0")] -pub unsafe fn vqrdmlshs_s32(a: i32, b: i32, c: i32) -> i32 { +pub fn vqrdmlshs_s32(a: i32, b: i32, c: i32) -> i32 { let a: int32x2_t = vdup_n_s32(a); let b: int32x2_t = vdup_n_s32(b); let c: int32x2_t = vdup_n_s32(c); - simd_extract!(vqrdmlsh_s32(a, b, c), 0) + unsafe { simd_extract!(vqrdmlsh_s32(a, b, c), 0) } } #[doc = "Signed saturating rounding doubling multiply returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhh_lane_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqrdmulh, LANE = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqrdmulhh_lane_s16(a: i16, b: int16x4_t) -> i16 { +pub fn vqrdmulhh_lane_s16(a: i16, b: int16x4_t) -> i16 { static_assert_uimm_bits!(LANE, 2); - vqrdmulhh_s16(a, simd_extract!(b, LANE as u32)) + unsafe { vqrdmulhh_s16(a, simd_extract!(b, LANE as u32)) } } #[doc = "Signed saturating rounding doubling multiply returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhh_laneq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqrdmulh, LANE = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqrdmulhh_laneq_s16(a: i16, b: int16x8_t) -> i16 { +pub fn vqrdmulhh_laneq_s16(a: i16, b: int16x8_t) -> i16 { static_assert_uimm_bits!(LANE, 3); - vqrdmulhh_s16(a, simd_extract!(b, LANE as u32)) + unsafe { vqrdmulhh_s16(a, simd_extract!(b, LANE as u32)) } } #[doc = "Signed saturating rounding doubling multiply returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhs_lane_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqrdmulh, LANE = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqrdmulhs_lane_s32(a: i32, b: int32x2_t) -> i32 { +pub fn vqrdmulhs_lane_s32(a: i32, b: int32x2_t) -> i32 { static_assert_uimm_bits!(LANE, 1); - vqrdmulhs_s32(a, simd_extract!(b, LANE as u32)) + unsafe { vqrdmulhs_s32(a, simd_extract!(b, LANE as u32)) } } #[doc = "Signed saturating rounding doubling multiply returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhs_laneq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqrdmulh, LANE = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqrdmulhs_laneq_s32(a: i32, b: int32x4_t) -> i32 { +pub fn vqrdmulhs_laneq_s32(a: i32, b: int32x4_t) -> i32 { static_assert_uimm_bits!(LANE, 2); - vqrdmulhs_s32(a, simd_extract!(b, LANE as u32)) + unsafe { vqrdmulhs_s32(a, simd_extract!(b, LANE as u32)) } } #[doc = "Signed saturating rounding doubling multiply returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhh_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqrdmulh))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqrdmulhh_s16(a: i16, b: i16) -> i16 { - simd_extract!(vqrdmulh_s16(vdup_n_s16(a), vdup_n_s16(b)), 0) +pub fn vqrdmulhh_s16(a: i16, b: i16) -> i16 { + unsafe { simd_extract!(vqrdmulh_s16(vdup_n_s16(a), vdup_n_s16(b)), 0) } } #[doc = "Signed saturating rounding doubling multiply returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhs_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqrdmulh))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqrdmulhs_s32(a: i32, b: i32) -> i32 { - simd_extract!(vqrdmulh_s32(vdup_n_s32(a), vdup_n_s32(b)), 0) +pub fn vqrdmulhs_s32(a: i32, b: i32) -> i32 { + unsafe { simd_extract!(vqrdmulh_s32(vdup_n_s32(a), vdup_n_s32(b)), 0) } } #[doc = "Signed saturating rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlb_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqrshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqrshlb_s8(a: i8, b: i8) -> i8 { +pub fn vqrshlb_s8(a: i8, b: i8) -> i8 { let a: int8x8_t = vdup_n_s8(a); let b: int8x8_t = vdup_n_s8(b); - simd_extract!(vqrshl_s8(a, b), 0) + unsafe { simd_extract!(vqrshl_s8(a, b), 0) } } #[doc = "Signed saturating rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlh_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqrshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqrshlh_s16(a: i16, b: i16) -> i16 { +pub fn vqrshlh_s16(a: i16, b: i16) -> i16 { let a: int16x4_t = vdup_n_s16(a); let b: int16x4_t = vdup_n_s16(b); - simd_extract!(vqrshl_s16(a, b), 0) + unsafe { simd_extract!(vqrshl_s16(a, b), 0) } } #[doc = "Unsigned signed saturating rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlb_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(uqrshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqrshlb_u8(a: u8, b: i8) -> u8 { +pub fn vqrshlb_u8(a: u8, b: i8) -> u8 { let a: uint8x8_t = vdup_n_u8(a); let b: int8x8_t = vdup_n_s8(b); - simd_extract!(vqrshl_u8(a, b), 0) + unsafe { simd_extract!(vqrshl_u8(a, b), 0) } } #[doc = "Unsigned signed saturating rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlh_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(uqrshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqrshlh_u16(a: u16, b: i16) -> u16 { +pub fn vqrshlh_u16(a: u16, b: i16) -> u16 { let a: uint16x4_t = vdup_n_u16(a); let b: int16x4_t = vdup_n_s16(b); - simd_extract!(vqrshl_u16(a, b), 0) + unsafe { simd_extract!(vqrshl_u16(a, b), 0) } } #[doc = "Signed saturating rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshld_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqrshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqrshld_s64(a: i64, b: i64) -> i64 { +pub fn vqrshld_s64(a: i64, b: i64) -> i64 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -19882,17 +18155,15 @@ pub unsafe fn vqrshld_s64(a: i64, b: i64) -> i64 { )] fn _vqrshld_s64(a: i64, b: i64) -> i64; } - _vqrshld_s64(a, b) + unsafe { _vqrshld_s64(a, b) } } #[doc = "Signed saturating rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshls_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqrshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqrshls_s32(a: i32, b: i32) -> i32 { +pub fn vqrshls_s32(a: i32, b: i32) -> i32 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -19900,17 +18171,15 @@ pub unsafe fn vqrshls_s32(a: i32, b: i32) -> i32 { )] fn _vqrshls_s32(a: i32, b: i32) -> i32; } - _vqrshls_s32(a, b) + unsafe { _vqrshls_s32(a, b) } } #[doc = "Unsigned signed saturating rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshls_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(uqrshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqrshls_u32(a: u32, b: i32) -> u32 { +pub fn vqrshls_u32(a: u32, b: i32) -> u32 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -19918,17 +18187,15 @@ pub unsafe fn vqrshls_u32(a: u32, b: i32) -> u32 { )] fn _vqrshls_u32(a: u32, b: i32) -> u32; } - _vqrshls_u32(a, b) + unsafe { _vqrshls_u32(a, b) } } #[doc = "Unsigned signed saturating rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshld_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(uqrshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqrshld_u64(a: u64, b: i64) -> u64 { +pub fn vqrshld_u64(a: u64, b: i64) -> u64 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -19936,448 +18203,388 @@ pub unsafe fn vqrshld_u64(a: u64, b: i64) -> u64 { )] fn _vqrshld_u64(a: u64, b: i64) -> u64; } - _vqrshld_u64(a, b) + unsafe { _vqrshld_u64(a, b) } } #[doc = "Signed saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_high_n_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqrshrn2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqrshrn_high_n_s16(a: int8x8_t, b: int16x8_t) -> int8x16_t { +pub fn vqrshrn_high_n_s16(a: int8x8_t, b: int16x8_t) -> int8x16_t { static_assert!(N >= 1 && N <= 8); - simd_shuffle!( - a, - vqrshrn_n_s16::(b), - [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] - ) + unsafe { + simd_shuffle!( + a, + vqrshrn_n_s16::(b), + [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] + ) + } } #[doc = "Signed saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_high_n_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqrshrn2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqrshrn_high_n_s32(a: int16x4_t, b: int32x4_t) -> int16x8_t { +pub fn vqrshrn_high_n_s32(a: int16x4_t, b: int32x4_t) -> int16x8_t { static_assert!(N >= 1 && N <= 16); - simd_shuffle!(a, vqrshrn_n_s32::(b), [0, 1, 2, 3, 4, 5, 6, 7]) + unsafe { simd_shuffle!(a, vqrshrn_n_s32::(b), [0, 1, 2, 3, 4, 5, 6, 7]) } } #[doc = "Signed saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_high_n_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqrshrn2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqrshrn_high_n_s64(a: int32x2_t, b: int64x2_t) -> int32x4_t { +pub fn vqrshrn_high_n_s64(a: int32x2_t, b: int64x2_t) -> int32x4_t { static_assert!(N >= 1 && N <= 32); - simd_shuffle!(a, vqrshrn_n_s64::(b), [0, 1, 2, 3]) + unsafe { simd_shuffle!(a, vqrshrn_n_s64::(b), [0, 1, 2, 3]) } } #[doc = "Unsigned saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_high_n_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(uqrshrn2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqrshrn_high_n_u16(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t { +pub fn vqrshrn_high_n_u16(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t { static_assert!(N >= 1 && N <= 8); - simd_shuffle!( - a, - vqrshrn_n_u16::(b), - [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] - ) + unsafe { + simd_shuffle!( + a, + vqrshrn_n_u16::(b), + [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] + ) + } } #[doc = "Unsigned saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_high_n_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(uqrshrn2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqrshrn_high_n_u32(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t { +pub fn vqrshrn_high_n_u32(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t { static_assert!(N >= 1 && N <= 16); - simd_shuffle!(a, vqrshrn_n_u32::(b), [0, 1, 2, 3, 4, 5, 6, 7]) + unsafe { simd_shuffle!(a, vqrshrn_n_u32::(b), [0, 1, 2, 3, 4, 5, 6, 7]) } } #[doc = "Unsigned saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_high_n_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(uqrshrn2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqrshrn_high_n_u64(a: uint32x2_t, b: uint64x2_t) -> uint32x4_t { +pub fn vqrshrn_high_n_u64(a: uint32x2_t, b: uint64x2_t) -> uint32x4_t { static_assert!(N >= 1 && N <= 32); - simd_shuffle!(a, vqrshrn_n_u64::(b), [0, 1, 2, 3]) + unsafe { simd_shuffle!(a, vqrshrn_n_u64::(b), [0, 1, 2, 3]) } } #[doc = "Unsigned saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrnd_n_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(uqrshrn, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqrshrnd_n_u64(a: u64) -> u32 { +pub fn vqrshrnd_n_u64(a: u64) -> u32 { static_assert!(N >= 1 && N <= 32); let a: uint64x2_t = vdupq_n_u64(a); - simd_extract!(vqrshrn_n_u64::(a), 0) + unsafe { simd_extract!(vqrshrn_n_u64::(a), 0) } } #[doc = "Unsigned saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrnh_n_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(uqrshrn, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqrshrnh_n_u16(a: u16) -> u8 { +pub fn vqrshrnh_n_u16(a: u16) -> u8 { static_assert!(N >= 1 && N <= 8); let a: uint16x8_t = vdupq_n_u16(a); - simd_extract!(vqrshrn_n_u16::(a), 0) + unsafe { simd_extract!(vqrshrn_n_u16::(a), 0) } } #[doc = "Unsigned saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrns_n_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(uqrshrn, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqrshrns_n_u32(a: u32) -> u16 { +pub fn vqrshrns_n_u32(a: u32) -> u16 { static_assert!(N >= 1 && N <= 16); let a: uint32x4_t = vdupq_n_u32(a); - simd_extract!(vqrshrn_n_u32::(a), 0) + unsafe { simd_extract!(vqrshrn_n_u32::(a), 0) } } #[doc = "Signed saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrnh_n_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqrshrn, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqrshrnh_n_s16(a: i16) -> i8 { +pub fn vqrshrnh_n_s16(a: i16) -> i8 { static_assert!(N >= 1 && N <= 8); let a: int16x8_t = vdupq_n_s16(a); - simd_extract!(vqrshrn_n_s16::(a), 0) + unsafe { simd_extract!(vqrshrn_n_s16::(a), 0) } } #[doc = "Signed saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrns_n_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqrshrn, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqrshrns_n_s32(a: i32) -> i16 { +pub fn vqrshrns_n_s32(a: i32) -> i16 { static_assert!(N >= 1 && N <= 16); let a: int32x4_t = vdupq_n_s32(a); - simd_extract!(vqrshrn_n_s32::(a), 0) + unsafe { simd_extract!(vqrshrn_n_s32::(a), 0) } } #[doc = "Signed saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrnd_n_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqrshrn, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqrshrnd_n_s64(a: i64) -> i32 { +pub fn vqrshrnd_n_s64(a: i64) -> i32 { static_assert!(N >= 1 && N <= 32); let a: int64x2_t = vdupq_n_s64(a); - simd_extract!(vqrshrn_n_s64::(a), 0) + unsafe { simd_extract!(vqrshrn_n_s64::(a), 0) } } #[doc = "Signed saturating rounded shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_high_n_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqrshrun2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqrshrun_high_n_s16(a: uint8x8_t, b: int16x8_t) -> uint8x16_t { +pub fn vqrshrun_high_n_s16(a: uint8x8_t, b: int16x8_t) -> uint8x16_t { static_assert!(N >= 1 && N <= 8); - simd_shuffle!( - a, - vqrshrun_n_s16::(b), - [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] - ) + unsafe { + simd_shuffle!( + a, + vqrshrun_n_s16::(b), + [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] + ) + } } #[doc = "Signed saturating rounded shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_high_n_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqrshrun2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqrshrun_high_n_s32(a: uint16x4_t, b: int32x4_t) -> uint16x8_t { +pub fn vqrshrun_high_n_s32(a: uint16x4_t, b: int32x4_t) -> uint16x8_t { static_assert!(N >= 1 && N <= 16); - simd_shuffle!(a, vqrshrun_n_s32::(b), [0, 1, 2, 3, 4, 5, 6, 7]) + unsafe { simd_shuffle!(a, vqrshrun_n_s32::(b), [0, 1, 2, 3, 4, 5, 6, 7]) } } #[doc = "Signed saturating rounded shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_high_n_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqrshrun2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqrshrun_high_n_s64(a: uint32x2_t, b: int64x2_t) -> uint32x4_t { +pub fn vqrshrun_high_n_s64(a: uint32x2_t, b: int64x2_t) -> uint32x4_t { static_assert!(N >= 1 && N <= 32); - simd_shuffle!(a, vqrshrun_n_s64::(b), [0, 1, 2, 3]) + unsafe { simd_shuffle!(a, vqrshrun_n_s64::(b), [0, 1, 2, 3]) } } #[doc = "Signed saturating rounded shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrund_n_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqrshrun, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqrshrund_n_s64(a: i64) -> u32 { +pub fn vqrshrund_n_s64(a: i64) -> u32 { static_assert!(N >= 1 && N <= 32); let a: int64x2_t = vdupq_n_s64(a); - simd_extract!(vqrshrun_n_s64::(a), 0) + unsafe { simd_extract!(vqrshrun_n_s64::(a), 0) } } #[doc = "Signed saturating rounded shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrunh_n_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqrshrun, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqrshrunh_n_s16(a: i16) -> u8 { +pub fn vqrshrunh_n_s16(a: i16) -> u8 { static_assert!(N >= 1 && N <= 8); let a: int16x8_t = vdupq_n_s16(a); - simd_extract!(vqrshrun_n_s16::(a), 0) + unsafe { simd_extract!(vqrshrun_n_s16::(a), 0) } } #[doc = "Signed saturating rounded shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshruns_n_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqrshrun, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqrshruns_n_s32(a: i32) -> u16 { +pub fn vqrshruns_n_s32(a: i32) -> u16 { static_assert!(N >= 1 && N <= 16); let a: int32x4_t = vdupq_n_s32(a); - simd_extract!(vqrshrun_n_s32::(a), 0) + unsafe { simd_extract!(vqrshrun_n_s32::(a), 0) } } #[doc = "Signed saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlb_n_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqshl, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshlb_n_s8(a: i8) -> i8 { +pub fn vqshlb_n_s8(a: i8) -> i8 { static_assert_uimm_bits!(N, 3); - simd_extract!(vqshl_n_s8::(vdup_n_s8(a)), 0) + unsafe { simd_extract!(vqshl_n_s8::(vdup_n_s8(a)), 0) } } #[doc = "Signed saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshld_n_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqshl, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshld_n_s64(a: i64) -> i64 { +pub fn vqshld_n_s64(a: i64) -> i64 { static_assert_uimm_bits!(N, 6); - simd_extract!(vqshl_n_s64::(vdup_n_s64(a)), 0) + unsafe { simd_extract!(vqshl_n_s64::(vdup_n_s64(a)), 0) } } #[doc = "Signed saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlh_n_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqshl, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshlh_n_s16(a: i16) -> i16 { +pub fn vqshlh_n_s16(a: i16) -> i16 { static_assert_uimm_bits!(N, 4); - simd_extract!(vqshl_n_s16::(vdup_n_s16(a)), 0) + unsafe { simd_extract!(vqshl_n_s16::(vdup_n_s16(a)), 0) } } #[doc = "Signed saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshls_n_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqshl, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshls_n_s32(a: i32) -> i32 { +pub fn vqshls_n_s32(a: i32) -> i32 { static_assert_uimm_bits!(N, 5); - simd_extract!(vqshl_n_s32::(vdup_n_s32(a)), 0) + unsafe { simd_extract!(vqshl_n_s32::(vdup_n_s32(a)), 0) } } #[doc = "Unsigned saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlb_n_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(uqshl, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshlb_n_u8(a: u8) -> u8 { +pub fn vqshlb_n_u8(a: u8) -> u8 { static_assert_uimm_bits!(N, 3); - simd_extract!(vqshl_n_u8::(vdup_n_u8(a)), 0) + unsafe { simd_extract!(vqshl_n_u8::(vdup_n_u8(a)), 0) } } #[doc = "Unsigned saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshld_n_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(uqshl, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshld_n_u64(a: u64) -> u64 { +pub fn vqshld_n_u64(a: u64) -> u64 { static_assert_uimm_bits!(N, 6); - simd_extract!(vqshl_n_u64::(vdup_n_u64(a)), 0) + unsafe { simd_extract!(vqshl_n_u64::(vdup_n_u64(a)), 0) } } #[doc = "Unsigned saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlh_n_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(uqshl, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshlh_n_u16(a: u16) -> u16 { +pub fn vqshlh_n_u16(a: u16) -> u16 { static_assert_uimm_bits!(N, 4); - simd_extract!(vqshl_n_u16::(vdup_n_u16(a)), 0) + unsafe { simd_extract!(vqshl_n_u16::(vdup_n_u16(a)), 0) } } #[doc = "Unsigned saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshls_n_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(uqshl, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshls_n_u32(a: u32) -> u32 { +pub fn vqshls_n_u32(a: u32) -> u32 { static_assert_uimm_bits!(N, 5); - simd_extract!(vqshl_n_u32::(vdup_n_u32(a)), 0) + unsafe { simd_extract!(vqshl_n_u32::(vdup_n_u32(a)), 0) } } #[doc = "Signed saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlb_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshlb_s8(a: i8, b: i8) -> i8 { +pub fn vqshlb_s8(a: i8, b: i8) -> i8 { let c: int8x8_t = vqshl_s8(vdup_n_s8(a), vdup_n_s8(b)); - simd_extract!(c, 0) + unsafe { simd_extract!(c, 0) } } #[doc = "Signed saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlh_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshlh_s16(a: i16, b: i16) -> i16 { +pub fn vqshlh_s16(a: i16, b: i16) -> i16 { let c: int16x4_t = vqshl_s16(vdup_n_s16(a), vdup_n_s16(b)); - simd_extract!(c, 0) + unsafe { simd_extract!(c, 0) } } #[doc = "Signed saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshls_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshls_s32(a: i32, b: i32) -> i32 { +pub fn vqshls_s32(a: i32, b: i32) -> i32 { let c: int32x2_t = vqshl_s32(vdup_n_s32(a), vdup_n_s32(b)); - simd_extract!(c, 0) + unsafe { simd_extract!(c, 0) } } #[doc = "Unsigned saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlb_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(uqshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshlb_u8(a: u8, b: i8) -> u8 { +pub fn vqshlb_u8(a: u8, b: i8) -> u8 { let c: uint8x8_t = vqshl_u8(vdup_n_u8(a), vdup_n_s8(b)); - simd_extract!(c, 0) + unsafe { simd_extract!(c, 0) } } #[doc = "Unsigned saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlh_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(uqshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshlh_u16(a: u16, b: i16) -> u16 { +pub fn vqshlh_u16(a: u16, b: i16) -> u16 { let c: uint16x4_t = vqshl_u16(vdup_n_u16(a), vdup_n_s16(b)); - simd_extract!(c, 0) + unsafe { simd_extract!(c, 0) } } #[doc = "Unsigned saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshls_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(uqshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshls_u32(a: u32, b: i32) -> u32 { +pub fn vqshls_u32(a: u32, b: i32) -> u32 { let c: uint32x2_t = vqshl_u32(vdup_n_u32(a), vdup_n_s32(b)); - simd_extract!(c, 0) + unsafe { simd_extract!(c, 0) } } #[doc = "Signed saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshld_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshld_s64(a: i64, b: i64) -> i64 { +pub fn vqshld_s64(a: i64, b: i64) -> i64 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -20385,17 +18592,15 @@ pub unsafe fn vqshld_s64(a: i64, b: i64) -> i64 { )] fn _vqshld_s64(a: i64, b: i64) -> i64; } - _vqshld_s64(a, b) + unsafe { _vqshld_s64(a, b) } } #[doc = "Unsigned saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshld_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(uqshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshld_u64(a: u64, b: i64) -> u64 { +pub fn vqshld_u64(a: u64, b: i64) -> u64 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -20403,156 +18608,138 @@ pub unsafe fn vqshld_u64(a: u64, b: i64) -> u64 { )] fn _vqshld_u64(a: u64, b: i64) -> u64; } - _vqshld_u64(a, b) + unsafe { _vqshld_u64(a, b) } } #[doc = "Signed saturating shift left unsigned"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlub_n_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqshlu, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshlub_n_s8(a: i8) -> u8 { +pub fn vqshlub_n_s8(a: i8) -> u8 { static_assert_uimm_bits!(N, 3); - simd_extract!(vqshlu_n_s8::(vdup_n_s8(a)), 0) + unsafe { simd_extract!(vqshlu_n_s8::(vdup_n_s8(a)), 0) } } #[doc = "Signed saturating shift left unsigned"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlud_n_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqshlu, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshlud_n_s64(a: i64) -> u64 { +pub fn vqshlud_n_s64(a: i64) -> u64 { static_assert_uimm_bits!(N, 6); - simd_extract!(vqshlu_n_s64::(vdup_n_s64(a)), 0) + unsafe { simd_extract!(vqshlu_n_s64::(vdup_n_s64(a)), 0) } } #[doc = "Signed saturating shift left unsigned"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluh_n_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqshlu, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshluh_n_s16(a: i16) -> u16 { +pub fn vqshluh_n_s16(a: i16) -> u16 { static_assert_uimm_bits!(N, 4); - simd_extract!(vqshlu_n_s16::(vdup_n_s16(a)), 0) + unsafe { simd_extract!(vqshlu_n_s16::(vdup_n_s16(a)), 0) } } #[doc = "Signed saturating shift left unsigned"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlus_n_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqshlu, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshlus_n_s32(a: i32) -> u32 { +pub fn vqshlus_n_s32(a: i32) -> u32 { static_assert_uimm_bits!(N, 5); - simd_extract!(vqshlu_n_s32::(vdup_n_s32(a)), 0) + unsafe { simd_extract!(vqshlu_n_s32::(vdup_n_s32(a)), 0) } } #[doc = "Signed saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqshrn2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshrn_high_n_s16(a: int8x8_t, b: int16x8_t) -> int8x16_t { +pub fn vqshrn_high_n_s16(a: int8x8_t, b: int16x8_t) -> int8x16_t { static_assert!(N >= 1 && N <= 8); - simd_shuffle!( - a, - vqshrn_n_s16::(b), - [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] - ) + unsafe { + simd_shuffle!( + a, + vqshrn_n_s16::(b), + [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] + ) + } } #[doc = "Signed saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqshrn2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshrn_high_n_s32(a: int16x4_t, b: int32x4_t) -> int16x8_t { +pub fn vqshrn_high_n_s32(a: int16x4_t, b: int32x4_t) -> int16x8_t { static_assert!(N >= 1 && N <= 16); - simd_shuffle!(a, vqshrn_n_s32::(b), [0, 1, 2, 3, 4, 5, 6, 7]) + unsafe { simd_shuffle!(a, vqshrn_n_s32::(b), [0, 1, 2, 3, 4, 5, 6, 7]) } } #[doc = "Signed saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqshrn2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshrn_high_n_s64(a: int32x2_t, b: int64x2_t) -> int32x4_t { +pub fn vqshrn_high_n_s64(a: int32x2_t, b: int64x2_t) -> int32x4_t { static_assert!(N >= 1 && N <= 32); - simd_shuffle!(a, vqshrn_n_s64::(b), [0, 1, 2, 3]) + unsafe { simd_shuffle!(a, vqshrn_n_s64::(b), [0, 1, 2, 3]) } } #[doc = "Unsigned saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(uqshrn2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshrn_high_n_u16(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t { +pub fn vqshrn_high_n_u16(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t { static_assert!(N >= 1 && N <= 8); - simd_shuffle!( - a, - vqshrn_n_u16::(b), - [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] - ) + unsafe { + simd_shuffle!( + a, + vqshrn_n_u16::(b), + [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] + ) + } } #[doc = "Unsigned saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(uqshrn2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshrn_high_n_u32(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t { +pub fn vqshrn_high_n_u32(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t { static_assert!(N >= 1 && N <= 16); - simd_shuffle!(a, vqshrn_n_u32::(b), [0, 1, 2, 3, 4, 5, 6, 7]) + unsafe { simd_shuffle!(a, vqshrn_n_u32::(b), [0, 1, 2, 3, 4, 5, 6, 7]) } } #[doc = "Unsigned saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(uqshrn2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshrn_high_n_u64(a: uint32x2_t, b: uint64x2_t) -> uint32x4_t { +pub fn vqshrn_high_n_u64(a: uint32x2_t, b: uint64x2_t) -> uint32x4_t { static_assert!(N >= 1 && N <= 32); - simd_shuffle!(a, vqshrn_n_u64::(b), [0, 1, 2, 3]) + unsafe { simd_shuffle!(a, vqshrn_n_u64::(b), [0, 1, 2, 3]) } } #[doc = "Signed saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrnd_n_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqshrn, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshrnd_n_s64(a: i64) -> i32 { +pub fn vqshrnd_n_s64(a: i64) -> i32 { static_assert!(N >= 1 && N <= 32); unsafe extern "unadjusted" { #[cfg_attr( @@ -20561,18 +18748,16 @@ pub unsafe fn vqshrnd_n_s64(a: i64) -> i32 { )] fn _vqshrnd_n_s64(a: i64, n: i32) -> i32; } - _vqshrnd_n_s64(a, N) + unsafe { _vqshrnd_n_s64(a, N) } } #[doc = "Unsigned saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrnd_n_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(uqshrn, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshrnd_n_u64(a: u64) -> u32 { +pub fn vqshrnd_n_u64(a: u64) -> u32 { static_assert!(N >= 1 && N <= 32); unsafe extern "unadjusted" { #[cfg_attr( @@ -20581,203 +18766,175 @@ pub unsafe fn vqshrnd_n_u64(a: u64) -> u32 { )] fn _vqshrnd_n_u64(a: u64, n: i32) -> u32; } - _vqshrnd_n_u64(a, N) + unsafe { _vqshrnd_n_u64(a, N) } } #[doc = "Signed saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrnh_n_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqshrn, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshrnh_n_s16(a: i16) -> i8 { +pub fn vqshrnh_n_s16(a: i16) -> i8 { static_assert!(N >= 1 && N <= 8); - simd_extract!(vqshrn_n_s16::(vdupq_n_s16(a)), 0) + unsafe { simd_extract!(vqshrn_n_s16::(vdupq_n_s16(a)), 0) } } #[doc = "Signed saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrns_n_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqshrn, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshrns_n_s32(a: i32) -> i16 { +pub fn vqshrns_n_s32(a: i32) -> i16 { static_assert!(N >= 1 && N <= 16); - simd_extract!(vqshrn_n_s32::(vdupq_n_s32(a)), 0) + unsafe { simd_extract!(vqshrn_n_s32::(vdupq_n_s32(a)), 0) } } #[doc = "Unsigned saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrnh_n_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(uqshrn, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshrnh_n_u16(a: u16) -> u8 { +pub fn vqshrnh_n_u16(a: u16) -> u8 { static_assert!(N >= 1 && N <= 8); - simd_extract!(vqshrn_n_u16::(vdupq_n_u16(a)), 0) + unsafe { simd_extract!(vqshrn_n_u16::(vdupq_n_u16(a)), 0) } } #[doc = "Unsigned saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrns_n_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(uqshrn, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshrns_n_u32(a: u32) -> u16 { +pub fn vqshrns_n_u32(a: u32) -> u16 { static_assert!(N >= 1 && N <= 16); - simd_extract!(vqshrn_n_u32::(vdupq_n_u32(a)), 0) + unsafe { simd_extract!(vqshrn_n_u32::(vdupq_n_u32(a)), 0) } } #[doc = "Signed saturating shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_high_n_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqshrun2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshrun_high_n_s16(a: uint8x8_t, b: int16x8_t) -> uint8x16_t { +pub fn vqshrun_high_n_s16(a: uint8x8_t, b: int16x8_t) -> uint8x16_t { static_assert!(N >= 1 && N <= 8); - simd_shuffle!( - a, - vqshrun_n_s16::(b), - [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] - ) + unsafe { + simd_shuffle!( + a, + vqshrun_n_s16::(b), + [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] + ) + } } #[doc = "Signed saturating shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_high_n_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqshrun2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshrun_high_n_s32(a: uint16x4_t, b: int32x4_t) -> uint16x8_t { +pub fn vqshrun_high_n_s32(a: uint16x4_t, b: int32x4_t) -> uint16x8_t { static_assert!(N >= 1 && N <= 16); - simd_shuffle!(a, vqshrun_n_s32::(b), [0, 1, 2, 3, 4, 5, 6, 7]) + unsafe { simd_shuffle!(a, vqshrun_n_s32::(b), [0, 1, 2, 3, 4, 5, 6, 7]) } } #[doc = "Signed saturating shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_high_n_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqshrun2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshrun_high_n_s64(a: uint32x2_t, b: int64x2_t) -> uint32x4_t { +pub fn vqshrun_high_n_s64(a: uint32x2_t, b: int64x2_t) -> uint32x4_t { static_assert!(N >= 1 && N <= 32); - simd_shuffle!(a, vqshrun_n_s64::(b), [0, 1, 2, 3]) + unsafe { simd_shuffle!(a, vqshrun_n_s64::(b), [0, 1, 2, 3]) } } #[doc = "Signed saturating shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrund_n_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqshrun, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshrund_n_s64(a: i64) -> u32 { +pub fn vqshrund_n_s64(a: i64) -> u32 { static_assert!(N >= 1 && N <= 32); - simd_extract!(vqshrun_n_s64::(vdupq_n_s64(a)), 0) + unsafe { simd_extract!(vqshrun_n_s64::(vdupq_n_s64(a)), 0) } } #[doc = "Signed saturating shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrunh_n_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqshrun, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshrunh_n_s16(a: i16) -> u8 { +pub fn vqshrunh_n_s16(a: i16) -> u8 { static_assert!(N >= 1 && N <= 8); - simd_extract!(vqshrun_n_s16::(vdupq_n_s16(a)), 0) + unsafe { simd_extract!(vqshrun_n_s16::(vdupq_n_s16(a)), 0) } } #[doc = "Signed saturating shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshruns_n_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sqshrun, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshruns_n_s32(a: i32) -> u16 { +pub fn vqshruns_n_s32(a: i32) -> u16 { static_assert!(N >= 1 && N <= 16); - simd_extract!(vqshrun_n_s32::(vdupq_n_s32(a)), 0) + unsafe { simd_extract!(vqshrun_n_s32::(vdupq_n_s32(a)), 0) } } #[doc = "Saturating subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubb_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(sqsub))] -pub unsafe fn vqsubb_s8(a: i8, b: i8) -> i8 { +pub fn vqsubb_s8(a: i8, b: i8) -> i8 { let a: int8x8_t = vdup_n_s8(a); let b: int8x8_t = vdup_n_s8(b); - simd_extract!(vqsub_s8(a, b), 0) + unsafe { simd_extract!(vqsub_s8(a, b), 0) } } #[doc = "Saturating subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubh_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(sqsub))] -pub unsafe fn vqsubh_s16(a: i16, b: i16) -> i16 { +pub fn vqsubh_s16(a: i16, b: i16) -> i16 { let a: int16x4_t = vdup_n_s16(a); let b: int16x4_t = vdup_n_s16(b); - simd_extract!(vqsub_s16(a, b), 0) + unsafe { simd_extract!(vqsub_s16(a, b), 0) } } #[doc = "Saturating subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubb_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(uqsub))] -pub unsafe fn vqsubb_u8(a: u8, b: u8) -> u8 { +pub fn vqsubb_u8(a: u8, b: u8) -> u8 { let a: uint8x8_t = vdup_n_u8(a); let b: uint8x8_t = vdup_n_u8(b); - simd_extract!(vqsub_u8(a, b), 0) + unsafe { simd_extract!(vqsub_u8(a, b), 0) } } #[doc = "Saturating subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubh_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(uqsub))] -pub unsafe fn vqsubh_u16(a: u16, b: u16) -> u16 { +pub fn vqsubh_u16(a: u16, b: u16) -> u16 { let a: uint16x4_t = vdup_n_u16(a); let b: uint16x4_t = vdup_n_u16(b); - simd_extract!(vqsub_u16(a, b), 0) + unsafe { simd_extract!(vqsub_u16(a, b), 0) } } #[doc = "Saturating subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubs_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(sqsub))] -pub unsafe fn vqsubs_s32(a: i32, b: i32) -> i32 { +pub fn vqsubs_s32(a: i32, b: i32) -> i32 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -20785,17 +18942,15 @@ pub unsafe fn vqsubs_s32(a: i32, b: i32) -> i32 { )] fn _vqsubs_s32(a: i32, b: i32) -> i32; } - _vqsubs_s32(a, b) + unsafe { _vqsubs_s32(a, b) } } #[doc = "Saturating subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubd_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(sqsub))] -pub unsafe fn vqsubd_s64(a: i64, b: i64) -> i64 { +pub fn vqsubd_s64(a: i64, b: i64) -> i64 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -20803,17 +18958,15 @@ pub unsafe fn vqsubd_s64(a: i64, b: i64) -> i64 { )] fn _vqsubd_s64(a: i64, b: i64) -> i64; } - _vqsubd_s64(a, b) + unsafe { _vqsubd_s64(a, b) } } #[doc = "Saturating subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubs_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(uqsub))] -pub unsafe fn vqsubs_u32(a: u32, b: u32) -> u32 { +pub fn vqsubs_u32(a: u32, b: u32) -> u32 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -20821,17 +18974,15 @@ pub unsafe fn vqsubs_u32(a: u32, b: u32) -> u32 { )] fn _vqsubs_u32(a: u32, b: u32) -> u32; } - _vqsubs_u32(a, b) + unsafe { _vqsubs_u32(a, b) } } #[doc = "Saturating subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubd_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(uqsub))] -pub unsafe fn vqsubd_u64(a: u64, b: u64) -> u64 { +pub fn vqsubd_u64(a: u64, b: u64) -> u64 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -20839,17 +18990,15 @@ pub unsafe fn vqsubd_u64(a: u64, b: u64) -> u64 { )] fn _vqsubd_u64(a: u64, b: u64) -> u64; } - _vqsubd_u64(a, b) + unsafe { _vqsubd_u64(a, b) } } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -unsafe fn vqtbl1(a: int8x16_t, b: uint8x8_t) -> int8x8_t { +fn vqtbl1(a: int8x16_t, b: uint8x8_t) -> int8x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -20857,17 +19006,15 @@ unsafe fn vqtbl1(a: int8x16_t, b: uint8x8_t) -> int8x8_t { )] fn _vqtbl1(a: int8x16_t, b: uint8x8_t) -> int8x8_t; } - _vqtbl1(a, b) + unsafe { _vqtbl1(a, b) } } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1q)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -unsafe fn vqtbl1q(a: int8x16_t, b: uint8x16_t) -> int8x16_t { +fn vqtbl1q(a: int8x16_t, b: uint8x16_t) -> int8x16_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -20875,87 +19022,81 @@ unsafe fn vqtbl1q(a: int8x16_t, b: uint8x16_t) -> int8x16_t { )] fn _vqtbl1q(a: int8x16_t, b: uint8x16_t) -> int8x16_t; } - _vqtbl1q(a, b) + unsafe { _vqtbl1q(a, b) } } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqtbl1_s8(a: int8x16_t, b: uint8x8_t) -> int8x8_t { +pub fn vqtbl1_s8(a: int8x16_t, b: uint8x8_t) -> int8x8_t { vqtbl1(a, b) } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1q_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqtbl1q_s8(a: int8x16_t, b: uint8x16_t) -> int8x16_t { +pub fn vqtbl1q_s8(a: int8x16_t, b: uint8x16_t) -> int8x16_t { vqtbl1q(a, b) } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqtbl1_u8(a: uint8x16_t, b: uint8x8_t) -> uint8x8_t { - let x = transmute(vqtbl1(transmute(a), b)); - x +pub fn vqtbl1_u8(a: uint8x16_t, b: uint8x8_t) -> uint8x8_t { + unsafe { + let x = transmute(vqtbl1(transmute(a), b)); + x + } } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1q_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqtbl1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { - let x = transmute(vqtbl1q(transmute(a), b)); - x +pub fn vqtbl1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + unsafe { + let x = transmute(vqtbl1q(transmute(a), b)); + x + } } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqtbl1_p8(a: poly8x16_t, b: uint8x8_t) -> poly8x8_t { - let x = transmute(vqtbl1(transmute(a), b)); - x +pub fn vqtbl1_p8(a: poly8x16_t, b: uint8x8_t) -> poly8x8_t { + unsafe { + let x = transmute(vqtbl1(transmute(a), b)); + x + } } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1q_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqtbl1q_p8(a: poly8x16_t, b: uint8x16_t) -> poly8x16_t { - let x = transmute(vqtbl1q(transmute(a), b)); - x +pub fn vqtbl1q_p8(a: poly8x16_t, b: uint8x16_t) -> poly8x16_t { + unsafe { + let x = transmute(vqtbl1q(transmute(a), b)); + x + } } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -unsafe fn vqtbl2(a: int8x16_t, b: int8x16_t, c: uint8x8_t) -> int8x8_t { +fn vqtbl2(a: int8x16_t, b: int8x16_t, c: uint8x8_t) -> int8x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -20963,17 +19104,15 @@ unsafe fn vqtbl2(a: int8x16_t, b: int8x16_t, c: uint8x8_t) -> int8x8_t { )] fn _vqtbl2(a: int8x16_t, b: int8x16_t, c: uint8x8_t) -> int8x8_t; } - _vqtbl2(a, b, c) + unsafe { _vqtbl2(a, b, c) } } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2q)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -unsafe fn vqtbl2q(a: int8x16_t, b: int8x16_t, c: uint8x16_t) -> int8x16_t { +fn vqtbl2q(a: int8x16_t, b: int8x16_t, c: uint8x16_t) -> int8x16_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -20981,52 +19120,44 @@ unsafe fn vqtbl2q(a: int8x16_t, b: int8x16_t, c: uint8x16_t) -> int8x16_t { )] fn _vqtbl2q(a: int8x16_t, b: int8x16_t, c: uint8x16_t) -> int8x16_t; } - _vqtbl2q(a, b, c) + unsafe { _vqtbl2q(a, b, c) } } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqtbl2_s8(a: int8x16x2_t, b: uint8x8_t) -> int8x8_t { +pub fn vqtbl2_s8(a: int8x16x2_t, b: uint8x8_t) -> int8x8_t { vqtbl2(a.0, a.1, b) } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2q_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqtbl2q_s8(a: int8x16x2_t, b: uint8x16_t) -> int8x16_t { +pub fn vqtbl2q_s8(a: int8x16x2_t, b: uint8x16_t) -> int8x16_t { vqtbl2q(a.0, a.1, b) } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqtbl2_u8(a: uint8x16x2_t, b: uint8x8_t) -> uint8x8_t { - transmute(vqtbl2(transmute(a.0), transmute(a.1), b)) +pub fn vqtbl2_u8(a: uint8x16x2_t, b: uint8x8_t) -> uint8x8_t { + unsafe { transmute(vqtbl2(transmute(a.0), transmute(a.1), b)) } } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqtbl2_u8(a: uint8x16x2_t, b: uint8x8_t) -> uint8x8_t { +pub fn vqtbl2_u8(a: uint8x16x2_t, b: uint8x8_t) -> uint8x8_t { let mut a: uint8x16x2_t = a; a.0 = simd_shuffle!( a.0, @@ -21039,31 +19170,29 @@ pub unsafe fn vqtbl2_u8(a: uint8x16x2_t, b: uint8x8_t) -> uint8x8_t { [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] ); let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: uint8x8_t = transmute(vqtbl2(transmute(a.0), transmute(a.1), b)); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: uint8x8_t = transmute(vqtbl2(transmute(a.0), transmute(a.1), b)); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2q_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqtbl2q_u8(a: uint8x16x2_t, b: uint8x16_t) -> uint8x16_t { - transmute(vqtbl2q(transmute(a.0), transmute(a.1), b)) +pub fn vqtbl2q_u8(a: uint8x16x2_t, b: uint8x16_t) -> uint8x16_t { + unsafe { transmute(vqtbl2q(transmute(a.0), transmute(a.1), b)) } } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2q_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqtbl2q_u8(a: uint8x16x2_t, b: uint8x16_t) -> uint8x16_t { +pub fn vqtbl2q_u8(a: uint8x16x2_t, b: uint8x16_t) -> uint8x16_t { let mut a: uint8x16x2_t = a; a.0 = simd_shuffle!( a.0, @@ -21076,35 +19205,33 @@ pub unsafe fn vqtbl2q_u8(a: uint8x16x2_t, b: uint8x16_t) -> uint8x16_t { [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] ); let b: uint8x16_t = simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: uint8x16_t = transmute(vqtbl2q(transmute(a.0), transmute(a.1), b)); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) + unsafe { + let ret_val: uint8x16_t = transmute(vqtbl2q(transmute(a.0), transmute(a.1), b)); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqtbl2_p8(a: poly8x16x2_t, b: uint8x8_t) -> poly8x8_t { - transmute(vqtbl2(transmute(a.0), transmute(a.1), b)) +pub fn vqtbl2_p8(a: poly8x16x2_t, b: uint8x8_t) -> poly8x8_t { + unsafe { transmute(vqtbl2(transmute(a.0), transmute(a.1), b)) } } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqtbl2_p8(a: poly8x16x2_t, b: uint8x8_t) -> poly8x8_t { +pub fn vqtbl2_p8(a: poly8x16x2_t, b: uint8x8_t) -> poly8x8_t { let mut a: poly8x16x2_t = a; a.0 = simd_shuffle!( a.0, @@ -21117,31 +19244,29 @@ pub unsafe fn vqtbl2_p8(a: poly8x16x2_t, b: uint8x8_t) -> poly8x8_t { [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] ); let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: poly8x8_t = transmute(vqtbl2(transmute(a.0), transmute(a.1), b)); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: poly8x8_t = transmute(vqtbl2(transmute(a.0), transmute(a.1), b)); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2q_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqtbl2q_p8(a: poly8x16x2_t, b: uint8x16_t) -> poly8x16_t { - transmute(vqtbl2q(transmute(a.0), transmute(a.1), b)) +pub fn vqtbl2q_p8(a: poly8x16x2_t, b: uint8x16_t) -> poly8x16_t { + unsafe { transmute(vqtbl2q(transmute(a.0), transmute(a.1), b)) } } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2q_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqtbl2q_p8(a: poly8x16x2_t, b: uint8x16_t) -> poly8x16_t { +pub fn vqtbl2q_p8(a: poly8x16x2_t, b: uint8x16_t) -> poly8x16_t { let mut a: poly8x16x2_t = a; a.0 = simd_shuffle!( a.0, @@ -21154,22 +19279,22 @@ pub unsafe fn vqtbl2q_p8(a: poly8x16x2_t, b: uint8x16_t) -> poly8x16_t { [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] ); let b: uint8x16_t = simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: poly8x16_t = transmute(vqtbl2q(transmute(a.0), transmute(a.1), b)); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) + unsafe { + let ret_val: poly8x16_t = transmute(vqtbl2q(transmute(a.0), transmute(a.1), b)); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -unsafe fn vqtbl3(a: int8x16_t, b: int8x16_t, c: int8x16_t, d: uint8x8_t) -> int8x8_t { +fn vqtbl3(a: int8x16_t, b: int8x16_t, c: int8x16_t, d: uint8x8_t) -> int8x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -21177,17 +19302,15 @@ unsafe fn vqtbl3(a: int8x16_t, b: int8x16_t, c: int8x16_t, d: uint8x8_t) -> int8 )] fn _vqtbl3(a: int8x16_t, b: int8x16_t, c: int8x16_t, d: uint8x8_t) -> int8x8_t; } - _vqtbl3(a, b, c, d) + unsafe { _vqtbl3(a, b, c, d) } } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3q)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -unsafe fn vqtbl3q(a: int8x16_t, b: int8x16_t, c: int8x16_t, d: uint8x16_t) -> int8x16_t { +fn vqtbl3q(a: int8x16_t, b: int8x16_t, c: int8x16_t, d: uint8x16_t) -> int8x16_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -21195,52 +19318,44 @@ unsafe fn vqtbl3q(a: int8x16_t, b: int8x16_t, c: int8x16_t, d: uint8x16_t) -> in )] fn _vqtbl3q(a: int8x16_t, b: int8x16_t, c: int8x16_t, d: uint8x16_t) -> int8x16_t; } - _vqtbl3q(a, b, c, d) + unsafe { _vqtbl3q(a, b, c, d) } } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqtbl3_s8(a: int8x16x3_t, b: uint8x8_t) -> int8x8_t { +pub fn vqtbl3_s8(a: int8x16x3_t, b: uint8x8_t) -> int8x8_t { vqtbl3(a.0, a.1, a.2, b) } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3q_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqtbl3q_s8(a: int8x16x3_t, b: uint8x16_t) -> int8x16_t { +pub fn vqtbl3q_s8(a: int8x16x3_t, b: uint8x16_t) -> int8x16_t { vqtbl3q(a.0, a.1, a.2, b) } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqtbl3_u8(a: uint8x16x3_t, b: uint8x8_t) -> uint8x8_t { - transmute(vqtbl3(transmute(a.0), transmute(a.1), transmute(a.2), b)) +pub fn vqtbl3_u8(a: uint8x16x3_t, b: uint8x8_t) -> uint8x8_t { + unsafe { transmute(vqtbl3(transmute(a.0), transmute(a.1), transmute(a.2), b)) } } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqtbl3_u8(a: uint8x16x3_t, b: uint8x8_t) -> uint8x8_t { +pub fn vqtbl3_u8(a: uint8x16x3_t, b: uint8x8_t) -> uint8x8_t { let mut a: uint8x16x3_t = a; a.0 = simd_shuffle!( a.0, @@ -21258,31 +19373,30 @@ pub unsafe fn vqtbl3_u8(a: uint8x16x3_t, b: uint8x8_t) -> uint8x8_t { [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] ); let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: uint8x8_t = transmute(vqtbl3(transmute(a.0), transmute(a.1), transmute(a.2), b)); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: uint8x8_t = + transmute(vqtbl3(transmute(a.0), transmute(a.1), transmute(a.2), b)); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3q_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqtbl3q_u8(a: uint8x16x3_t, b: uint8x16_t) -> uint8x16_t { - transmute(vqtbl3q(transmute(a.0), transmute(a.1), transmute(a.2), b)) +pub fn vqtbl3q_u8(a: uint8x16x3_t, b: uint8x16_t) -> uint8x16_t { + unsafe { transmute(vqtbl3q(transmute(a.0), transmute(a.1), transmute(a.2), b)) } } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3q_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqtbl3q_u8(a: uint8x16x3_t, b: uint8x16_t) -> uint8x16_t { +pub fn vqtbl3q_u8(a: uint8x16x3_t, b: uint8x16_t) -> uint8x16_t { let mut a: uint8x16x3_t = a; a.0 = simd_shuffle!( a.0, @@ -21300,35 +19414,34 @@ pub unsafe fn vqtbl3q_u8(a: uint8x16x3_t, b: uint8x16_t) -> uint8x16_t { [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] ); let b: uint8x16_t = simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: uint8x16_t = transmute(vqtbl3q(transmute(a.0), transmute(a.1), transmute(a.2), b)); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) + unsafe { + let ret_val: uint8x16_t = + transmute(vqtbl3q(transmute(a.0), transmute(a.1), transmute(a.2), b)); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqtbl3_p8(a: poly8x16x3_t, b: uint8x8_t) -> poly8x8_t { - transmute(vqtbl3(transmute(a.0), transmute(a.1), transmute(a.2), b)) +pub fn vqtbl3_p8(a: poly8x16x3_t, b: uint8x8_t) -> poly8x8_t { + unsafe { transmute(vqtbl3(transmute(a.0), transmute(a.1), transmute(a.2), b)) } } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqtbl3_p8(a: poly8x16x3_t, b: uint8x8_t) -> poly8x8_t { +pub fn vqtbl3_p8(a: poly8x16x3_t, b: uint8x8_t) -> poly8x8_t { let mut a: poly8x16x3_t = a; a.0 = simd_shuffle!( a.0, @@ -21346,31 +19459,30 @@ pub unsafe fn vqtbl3_p8(a: poly8x16x3_t, b: uint8x8_t) -> poly8x8_t { [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] ); let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: poly8x8_t = transmute(vqtbl3(transmute(a.0), transmute(a.1), transmute(a.2), b)); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: poly8x8_t = + transmute(vqtbl3(transmute(a.0), transmute(a.1), transmute(a.2), b)); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3q_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqtbl3q_p8(a: poly8x16x3_t, b: uint8x16_t) -> poly8x16_t { - transmute(vqtbl3q(transmute(a.0), transmute(a.1), transmute(a.2), b)) +pub fn vqtbl3q_p8(a: poly8x16x3_t, b: uint8x16_t) -> poly8x16_t { + unsafe { transmute(vqtbl3q(transmute(a.0), transmute(a.1), transmute(a.2), b)) } } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3q_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqtbl3q_p8(a: poly8x16x3_t, b: uint8x16_t) -> poly8x16_t { +pub fn vqtbl3q_p8(a: poly8x16x3_t, b: uint8x16_t) -> poly8x16_t { let mut a: poly8x16x3_t = a; a.0 = simd_shuffle!( a.0, @@ -21388,22 +19500,23 @@ pub unsafe fn vqtbl3q_p8(a: poly8x16x3_t, b: uint8x16_t) -> poly8x16_t { [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] ); let b: uint8x16_t = simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: poly8x16_t = transmute(vqtbl3q(transmute(a.0), transmute(a.1), transmute(a.2), b)); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) + unsafe { + let ret_val: poly8x16_t = + transmute(vqtbl3q(transmute(a.0), transmute(a.1), transmute(a.2), b)); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -unsafe fn vqtbl4(a: int8x16_t, b: int8x16_t, c: int8x16_t, d: int8x16_t, e: uint8x8_t) -> int8x8_t { +fn vqtbl4(a: int8x16_t, b: int8x16_t, c: int8x16_t, d: int8x16_t, e: uint8x8_t) -> int8x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -21417,23 +19530,15 @@ unsafe fn vqtbl4(a: int8x16_t, b: int8x16_t, c: int8x16_t, d: int8x16_t, e: uint e: uint8x8_t, ) -> int8x8_t; } - _vqtbl4(a, b, c, d, e) + unsafe { _vqtbl4(a, b, c, d, e) } } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4q)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -unsafe fn vqtbl4q( - a: int8x16_t, - b: int8x16_t, - c: int8x16_t, - d: int8x16_t, - e: uint8x16_t, -) -> int8x16_t { +fn vqtbl4q(a: int8x16_t, b: int8x16_t, c: int8x16_t, d: int8x16_t, e: uint8x16_t) -> int8x16_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -21447,58 +19552,52 @@ unsafe fn vqtbl4q( e: uint8x16_t, ) -> int8x16_t; } - _vqtbl4q(a, b, c, d, e) + unsafe { _vqtbl4q(a, b, c, d, e) } } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqtbl4_s8(a: int8x16x4_t, b: uint8x8_t) -> int8x8_t { +pub fn vqtbl4_s8(a: int8x16x4_t, b: uint8x8_t) -> int8x8_t { vqtbl4(a.0, a.1, a.2, a.3, b) } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4q_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqtbl4q_s8(a: int8x16x4_t, b: uint8x16_t) -> int8x16_t { +pub fn vqtbl4q_s8(a: int8x16x4_t, b: uint8x16_t) -> int8x16_t { vqtbl4q(a.0, a.1, a.2, a.3, b) } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqtbl4_u8(a: uint8x16x4_t, b: uint8x8_t) -> uint8x8_t { - transmute(vqtbl4( - transmute(a.0), - transmute(a.1), - transmute(a.2), - transmute(a.3), - b, - )) +pub fn vqtbl4_u8(a: uint8x16x4_t, b: uint8x8_t) -> uint8x8_t { + unsafe { + transmute(vqtbl4( + transmute(a.0), + transmute(a.1), + transmute(a.2), + transmute(a.3), + b, + )) + } } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqtbl4_u8(a: uint8x16x4_t, b: uint8x8_t) -> uint8x8_t { +pub fn vqtbl4_u8(a: uint8x16x4_t, b: uint8x8_t) -> uint8x8_t { let mut a: uint8x16x4_t = a; a.0 = simd_shuffle!( a.0, @@ -21521,43 +19620,43 @@ pub unsafe fn vqtbl4_u8(a: uint8x16x4_t, b: uint8x8_t) -> uint8x8_t { [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] ); let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: uint8x8_t = transmute(vqtbl4( - transmute(a.0), - transmute(a.1), - transmute(a.2), - transmute(a.3), - b, - )); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: uint8x8_t = transmute(vqtbl4( + transmute(a.0), + transmute(a.1), + transmute(a.2), + transmute(a.3), + b, + )); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4q_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqtbl4q_u8(a: uint8x16x4_t, b: uint8x16_t) -> uint8x16_t { - transmute(vqtbl4q( - transmute(a.0), - transmute(a.1), - transmute(a.2), - transmute(a.3), - b, - )) +pub fn vqtbl4q_u8(a: uint8x16x4_t, b: uint8x16_t) -> uint8x16_t { + unsafe { + transmute(vqtbl4q( + transmute(a.0), + transmute(a.1), + transmute(a.2), + transmute(a.3), + b, + )) + } } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4q_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqtbl4q_u8(a: uint8x16x4_t, b: uint8x16_t) -> uint8x16_t { +pub fn vqtbl4q_u8(a: uint8x16x4_t, b: uint8x16_t) -> uint8x16_t { let mut a: uint8x16x4_t = a; a.0 = simd_shuffle!( a.0, @@ -21580,47 +19679,47 @@ pub unsafe fn vqtbl4q_u8(a: uint8x16x4_t, b: uint8x16_t) -> uint8x16_t { [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] ); let b: uint8x16_t = simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: uint8x16_t = transmute(vqtbl4q( - transmute(a.0), - transmute(a.1), - transmute(a.2), - transmute(a.3), - b, - )); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) + unsafe { + let ret_val: uint8x16_t = transmute(vqtbl4q( + transmute(a.0), + transmute(a.1), + transmute(a.2), + transmute(a.3), + b, + )); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqtbl4_p8(a: poly8x16x4_t, b: uint8x8_t) -> poly8x8_t { - transmute(vqtbl4( - transmute(a.0), - transmute(a.1), - transmute(a.2), - transmute(a.3), - b, - )) +pub fn vqtbl4_p8(a: poly8x16x4_t, b: uint8x8_t) -> poly8x8_t { + unsafe { + transmute(vqtbl4( + transmute(a.0), + transmute(a.1), + transmute(a.2), + transmute(a.3), + b, + )) + } } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqtbl4_p8(a: poly8x16x4_t, b: uint8x8_t) -> poly8x8_t { +pub fn vqtbl4_p8(a: poly8x16x4_t, b: uint8x8_t) -> poly8x8_t { let mut a: poly8x16x4_t = a; a.0 = simd_shuffle!( a.0, @@ -21643,43 +19742,43 @@ pub unsafe fn vqtbl4_p8(a: poly8x16x4_t, b: uint8x8_t) -> poly8x8_t { [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] ); let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: poly8x8_t = transmute(vqtbl4( - transmute(a.0), - transmute(a.1), - transmute(a.2), - transmute(a.3), - b, - )); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: poly8x8_t = transmute(vqtbl4( + transmute(a.0), + transmute(a.1), + transmute(a.2), + transmute(a.3), + b, + )); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4q_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqtbl4q_p8(a: poly8x16x4_t, b: uint8x16_t) -> poly8x16_t { - transmute(vqtbl4q( - transmute(a.0), - transmute(a.1), - transmute(a.2), - transmute(a.3), - b, - )) +pub fn vqtbl4q_p8(a: poly8x16x4_t, b: uint8x16_t) -> poly8x16_t { + unsafe { + transmute(vqtbl4q( + transmute(a.0), + transmute(a.1), + transmute(a.2), + transmute(a.3), + b, + )) + } } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4q_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqtbl4q_p8(a: poly8x16x4_t, b: uint8x16_t) -> poly8x16_t { +pub fn vqtbl4q_p8(a: poly8x16x4_t, b: uint8x16_t) -> poly8x16_t { let mut a: poly8x16x4_t = a; a.0 = simd_shuffle!( a.0, @@ -21702,28 +19801,28 @@ pub unsafe fn vqtbl4q_p8(a: poly8x16x4_t, b: uint8x16_t) -> poly8x16_t { [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] ); let b: uint8x16_t = simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: poly8x16_t = transmute(vqtbl4q( - transmute(a.0), - transmute(a.1), - transmute(a.2), - transmute(a.3), - b, - )); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) + unsafe { + let ret_val: poly8x16_t = transmute(vqtbl4q( + transmute(a.0), + transmute(a.1), + transmute(a.2), + transmute(a.3), + b, + )); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -unsafe fn vqtbx1(a: int8x8_t, b: int8x16_t, c: uint8x8_t) -> int8x8_t { +fn vqtbx1(a: int8x8_t, b: int8x16_t, c: uint8x8_t) -> int8x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -21731,17 +19830,15 @@ unsafe fn vqtbx1(a: int8x8_t, b: int8x16_t, c: uint8x8_t) -> int8x8_t { )] fn _vqtbx1(a: int8x8_t, b: int8x16_t, c: uint8x8_t) -> int8x8_t; } - _vqtbx1(a, b, c) + unsafe { _vqtbx1(a, b, c) } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1q)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -unsafe fn vqtbx1q(a: int8x16_t, b: int8x16_t, c: uint8x16_t) -> int8x16_t { +fn vqtbx1q(a: int8x16_t, b: int8x16_t, c: uint8x16_t) -> int8x16_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -21749,87 +19846,81 @@ unsafe fn vqtbx1q(a: int8x16_t, b: int8x16_t, c: uint8x16_t) -> int8x16_t { )] fn _vqtbx1q(a: int8x16_t, b: int8x16_t, c: uint8x16_t) -> int8x16_t; } - _vqtbx1q(a, b, c) + unsafe { _vqtbx1q(a, b, c) } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqtbx1_s8(a: int8x8_t, b: int8x16_t, c: uint8x8_t) -> int8x8_t { +pub fn vqtbx1_s8(a: int8x8_t, b: int8x16_t, c: uint8x8_t) -> int8x8_t { vqtbx1(a, b, c) } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1q_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqtbx1q_s8(a: int8x16_t, b: int8x16_t, c: uint8x16_t) -> int8x16_t { +pub fn vqtbx1q_s8(a: int8x16_t, b: int8x16_t, c: uint8x16_t) -> int8x16_t { vqtbx1q(a, b, c) } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqtbx1_u8(a: uint8x8_t, b: uint8x16_t, c: uint8x8_t) -> uint8x8_t { - let x = transmute(vqtbx1(transmute(a), transmute(b), c)); - x +pub fn vqtbx1_u8(a: uint8x8_t, b: uint8x16_t, c: uint8x8_t) -> uint8x8_t { + unsafe { + let x = transmute(vqtbx1(transmute(a), transmute(b), c)); + x + } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1q_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqtbx1q_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t { - let x = transmute(vqtbx1q(transmute(a), transmute(b), c)); - x +pub fn vqtbx1q_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t { + unsafe { + let x = transmute(vqtbx1q(transmute(a), transmute(b), c)); + x + } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqtbx1_p8(a: poly8x8_t, b: poly8x16_t, c: uint8x8_t) -> poly8x8_t { - let x = transmute(vqtbx1(transmute(a), transmute(b), c)); - x +pub fn vqtbx1_p8(a: poly8x8_t, b: poly8x16_t, c: uint8x8_t) -> poly8x8_t { + unsafe { + let x = transmute(vqtbx1(transmute(a), transmute(b), c)); + x + } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1q_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqtbx1q_p8(a: poly8x16_t, b: poly8x16_t, c: uint8x16_t) -> poly8x16_t { - let x = transmute(vqtbx1q(transmute(a), transmute(b), c)); - x +pub fn vqtbx1q_p8(a: poly8x16_t, b: poly8x16_t, c: uint8x16_t) -> poly8x16_t { + unsafe { + let x = transmute(vqtbx1q(transmute(a), transmute(b), c)); + x + } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -unsafe fn vqtbx2(a: int8x8_t, b: int8x16_t, c: int8x16_t, d: uint8x8_t) -> int8x8_t { +fn vqtbx2(a: int8x8_t, b: int8x16_t, c: int8x16_t, d: uint8x8_t) -> int8x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -21837,17 +19928,15 @@ unsafe fn vqtbx2(a: int8x8_t, b: int8x16_t, c: int8x16_t, d: uint8x8_t) -> int8x )] fn _vqtbx2(a: int8x8_t, b: int8x16_t, c: int8x16_t, d: uint8x8_t) -> int8x8_t; } - _vqtbx2(a, b, c, d) + unsafe { _vqtbx2(a, b, c, d) } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2q)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -unsafe fn vqtbx2q(a: int8x16_t, b: int8x16_t, c: int8x16_t, d: uint8x16_t) -> int8x16_t { +fn vqtbx2q(a: int8x16_t, b: int8x16_t, c: int8x16_t, d: uint8x16_t) -> int8x16_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -21855,52 +19944,44 @@ unsafe fn vqtbx2q(a: int8x16_t, b: int8x16_t, c: int8x16_t, d: uint8x16_t) -> in )] fn _vqtbx2q(a: int8x16_t, b: int8x16_t, c: int8x16_t, d: uint8x16_t) -> int8x16_t; } - _vqtbx2q(a, b, c, d) + unsafe { _vqtbx2q(a, b, c, d) } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqtbx2_s8(a: int8x8_t, b: int8x16x2_t, c: uint8x8_t) -> int8x8_t { +pub fn vqtbx2_s8(a: int8x8_t, b: int8x16x2_t, c: uint8x8_t) -> int8x8_t { vqtbx2(a, b.0, b.1, c) } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2q_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqtbx2q_s8(a: int8x16_t, b: int8x16x2_t, c: uint8x16_t) -> int8x16_t { +pub fn vqtbx2q_s8(a: int8x16_t, b: int8x16x2_t, c: uint8x16_t) -> int8x16_t { vqtbx2q(a, b.0, b.1, c) } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqtbx2_u8(a: uint8x8_t, b: uint8x16x2_t, c: uint8x8_t) -> uint8x8_t { - transmute(vqtbx2(transmute(a), transmute(b.0), transmute(b.1), c)) +pub fn vqtbx2_u8(a: uint8x8_t, b: uint8x16x2_t, c: uint8x8_t) -> uint8x8_t { + unsafe { transmute(vqtbx2(transmute(a), transmute(b.0), transmute(b.1), c)) } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqtbx2_u8(a: uint8x8_t, b: uint8x16x2_t, c: uint8x8_t) -> uint8x8_t { +pub fn vqtbx2_u8(a: uint8x8_t, b: uint8x16x2_t, c: uint8x8_t) -> uint8x8_t { let mut b: uint8x16x2_t = b; let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); b.0 = simd_shuffle!( @@ -21914,31 +19995,29 @@ pub unsafe fn vqtbx2_u8(a: uint8x8_t, b: uint8x16x2_t, c: uint8x8_t) -> uint8x8_ [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] ); let c: uint8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: uint8x8_t = transmute(vqtbx2(transmute(a), transmute(b.0), transmute(b.1), c)); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: uint8x8_t = transmute(vqtbx2(transmute(a), transmute(b.0), transmute(b.1), c)); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2q_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqtbx2q_u8(a: uint8x16_t, b: uint8x16x2_t, c: uint8x16_t) -> uint8x16_t { - transmute(vqtbx2q(transmute(a), transmute(b.0), transmute(b.1), c)) +pub fn vqtbx2q_u8(a: uint8x16_t, b: uint8x16x2_t, c: uint8x16_t) -> uint8x16_t { + unsafe { transmute(vqtbx2q(transmute(a), transmute(b.0), transmute(b.1), c)) } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2q_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqtbx2q_u8(a: uint8x16_t, b: uint8x16x2_t, c: uint8x16_t) -> uint8x16_t { +pub fn vqtbx2q_u8(a: uint8x16_t, b: uint8x16x2_t, c: uint8x16_t) -> uint8x16_t { let mut b: uint8x16x2_t = b; let a: uint8x16_t = simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); b.0 = simd_shuffle!( @@ -21952,35 +20031,34 @@ pub unsafe fn vqtbx2q_u8(a: uint8x16_t, b: uint8x16x2_t, c: uint8x16_t) -> uint8 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] ); let c: uint8x16_t = simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: uint8x16_t = transmute(vqtbx2q(transmute(a), transmute(b.0), transmute(b.1), c)); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) + unsafe { + let ret_val: uint8x16_t = + transmute(vqtbx2q(transmute(a), transmute(b.0), transmute(b.1), c)); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqtbx2_p8(a: poly8x8_t, b: poly8x16x2_t, c: uint8x8_t) -> poly8x8_t { - transmute(vqtbx2(transmute(a), transmute(b.0), transmute(b.1), c)) +pub fn vqtbx2_p8(a: poly8x8_t, b: poly8x16x2_t, c: uint8x8_t) -> poly8x8_t { + unsafe { transmute(vqtbx2(transmute(a), transmute(b.0), transmute(b.1), c)) } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqtbx2_p8(a: poly8x8_t, b: poly8x16x2_t, c: uint8x8_t) -> poly8x8_t { +pub fn vqtbx2_p8(a: poly8x8_t, b: poly8x16x2_t, c: uint8x8_t) -> poly8x8_t { let mut b: poly8x16x2_t = b; let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); b.0 = simd_shuffle!( @@ -21994,31 +20072,29 @@ pub unsafe fn vqtbx2_p8(a: poly8x8_t, b: poly8x16x2_t, c: uint8x8_t) -> poly8x8_ [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] ); let c: uint8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: poly8x8_t = transmute(vqtbx2(transmute(a), transmute(b.0), transmute(b.1), c)); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: poly8x8_t = transmute(vqtbx2(transmute(a), transmute(b.0), transmute(b.1), c)); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2q_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqtbx2q_p8(a: poly8x16_t, b: poly8x16x2_t, c: uint8x16_t) -> poly8x16_t { - transmute(vqtbx2q(transmute(a), transmute(b.0), transmute(b.1), c)) +pub fn vqtbx2q_p8(a: poly8x16_t, b: poly8x16x2_t, c: uint8x16_t) -> poly8x16_t { + unsafe { transmute(vqtbx2q(transmute(a), transmute(b.0), transmute(b.1), c)) } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2q_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqtbx2q_p8(a: poly8x16_t, b: poly8x16x2_t, c: uint8x16_t) -> poly8x16_t { +pub fn vqtbx2q_p8(a: poly8x16_t, b: poly8x16x2_t, c: uint8x16_t) -> poly8x16_t { let mut b: poly8x16x2_t = b; let a: poly8x16_t = simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); b.0 = simd_shuffle!( @@ -22032,22 +20108,23 @@ pub unsafe fn vqtbx2q_p8(a: poly8x16_t, b: poly8x16x2_t, c: uint8x16_t) -> poly8 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] ); let c: uint8x16_t = simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: poly8x16_t = transmute(vqtbx2q(transmute(a), transmute(b.0), transmute(b.1), c)); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) + unsafe { + let ret_val: poly8x16_t = + transmute(vqtbx2q(transmute(a), transmute(b.0), transmute(b.1), c)); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -unsafe fn vqtbx3(a: int8x8_t, b: int8x16_t, c: int8x16_t, d: int8x16_t, e: uint8x8_t) -> int8x8_t { +fn vqtbx3(a: int8x8_t, b: int8x16_t, c: int8x16_t, d: int8x16_t, e: uint8x8_t) -> int8x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -22056,23 +20133,15 @@ unsafe fn vqtbx3(a: int8x8_t, b: int8x16_t, c: int8x16_t, d: int8x16_t, e: uint8 fn _vqtbx3(a: int8x8_t, b: int8x16_t, c: int8x16_t, d: int8x16_t, e: uint8x8_t) -> int8x8_t; } - _vqtbx3(a, b, c, d, e) + unsafe { _vqtbx3(a, b, c, d, e) } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3q)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -unsafe fn vqtbx3q( - a: int8x16_t, - b: int8x16_t, - c: int8x16_t, - d: int8x16_t, - e: uint8x16_t, -) -> int8x16_t { +fn vqtbx3q(a: int8x16_t, b: int8x16_t, c: int8x16_t, d: int8x16_t, e: uint8x16_t) -> int8x16_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -22086,58 +20155,52 @@ unsafe fn vqtbx3q( e: uint8x16_t, ) -> int8x16_t; } - _vqtbx3q(a, b, c, d, e) + unsafe { _vqtbx3q(a, b, c, d, e) } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqtbx3_s8(a: int8x8_t, b: int8x16x3_t, c: uint8x8_t) -> int8x8_t { +pub fn vqtbx3_s8(a: int8x8_t, b: int8x16x3_t, c: uint8x8_t) -> int8x8_t { vqtbx3(a, b.0, b.1, b.2, c) } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3q_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqtbx3q_s8(a: int8x16_t, b: int8x16x3_t, c: uint8x16_t) -> int8x16_t { +pub fn vqtbx3q_s8(a: int8x16_t, b: int8x16x3_t, c: uint8x16_t) -> int8x16_t { vqtbx3q(a, b.0, b.1, b.2, c) } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqtbx3_u8(a: uint8x8_t, b: uint8x16x3_t, c: uint8x8_t) -> uint8x8_t { - transmute(vqtbx3( - transmute(a), - transmute(b.0), - transmute(b.1), - transmute(b.2), - c, - )) +pub fn vqtbx3_u8(a: uint8x8_t, b: uint8x16x3_t, c: uint8x8_t) -> uint8x8_t { + unsafe { + transmute(vqtbx3( + transmute(a), + transmute(b.0), + transmute(b.1), + transmute(b.2), + c, + )) + } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqtbx3_u8(a: uint8x8_t, b: uint8x16x3_t, c: uint8x8_t) -> uint8x8_t { +pub fn vqtbx3_u8(a: uint8x8_t, b: uint8x16x3_t, c: uint8x8_t) -> uint8x8_t { let mut b: uint8x16x3_t = b; let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); b.0 = simd_shuffle!( @@ -22156,43 +20219,43 @@ pub unsafe fn vqtbx3_u8(a: uint8x8_t, b: uint8x16x3_t, c: uint8x8_t) -> uint8x8_ [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] ); let c: uint8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: uint8x8_t = transmute(vqtbx3( - transmute(a), - transmute(b.0), - transmute(b.1), - transmute(b.2), - c, - )); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: uint8x8_t = transmute(vqtbx3( + transmute(a), + transmute(b.0), + transmute(b.1), + transmute(b.2), + c, + )); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3q_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqtbx3q_u8(a: uint8x16_t, b: uint8x16x3_t, c: uint8x16_t) -> uint8x16_t { - transmute(vqtbx3q( - transmute(a), - transmute(b.0), - transmute(b.1), - transmute(b.2), - c, - )) +pub fn vqtbx3q_u8(a: uint8x16_t, b: uint8x16x3_t, c: uint8x16_t) -> uint8x16_t { + unsafe { + transmute(vqtbx3q( + transmute(a), + transmute(b.0), + transmute(b.1), + transmute(b.2), + c, + )) + } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3q_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqtbx3q_u8(a: uint8x16_t, b: uint8x16x3_t, c: uint8x16_t) -> uint8x16_t { +pub fn vqtbx3q_u8(a: uint8x16_t, b: uint8x16x3_t, c: uint8x16_t) -> uint8x16_t { let mut b: uint8x16x3_t = b; let a: uint8x16_t = simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); b.0 = simd_shuffle!( @@ -22211,47 +20274,47 @@ pub unsafe fn vqtbx3q_u8(a: uint8x16_t, b: uint8x16x3_t, c: uint8x16_t) -> uint8 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] ); let c: uint8x16_t = simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: uint8x16_t = transmute(vqtbx3q( - transmute(a), - transmute(b.0), - transmute(b.1), - transmute(b.2), - c, - )); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) + unsafe { + let ret_val: uint8x16_t = transmute(vqtbx3q( + transmute(a), + transmute(b.0), + transmute(b.1), + transmute(b.2), + c, + )); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqtbx3_p8(a: poly8x8_t, b: poly8x16x3_t, c: uint8x8_t) -> poly8x8_t { - transmute(vqtbx3( - transmute(a), - transmute(b.0), - transmute(b.1), - transmute(b.2), - c, - )) +pub fn vqtbx3_p8(a: poly8x8_t, b: poly8x16x3_t, c: uint8x8_t) -> poly8x8_t { + unsafe { + transmute(vqtbx3( + transmute(a), + transmute(b.0), + transmute(b.1), + transmute(b.2), + c, + )) + } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqtbx3_p8(a: poly8x8_t, b: poly8x16x3_t, c: uint8x8_t) -> poly8x8_t { +pub fn vqtbx3_p8(a: poly8x8_t, b: poly8x16x3_t, c: uint8x8_t) -> poly8x8_t { let mut b: poly8x16x3_t = b; let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); b.0 = simd_shuffle!( @@ -22270,43 +20333,43 @@ pub unsafe fn vqtbx3_p8(a: poly8x8_t, b: poly8x16x3_t, c: uint8x8_t) -> poly8x8_ [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] ); let c: uint8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: poly8x8_t = transmute(vqtbx3( - transmute(a), - transmute(b.0), - transmute(b.1), - transmute(b.2), - c, - )); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: poly8x8_t = transmute(vqtbx3( + transmute(a), + transmute(b.0), + transmute(b.1), + transmute(b.2), + c, + )); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3q_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqtbx3q_p8(a: poly8x16_t, b: poly8x16x3_t, c: uint8x16_t) -> poly8x16_t { - transmute(vqtbx3q( - transmute(a), - transmute(b.0), - transmute(b.1), - transmute(b.2), - c, - )) +pub fn vqtbx3q_p8(a: poly8x16_t, b: poly8x16x3_t, c: uint8x16_t) -> poly8x16_t { + unsafe { + transmute(vqtbx3q( + transmute(a), + transmute(b.0), + transmute(b.1), + transmute(b.2), + c, + )) + } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3q_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqtbx3q_p8(a: poly8x16_t, b: poly8x16x3_t, c: uint8x16_t) -> poly8x16_t { +pub fn vqtbx3q_p8(a: poly8x16_t, b: poly8x16x3_t, c: uint8x16_t) -> poly8x16_t { let mut b: poly8x16x3_t = b; let a: poly8x16_t = simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); b.0 = simd_shuffle!( @@ -22325,28 +20388,28 @@ pub unsafe fn vqtbx3q_p8(a: poly8x16_t, b: poly8x16x3_t, c: uint8x16_t) -> poly8 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] ); let c: uint8x16_t = simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: poly8x16_t = transmute(vqtbx3q( - transmute(a), - transmute(b.0), - transmute(b.1), - transmute(b.2), - c, - )); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) + unsafe { + let ret_val: poly8x16_t = transmute(vqtbx3q( + transmute(a), + transmute(b.0), + transmute(b.1), + transmute(b.2), + c, + )); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -unsafe fn vqtbx4( +fn vqtbx4( a: int8x8_t, b: int8x16_t, c: int8x16_t, @@ -22368,17 +20431,15 @@ unsafe fn vqtbx4( f: uint8x8_t, ) -> int8x8_t; } - _vqtbx4(a, b, c, d, e, f) + unsafe { _vqtbx4(a, b, c, d, e, f) } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4q)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -unsafe fn vqtbx4q( +fn vqtbx4q( a: int8x16_t, b: int8x16_t, c: int8x16_t, @@ -22400,59 +20461,53 @@ unsafe fn vqtbx4q( f: uint8x16_t, ) -> int8x16_t; } - _vqtbx4q(a, b, c, d, e, f) + unsafe { _vqtbx4q(a, b, c, d, e, f) } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqtbx4_s8(a: int8x8_t, b: int8x16x4_t, c: uint8x8_t) -> int8x8_t { +pub fn vqtbx4_s8(a: int8x8_t, b: int8x16x4_t, c: uint8x8_t) -> int8x8_t { vqtbx4(a, b.0, b.1, b.2, b.3, c) } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4q_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqtbx4q_s8(a: int8x16_t, b: int8x16x4_t, c: uint8x16_t) -> int8x16_t { +pub fn vqtbx4q_s8(a: int8x16_t, b: int8x16x4_t, c: uint8x16_t) -> int8x16_t { vqtbx4q(a, b.0, b.1, b.2, b.3, c) } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqtbx4_u8(a: uint8x8_t, b: uint8x16x4_t, c: uint8x8_t) -> uint8x8_t { - transmute(vqtbx4( - transmute(a), - transmute(b.0), - transmute(b.1), - transmute(b.2), - transmute(b.3), - c, - )) +pub fn vqtbx4_u8(a: uint8x8_t, b: uint8x16x4_t, c: uint8x8_t) -> uint8x8_t { + unsafe { + transmute(vqtbx4( + transmute(a), + transmute(b.0), + transmute(b.1), + transmute(b.2), + transmute(b.3), + c, + )) + } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqtbx4_u8(a: uint8x8_t, b: uint8x16x4_t, c: uint8x8_t) -> uint8x8_t { +pub fn vqtbx4_u8(a: uint8x8_t, b: uint8x16x4_t, c: uint8x8_t) -> uint8x8_t { let mut b: uint8x16x4_t = b; let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); b.0 = simd_shuffle!( @@ -22476,45 +20531,45 @@ pub unsafe fn vqtbx4_u8(a: uint8x8_t, b: uint8x16x4_t, c: uint8x8_t) -> uint8x8_ [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] ); let c: uint8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: uint8x8_t = transmute(vqtbx4( - transmute(a), - transmute(b.0), - transmute(b.1), - transmute(b.2), - transmute(b.3), - c, - )); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: uint8x8_t = transmute(vqtbx4( + transmute(a), + transmute(b.0), + transmute(b.1), + transmute(b.2), + transmute(b.3), + c, + )); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4q_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqtbx4q_u8(a: uint8x16_t, b: uint8x16x4_t, c: uint8x16_t) -> uint8x16_t { - transmute(vqtbx4q( - transmute(a), - transmute(b.0), - transmute(b.1), - transmute(b.2), - transmute(b.3), - c, - )) +pub fn vqtbx4q_u8(a: uint8x16_t, b: uint8x16x4_t, c: uint8x16_t) -> uint8x16_t { + unsafe { + transmute(vqtbx4q( + transmute(a), + transmute(b.0), + transmute(b.1), + transmute(b.2), + transmute(b.3), + c, + )) + } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4q_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqtbx4q_u8(a: uint8x16_t, b: uint8x16x4_t, c: uint8x16_t) -> uint8x16_t { +pub fn vqtbx4q_u8(a: uint8x16_t, b: uint8x16x4_t, c: uint8x16_t) -> uint8x16_t { let mut b: uint8x16x4_t = b; let a: uint8x16_t = simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); b.0 = simd_shuffle!( @@ -22538,49 +20593,49 @@ pub unsafe fn vqtbx4q_u8(a: uint8x16_t, b: uint8x16x4_t, c: uint8x16_t) -> uint8 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] ); let c: uint8x16_t = simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: uint8x16_t = transmute(vqtbx4q( - transmute(a), - transmute(b.0), - transmute(b.1), - transmute(b.2), - transmute(b.3), - c, - )); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) + unsafe { + let ret_val: uint8x16_t = transmute(vqtbx4q( + transmute(a), + transmute(b.0), + transmute(b.1), + transmute(b.2), + transmute(b.3), + c, + )); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqtbx4_p8(a: poly8x8_t, b: poly8x16x4_t, c: uint8x8_t) -> poly8x8_t { - transmute(vqtbx4( - transmute(a), - transmute(b.0), - transmute(b.1), - transmute(b.2), - transmute(b.3), - c, - )) +pub fn vqtbx4_p8(a: poly8x8_t, b: poly8x16x4_t, c: uint8x8_t) -> poly8x8_t { + unsafe { + transmute(vqtbx4( + transmute(a), + transmute(b.0), + transmute(b.1), + transmute(b.2), + transmute(b.3), + c, + )) + } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqtbx4_p8(a: poly8x8_t, b: poly8x16x4_t, c: uint8x8_t) -> poly8x8_t { +pub fn vqtbx4_p8(a: poly8x8_t, b: poly8x16x4_t, c: uint8x8_t) -> poly8x8_t { let mut b: poly8x16x4_t = b; let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); b.0 = simd_shuffle!( @@ -22604,45 +20659,45 @@ pub unsafe fn vqtbx4_p8(a: poly8x8_t, b: poly8x16x4_t, c: uint8x8_t) -> poly8x8_ [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] ); let c: uint8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: poly8x8_t = transmute(vqtbx4( - transmute(a), - transmute(b.0), - transmute(b.1), - transmute(b.2), - transmute(b.3), - c, - )); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: poly8x8_t = transmute(vqtbx4( + transmute(a), + transmute(b.0), + transmute(b.1), + transmute(b.2), + transmute(b.3), + c, + )); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4q_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqtbx4q_p8(a: poly8x16_t, b: poly8x16x4_t, c: uint8x16_t) -> poly8x16_t { - transmute(vqtbx4q( - transmute(a), - transmute(b.0), - transmute(b.1), - transmute(b.2), - transmute(b.3), - c, - )) +pub fn vqtbx4q_p8(a: poly8x16_t, b: poly8x16x4_t, c: uint8x16_t) -> poly8x16_t { + unsafe { + transmute(vqtbx4q( + transmute(a), + transmute(b.0), + transmute(b.1), + transmute(b.2), + transmute(b.3), + c, + )) + } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4q_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqtbx4q_p8(a: poly8x16_t, b: poly8x16x4_t, c: uint8x16_t) -> poly8x16_t { +pub fn vqtbx4q_p8(a: poly8x16_t, b: poly8x16x4_t, c: uint8x16_t) -> poly8x16_t { let mut b: poly8x16x4_t = b; let a: poly8x16_t = simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); b.0 = simd_shuffle!( @@ -22666,29 +20721,29 @@ pub unsafe fn vqtbx4q_p8(a: poly8x16_t, b: poly8x16x4_t, c: uint8x16_t) -> poly8 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] ); let c: uint8x16_t = simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: poly8x16_t = transmute(vqtbx4q( - transmute(a), - transmute(b.0), - transmute(b.1), - transmute(b.2), - transmute(b.3), - c, - )); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) + unsafe { + let ret_val: poly8x16_t = transmute(vqtbx4q( + transmute(a), + transmute(b.0), + transmute(b.1), + transmute(b.2), + transmute(b.3), + c, + )); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } #[doc = "Rotate and exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrax1q_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,sha3")] #[cfg_attr(test, assert_instr(rax1))] #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] -pub unsafe fn vrax1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { +pub fn vrax1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -22696,17 +20751,15 @@ pub unsafe fn vrax1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { )] fn _vrax1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t; } - _vrax1q_u64(a, b) + unsafe { _vrax1q_u64(a, b) } } #[doc = "Reverse bit order"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbit_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(rbit))] -pub unsafe fn vrbit_s8(a: int8x8_t) -> int8x8_t { +pub fn vrbit_s8(a: int8x8_t) -> int8x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -22714,17 +20767,15 @@ pub unsafe fn vrbit_s8(a: int8x8_t) -> int8x8_t { )] fn _vrbit_s8(a: int8x8_t) -> int8x8_t; } - _vrbit_s8(a) + unsafe { _vrbit_s8(a) } } #[doc = "Reverse bit order"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbitq_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(rbit))] -pub unsafe fn vrbitq_s8(a: int8x16_t) -> int8x16_t { +pub fn vrbitq_s8(a: int8x16_t) -> int8x16_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -22732,129 +20783,119 @@ pub unsafe fn vrbitq_s8(a: int8x16_t) -> int8x16_t { )] fn _vrbitq_s8(a: int8x16_t) -> int8x16_t; } - _vrbitq_s8(a) + unsafe { _vrbitq_s8(a) } } #[doc = "Reverse bit order"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbit_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(rbit))] -pub unsafe fn vrbit_u8(a: uint8x8_t) -> uint8x8_t { - transmute(vrbit_s8(transmute(a))) +pub fn vrbit_u8(a: uint8x8_t) -> uint8x8_t { + unsafe { transmute(vrbit_s8(transmute(a))) } } #[doc = "Reverse bit order"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbit_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(rbit))] -pub unsafe fn vrbit_u8(a: uint8x8_t) -> uint8x8_t { +pub fn vrbit_u8(a: uint8x8_t) -> uint8x8_t { let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: uint8x8_t = transmute(vrbit_s8(transmute(a))); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: uint8x8_t = transmute(vrbit_s8(transmute(a))); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Reverse bit order"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbitq_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(rbit))] -pub unsafe fn vrbitq_u8(a: uint8x16_t) -> uint8x16_t { - transmute(vrbitq_s8(transmute(a))) +pub fn vrbitq_u8(a: uint8x16_t) -> uint8x16_t { + unsafe { transmute(vrbitq_s8(transmute(a))) } } #[doc = "Reverse bit order"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbitq_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(rbit))] -pub unsafe fn vrbitq_u8(a: uint8x16_t) -> uint8x16_t { +pub fn vrbitq_u8(a: uint8x16_t) -> uint8x16_t { let a: uint8x16_t = simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: uint8x16_t = transmute(vrbitq_s8(transmute(a))); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) + unsafe { + let ret_val: uint8x16_t = transmute(vrbitq_s8(transmute(a))); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } #[doc = "Reverse bit order"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbit_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(rbit))] -pub unsafe fn vrbit_p8(a: poly8x8_t) -> poly8x8_t { - transmute(vrbit_s8(transmute(a))) +pub fn vrbit_p8(a: poly8x8_t) -> poly8x8_t { + unsafe { transmute(vrbit_s8(transmute(a))) } } #[doc = "Reverse bit order"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbit_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(rbit))] -pub unsafe fn vrbit_p8(a: poly8x8_t) -> poly8x8_t { +pub fn vrbit_p8(a: poly8x8_t) -> poly8x8_t { let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: poly8x8_t = transmute(vrbit_s8(transmute(a))); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: poly8x8_t = transmute(vrbit_s8(transmute(a))); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Reverse bit order"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbitq_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(rbit))] -pub unsafe fn vrbitq_p8(a: poly8x16_t) -> poly8x16_t { - transmute(vrbitq_s8(transmute(a))) +pub fn vrbitq_p8(a: poly8x16_t) -> poly8x16_t { + unsafe { transmute(vrbitq_s8(transmute(a))) } } #[doc = "Reverse bit order"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbitq_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(rbit))] -pub unsafe fn vrbitq_p8(a: poly8x16_t) -> poly8x16_t { +pub fn vrbitq_p8(a: poly8x16_t) -> poly8x16_t { let a: poly8x16_t = simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: poly8x16_t = transmute(vrbitq_s8(transmute(a))); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) + unsafe { + let ret_val: poly8x16_t = transmute(vrbitq_s8(transmute(a))); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } #[doc = "Reciprocal estimate."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpe_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(frecpe))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrecpe_f64(a: float64x1_t) -> float64x1_t { +pub fn vrecpe_f64(a: float64x1_t) -> float64x1_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -22862,17 +20903,15 @@ pub unsafe fn vrecpe_f64(a: float64x1_t) -> float64x1_t { )] fn _vrecpe_f64(a: float64x1_t) -> float64x1_t; } - _vrecpe_f64(a) + unsafe { _vrecpe_f64(a) } } #[doc = "Reciprocal estimate."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpeq_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(frecpe))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrecpeq_f64(a: float64x2_t) -> float64x2_t { +pub fn vrecpeq_f64(a: float64x2_t) -> float64x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -22880,17 +20919,15 @@ pub unsafe fn vrecpeq_f64(a: float64x2_t) -> float64x2_t { )] fn _vrecpeq_f64(a: float64x2_t) -> float64x2_t; } - _vrecpeq_f64(a) + unsafe { _vrecpeq_f64(a) } } #[doc = "Reciprocal estimate."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecped_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(frecpe))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrecped_f64(a: f64) -> f64 { +pub fn vrecped_f64(a: f64) -> f64 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -22898,17 +20935,15 @@ pub unsafe fn vrecped_f64(a: f64) -> f64 { )] fn _vrecped_f64(a: f64) -> f64; } - _vrecped_f64(a) + unsafe { _vrecped_f64(a) } } #[doc = "Reciprocal estimate."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpes_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(frecpe))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrecpes_f32(a: f32) -> f32 { +pub fn vrecpes_f32(a: f32) -> f32 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -22916,17 +20951,15 @@ pub unsafe fn vrecpes_f32(a: f32) -> f32 { )] fn _vrecpes_f32(a: f32) -> f32; } - _vrecpes_f32(a) + unsafe { _vrecpes_f32(a) } } #[doc = "Reciprocal estimate."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpeh_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(frecpe))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vrecpeh_f16(a: f16) -> f16 { +pub fn vrecpeh_f16(a: f16) -> f16 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -22934,17 +20967,15 @@ pub unsafe fn vrecpeh_f16(a: f16) -> f16 { )] fn _vrecpeh_f16(a: f16) -> f16; } - _vrecpeh_f16(a) + unsafe { _vrecpeh_f16(a) } } #[doc = "Floating-point reciprocal step"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecps_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(frecps))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrecps_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { +pub fn vrecps_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -22952,17 +20983,15 @@ pub unsafe fn vrecps_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { )] fn _vrecps_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t; } - _vrecps_f64(a, b) + unsafe { _vrecps_f64(a, b) } } #[doc = "Floating-point reciprocal step"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpsq_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(frecps))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrecpsq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { +pub fn vrecpsq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -22970,17 +20999,15 @@ pub unsafe fn vrecpsq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { )] fn _vrecpsq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t; } - _vrecpsq_f64(a, b) + unsafe { _vrecpsq_f64(a, b) } } #[doc = "Floating-point reciprocal step"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpsd_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(frecps))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrecpsd_f64(a: f64, b: f64) -> f64 { +pub fn vrecpsd_f64(a: f64, b: f64) -> f64 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -22988,17 +21015,15 @@ pub unsafe fn vrecpsd_f64(a: f64, b: f64) -> f64 { )] fn _vrecpsd_f64(a: f64, b: f64) -> f64; } - _vrecpsd_f64(a, b) + unsafe { _vrecpsd_f64(a, b) } } #[doc = "Floating-point reciprocal step"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpss_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(frecps))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrecpss_f32(a: f32, b: f32) -> f32 { +pub fn vrecpss_f32(a: f32, b: f32) -> f32 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -23006,17 +21031,15 @@ pub unsafe fn vrecpss_f32(a: f32, b: f32) -> f32 { )] fn _vrecpss_f32(a: f32, b: f32) -> f32; } - _vrecpss_f32(a, b) + unsafe { _vrecpss_f32(a, b) } } #[doc = "Floating-point reciprocal step"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpsh_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(frecps))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vrecpsh_f16(a: f16, b: f16) -> f16 { +pub fn vrecpsh_f16(a: f16, b: f16) -> f16 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -23024,17 +21047,15 @@ pub unsafe fn vrecpsh_f16(a: f16, b: f16) -> f16 { )] fn _vrecpsh_f16(a: f16, b: f16) -> f16; } - _vrecpsh_f16(a, b) + unsafe { _vrecpsh_f16(a, b) } } #[doc = "Floating-point reciprocal exponent"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpxd_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(frecpx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrecpxd_f64(a: f64) -> f64 { +pub fn vrecpxd_f64(a: f64) -> f64 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -23042,17 +21063,15 @@ pub unsafe fn vrecpxd_f64(a: f64) -> f64 { )] fn _vrecpxd_f64(a: f64) -> f64; } - _vrecpxd_f64(a) + unsafe { _vrecpxd_f64(a) } } #[doc = "Floating-point reciprocal exponent"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpxs_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(frecpx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrecpxs_f32(a: f32) -> f32 { +pub fn vrecpxs_f32(a: f32) -> f32 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -23060,17 +21079,15 @@ pub unsafe fn vrecpxs_f32(a: f32) -> f32 { )] fn _vrecpxs_f32(a: f32) -> f32; } - _vrecpxs_f32(a) + unsafe { _vrecpxs_f32(a) } } #[doc = "Floating-point reciprocal exponent"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpxh_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(frecpx))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vrecpxh_f16(a: f16) -> f16 { +pub fn vrecpxh_f16(a: f16) -> f16 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -23078,1571 +21095,1413 @@ pub unsafe fn vrecpxh_f16(a: f16) -> f16 { )] fn _vrecpxh_f16(a: f16) -> f16; } - _vrecpxh_f16(a) + unsafe { _vrecpxh_f16(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpret_f64_f16(a: float16x4_t) -> float64x1_t { - transmute(a) +pub fn vreinterpret_f64_f16(a: float16x4_t) -> float64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpret_f64_f16(a: float16x4_t) -> float64x1_t { +pub fn vreinterpret_f64_f16(a: float16x4_t) -> float64x1_t { let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - transmute(a) + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpretq_f64_f16(a: float16x8_t) -> float64x2_t { - transmute(a) +pub fn vreinterpretq_f64_f16(a: float16x8_t) -> float64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpretq_f64_f16(a: float16x8_t) -> float64x2_t { +pub fn vreinterpretq_f64_f16(a: float16x8_t) -> float64x2_t { let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: float64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: float64x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpret_f16_f64(a: float64x1_t) -> float16x4_t { - transmute(a) +pub fn vreinterpret_f16_f64(a: float64x1_t) -> float16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpret_f16_f64(a: float64x1_t) -> float16x4_t { - let ret_val: float16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) +pub fn vreinterpret_f16_f64(a: float64x1_t) -> float16x4_t { + unsafe { + let ret_val: float16x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpretq_f16_f64(a: float64x2_t) -> float16x8_t { - transmute(a) +pub fn vreinterpretq_f16_f64(a: float64x2_t) -> float16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpretq_f16_f64(a: float64x2_t) -> float16x8_t { +pub fn vreinterpretq_f16_f64(a: float64x2_t) -> float16x8_t { let a: float64x2_t = simd_shuffle!(a, a, [1, 0]); - let ret_val: float16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: float16x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p128)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpretq_f64_p128(a: p128) -> float64x2_t { - transmute(a) +pub fn vreinterpretq_f64_p128(a: p128) -> float64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p128)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpretq_f64_p128(a: p128) -> float64x2_t { - let ret_val: float64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) +pub fn vreinterpretq_f64_p128(a: p128) -> float64x2_t { + unsafe { + let ret_val: float64x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpret_f64_f32(a: float32x2_t) -> float64x1_t { - transmute(a) +pub fn vreinterpret_f64_f32(a: float32x2_t) -> float64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpret_f64_f32(a: float32x2_t) -> float64x1_t { +pub fn vreinterpret_f64_f32(a: float32x2_t) -> float64x1_t { let a: float32x2_t = simd_shuffle!(a, a, [1, 0]); - transmute(a) + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpret_p64_f32(a: float32x2_t) -> poly64x1_t { - transmute(a) +pub fn vreinterpret_p64_f32(a: float32x2_t) -> poly64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpret_p64_f32(a: float32x2_t) -> poly64x1_t { +pub fn vreinterpret_p64_f32(a: float32x2_t) -> poly64x1_t { let a: float32x2_t = simd_shuffle!(a, a, [1, 0]); - transmute(a) + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpretq_f64_f32(a: float32x4_t) -> float64x2_t { - transmute(a) +pub fn vreinterpretq_f64_f32(a: float32x4_t) -> float64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpretq_f64_f32(a: float32x4_t) -> float64x2_t { +pub fn vreinterpretq_f64_f32(a: float32x4_t) -> float64x2_t { let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - let ret_val: float64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: float64x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpretq_p64_f32(a: float32x4_t) -> poly64x2_t { - transmute(a) +pub fn vreinterpretq_p64_f32(a: float32x4_t) -> poly64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpretq_p64_f32(a: float32x4_t) -> poly64x2_t { +pub fn vreinterpretq_p64_f32(a: float32x4_t) -> poly64x2_t { let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - let ret_val: poly64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: poly64x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpret_f32_f64(a: float64x1_t) -> float32x2_t { - transmute(a) +pub fn vreinterpret_f32_f64(a: float64x1_t) -> float32x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpret_f32_f64(a: float64x1_t) -> float32x2_t { - let ret_val: float32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) +pub fn vreinterpret_f32_f64(a: float64x1_t) -> float32x2_t { + unsafe { + let ret_val: float32x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpret_s8_f64(a: float64x1_t) -> int8x8_t { - transmute(a) +pub fn vreinterpret_s8_f64(a: float64x1_t) -> int8x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpret_s8_f64(a: float64x1_t) -> int8x8_t { - let ret_val: int8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) +pub fn vreinterpret_s8_f64(a: float64x1_t) -> int8x8_t { + unsafe { + let ret_val: int8x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpret_s16_f64(a: float64x1_t) -> int16x4_t { - transmute(a) +pub fn vreinterpret_s16_f64(a: float64x1_t) -> int16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpret_s16_f64(a: float64x1_t) -> int16x4_t { - let ret_val: int16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) +pub fn vreinterpret_s16_f64(a: float64x1_t) -> int16x4_t { + unsafe { + let ret_val: int16x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpret_s32_f64(a: float64x1_t) -> int32x2_t { - transmute(a) +pub fn vreinterpret_s32_f64(a: float64x1_t) -> int32x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpret_s32_f64(a: float64x1_t) -> int32x2_t { - let ret_val: int32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) +pub fn vreinterpret_s32_f64(a: float64x1_t) -> int32x2_t { + unsafe { + let ret_val: int32x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpret_s64_f64(a: float64x1_t) -> int64x1_t { - transmute(a) +pub fn vreinterpret_s64_f64(a: float64x1_t) -> int64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpret_u8_f64(a: float64x1_t) -> uint8x8_t { - transmute(a) +pub fn vreinterpret_u8_f64(a: float64x1_t) -> uint8x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpret_u8_f64(a: float64x1_t) -> uint8x8_t { - let ret_val: uint8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) +pub fn vreinterpret_u8_f64(a: float64x1_t) -> uint8x8_t { + unsafe { + let ret_val: uint8x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpret_u16_f64(a: float64x1_t) -> uint16x4_t { - transmute(a) +pub fn vreinterpret_u16_f64(a: float64x1_t) -> uint16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpret_u16_f64(a: float64x1_t) -> uint16x4_t { - let ret_val: uint16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) +pub fn vreinterpret_u16_f64(a: float64x1_t) -> uint16x4_t { + unsafe { + let ret_val: uint16x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpret_u32_f64(a: float64x1_t) -> uint32x2_t { - transmute(a) +pub fn vreinterpret_u32_f64(a: float64x1_t) -> uint32x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpret_u32_f64(a: float64x1_t) -> uint32x2_t { - let ret_val: uint32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) +pub fn vreinterpret_u32_f64(a: float64x1_t) -> uint32x2_t { + unsafe { + let ret_val: uint32x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpret_u64_f64(a: float64x1_t) -> uint64x1_t { - transmute(a) +pub fn vreinterpret_u64_f64(a: float64x1_t) -> uint64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpret_p8_f64(a: float64x1_t) -> poly8x8_t { - transmute(a) +pub fn vreinterpret_p8_f64(a: float64x1_t) -> poly8x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpret_p8_f64(a: float64x1_t) -> poly8x8_t { - let ret_val: poly8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) +pub fn vreinterpret_p8_f64(a: float64x1_t) -> poly8x8_t { + unsafe { + let ret_val: poly8x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpret_p16_f64(a: float64x1_t) -> poly16x4_t { - transmute(a) +pub fn vreinterpret_p16_f64(a: float64x1_t) -> poly16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpret_p16_f64(a: float64x1_t) -> poly16x4_t { - let ret_val: poly16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) +pub fn vreinterpret_p16_f64(a: float64x1_t) -> poly16x4_t { + unsafe { + let ret_val: poly16x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpret_p64_f64(a: float64x1_t) -> poly64x1_t { - transmute(a) +pub fn vreinterpret_p64_f64(a: float64x1_t) -> poly64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpretq_p128_f64(a: float64x2_t) -> p128 { - transmute(a) +pub fn vreinterpretq_p128_f64(a: float64x2_t) -> p128 { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpretq_p128_f64(a: float64x2_t) -> p128 { +pub fn vreinterpretq_p128_f64(a: float64x2_t) -> p128 { let a: float64x2_t = simd_shuffle!(a, a, [1, 0]); - transmute(a) + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpretq_f32_f64(a: float64x2_t) -> float32x4_t { - transmute(a) +pub fn vreinterpretq_f32_f64(a: float64x2_t) -> float32x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpretq_f32_f64(a: float64x2_t) -> float32x4_t { +pub fn vreinterpretq_f32_f64(a: float64x2_t) -> float32x4_t { let a: float64x2_t = simd_shuffle!(a, a, [1, 0]); - let ret_val: float32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + unsafe { + let ret_val: float32x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpretq_s8_f64(a: float64x2_t) -> int8x16_t { - transmute(a) +pub fn vreinterpretq_s8_f64(a: float64x2_t) -> int8x16_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpretq_s8_f64(a: float64x2_t) -> int8x16_t { +pub fn vreinterpretq_s8_f64(a: float64x2_t) -> int8x16_t { let a: float64x2_t = simd_shuffle!(a, a, [1, 0]); - let ret_val: int8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) + unsafe { + let ret_val: int8x16_t = transmute(a); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpretq_s16_f64(a: float64x2_t) -> int16x8_t { - transmute(a) +pub fn vreinterpretq_s16_f64(a: float64x2_t) -> int16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpretq_s16_f64(a: float64x2_t) -> int16x8_t { +pub fn vreinterpretq_s16_f64(a: float64x2_t) -> int16x8_t { let a: float64x2_t = simd_shuffle!(a, a, [1, 0]); - let ret_val: int16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: int16x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpretq_s32_f64(a: float64x2_t) -> int32x4_t { - transmute(a) +pub fn vreinterpretq_s32_f64(a: float64x2_t) -> int32x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpretq_s32_f64(a: float64x2_t) -> int32x4_t { +pub fn vreinterpretq_s32_f64(a: float64x2_t) -> int32x4_t { let a: float64x2_t = simd_shuffle!(a, a, [1, 0]); - let ret_val: int32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + unsafe { + let ret_val: int32x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpretq_s64_f64(a: float64x2_t) -> int64x2_t { - transmute(a) +pub fn vreinterpretq_s64_f64(a: float64x2_t) -> int64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpretq_s64_f64(a: float64x2_t) -> int64x2_t { +pub fn vreinterpretq_s64_f64(a: float64x2_t) -> int64x2_t { let a: float64x2_t = simd_shuffle!(a, a, [1, 0]); - let ret_val: int64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: int64x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpretq_u8_f64(a: float64x2_t) -> uint8x16_t { - transmute(a) +pub fn vreinterpretq_u8_f64(a: float64x2_t) -> uint8x16_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpretq_u8_f64(a: float64x2_t) -> uint8x16_t { +pub fn vreinterpretq_u8_f64(a: float64x2_t) -> uint8x16_t { let a: float64x2_t = simd_shuffle!(a, a, [1, 0]); - let ret_val: uint8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) + unsafe { + let ret_val: uint8x16_t = transmute(a); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpretq_u16_f64(a: float64x2_t) -> uint16x8_t { - transmute(a) +pub fn vreinterpretq_u16_f64(a: float64x2_t) -> uint16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpretq_u16_f64(a: float64x2_t) -> uint16x8_t { +pub fn vreinterpretq_u16_f64(a: float64x2_t) -> uint16x8_t { let a: float64x2_t = simd_shuffle!(a, a, [1, 0]); - let ret_val: uint16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: uint16x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpretq_u32_f64(a: float64x2_t) -> uint32x4_t { - transmute(a) +pub fn vreinterpretq_u32_f64(a: float64x2_t) -> uint32x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpretq_u32_f64(a: float64x2_t) -> uint32x4_t { +pub fn vreinterpretq_u32_f64(a: float64x2_t) -> uint32x4_t { let a: float64x2_t = simd_shuffle!(a, a, [1, 0]); - let ret_val: uint32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + unsafe { + let ret_val: uint32x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpretq_u64_f64(a: float64x2_t) -> uint64x2_t { - transmute(a) +pub fn vreinterpretq_u64_f64(a: float64x2_t) -> uint64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpretq_u64_f64(a: float64x2_t) -> uint64x2_t { +pub fn vreinterpretq_u64_f64(a: float64x2_t) -> uint64x2_t { let a: float64x2_t = simd_shuffle!(a, a, [1, 0]); - let ret_val: uint64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: uint64x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpretq_p8_f64(a: float64x2_t) -> poly8x16_t { - transmute(a) +pub fn vreinterpretq_p8_f64(a: float64x2_t) -> poly8x16_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpretq_p8_f64(a: float64x2_t) -> poly8x16_t { +pub fn vreinterpretq_p8_f64(a: float64x2_t) -> poly8x16_t { let a: float64x2_t = simd_shuffle!(a, a, [1, 0]); - let ret_val: poly8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) + unsafe { + let ret_val: poly8x16_t = transmute(a); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpretq_p16_f64(a: float64x2_t) -> poly16x8_t { - transmute(a) +pub fn vreinterpretq_p16_f64(a: float64x2_t) -> poly16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpretq_p16_f64(a: float64x2_t) -> poly16x8_t { +pub fn vreinterpretq_p16_f64(a: float64x2_t) -> poly16x8_t { let a: float64x2_t = simd_shuffle!(a, a, [1, 0]); - let ret_val: poly16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: poly16x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpretq_p64_f64(a: float64x2_t) -> poly64x2_t { - transmute(a) +pub fn vreinterpretq_p64_f64(a: float64x2_t) -> poly64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpretq_p64_f64(a: float64x2_t) -> poly64x2_t { +pub fn vreinterpretq_p64_f64(a: float64x2_t) -> poly64x2_t { let a: float64x2_t = simd_shuffle!(a, a, [1, 0]); - let ret_val: poly64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: poly64x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpret_f64_s8(a: int8x8_t) -> float64x1_t { - transmute(a) +pub fn vreinterpret_f64_s8(a: int8x8_t) -> float64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpret_f64_s8(a: int8x8_t) -> float64x1_t { +pub fn vreinterpret_f64_s8(a: int8x8_t) -> float64x1_t { let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - transmute(a) + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpretq_f64_s8(a: int8x16_t) -> float64x2_t { - transmute(a) +pub fn vreinterpretq_f64_s8(a: int8x16_t) -> float64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpretq_f64_s8(a: int8x16_t) -> float64x2_t { +pub fn vreinterpretq_f64_s8(a: int8x16_t) -> float64x2_t { let a: int8x16_t = simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: float64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: float64x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpret_f64_s16(a: int16x4_t) -> float64x1_t { - transmute(a) +pub fn vreinterpret_f64_s16(a: int16x4_t) -> float64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpret_f64_s16(a: int16x4_t) -> float64x1_t { +pub fn vreinterpret_f64_s16(a: int16x4_t) -> float64x1_t { let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - transmute(a) + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpretq_f64_s16(a: int16x8_t) -> float64x2_t { - transmute(a) +pub fn vreinterpretq_f64_s16(a: int16x8_t) -> float64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpretq_f64_s16(a: int16x8_t) -> float64x2_t { +pub fn vreinterpretq_f64_s16(a: int16x8_t) -> float64x2_t { let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: float64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: float64x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpret_f64_s32(a: int32x2_t) -> float64x1_t { - transmute(a) +pub fn vreinterpret_f64_s32(a: int32x2_t) -> float64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpret_f64_s32(a: int32x2_t) -> float64x1_t { +pub fn vreinterpret_f64_s32(a: int32x2_t) -> float64x1_t { let a: int32x2_t = simd_shuffle!(a, a, [1, 0]); - transmute(a) + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpretq_f64_s32(a: int32x4_t) -> float64x2_t { - transmute(a) +pub fn vreinterpretq_f64_s32(a: int32x4_t) -> float64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpretq_f64_s32(a: int32x4_t) -> float64x2_t { +pub fn vreinterpretq_f64_s32(a: int32x4_t) -> float64x2_t { let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - let ret_val: float64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: float64x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpret_f64_s64(a: int64x1_t) -> float64x1_t { - transmute(a) +pub fn vreinterpret_f64_s64(a: int64x1_t) -> float64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpret_p64_s64(a: int64x1_t) -> poly64x1_t { - transmute(a) +pub fn vreinterpret_p64_s64(a: int64x1_t) -> poly64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpretq_f64_s64(a: int64x2_t) -> float64x2_t { - transmute(a) +pub fn vreinterpretq_f64_s64(a: int64x2_t) -> float64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpretq_f64_s64(a: int64x2_t) -> float64x2_t { +pub fn vreinterpretq_f64_s64(a: int64x2_t) -> float64x2_t { let a: int64x2_t = simd_shuffle!(a, a, [1, 0]); - let ret_val: float64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: float64x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpretq_p64_s64(a: int64x2_t) -> poly64x2_t { - transmute(a) +pub fn vreinterpretq_p64_s64(a: int64x2_t) -> poly64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpretq_p64_s64(a: int64x2_t) -> poly64x2_t { +pub fn vreinterpretq_p64_s64(a: int64x2_t) -> poly64x2_t { let a: int64x2_t = simd_shuffle!(a, a, [1, 0]); - let ret_val: poly64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: poly64x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpret_f64_u8(a: uint8x8_t) -> float64x1_t { - transmute(a) +pub fn vreinterpret_f64_u8(a: uint8x8_t) -> float64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpret_f64_u8(a: uint8x8_t) -> float64x1_t { +pub fn vreinterpret_f64_u8(a: uint8x8_t) -> float64x1_t { let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - transmute(a) + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpretq_f64_u8(a: uint8x16_t) -> float64x2_t { - transmute(a) +pub fn vreinterpretq_f64_u8(a: uint8x16_t) -> float64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpretq_f64_u8(a: uint8x16_t) -> float64x2_t { +pub fn vreinterpretq_f64_u8(a: uint8x16_t) -> float64x2_t { let a: uint8x16_t = simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: float64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: float64x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpret_f64_u16(a: uint16x4_t) -> float64x1_t { - transmute(a) +pub fn vreinterpret_f64_u16(a: uint16x4_t) -> float64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpret_f64_u16(a: uint16x4_t) -> float64x1_t { +pub fn vreinterpret_f64_u16(a: uint16x4_t) -> float64x1_t { let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - transmute(a) + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpretq_f64_u16(a: uint16x8_t) -> float64x2_t { - transmute(a) +pub fn vreinterpretq_f64_u16(a: uint16x8_t) -> float64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpretq_f64_u16(a: uint16x8_t) -> float64x2_t { +pub fn vreinterpretq_f64_u16(a: uint16x8_t) -> float64x2_t { let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: float64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: float64x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpret_f64_u32(a: uint32x2_t) -> float64x1_t { - transmute(a) +pub fn vreinterpret_f64_u32(a: uint32x2_t) -> float64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpret_f64_u32(a: uint32x2_t) -> float64x1_t { +pub fn vreinterpret_f64_u32(a: uint32x2_t) -> float64x1_t { let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]); - transmute(a) + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpretq_f64_u32(a: uint32x4_t) -> float64x2_t { - transmute(a) +pub fn vreinterpretq_f64_u32(a: uint32x4_t) -> float64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpretq_f64_u32(a: uint32x4_t) -> float64x2_t { +pub fn vreinterpretq_f64_u32(a: uint32x4_t) -> float64x2_t { let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - let ret_val: float64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: float64x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpret_f64_u64(a: uint64x1_t) -> float64x1_t { - transmute(a) +pub fn vreinterpret_f64_u64(a: uint64x1_t) -> float64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpret_p64_u64(a: uint64x1_t) -> poly64x1_t { - transmute(a) +pub fn vreinterpret_p64_u64(a: uint64x1_t) -> poly64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpretq_f64_u64(a: uint64x2_t) -> float64x2_t { - transmute(a) +pub fn vreinterpretq_f64_u64(a: uint64x2_t) -> float64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpretq_f64_u64(a: uint64x2_t) -> float64x2_t { +pub fn vreinterpretq_f64_u64(a: uint64x2_t) -> float64x2_t { let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]); - let ret_val: float64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: float64x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpretq_p64_u64(a: uint64x2_t) -> poly64x2_t { - transmute(a) +pub fn vreinterpretq_p64_u64(a: uint64x2_t) -> poly64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpretq_p64_u64(a: uint64x2_t) -> poly64x2_t { +pub fn vreinterpretq_p64_u64(a: uint64x2_t) -> poly64x2_t { let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]); - let ret_val: poly64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: poly64x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpret_f64_p8(a: poly8x8_t) -> float64x1_t { - transmute(a) +pub fn vreinterpret_f64_p8(a: poly8x8_t) -> float64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpret_f64_p8(a: poly8x8_t) -> float64x1_t { +pub fn vreinterpret_f64_p8(a: poly8x8_t) -> float64x1_t { let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - transmute(a) + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpretq_f64_p8(a: poly8x16_t) -> float64x2_t { - transmute(a) +pub fn vreinterpretq_f64_p8(a: poly8x16_t) -> float64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpretq_f64_p8(a: poly8x16_t) -> float64x2_t { +pub fn vreinterpretq_f64_p8(a: poly8x16_t) -> float64x2_t { let a: poly8x16_t = simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: float64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: float64x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpret_f64_p16(a: poly16x4_t) -> float64x1_t { - transmute(a) +pub fn vreinterpret_f64_p16(a: poly16x4_t) -> float64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpret_f64_p16(a: poly16x4_t) -> float64x1_t { +pub fn vreinterpret_f64_p16(a: poly16x4_t) -> float64x1_t { let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - transmute(a) + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpretq_f64_p16(a: poly16x8_t) -> float64x2_t { - transmute(a) +pub fn vreinterpretq_f64_p16(a: poly16x8_t) -> float64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpretq_f64_p16(a: poly16x8_t) -> float64x2_t { +pub fn vreinterpretq_f64_p16(a: poly16x8_t) -> float64x2_t { let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: float64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: float64x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpret_f32_p64(a: poly64x1_t) -> float32x2_t { - transmute(a) +pub fn vreinterpret_f32_p64(a: poly64x1_t) -> float32x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpret_f32_p64(a: poly64x1_t) -> float32x2_t { - let ret_val: float32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) +pub fn vreinterpret_f32_p64(a: poly64x1_t) -> float32x2_t { + unsafe { + let ret_val: float32x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpret_f64_p64(a: poly64x1_t) -> float64x1_t { - transmute(a) +pub fn vreinterpret_f64_p64(a: poly64x1_t) -> float64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpret_s64_p64(a: poly64x1_t) -> int64x1_t { - transmute(a) +pub fn vreinterpret_s64_p64(a: poly64x1_t) -> int64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpret_u64_p64(a: poly64x1_t) -> uint64x1_t { - transmute(a) +pub fn vreinterpret_u64_p64(a: poly64x1_t) -> uint64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpretq_f32_p64(a: poly64x2_t) -> float32x4_t { - transmute(a) +pub fn vreinterpretq_f32_p64(a: poly64x2_t) -> float32x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpretq_f32_p64(a: poly64x2_t) -> float32x4_t { +pub fn vreinterpretq_f32_p64(a: poly64x2_t) -> float32x4_t { let a: poly64x2_t = simd_shuffle!(a, a, [1, 0]); - let ret_val: float32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + unsafe { + let ret_val: float32x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpretq_f64_p64(a: poly64x2_t) -> float64x2_t { - transmute(a) +pub fn vreinterpretq_f64_p64(a: poly64x2_t) -> float64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpretq_f64_p64(a: poly64x2_t) -> float64x2_t { +pub fn vreinterpretq_f64_p64(a: poly64x2_t) -> float64x2_t { let a: poly64x2_t = simd_shuffle!(a, a, [1, 0]); - let ret_val: float64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: float64x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpretq_s64_p64(a: poly64x2_t) -> int64x2_t { - transmute(a) +pub fn vreinterpretq_s64_p64(a: poly64x2_t) -> int64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpretq_s64_p64(a: poly64x2_t) -> int64x2_t { +pub fn vreinterpretq_s64_p64(a: poly64x2_t) -> int64x2_t { let a: poly64x2_t = simd_shuffle!(a, a, [1, 0]); - let ret_val: int64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: int64x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpretq_u64_p64(a: poly64x2_t) -> uint64x2_t { - transmute(a) +pub fn vreinterpretq_u64_p64(a: poly64x2_t) -> uint64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vreinterpretq_u64_p64(a: poly64x2_t) -> uint64x2_t { +pub fn vreinterpretq_u64_p64(a: poly64x2_t) -> uint64x2_t { let a: poly64x2_t = simd_shuffle!(a, a, [1, 0]); - let ret_val: uint64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: uint64x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Floating-point round to 32-bit integer, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd32x_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,frintts")] #[unstable(feature = "stdarch_neon_ftts", issue = "117227")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint32x))] -pub unsafe fn vrnd32x_f32(a: float32x2_t) -> float32x2_t { +pub fn vrnd32x_f32(a: float32x2_t) -> float32x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -24650,17 +22509,15 @@ pub unsafe fn vrnd32x_f32(a: float32x2_t) -> float32x2_t { )] fn _vrnd32x_f32(a: float32x2_t) -> float32x2_t; } - _vrnd32x_f32(a) + unsafe { _vrnd32x_f32(a) } } #[doc = "Floating-point round to 32-bit integer, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd32xq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,frintts")] #[unstable(feature = "stdarch_neon_ftts", issue = "117227")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint32x))] -pub unsafe fn vrnd32xq_f32(a: float32x4_t) -> float32x4_t { +pub fn vrnd32xq_f32(a: float32x4_t) -> float32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -24668,17 +22525,15 @@ pub unsafe fn vrnd32xq_f32(a: float32x4_t) -> float32x4_t { )] fn _vrnd32xq_f32(a: float32x4_t) -> float32x4_t; } - _vrnd32xq_f32(a) + unsafe { _vrnd32xq_f32(a) } } #[doc = "Floating-point round to 32-bit integer, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd32xq_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,frintts")] #[unstable(feature = "stdarch_neon_ftts", issue = "117227")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint32x))] -pub unsafe fn vrnd32xq_f64(a: float64x2_t) -> float64x2_t { +pub fn vrnd32xq_f64(a: float64x2_t) -> float64x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -24686,17 +22541,15 @@ pub unsafe fn vrnd32xq_f64(a: float64x2_t) -> float64x2_t { )] fn _vrnd32xq_f64(a: float64x2_t) -> float64x2_t; } - _vrnd32xq_f64(a) + unsafe { _vrnd32xq_f64(a) } } #[doc = "Floating-point round to 32-bit integer, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd32x_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,frintts")] #[unstable(feature = "stdarch_neon_ftts", issue = "117227")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint32x))] -pub unsafe fn vrnd32x_f64(a: float64x1_t) -> float64x1_t { +pub fn vrnd32x_f64(a: float64x1_t) -> float64x1_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -24704,17 +22557,15 @@ pub unsafe fn vrnd32x_f64(a: float64x1_t) -> float64x1_t { )] fn _vrnd32x_f64(a: f64) -> f64; } - transmute(_vrnd32x_f64(simd_extract!(a, 0))) + unsafe { transmute(_vrnd32x_f64(simd_extract!(a, 0))) } } #[doc = "Floating-point round to 32-bit integer toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd32z_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,frintts")] #[unstable(feature = "stdarch_neon_ftts", issue = "117227")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint32z))] -pub unsafe fn vrnd32z_f32(a: float32x2_t) -> float32x2_t { +pub fn vrnd32z_f32(a: float32x2_t) -> float32x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -24722,17 +22573,15 @@ pub unsafe fn vrnd32z_f32(a: float32x2_t) -> float32x2_t { )] fn _vrnd32z_f32(a: float32x2_t) -> float32x2_t; } - _vrnd32z_f32(a) + unsafe { _vrnd32z_f32(a) } } #[doc = "Floating-point round to 32-bit integer toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd32zq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,frintts")] #[unstable(feature = "stdarch_neon_ftts", issue = "117227")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint32z))] -pub unsafe fn vrnd32zq_f32(a: float32x4_t) -> float32x4_t { +pub fn vrnd32zq_f32(a: float32x4_t) -> float32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -24740,17 +22589,15 @@ pub unsafe fn vrnd32zq_f32(a: float32x4_t) -> float32x4_t { )] fn _vrnd32zq_f32(a: float32x4_t) -> float32x4_t; } - _vrnd32zq_f32(a) + unsafe { _vrnd32zq_f32(a) } } #[doc = "Floating-point round to 32-bit integer toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd32zq_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,frintts")] #[unstable(feature = "stdarch_neon_ftts", issue = "117227")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint32z))] -pub unsafe fn vrnd32zq_f64(a: float64x2_t) -> float64x2_t { +pub fn vrnd32zq_f64(a: float64x2_t) -> float64x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -24758,17 +22605,15 @@ pub unsafe fn vrnd32zq_f64(a: float64x2_t) -> float64x2_t { )] fn _vrnd32zq_f64(a: float64x2_t) -> float64x2_t; } - _vrnd32zq_f64(a) + unsafe { _vrnd32zq_f64(a) } } #[doc = "Floating-point round to 32-bit integer toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd32z_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,frintts")] #[unstable(feature = "stdarch_neon_ftts", issue = "117227")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint32z))] -pub unsafe fn vrnd32z_f64(a: float64x1_t) -> float64x1_t { +pub fn vrnd32z_f64(a: float64x1_t) -> float64x1_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -24776,17 +22621,15 @@ pub unsafe fn vrnd32z_f64(a: float64x1_t) -> float64x1_t { )] fn _vrnd32z_f64(a: f64) -> f64; } - transmute(_vrnd32z_f64(simd_extract!(a, 0))) + unsafe { transmute(_vrnd32z_f64(simd_extract!(a, 0))) } } #[doc = "Floating-point round to 64-bit integer, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd64x_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,frintts")] #[unstable(feature = "stdarch_neon_ftts", issue = "117227")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint64x))] -pub unsafe fn vrnd64x_f32(a: float32x2_t) -> float32x2_t { +pub fn vrnd64x_f32(a: float32x2_t) -> float32x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -24794,17 +22637,15 @@ pub unsafe fn vrnd64x_f32(a: float32x2_t) -> float32x2_t { )] fn _vrnd64x_f32(a: float32x2_t) -> float32x2_t; } - _vrnd64x_f32(a) + unsafe { _vrnd64x_f32(a) } } #[doc = "Floating-point round to 64-bit integer, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd64xq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,frintts")] #[unstable(feature = "stdarch_neon_ftts", issue = "117227")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint64x))] -pub unsafe fn vrnd64xq_f32(a: float32x4_t) -> float32x4_t { +pub fn vrnd64xq_f32(a: float32x4_t) -> float32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -24812,17 +22653,15 @@ pub unsafe fn vrnd64xq_f32(a: float32x4_t) -> float32x4_t { )] fn _vrnd64xq_f32(a: float32x4_t) -> float32x4_t; } - _vrnd64xq_f32(a) + unsafe { _vrnd64xq_f32(a) } } #[doc = "Floating-point round to 64-bit integer, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd64xq_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,frintts")] #[unstable(feature = "stdarch_neon_ftts", issue = "117227")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint64x))] -pub unsafe fn vrnd64xq_f64(a: float64x2_t) -> float64x2_t { +pub fn vrnd64xq_f64(a: float64x2_t) -> float64x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -24830,17 +22669,15 @@ pub unsafe fn vrnd64xq_f64(a: float64x2_t) -> float64x2_t { )] fn _vrnd64xq_f64(a: float64x2_t) -> float64x2_t; } - _vrnd64xq_f64(a) + unsafe { _vrnd64xq_f64(a) } } #[doc = "Floating-point round to 64-bit integer, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd64x_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,frintts")] #[unstable(feature = "stdarch_neon_ftts", issue = "117227")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint64x))] -pub unsafe fn vrnd64x_f64(a: float64x1_t) -> float64x1_t { +pub fn vrnd64x_f64(a: float64x1_t) -> float64x1_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -24848,17 +22685,15 @@ pub unsafe fn vrnd64x_f64(a: float64x1_t) -> float64x1_t { )] fn _vrnd64x_f64(a: f64) -> f64; } - transmute(_vrnd64x_f64(simd_extract!(a, 0))) + unsafe { transmute(_vrnd64x_f64(simd_extract!(a, 0))) } } #[doc = "Floating-point round to 64-bit integer toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd64z_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,frintts")] #[unstable(feature = "stdarch_neon_ftts", issue = "117227")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint64z))] -pub unsafe fn vrnd64z_f32(a: float32x2_t) -> float32x2_t { +pub fn vrnd64z_f32(a: float32x2_t) -> float32x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -24866,17 +22701,15 @@ pub unsafe fn vrnd64z_f32(a: float32x2_t) -> float32x2_t { )] fn _vrnd64z_f32(a: float32x2_t) -> float32x2_t; } - _vrnd64z_f32(a) + unsafe { _vrnd64z_f32(a) } } #[doc = "Floating-point round to 64-bit integer toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd64zq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,frintts")] #[unstable(feature = "stdarch_neon_ftts", issue = "117227")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint64z))] -pub unsafe fn vrnd64zq_f32(a: float32x4_t) -> float32x4_t { +pub fn vrnd64zq_f32(a: float32x4_t) -> float32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -24884,17 +22717,15 @@ pub unsafe fn vrnd64zq_f32(a: float32x4_t) -> float32x4_t { )] fn _vrnd64zq_f32(a: float32x4_t) -> float32x4_t; } - _vrnd64zq_f32(a) + unsafe { _vrnd64zq_f32(a) } } #[doc = "Floating-point round to 64-bit integer toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd64zq_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,frintts")] #[unstable(feature = "stdarch_neon_ftts", issue = "117227")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint64z))] -pub unsafe fn vrnd64zq_f64(a: float64x2_t) -> float64x2_t { +pub fn vrnd64zq_f64(a: float64x2_t) -> float64x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -24902,17 +22733,15 @@ pub unsafe fn vrnd64zq_f64(a: float64x2_t) -> float64x2_t { )] fn _vrnd64zq_f64(a: float64x2_t) -> float64x2_t; } - _vrnd64zq_f64(a) + unsafe { _vrnd64zq_f64(a) } } #[doc = "Floating-point round to 64-bit integer toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd64z_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,frintts")] #[unstable(feature = "stdarch_neon_ftts", issue = "117227")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint64z))] -pub unsafe fn vrnd64z_f64(a: float64x1_t) -> float64x1_t { +pub fn vrnd64z_f64(a: float64x1_t) -> float64x1_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -24920,17 +22749,15 @@ pub unsafe fn vrnd64z_f64(a: float64x1_t) -> float64x1_t { )] fn _vrnd64z_f64(a: f64) -> f64; } - transmute(_vrnd64z_f64(simd_extract!(a, 0))) + unsafe { transmute(_vrnd64z_f64(simd_extract!(a, 0))) } } #[doc = "Floating-point round to integral, toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(frintz))] -pub unsafe fn vrnd_f16(a: float16x4_t) -> float16x4_t { +pub fn vrnd_f16(a: float16x4_t) -> float16x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -24938,17 +22765,15 @@ pub unsafe fn vrnd_f16(a: float16x4_t) -> float16x4_t { )] fn _vrnd_f16(a: float16x4_t) -> float16x4_t; } - _vrnd_f16(a) + unsafe { _vrnd_f16(a) } } #[doc = "Floating-point round to integral, toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndq_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(frintz))] -pub unsafe fn vrndq_f16(a: float16x8_t) -> float16x8_t { +pub fn vrndq_f16(a: float16x8_t) -> float16x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -24956,17 +22781,15 @@ pub unsafe fn vrndq_f16(a: float16x8_t) -> float16x8_t { )] fn _vrndq_f16(a: float16x8_t) -> float16x8_t; } - _vrndq_f16(a) + unsafe { _vrndq_f16(a) } } #[doc = "Floating-point round to integral, toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(frintz))] -pub unsafe fn vrnd_f32(a: float32x2_t) -> float32x2_t { +pub fn vrnd_f32(a: float32x2_t) -> float32x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -24974,17 +22797,15 @@ pub unsafe fn vrnd_f32(a: float32x2_t) -> float32x2_t { )] fn _vrnd_f32(a: float32x2_t) -> float32x2_t; } - _vrnd_f32(a) + unsafe { _vrnd_f32(a) } } #[doc = "Floating-point round to integral, toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(frintz))] -pub unsafe fn vrndq_f32(a: float32x4_t) -> float32x4_t { +pub fn vrndq_f32(a: float32x4_t) -> float32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -24992,17 +22813,15 @@ pub unsafe fn vrndq_f32(a: float32x4_t) -> float32x4_t { )] fn _vrndq_f32(a: float32x4_t) -> float32x4_t; } - _vrndq_f32(a) + unsafe { _vrndq_f32(a) } } #[doc = "Floating-point round to integral, toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(frintz))] -pub unsafe fn vrnd_f64(a: float64x1_t) -> float64x1_t { +pub fn vrnd_f64(a: float64x1_t) -> float64x1_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -25010,17 +22829,15 @@ pub unsafe fn vrnd_f64(a: float64x1_t) -> float64x1_t { )] fn _vrnd_f64(a: float64x1_t) -> float64x1_t; } - _vrnd_f64(a) + unsafe { _vrnd_f64(a) } } #[doc = "Floating-point round to integral, toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndq_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(frintz))] -pub unsafe fn vrndq_f64(a: float64x2_t) -> float64x2_t { +pub fn vrndq_f64(a: float64x2_t) -> float64x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -25028,17 +22845,15 @@ pub unsafe fn vrndq_f64(a: float64x2_t) -> float64x2_t { )] fn _vrndq_f64(a: float64x2_t) -> float64x2_t; } - _vrndq_f64(a) + unsafe { _vrndq_f64(a) } } #[doc = "Floating-point round to integral, to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnda_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(frinta))] -pub unsafe fn vrnda_f16(a: float16x4_t) -> float16x4_t { +pub fn vrnda_f16(a: float16x4_t) -> float16x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -25046,17 +22861,15 @@ pub unsafe fn vrnda_f16(a: float16x4_t) -> float16x4_t { )] fn _vrnda_f16(a: float16x4_t) -> float16x4_t; } - _vrnda_f16(a) + unsafe { _vrnda_f16(a) } } #[doc = "Floating-point round to integral, to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndaq_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(frinta))] -pub unsafe fn vrndaq_f16(a: float16x8_t) -> float16x8_t { +pub fn vrndaq_f16(a: float16x8_t) -> float16x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -25064,17 +22877,15 @@ pub unsafe fn vrndaq_f16(a: float16x8_t) -> float16x8_t { )] fn _vrndaq_f16(a: float16x8_t) -> float16x8_t; } - _vrndaq_f16(a) + unsafe { _vrndaq_f16(a) } } #[doc = "Floating-point round to integral, to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnda_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(frinta))] -pub unsafe fn vrnda_f32(a: float32x2_t) -> float32x2_t { +pub fn vrnda_f32(a: float32x2_t) -> float32x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -25082,17 +22893,15 @@ pub unsafe fn vrnda_f32(a: float32x2_t) -> float32x2_t { )] fn _vrnda_f32(a: float32x2_t) -> float32x2_t; } - _vrnda_f32(a) + unsafe { _vrnda_f32(a) } } #[doc = "Floating-point round to integral, to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndaq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(frinta))] -pub unsafe fn vrndaq_f32(a: float32x4_t) -> float32x4_t { +pub fn vrndaq_f32(a: float32x4_t) -> float32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -25100,17 +22909,15 @@ pub unsafe fn vrndaq_f32(a: float32x4_t) -> float32x4_t { )] fn _vrndaq_f32(a: float32x4_t) -> float32x4_t; } - _vrndaq_f32(a) + unsafe { _vrndaq_f32(a) } } #[doc = "Floating-point round to integral, to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnda_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(frinta))] -pub unsafe fn vrnda_f64(a: float64x1_t) -> float64x1_t { +pub fn vrnda_f64(a: float64x1_t) -> float64x1_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -25118,17 +22925,15 @@ pub unsafe fn vrnda_f64(a: float64x1_t) -> float64x1_t { )] fn _vrnda_f64(a: float64x1_t) -> float64x1_t; } - _vrnda_f64(a) + unsafe { _vrnda_f64(a) } } #[doc = "Floating-point round to integral, to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndaq_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(frinta))] -pub unsafe fn vrndaq_f64(a: float64x2_t) -> float64x2_t { +pub fn vrndaq_f64(a: float64x2_t) -> float64x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -25136,17 +22941,15 @@ pub unsafe fn vrndaq_f64(a: float64x2_t) -> float64x2_t { )] fn _vrndaq_f64(a: float64x2_t) -> float64x2_t; } - _vrndaq_f64(a) + unsafe { _vrndaq_f64(a) } } #[doc = "Floating-point round to integral, to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndah_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(frinta))] -pub unsafe fn vrndah_f16(a: f16) -> f16 { +pub fn vrndah_f16(a: f16) -> f16 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -25154,17 +22957,15 @@ pub unsafe fn vrndah_f16(a: f16) -> f16 { )] fn _vrndah_f16(a: f16) -> f16; } - _vrndah_f16(a) + unsafe { _vrndah_f16(a) } } #[doc = "Floating-point round to integral, to nearest with ties to away"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndh_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(frintz))] -pub unsafe fn vrndh_f16(a: f16) -> f16 { +pub fn vrndh_f16(a: f16) -> f16 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -25172,17 +22973,15 @@ pub unsafe fn vrndh_f16(a: f16) -> f16 { )] fn _vrndh_f16(a: f16) -> f16; } - _vrndh_f16(a) + unsafe { _vrndh_f16(a) } } #[doc = "Floating-point round to integral, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndi_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(frinti))] -pub unsafe fn vrndi_f16(a: float16x4_t) -> float16x4_t { +pub fn vrndi_f16(a: float16x4_t) -> float16x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -25190,17 +22989,15 @@ pub unsafe fn vrndi_f16(a: float16x4_t) -> float16x4_t { )] fn _vrndi_f16(a: float16x4_t) -> float16x4_t; } - _vrndi_f16(a) + unsafe { _vrndi_f16(a) } } #[doc = "Floating-point round to integral, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndiq_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(frinti))] -pub unsafe fn vrndiq_f16(a: float16x8_t) -> float16x8_t { +pub fn vrndiq_f16(a: float16x8_t) -> float16x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -25208,17 +23005,15 @@ pub unsafe fn vrndiq_f16(a: float16x8_t) -> float16x8_t { )] fn _vrndiq_f16(a: float16x8_t) -> float16x8_t; } - _vrndiq_f16(a) + unsafe { _vrndiq_f16(a) } } #[doc = "Floating-point round to integral, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndi_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(frinti))] -pub unsafe fn vrndi_f32(a: float32x2_t) -> float32x2_t { +pub fn vrndi_f32(a: float32x2_t) -> float32x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -25226,17 +23021,15 @@ pub unsafe fn vrndi_f32(a: float32x2_t) -> float32x2_t { )] fn _vrndi_f32(a: float32x2_t) -> float32x2_t; } - _vrndi_f32(a) + unsafe { _vrndi_f32(a) } } #[doc = "Floating-point round to integral, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndiq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(frinti))] -pub unsafe fn vrndiq_f32(a: float32x4_t) -> float32x4_t { +pub fn vrndiq_f32(a: float32x4_t) -> float32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -25244,17 +23037,15 @@ pub unsafe fn vrndiq_f32(a: float32x4_t) -> float32x4_t { )] fn _vrndiq_f32(a: float32x4_t) -> float32x4_t; } - _vrndiq_f32(a) + unsafe { _vrndiq_f32(a) } } #[doc = "Floating-point round to integral, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndi_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(frinti))] -pub unsafe fn vrndi_f64(a: float64x1_t) -> float64x1_t { +pub fn vrndi_f64(a: float64x1_t) -> float64x1_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -25262,17 +23053,15 @@ pub unsafe fn vrndi_f64(a: float64x1_t) -> float64x1_t { )] fn _vrndi_f64(a: float64x1_t) -> float64x1_t; } - _vrndi_f64(a) + unsafe { _vrndi_f64(a) } } #[doc = "Floating-point round to integral, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndiq_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(frinti))] -pub unsafe fn vrndiq_f64(a: float64x2_t) -> float64x2_t { +pub fn vrndiq_f64(a: float64x2_t) -> float64x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -25280,17 +23069,15 @@ pub unsafe fn vrndiq_f64(a: float64x2_t) -> float64x2_t { )] fn _vrndiq_f64(a: float64x2_t) -> float64x2_t; } - _vrndiq_f64(a) + unsafe { _vrndiq_f64(a) } } #[doc = "Floating-point round to integral, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndih_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(frinti))] -pub unsafe fn vrndih_f16(a: f16) -> f16 { +pub fn vrndih_f16(a: f16) -> f16 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -25298,17 +23085,15 @@ pub unsafe fn vrndih_f16(a: f16) -> f16 { )] fn _vrndih_f16(a: f16) -> f16; } - _vrndih_f16(a) + unsafe { _vrndih_f16(a) } } #[doc = "Floating-point round to integral, toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndm_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(frintm))] -pub unsafe fn vrndm_f16(a: float16x4_t) -> float16x4_t { +pub fn vrndm_f16(a: float16x4_t) -> float16x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -25316,17 +23101,15 @@ pub unsafe fn vrndm_f16(a: float16x4_t) -> float16x4_t { )] fn _vrndm_f16(a: float16x4_t) -> float16x4_t; } - _vrndm_f16(a) + unsafe { _vrndm_f16(a) } } #[doc = "Floating-point round to integral, toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndmq_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(frintm))] -pub unsafe fn vrndmq_f16(a: float16x8_t) -> float16x8_t { +pub fn vrndmq_f16(a: float16x8_t) -> float16x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -25334,17 +23117,15 @@ pub unsafe fn vrndmq_f16(a: float16x8_t) -> float16x8_t { )] fn _vrndmq_f16(a: float16x8_t) -> float16x8_t; } - _vrndmq_f16(a) + unsafe { _vrndmq_f16(a) } } #[doc = "Floating-point round to integral, toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndm_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(frintm))] -pub unsafe fn vrndm_f32(a: float32x2_t) -> float32x2_t { +pub fn vrndm_f32(a: float32x2_t) -> float32x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -25352,17 +23133,15 @@ pub unsafe fn vrndm_f32(a: float32x2_t) -> float32x2_t { )] fn _vrndm_f32(a: float32x2_t) -> float32x2_t; } - _vrndm_f32(a) + unsafe { _vrndm_f32(a) } } #[doc = "Floating-point round to integral, toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndmq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(frintm))] -pub unsafe fn vrndmq_f32(a: float32x4_t) -> float32x4_t { +pub fn vrndmq_f32(a: float32x4_t) -> float32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -25370,17 +23149,15 @@ pub unsafe fn vrndmq_f32(a: float32x4_t) -> float32x4_t { )] fn _vrndmq_f32(a: float32x4_t) -> float32x4_t; } - _vrndmq_f32(a) + unsafe { _vrndmq_f32(a) } } #[doc = "Floating-point round to integral, toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndm_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(frintm))] -pub unsafe fn vrndm_f64(a: float64x1_t) -> float64x1_t { +pub fn vrndm_f64(a: float64x1_t) -> float64x1_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -25388,17 +23165,15 @@ pub unsafe fn vrndm_f64(a: float64x1_t) -> float64x1_t { )] fn _vrndm_f64(a: float64x1_t) -> float64x1_t; } - _vrndm_f64(a) + unsafe { _vrndm_f64(a) } } #[doc = "Floating-point round to integral, toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndmq_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(frintm))] -pub unsafe fn vrndmq_f64(a: float64x2_t) -> float64x2_t { +pub fn vrndmq_f64(a: float64x2_t) -> float64x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -25406,17 +23181,15 @@ pub unsafe fn vrndmq_f64(a: float64x2_t) -> float64x2_t { )] fn _vrndmq_f64(a: float64x2_t) -> float64x2_t; } - _vrndmq_f64(a) + unsafe { _vrndmq_f64(a) } } #[doc = "Floating-point round to integral, toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndmh_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(frintm))] -pub unsafe fn vrndmh_f16(a: f16) -> f16 { +pub fn vrndmh_f16(a: f16) -> f16 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -25424,17 +23197,15 @@ pub unsafe fn vrndmh_f16(a: f16) -> f16 { )] fn _vrndmh_f16(a: f16) -> f16; } - _vrndmh_f16(a) + unsafe { _vrndmh_f16(a) } } #[doc = "Floating-point round to integral, to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndn_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(frintn))] -pub unsafe fn vrndn_f64(a: float64x1_t) -> float64x1_t { +pub fn vrndn_f64(a: float64x1_t) -> float64x1_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -25442,17 +23213,15 @@ pub unsafe fn vrndn_f64(a: float64x1_t) -> float64x1_t { )] fn _vrndn_f64(a: float64x1_t) -> float64x1_t; } - _vrndn_f64(a) + unsafe { _vrndn_f64(a) } } #[doc = "Floating-point round to integral, to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndnq_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(frintn))] -pub unsafe fn vrndnq_f64(a: float64x2_t) -> float64x2_t { +pub fn vrndnq_f64(a: float64x2_t) -> float64x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -25460,17 +23229,15 @@ pub unsafe fn vrndnq_f64(a: float64x2_t) -> float64x2_t { )] fn _vrndnq_f64(a: float64x2_t) -> float64x2_t; } - _vrndnq_f64(a) + unsafe { _vrndnq_f64(a) } } #[doc = "Floating-point round to integral, toward minus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndnh_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(frintn))] -pub unsafe fn vrndnh_f16(a: f16) -> f16 { +pub fn vrndnh_f16(a: f16) -> f16 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -25478,17 +23245,15 @@ pub unsafe fn vrndnh_f16(a: f16) -> f16 { )] fn _vrndnh_f16(a: f16) -> f16; } - _vrndnh_f16(a) + unsafe { _vrndnh_f16(a) } } #[doc = "Floating-point round to integral, to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndns_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(frintn))] -pub unsafe fn vrndns_f32(a: f32) -> f32 { +pub fn vrndns_f32(a: f32) -> f32 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -25496,17 +23261,15 @@ pub unsafe fn vrndns_f32(a: f32) -> f32 { )] fn _vrndns_f32(a: f32) -> f32; } - _vrndns_f32(a) + unsafe { _vrndns_f32(a) } } #[doc = "Floating-point round to integral, toward plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndp_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(frintp))] -pub unsafe fn vrndp_f16(a: float16x4_t) -> float16x4_t { +pub fn vrndp_f16(a: float16x4_t) -> float16x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -25514,17 +23277,15 @@ pub unsafe fn vrndp_f16(a: float16x4_t) -> float16x4_t { )] fn _vrndp_f16(a: float16x4_t) -> float16x4_t; } - _vrndp_f16(a) + unsafe { _vrndp_f16(a) } } #[doc = "Floating-point round to integral, toward plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndpq_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(frintp))] -pub unsafe fn vrndpq_f16(a: float16x8_t) -> float16x8_t { +pub fn vrndpq_f16(a: float16x8_t) -> float16x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -25532,17 +23293,15 @@ pub unsafe fn vrndpq_f16(a: float16x8_t) -> float16x8_t { )] fn _vrndpq_f16(a: float16x8_t) -> float16x8_t; } - _vrndpq_f16(a) + unsafe { _vrndpq_f16(a) } } #[doc = "Floating-point round to integral, toward plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndp_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(frintp))] -pub unsafe fn vrndp_f32(a: float32x2_t) -> float32x2_t { +pub fn vrndp_f32(a: float32x2_t) -> float32x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -25550,17 +23309,15 @@ pub unsafe fn vrndp_f32(a: float32x2_t) -> float32x2_t { )] fn _vrndp_f32(a: float32x2_t) -> float32x2_t; } - _vrndp_f32(a) + unsafe { _vrndp_f32(a) } } #[doc = "Floating-point round to integral, toward plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndpq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(frintp))] -pub unsafe fn vrndpq_f32(a: float32x4_t) -> float32x4_t { +pub fn vrndpq_f32(a: float32x4_t) -> float32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -25568,17 +23325,15 @@ pub unsafe fn vrndpq_f32(a: float32x4_t) -> float32x4_t { )] fn _vrndpq_f32(a: float32x4_t) -> float32x4_t; } - _vrndpq_f32(a) + unsafe { _vrndpq_f32(a) } } #[doc = "Floating-point round to integral, toward plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndp_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(frintp))] -pub unsafe fn vrndp_f64(a: float64x1_t) -> float64x1_t { +pub fn vrndp_f64(a: float64x1_t) -> float64x1_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -25586,17 +23341,15 @@ pub unsafe fn vrndp_f64(a: float64x1_t) -> float64x1_t { )] fn _vrndp_f64(a: float64x1_t) -> float64x1_t; } - _vrndp_f64(a) + unsafe { _vrndp_f64(a) } } #[doc = "Floating-point round to integral, toward plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndpq_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(frintp))] -pub unsafe fn vrndpq_f64(a: float64x2_t) -> float64x2_t { +pub fn vrndpq_f64(a: float64x2_t) -> float64x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -25604,17 +23357,15 @@ pub unsafe fn vrndpq_f64(a: float64x2_t) -> float64x2_t { )] fn _vrndpq_f64(a: float64x2_t) -> float64x2_t; } - _vrndpq_f64(a) + unsafe { _vrndpq_f64(a) } } #[doc = "Floating-point round to integral, toward plus infinity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndph_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(frintp))] -pub unsafe fn vrndph_f16(a: f16) -> f16 { +pub fn vrndph_f16(a: f16) -> f16 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -25622,17 +23373,15 @@ pub unsafe fn vrndph_f16(a: f16) -> f16 { )] fn _vrndph_f16(a: f16) -> f16; } - _vrndph_f16(a) + unsafe { _vrndph_f16(a) } } #[doc = "Floating-point round to integral exact, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndx_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(frintx))] -pub unsafe fn vrndx_f16(a: float16x4_t) -> float16x4_t { +pub fn vrndx_f16(a: float16x4_t) -> float16x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -25640,17 +23389,15 @@ pub unsafe fn vrndx_f16(a: float16x4_t) -> float16x4_t { )] fn _vrndx_f16(a: float16x4_t) -> float16x4_t; } - _vrndx_f16(a) + unsafe { _vrndx_f16(a) } } #[doc = "Floating-point round to integral exact, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndxq_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(frintx))] -pub unsafe fn vrndxq_f16(a: float16x8_t) -> float16x8_t { +pub fn vrndxq_f16(a: float16x8_t) -> float16x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -25658,17 +23405,15 @@ pub unsafe fn vrndxq_f16(a: float16x8_t) -> float16x8_t { )] fn _vrndxq_f16(a: float16x8_t) -> float16x8_t; } - _vrndxq_f16(a) + unsafe { _vrndxq_f16(a) } } #[doc = "Floating-point round to integral exact, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndx_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(frintx))] -pub unsafe fn vrndx_f32(a: float32x2_t) -> float32x2_t { +pub fn vrndx_f32(a: float32x2_t) -> float32x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -25676,17 +23421,15 @@ pub unsafe fn vrndx_f32(a: float32x2_t) -> float32x2_t { )] fn _vrndx_f32(a: float32x2_t) -> float32x2_t; } - _vrndx_f32(a) + unsafe { _vrndx_f32(a) } } #[doc = "Floating-point round to integral exact, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndxq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(frintx))] -pub unsafe fn vrndxq_f32(a: float32x4_t) -> float32x4_t { +pub fn vrndxq_f32(a: float32x4_t) -> float32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -25694,17 +23437,15 @@ pub unsafe fn vrndxq_f32(a: float32x4_t) -> float32x4_t { )] fn _vrndxq_f32(a: float32x4_t) -> float32x4_t; } - _vrndxq_f32(a) + unsafe { _vrndxq_f32(a) } } #[doc = "Floating-point round to integral exact, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndx_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(frintx))] -pub unsafe fn vrndx_f64(a: float64x1_t) -> float64x1_t { +pub fn vrndx_f64(a: float64x1_t) -> float64x1_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -25712,17 +23453,15 @@ pub unsafe fn vrndx_f64(a: float64x1_t) -> float64x1_t { )] fn _vrndx_f64(a: float64x1_t) -> float64x1_t; } - _vrndx_f64(a) + unsafe { _vrndx_f64(a) } } #[doc = "Floating-point round to integral exact, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndxq_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(frintx))] -pub unsafe fn vrndxq_f64(a: float64x2_t) -> float64x2_t { +pub fn vrndxq_f64(a: float64x2_t) -> float64x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -25730,17 +23469,15 @@ pub unsafe fn vrndxq_f64(a: float64x2_t) -> float64x2_t { )] fn _vrndxq_f64(a: float64x2_t) -> float64x2_t; } - _vrndxq_f64(a) + unsafe { _vrndxq_f64(a) } } #[doc = "Floating-point round to integral, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndxh_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(frintx))] -pub unsafe fn vrndxh_f16(a: f16) -> f16 { +pub fn vrndxh_f16(a: f16) -> f16 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -25748,17 +23485,15 @@ pub unsafe fn vrndxh_f16(a: f16) -> f16 { )] fn _vrndxh_f16(a: f16) -> f16; } - _vrndxh_f16(a) + unsafe { _vrndxh_f16(a) } } #[doc = "Signed rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshld_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(srshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrshld_s64(a: i64, b: i64) -> i64 { +pub fn vrshld_s64(a: i64, b: i64) -> i64 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -25766,17 +23501,15 @@ pub unsafe fn vrshld_s64(a: i64, b: i64) -> i64 { )] fn _vrshld_s64(a: i64, b: i64) -> i64; } - _vrshld_s64(a, b) + unsafe { _vrshld_s64(a, b) } } #[doc = "Unsigned rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshld_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(urshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrshld_u64(a: u64, b: i64) -> u64 { +pub fn vrshld_u64(a: u64, b: i64) -> u64 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -25784,129 +23517,115 @@ pub unsafe fn vrshld_u64(a: u64, b: i64) -> u64 { )] fn _vrshld_u64(a: u64, b: i64) -> u64; } - _vrshld_u64(a, b) + unsafe { _vrshld_u64(a, b) } } #[doc = "Signed rounding shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrd_n_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(srshr, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrshrd_n_s64(a: i64) -> i64 { +pub fn vrshrd_n_s64(a: i64) -> i64 { static_assert!(N >= 1 && N <= 64); vrshld_s64(a, -N as i64) } #[doc = "Unsigned rounding shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrd_n_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(urshr, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrshrd_n_u64(a: u64) -> u64 { +pub fn vrshrd_n_u64(a: u64) -> u64 { static_assert!(N >= 1 && N <= 64); vrshld_u64(a, -N as i64) } #[doc = "Rounding shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_high_n_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(rshrn2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrshrn_high_n_s16(a: int8x8_t, b: int16x8_t) -> int8x16_t { +pub fn vrshrn_high_n_s16(a: int8x8_t, b: int16x8_t) -> int8x16_t { static_assert!(N >= 1 && N <= 8); - simd_shuffle!( - a, - vrshrn_n_s16::(b), - [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] - ) + unsafe { + simd_shuffle!( + a, + vrshrn_n_s16::(b), + [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] + ) + } } #[doc = "Rounding shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_high_n_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(rshrn2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrshrn_high_n_s32(a: int16x4_t, b: int32x4_t) -> int16x8_t { +pub fn vrshrn_high_n_s32(a: int16x4_t, b: int32x4_t) -> int16x8_t { static_assert!(N >= 1 && N <= 16); - simd_shuffle!(a, vrshrn_n_s32::(b), [0, 1, 2, 3, 4, 5, 6, 7]) + unsafe { simd_shuffle!(a, vrshrn_n_s32::(b), [0, 1, 2, 3, 4, 5, 6, 7]) } } #[doc = "Rounding shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_high_n_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(rshrn2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrshrn_high_n_s64(a: int32x2_t, b: int64x2_t) -> int32x4_t { +pub fn vrshrn_high_n_s64(a: int32x2_t, b: int64x2_t) -> int32x4_t { static_assert!(N >= 1 && N <= 32); - simd_shuffle!(a, vrshrn_n_s64::(b), [0, 1, 2, 3]) + unsafe { simd_shuffle!(a, vrshrn_n_s64::(b), [0, 1, 2, 3]) } } #[doc = "Rounding shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_high_n_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(rshrn2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrshrn_high_n_u16(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t { +pub fn vrshrn_high_n_u16(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t { static_assert!(N >= 1 && N <= 8); - simd_shuffle!( - a, - vrshrn_n_u16::(b), - [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] - ) + unsafe { + simd_shuffle!( + a, + vrshrn_n_u16::(b), + [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] + ) + } } #[doc = "Rounding shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_high_n_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(rshrn2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrshrn_high_n_u32(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t { +pub fn vrshrn_high_n_u32(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t { static_assert!(N >= 1 && N <= 16); - simd_shuffle!(a, vrshrn_n_u32::(b), [0, 1, 2, 3, 4, 5, 6, 7]) + unsafe { simd_shuffle!(a, vrshrn_n_u32::(b), [0, 1, 2, 3, 4, 5, 6, 7]) } } #[doc = "Rounding shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_high_n_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(rshrn2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrshrn_high_n_u64(a: uint32x2_t, b: uint64x2_t) -> uint32x4_t { +pub fn vrshrn_high_n_u64(a: uint32x2_t, b: uint64x2_t) -> uint32x4_t { static_assert!(N >= 1 && N <= 32); - simd_shuffle!(a, vrshrn_n_u64::(b), [0, 1, 2, 3]) + unsafe { simd_shuffle!(a, vrshrn_n_u64::(b), [0, 1, 2, 3]) } } #[doc = "Reciprocal square-root estimate."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrte_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(frsqrte))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrsqrte_f64(a: float64x1_t) -> float64x1_t { +pub fn vrsqrte_f64(a: float64x1_t) -> float64x1_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -25914,17 +23633,15 @@ pub unsafe fn vrsqrte_f64(a: float64x1_t) -> float64x1_t { )] fn _vrsqrte_f64(a: float64x1_t) -> float64x1_t; } - _vrsqrte_f64(a) + unsafe { _vrsqrte_f64(a) } } #[doc = "Reciprocal square-root estimate."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrteq_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(frsqrte))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrsqrteq_f64(a: float64x2_t) -> float64x2_t { +pub fn vrsqrteq_f64(a: float64x2_t) -> float64x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -25932,17 +23649,15 @@ pub unsafe fn vrsqrteq_f64(a: float64x2_t) -> float64x2_t { )] fn _vrsqrteq_f64(a: float64x2_t) -> float64x2_t; } - _vrsqrteq_f64(a) + unsafe { _vrsqrteq_f64(a) } } #[doc = "Reciprocal square-root estimate."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrted_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(frsqrte))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrsqrted_f64(a: f64) -> f64 { +pub fn vrsqrted_f64(a: f64) -> f64 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -25950,17 +23665,15 @@ pub unsafe fn vrsqrted_f64(a: f64) -> f64 { )] fn _vrsqrted_f64(a: f64) -> f64; } - _vrsqrted_f64(a) + unsafe { _vrsqrted_f64(a) } } #[doc = "Reciprocal square-root estimate."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrtes_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(frsqrte))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrsqrtes_f32(a: f32) -> f32 { +pub fn vrsqrtes_f32(a: f32) -> f32 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -25968,18 +23681,16 @@ pub unsafe fn vrsqrtes_f32(a: f32) -> f32 { )] fn _vrsqrtes_f32(a: f32) -> f32; } - _vrsqrtes_f32(a) + unsafe { _vrsqrtes_f32(a) } } #[doc = "Reciprocal square-root estimate."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrteh_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fp16")] #[cfg_attr(test, assert_instr(frsqrte))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vrsqrteh_f16(a: f16) -> f16 { +pub fn vrsqrteh_f16(a: f16) -> f16 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -25987,17 +23698,15 @@ pub unsafe fn vrsqrteh_f16(a: f16) -> f16 { )] fn _vrsqrteh_f16(a: f16) -> f16; } - _vrsqrteh_f16(a) + unsafe { _vrsqrteh_f16(a) } } #[doc = "Floating-point reciprocal square root step"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrts_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(frsqrts))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrsqrts_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { +pub fn vrsqrts_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -26005,17 +23714,15 @@ pub unsafe fn vrsqrts_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { )] fn _vrsqrts_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t; } - _vrsqrts_f64(a, b) + unsafe { _vrsqrts_f64(a, b) } } #[doc = "Floating-point reciprocal square root step"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrtsq_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(frsqrts))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrsqrtsq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { +pub fn vrsqrtsq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -26023,17 +23730,15 @@ pub unsafe fn vrsqrtsq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { )] fn _vrsqrtsq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t; } - _vrsqrtsq_f64(a, b) + unsafe { _vrsqrtsq_f64(a, b) } } #[doc = "Floating-point reciprocal square root step"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrtsd_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(frsqrts))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrsqrtsd_f64(a: f64, b: f64) -> f64 { +pub fn vrsqrtsd_f64(a: f64, b: f64) -> f64 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -26041,17 +23746,15 @@ pub unsafe fn vrsqrtsd_f64(a: f64, b: f64) -> f64 { )] fn _vrsqrtsd_f64(a: f64, b: f64) -> f64; } - _vrsqrtsd_f64(a, b) + unsafe { _vrsqrtsd_f64(a, b) } } #[doc = "Floating-point reciprocal square root step"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrtss_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(frsqrts))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrsqrtss_f32(a: f32, b: f32) -> f32 { +pub fn vrsqrtss_f32(a: f32, b: f32) -> f32 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -26059,17 +23762,15 @@ pub unsafe fn vrsqrtss_f32(a: f32, b: f32) -> f32 { )] fn _vrsqrtss_f32(a: f32, b: f32) -> f32; } - _vrsqrtss_f32(a, b) + unsafe { _vrsqrtss_f32(a, b) } } #[doc = "Floating-point reciprocal square root step"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrtsh_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fp16")] #[cfg_attr(test, assert_instr(frsqrts))] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vrsqrtsh_f16(a: f16, b: f16) -> f16 { +pub fn vrsqrtsh_f16(a: f16, b: f16) -> f16 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -26077,143 +23778,121 @@ pub unsafe fn vrsqrtsh_f16(a: f16, b: f16) -> f16 { )] fn _vrsqrtsh_f16(a: f16, b: f16) -> f16; } - _vrsqrtsh_f16(a, b) + unsafe { _vrsqrtsh_f16(a, b) } } #[doc = "Signed rounding shift right and accumulate."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsrad_n_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(srshr, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrsrad_n_s64(a: i64, b: i64) -> i64 { +pub fn vrsrad_n_s64(a: i64, b: i64) -> i64 { static_assert!(N >= 1 && N <= 64); let b: i64 = vrshrd_n_s64::(b); a.wrapping_add(b) } #[doc = "Unsigned rounding shift right and accumulate."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsrad_n_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(urshr, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrsrad_n_u64(a: u64, b: u64) -> u64 { +pub fn vrsrad_n_u64(a: u64, b: u64) -> u64 { static_assert!(N >= 1 && N <= 64); let b: u64 = vrshrd_n_u64::(b); a.wrapping_add(b) } #[doc = "Rounding subtract returning high narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(rsubhn2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrsubhn_high_s16(a: int8x8_t, b: int16x8_t, c: int16x8_t) -> int8x16_t { +pub fn vrsubhn_high_s16(a: int8x8_t, b: int16x8_t, c: int16x8_t) -> int8x16_t { let x: int8x8_t = vrsubhn_s16(b, c); - simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) + unsafe { simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) } } #[doc = "Rounding subtract returning high narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(rsubhn2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrsubhn_high_s32(a: int16x4_t, b: int32x4_t, c: int32x4_t) -> int16x8_t { +pub fn vrsubhn_high_s32(a: int16x4_t, b: int32x4_t, c: int32x4_t) -> int16x8_t { let x: int16x4_t = vrsubhn_s32(b, c); - simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7]) + unsafe { simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7]) } } #[doc = "Rounding subtract returning high narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(rsubhn2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrsubhn_high_s64(a: int32x2_t, b: int64x2_t, c: int64x2_t) -> int32x4_t { +pub fn vrsubhn_high_s64(a: int32x2_t, b: int64x2_t, c: int64x2_t) -> int32x4_t { let x: int32x2_t = vrsubhn_s64(b, c); - simd_shuffle!(a, x, [0, 1, 2, 3]) + unsafe { simd_shuffle!(a, x, [0, 1, 2, 3]) } } #[doc = "Rounding subtract returning high narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(rsubhn2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrsubhn_high_u16(a: uint8x8_t, b: uint16x8_t, c: uint16x8_t) -> uint8x16_t { +pub fn vrsubhn_high_u16(a: uint8x8_t, b: uint16x8_t, c: uint16x8_t) -> uint8x16_t { let x: uint8x8_t = vrsubhn_u16(b, c); - simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) + unsafe { simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) } } #[doc = "Rounding subtract returning high narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(rsubhn2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrsubhn_high_u32(a: uint16x4_t, b: uint32x4_t, c: uint32x4_t) -> uint16x8_t { +pub fn vrsubhn_high_u32(a: uint16x4_t, b: uint32x4_t, c: uint32x4_t) -> uint16x8_t { let x: uint16x4_t = vrsubhn_u32(b, c); - simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7]) + unsafe { simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7]) } } #[doc = "Rounding subtract returning high narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(rsubhn2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrsubhn_high_u64(a: uint32x2_t, b: uint64x2_t, c: uint64x2_t) -> uint32x4_t { +pub fn vrsubhn_high_u64(a: uint32x2_t, b: uint64x2_t, c: uint64x2_t) -> uint32x4_t { let x: uint32x2_t = vrsubhn_u64(b, c); - simd_shuffle!(a, x, [0, 1, 2, 3]) + unsafe { simd_shuffle!(a, x, [0, 1, 2, 3]) } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vset_lane_f64(a: f64, b: float64x1_t) -> float64x1_t { +pub fn vset_lane_f64(a: f64, b: float64x1_t) -> float64x1_t { static_assert!(LANE == 0); - simd_insert!(b, LANE as u32, a) + unsafe { simd_insert!(b, LANE as u32, a) } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vsetq_lane_f64(a: f64, b: float64x2_t) -> float64x2_t { +pub fn vsetq_lane_f64(a: f64, b: float64x2_t) -> float64x2_t { static_assert_uimm_bits!(LANE, 1); - simd_insert!(b, LANE as u32, a) + unsafe { simd_insert!(b, LANE as u32, a) } } #[doc = "SHA512 hash update part 2"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha512h2q_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,sha3")] #[cfg_attr(test, assert_instr(sha512h2))] #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] -pub unsafe fn vsha512h2q_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t { +pub fn vsha512h2q_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -26221,17 +23900,15 @@ pub unsafe fn vsha512h2q_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uin )] fn _vsha512h2q_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t; } - _vsha512h2q_u64(a, b, c) + unsafe { _vsha512h2q_u64(a, b, c) } } #[doc = "SHA512 hash update part 1"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha512hq_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,sha3")] #[cfg_attr(test, assert_instr(sha512h))] #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] -pub unsafe fn vsha512hq_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t { +pub fn vsha512hq_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -26239,17 +23916,15 @@ pub unsafe fn vsha512hq_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint )] fn _vsha512hq_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t; } - _vsha512hq_u64(a, b, c) + unsafe { _vsha512hq_u64(a, b, c) } } #[doc = "SHA512 schedule update 0"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha512su0q_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,sha3")] #[cfg_attr(test, assert_instr(sha512su0))] #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] -pub unsafe fn vsha512su0q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { +pub fn vsha512su0q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -26257,17 +23932,15 @@ pub unsafe fn vsha512su0q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { )] fn _vsha512su0q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t; } - _vsha512su0q_u64(a, b) + unsafe { _vsha512su0q_u64(a, b) } } #[doc = "SHA512 schedule update 1"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha512su1q_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,sha3")] #[cfg_attr(test, assert_instr(sha512su1))] #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] -pub unsafe fn vsha512su1q_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t { +pub fn vsha512su1q_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -26275,210 +23948,196 @@ pub unsafe fn vsha512su1q_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> ui )] fn _vsha512su1q_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t; } - _vsha512su1q_u64(a, b, c) + unsafe { _vsha512su1q_u64(a, b, c) } } #[doc = "Signed Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshld_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vshld_s64(a: i64, b: i64) -> i64 { - transmute(vshl_s64(transmute(a), transmute(b))) +pub fn vshld_s64(a: i64, b: i64) -> i64 { + unsafe { transmute(vshl_s64(transmute(a), transmute(b))) } } #[doc = "Unsigned Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshld_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ushl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vshld_u64(a: u64, b: i64) -> u64 { - transmute(vshl_u64(transmute(a), transmute(b))) +pub fn vshld_u64(a: u64, b: i64) -> u64 { + unsafe { transmute(vshl_u64(transmute(a), transmute(b))) } } #[doc = "Signed shift left long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_high_n_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sshll2, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vshll_high_n_s8(a: int8x16_t) -> int16x8_t { +pub fn vshll_high_n_s8(a: int8x16_t) -> int16x8_t { static_assert!(N >= 0 && N <= 8); - let b: int8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); - vshll_n_s8::(b) + unsafe { + let b: int8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); + vshll_n_s8::(b) + } } #[doc = "Signed shift left long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_high_n_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sshll2, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vshll_high_n_s16(a: int16x8_t) -> int32x4_t { +pub fn vshll_high_n_s16(a: int16x8_t) -> int32x4_t { static_assert!(N >= 0 && N <= 16); - let b: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); - vshll_n_s16::(b) + unsafe { + let b: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); + vshll_n_s16::(b) + } } #[doc = "Signed shift left long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_high_n_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sshll2, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vshll_high_n_s32(a: int32x4_t) -> int64x2_t { +pub fn vshll_high_n_s32(a: int32x4_t) -> int64x2_t { static_assert!(N >= 0 && N <= 32); - let b: int32x2_t = simd_shuffle!(a, a, [2, 3]); - vshll_n_s32::(b) + unsafe { + let b: int32x2_t = simd_shuffle!(a, a, [2, 3]); + vshll_n_s32::(b) + } } #[doc = "Signed shift left long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_high_n_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ushll2, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vshll_high_n_u8(a: uint8x16_t) -> uint16x8_t { +pub fn vshll_high_n_u8(a: uint8x16_t) -> uint16x8_t { static_assert!(N >= 0 && N <= 8); - let b: uint8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); - vshll_n_u8::(b) + unsafe { + let b: uint8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); + vshll_n_u8::(b) + } } #[doc = "Signed shift left long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_high_n_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ushll2, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vshll_high_n_u16(a: uint16x8_t) -> uint32x4_t { +pub fn vshll_high_n_u16(a: uint16x8_t) -> uint32x4_t { static_assert!(N >= 0 && N <= 16); - let b: uint16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); - vshll_n_u16::(b) + unsafe { + let b: uint16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); + vshll_n_u16::(b) + } } #[doc = "Signed shift left long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_high_n_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ushll2, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vshll_high_n_u32(a: uint32x4_t) -> uint64x2_t { +pub fn vshll_high_n_u32(a: uint32x4_t) -> uint64x2_t { static_assert!(N >= 0 && N <= 32); - let b: uint32x2_t = simd_shuffle!(a, a, [2, 3]); - vshll_n_u32::(b) + unsafe { + let b: uint32x2_t = simd_shuffle!(a, a, [2, 3]); + vshll_n_u32::(b) + } } #[doc = "Shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(shrn2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vshrn_high_n_s16(a: int8x8_t, b: int16x8_t) -> int8x16_t { +pub fn vshrn_high_n_s16(a: int8x8_t, b: int16x8_t) -> int8x16_t { static_assert!(N >= 1 && N <= 8); - simd_shuffle!( - a, - vshrn_n_s16::(b), - [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] - ) + unsafe { + simd_shuffle!( + a, + vshrn_n_s16::(b), + [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] + ) + } } #[doc = "Shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(shrn2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vshrn_high_n_s32(a: int16x4_t, b: int32x4_t) -> int16x8_t { +pub fn vshrn_high_n_s32(a: int16x4_t, b: int32x4_t) -> int16x8_t { static_assert!(N >= 1 && N <= 16); - simd_shuffle!(a, vshrn_n_s32::(b), [0, 1, 2, 3, 4, 5, 6, 7]) + unsafe { simd_shuffle!(a, vshrn_n_s32::(b), [0, 1, 2, 3, 4, 5, 6, 7]) } } #[doc = "Shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(shrn2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vshrn_high_n_s64(a: int32x2_t, b: int64x2_t) -> int32x4_t { +pub fn vshrn_high_n_s64(a: int32x2_t, b: int64x2_t) -> int32x4_t { static_assert!(N >= 1 && N <= 32); - simd_shuffle!(a, vshrn_n_s64::(b), [0, 1, 2, 3]) + unsafe { simd_shuffle!(a, vshrn_n_s64::(b), [0, 1, 2, 3]) } } #[doc = "Shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(shrn2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vshrn_high_n_u16(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t { +pub fn vshrn_high_n_u16(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t { static_assert!(N >= 1 && N <= 8); - simd_shuffle!( - a, - vshrn_n_u16::(b), - [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] - ) + unsafe { + simd_shuffle!( + a, + vshrn_n_u16::(b), + [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] + ) + } } #[doc = "Shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(shrn2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vshrn_high_n_u32(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t { +pub fn vshrn_high_n_u32(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t { static_assert!(N >= 1 && N <= 16); - simd_shuffle!(a, vshrn_n_u32::(b), [0, 1, 2, 3, 4, 5, 6, 7]) + unsafe { simd_shuffle!(a, vshrn_n_u32::(b), [0, 1, 2, 3, 4, 5, 6, 7]) } } #[doc = "Shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(shrn2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vshrn_high_n_u64(a: uint32x2_t, b: uint64x2_t) -> uint32x4_t { +pub fn vshrn_high_n_u64(a: uint32x2_t, b: uint64x2_t) -> uint32x4_t { static_assert!(N >= 1 && N <= 32); - simd_shuffle!(a, vshrn_n_u64::(b), [0, 1, 2, 3]) + unsafe { simd_shuffle!(a, vshrn_n_u64::(b), [0, 1, 2, 3]) } } #[doc = "Shift Left and Insert (immediate)"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_s8)"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sli, N = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vsli_n_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { +pub fn vsli_n_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { static_assert_uimm_bits!(N, 3); unsafe extern "unadjusted" { #[cfg_attr( @@ -26487,18 +24146,16 @@ pub unsafe fn vsli_n_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { )] fn _vsli_n_s8(a: int8x8_t, b: int8x8_t, n: i32) -> int8x8_t; } - _vsli_n_s8(a, b, N) + unsafe { _vsli_n_s8(a, b, N) } } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sli, N = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vsliq_n_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { +pub fn vsliq_n_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { static_assert_uimm_bits!(N, 3); unsafe extern "unadjusted" { #[cfg_attr( @@ -26507,18 +24164,16 @@ pub unsafe fn vsliq_n_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t )] fn _vsliq_n_s8(a: int8x16_t, b: int8x16_t, n: i32) -> int8x16_t; } - _vsliq_n_s8(a, b, N) + unsafe { _vsliq_n_s8(a, b, N) } } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sli, N = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vsli_n_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { +pub fn vsli_n_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { static_assert_uimm_bits!(N, 4); unsafe extern "unadjusted" { #[cfg_attr( @@ -26527,18 +24182,16 @@ pub unsafe fn vsli_n_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t )] fn _vsli_n_s16(a: int16x4_t, b: int16x4_t, n: i32) -> int16x4_t; } - _vsli_n_s16(a, b, N) + unsafe { _vsli_n_s16(a, b, N) } } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sli, N = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vsliq_n_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { +pub fn vsliq_n_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { static_assert_uimm_bits!(N, 4); unsafe extern "unadjusted" { #[cfg_attr( @@ -26547,18 +24200,16 @@ pub unsafe fn vsliq_n_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t )] fn _vsliq_n_s16(a: int16x8_t, b: int16x8_t, n: i32) -> int16x8_t; } - _vsliq_n_s16(a, b, N) + unsafe { _vsliq_n_s16(a, b, N) } } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sli, N = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vsli_n_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { +pub fn vsli_n_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { static_assert!(N >= 0 && N <= 31); unsafe extern "unadjusted" { #[cfg_attr( @@ -26567,18 +24218,16 @@ pub unsafe fn vsli_n_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t )] fn _vsli_n_s32(a: int32x2_t, b: int32x2_t, n: i32) -> int32x2_t; } - _vsli_n_s32(a, b, N) + unsafe { _vsli_n_s32(a, b, N) } } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sli, N = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vsliq_n_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { +pub fn vsliq_n_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { static_assert!(N >= 0 && N <= 31); unsafe extern "unadjusted" { #[cfg_attr( @@ -26587,18 +24236,16 @@ pub unsafe fn vsliq_n_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t )] fn _vsliq_n_s32(a: int32x4_t, b: int32x4_t, n: i32) -> int32x4_t; } - _vsliq_n_s32(a, b, N) + unsafe { _vsliq_n_s32(a, b, N) } } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sli, N = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vsli_n_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { +pub fn vsli_n_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { static_assert!(N >= 0 && N <= 63); unsafe extern "unadjusted" { #[cfg_attr( @@ -26607,18 +24254,16 @@ pub unsafe fn vsli_n_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t )] fn _vsli_n_s64(a: int64x1_t, b: int64x1_t, n: i32) -> int64x1_t; } - _vsli_n_s64(a, b, N) + unsafe { _vsli_n_s64(a, b, N) } } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sli, N = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vsliq_n_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { +pub fn vsliq_n_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { static_assert!(N >= 0 && N <= 63); unsafe extern "unadjusted" { #[cfg_attr( @@ -26627,225 +24272,191 @@ pub unsafe fn vsliq_n_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t )] fn _vsliq_n_s64(a: int64x2_t, b: int64x2_t, n: i32) -> int64x2_t; } - _vsliq_n_s64(a, b, N) + unsafe { _vsliq_n_s64(a, b, N) } } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sli, N = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vsli_n_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { +pub fn vsli_n_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { static_assert_uimm_bits!(N, 3); - transmute(vsli_n_s8::(transmute(a), transmute(b))) + unsafe { transmute(vsli_n_s8::(transmute(a), transmute(b))) } } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sli, N = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vsliq_n_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { +pub fn vsliq_n_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { static_assert_uimm_bits!(N, 3); - transmute(vsliq_n_s8::(transmute(a), transmute(b))) + unsafe { transmute(vsliq_n_s8::(transmute(a), transmute(b))) } } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sli, N = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vsli_n_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { +pub fn vsli_n_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { static_assert_uimm_bits!(N, 4); - transmute(vsli_n_s16::(transmute(a), transmute(b))) + unsafe { transmute(vsli_n_s16::(transmute(a), transmute(b))) } } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sli, N = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vsliq_n_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { +pub fn vsliq_n_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { static_assert_uimm_bits!(N, 4); - transmute(vsliq_n_s16::(transmute(a), transmute(b))) + unsafe { transmute(vsliq_n_s16::(transmute(a), transmute(b))) } } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sli, N = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vsli_n_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { +pub fn vsli_n_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { static_assert!(N >= 0 && N <= 31); - transmute(vsli_n_s32::(transmute(a), transmute(b))) + unsafe { transmute(vsli_n_s32::(transmute(a), transmute(b))) } } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sli, N = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vsliq_n_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { +pub fn vsliq_n_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { static_assert!(N >= 0 && N <= 31); - transmute(vsliq_n_s32::(transmute(a), transmute(b))) + unsafe { transmute(vsliq_n_s32::(transmute(a), transmute(b))) } } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sli, N = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vsli_n_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { +pub fn vsli_n_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { static_assert!(N >= 0 && N <= 63); - transmute(vsli_n_s64::(transmute(a), transmute(b))) + unsafe { transmute(vsli_n_s64::(transmute(a), transmute(b))) } } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sli, N = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vsliq_n_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { +pub fn vsliq_n_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { static_assert!(N >= 0 && N <= 63); - transmute(vsliq_n_s64::(transmute(a), transmute(b))) + unsafe { transmute(vsliq_n_s64::(transmute(a), transmute(b))) } } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sli, N = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vsli_n_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { +pub fn vsli_n_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { static_assert_uimm_bits!(N, 3); - transmute(vsli_n_s8::(transmute(a), transmute(b))) + unsafe { transmute(vsli_n_s8::(transmute(a), transmute(b))) } } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sli, N = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vsliq_n_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { +pub fn vsliq_n_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { static_assert_uimm_bits!(N, 3); - transmute(vsliq_n_s8::(transmute(a), transmute(b))) + unsafe { transmute(vsliq_n_s8::(transmute(a), transmute(b))) } } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sli, N = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vsli_n_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { +pub fn vsli_n_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { static_assert_uimm_bits!(N, 4); - transmute(vsli_n_s16::(transmute(a), transmute(b))) + unsafe { transmute(vsli_n_s16::(transmute(a), transmute(b))) } } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sli, N = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vsliq_n_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { +pub fn vsliq_n_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { static_assert_uimm_bits!(N, 4); - transmute(vsliq_n_s16::(transmute(a), transmute(b))) + unsafe { transmute(vsliq_n_s16::(transmute(a), transmute(b))) } } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(sli, N = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vsli_n_p64(a: poly64x1_t, b: poly64x1_t) -> poly64x1_t { +pub fn vsli_n_p64(a: poly64x1_t, b: poly64x1_t) -> poly64x1_t { static_assert!(N >= 0 && N <= 63); - transmute(vsli_n_s64::(transmute(a), transmute(b))) + unsafe { transmute(vsli_n_s64::(transmute(a), transmute(b))) } } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(sli, N = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vsliq_n_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { +pub fn vsliq_n_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { static_assert!(N >= 0 && N <= 63); - transmute(vsliq_n_s64::(transmute(a), transmute(b))) + unsafe { transmute(vsliq_n_s64::(transmute(a), transmute(b))) } } #[doc = "Shift left and insert"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vslid_n_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[rustc_legacy_const_generics(2)] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sli, N = 2))] -pub unsafe fn vslid_n_s64(a: i64, b: i64) -> i64 { +pub fn vslid_n_s64(a: i64, b: i64) -> i64 { static_assert!(N >= 0 && N <= 63); - transmute(vsli_n_s64::(transmute(a), transmute(b))) + unsafe { transmute(vsli_n_s64::(transmute(a), transmute(b))) } } #[doc = "Shift left and insert"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vslid_n_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[rustc_legacy_const_generics(2)] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sli, N = 2))] -pub unsafe fn vslid_n_u64(a: u64, b: u64) -> u64 { +pub fn vslid_n_u64(a: u64, b: u64) -> u64 { static_assert!(N >= 0 && N <= 63); - transmute(vsli_n_u64::(transmute(a), transmute(b))) + unsafe { transmute(vsli_n_u64::(transmute(a), transmute(b))) } } #[doc = "SM3PARTW1"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm3partw1q_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,sm4")] #[cfg_attr(test, assert_instr(sm3partw1))] #[unstable(feature = "stdarch_neon_sm4", issue = "117226")] -pub unsafe fn vsm3partw1q_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t { +pub fn vsm3partw1q_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -26853,17 +24464,15 @@ pub unsafe fn vsm3partw1q_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> ui )] fn _vsm3partw1q_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t; } - _vsm3partw1q_u32(a, b, c) + unsafe { _vsm3partw1q_u32(a, b, c) } } #[doc = "SM3PARTW2"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm3partw2q_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,sm4")] #[cfg_attr(test, assert_instr(sm3partw2))] #[unstable(feature = "stdarch_neon_sm4", issue = "117226")] -pub unsafe fn vsm3partw2q_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t { +pub fn vsm3partw2q_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -26871,17 +24480,15 @@ pub unsafe fn vsm3partw2q_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> ui )] fn _vsm3partw2q_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t; } - _vsm3partw2q_u32(a, b, c) + unsafe { _vsm3partw2q_u32(a, b, c) } } #[doc = "SM3SS1"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm3ss1q_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,sm4")] #[cfg_attr(test, assert_instr(sm3ss1))] #[unstable(feature = "stdarch_neon_sm4", issue = "117226")] -pub unsafe fn vsm3ss1q_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t { +pub fn vsm3ss1q_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -26889,22 +24496,16 @@ pub unsafe fn vsm3ss1q_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint3 )] fn _vsm3ss1q_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t; } - _vsm3ss1q_u32(a, b, c) + unsafe { _vsm3ss1q_u32(a, b, c) } } #[doc = "SM3TT1A"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm3tt1aq_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,sm4")] #[cfg_attr(test, assert_instr(sm3tt1a, IMM2 = 0))] #[rustc_legacy_const_generics(3)] #[unstable(feature = "stdarch_neon_sm4", issue = "117226")] -pub unsafe fn vsm3tt1aq_u32( - a: uint32x4_t, - b: uint32x4_t, - c: uint32x4_t, -) -> uint32x4_t { +pub fn vsm3tt1aq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t { static_assert_uimm_bits!(IMM2, 2); unsafe extern "unadjusted" { #[cfg_attr( @@ -26913,22 +24514,16 @@ pub unsafe fn vsm3tt1aq_u32( )] fn _vsm3tt1aq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t, n: i64) -> uint32x4_t; } - _vsm3tt1aq_u32(a, b, c, IMM2 as i64) + unsafe { _vsm3tt1aq_u32(a, b, c, IMM2 as i64) } } #[doc = "SM3TT1B"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm3tt1bq_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,sm4")] #[cfg_attr(test, assert_instr(sm3tt1b, IMM2 = 0))] #[rustc_legacy_const_generics(3)] #[unstable(feature = "stdarch_neon_sm4", issue = "117226")] -pub unsafe fn vsm3tt1bq_u32( - a: uint32x4_t, - b: uint32x4_t, - c: uint32x4_t, -) -> uint32x4_t { +pub fn vsm3tt1bq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t { static_assert_uimm_bits!(IMM2, 2); unsafe extern "unadjusted" { #[cfg_attr( @@ -26937,22 +24532,16 @@ pub unsafe fn vsm3tt1bq_u32( )] fn _vsm3tt1bq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t, n: i64) -> uint32x4_t; } - _vsm3tt1bq_u32(a, b, c, IMM2 as i64) + unsafe { _vsm3tt1bq_u32(a, b, c, IMM2 as i64) } } #[doc = "SM3TT2A"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm3tt2aq_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,sm4")] #[cfg_attr(test, assert_instr(sm3tt2a, IMM2 = 0))] #[rustc_legacy_const_generics(3)] #[unstable(feature = "stdarch_neon_sm4", issue = "117226")] -pub unsafe fn vsm3tt2aq_u32( - a: uint32x4_t, - b: uint32x4_t, - c: uint32x4_t, -) -> uint32x4_t { +pub fn vsm3tt2aq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t { static_assert_uimm_bits!(IMM2, 2); unsafe extern "unadjusted" { #[cfg_attr( @@ -26961,22 +24550,16 @@ pub unsafe fn vsm3tt2aq_u32( )] fn _vsm3tt2aq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t, n: i64) -> uint32x4_t; } - _vsm3tt2aq_u32(a, b, c, IMM2 as i64) + unsafe { _vsm3tt2aq_u32(a, b, c, IMM2 as i64) } } #[doc = "SM3TT2B"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm3tt2bq_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,sm4")] #[cfg_attr(test, assert_instr(sm3tt2b, IMM2 = 0))] #[rustc_legacy_const_generics(3)] #[unstable(feature = "stdarch_neon_sm4", issue = "117226")] -pub unsafe fn vsm3tt2bq_u32( - a: uint32x4_t, - b: uint32x4_t, - c: uint32x4_t, -) -> uint32x4_t { +pub fn vsm3tt2bq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t { static_assert_uimm_bits!(IMM2, 2); unsafe extern "unadjusted" { #[cfg_attr( @@ -26985,17 +24568,15 @@ pub unsafe fn vsm3tt2bq_u32( )] fn _vsm3tt2bq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t, n: i64) -> uint32x4_t; } - _vsm3tt2bq_u32(a, b, c, IMM2 as i64) + unsafe { _vsm3tt2bq_u32(a, b, c, IMM2 as i64) } } #[doc = "SM4 key"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm4ekeyq_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,sm4")] #[cfg_attr(test, assert_instr(sm4ekey))] #[unstable(feature = "stdarch_neon_sm4", issue = "117226")] -pub unsafe fn vsm4ekeyq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { +pub fn vsm4ekeyq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -27003,17 +24584,15 @@ pub unsafe fn vsm4ekeyq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { )] fn _vsm4ekeyq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t; } - _vsm4ekeyq_u32(a, b) + unsafe { _vsm4ekeyq_u32(a, b) } } #[doc = "SM4 encode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm4eq_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,sm4")] #[cfg_attr(test, assert_instr(sm4e))] #[unstable(feature = "stdarch_neon_sm4", issue = "117226")] -pub unsafe fn vsm4eq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { +pub fn vsm4eq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -27021,17 +24600,15 @@ pub unsafe fn vsm4eq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { )] fn _vsm4eq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t; } - _vsm4eq_u32(a, b) + unsafe { _vsm4eq_u32(a, b) } } #[doc = "Unsigned saturating Accumulate of Signed value."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqadd_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(usqadd))] -pub unsafe fn vsqadd_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t { +pub fn vsqadd_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -27039,17 +24616,15 @@ pub unsafe fn vsqadd_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t { )] fn _vsqadd_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t; } - _vsqadd_u8(a, b) + unsafe { _vsqadd_u8(a, b) } } #[doc = "Unsigned saturating Accumulate of Signed value."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqaddq_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(usqadd))] -pub unsafe fn vsqaddq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t { +pub fn vsqaddq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -27057,17 +24632,15 @@ pub unsafe fn vsqaddq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t { )] fn _vsqaddq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t; } - _vsqaddq_u8(a, b) + unsafe { _vsqaddq_u8(a, b) } } #[doc = "Unsigned saturating Accumulate of Signed value."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqadd_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(usqadd))] -pub unsafe fn vsqadd_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t { +pub fn vsqadd_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -27075,17 +24648,15 @@ pub unsafe fn vsqadd_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t { )] fn _vsqadd_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t; } - _vsqadd_u16(a, b) + unsafe { _vsqadd_u16(a, b) } } #[doc = "Unsigned saturating Accumulate of Signed value."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqaddq_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(usqadd))] -pub unsafe fn vsqaddq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t { +pub fn vsqaddq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -27093,17 +24664,15 @@ pub unsafe fn vsqaddq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t { )] fn _vsqaddq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t; } - _vsqaddq_u16(a, b) + unsafe { _vsqaddq_u16(a, b) } } #[doc = "Unsigned saturating Accumulate of Signed value."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqadd_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(usqadd))] -pub unsafe fn vsqadd_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t { +pub fn vsqadd_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -27111,17 +24680,15 @@ pub unsafe fn vsqadd_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t { )] fn _vsqadd_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t; } - _vsqadd_u32(a, b) + unsafe { _vsqadd_u32(a, b) } } #[doc = "Unsigned saturating Accumulate of Signed value."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqaddq_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(usqadd))] -pub unsafe fn vsqaddq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t { +pub fn vsqaddq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -27129,17 +24696,15 @@ pub unsafe fn vsqaddq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t { )] fn _vsqaddq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t; } - _vsqaddq_u32(a, b) + unsafe { _vsqaddq_u32(a, b) } } #[doc = "Unsigned saturating Accumulate of Signed value."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqadd_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(usqadd))] -pub unsafe fn vsqadd_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t { +pub fn vsqadd_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -27147,17 +24712,15 @@ pub unsafe fn vsqadd_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t { )] fn _vsqadd_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t; } - _vsqadd_u64(a, b) + unsafe { _vsqadd_u64(a, b) } } #[doc = "Unsigned saturating Accumulate of Signed value."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqaddq_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(usqadd))] -pub unsafe fn vsqaddq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t { +pub fn vsqaddq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -27165,39 +24728,33 @@ pub unsafe fn vsqaddq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t { )] fn _vsqaddq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t; } - _vsqaddq_u64(a, b) + unsafe { _vsqaddq_u64(a, b) } } #[doc = "Unsigned saturating accumulate of signed value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqaddb_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(usqadd))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vsqaddb_u8(a: u8, b: i8) -> u8 { - simd_extract!(vsqadd_u8(vdup_n_u8(a), vdup_n_s8(b)), 0) +pub fn vsqaddb_u8(a: u8, b: i8) -> u8 { + unsafe { simd_extract!(vsqadd_u8(vdup_n_u8(a), vdup_n_s8(b)), 0) } } #[doc = "Unsigned saturating accumulate of signed value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqaddh_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(usqadd))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vsqaddh_u16(a: u16, b: i16) -> u16 { - simd_extract!(vsqadd_u16(vdup_n_u16(a), vdup_n_s16(b)), 0) +pub fn vsqaddh_u16(a: u16, b: i16) -> u16 { + unsafe { simd_extract!(vsqadd_u16(vdup_n_u16(a), vdup_n_s16(b)), 0) } } #[doc = "Unsigned saturating accumulate of signed value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqaddd_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(usqadd))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vsqaddd_u64(a: u64, b: i64) -> u64 { +pub fn vsqaddd_u64(a: u64, b: i64) -> u64 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -27205,17 +24762,15 @@ pub unsafe fn vsqaddd_u64(a: u64, b: i64) -> u64 { )] fn _vsqaddd_u64(a: u64, b: i64) -> u64; } - _vsqaddd_u64(a, b) + unsafe { _vsqaddd_u64(a, b) } } #[doc = "Unsigned saturating accumulate of signed value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqadds_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(usqadd))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vsqadds_u32(a: u32, b: i32) -> u32 { +pub fn vsqadds_u32(a: u32, b: i32) -> u32 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -27223,83 +24778,69 @@ pub unsafe fn vsqadds_u32(a: u32, b: i32) -> u32 { )] fn _vsqadds_u32(a: u32, b: i32) -> u32; } - _vsqadds_u32(a, b) + unsafe { _vsqadds_u32(a, b) } } #[doc = "Calculates the square root of each lane."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqrt_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fsqrt))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vsqrt_f16(a: float16x4_t) -> float16x4_t { - simd_fsqrt(a) +pub fn vsqrt_f16(a: float16x4_t) -> float16x4_t { + unsafe { simd_fsqrt(a) } } #[doc = "Calculates the square root of each lane."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqrtq_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(test, assert_instr(fsqrt))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vsqrtq_f16(a: float16x8_t) -> float16x8_t { - simd_fsqrt(a) +pub fn vsqrtq_f16(a: float16x8_t) -> float16x8_t { + unsafe { simd_fsqrt(a) } } #[doc = "Calculates the square root of each lane."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqrt_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fsqrt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vsqrt_f32(a: float32x2_t) -> float32x2_t { - simd_fsqrt(a) +pub fn vsqrt_f32(a: float32x2_t) -> float32x2_t { + unsafe { simd_fsqrt(a) } } #[doc = "Calculates the square root of each lane."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqrtq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fsqrt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vsqrtq_f32(a: float32x4_t) -> float32x4_t { - simd_fsqrt(a) +pub fn vsqrtq_f32(a: float32x4_t) -> float32x4_t { + unsafe { simd_fsqrt(a) } } #[doc = "Calculates the square root of each lane."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqrt_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fsqrt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vsqrt_f64(a: float64x1_t) -> float64x1_t { - simd_fsqrt(a) +pub fn vsqrt_f64(a: float64x1_t) -> float64x1_t { + unsafe { simd_fsqrt(a) } } #[doc = "Calculates the square root of each lane."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqrtq_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fsqrt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vsqrtq_f64(a: float64x2_t) -> float64x2_t { - simd_fsqrt(a) +pub fn vsqrtq_f64(a: float64x2_t) -> float64x2_t { + unsafe { simd_fsqrt(a) } } #[doc = "Floating-point round to integral, using current rounding mode"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqrth_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(fsqrt))] -pub unsafe fn vsqrth_f16(a: f16) -> f16 { +pub fn vsqrth_f16(a: f16) -> f16 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -27307,18 +24848,16 @@ pub unsafe fn vsqrth_f16(a: f16) -> f16 { )] fn _vsqrth_f16(a: f16) -> f16; } - _vsqrth_f16(a) + unsafe { _vsqrth_f16(a) } } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sri, N = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vsri_n_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { +pub fn vsri_n_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { static_assert!(N >= 1 && N <= 8); unsafe extern "unadjusted" { #[cfg_attr( @@ -27327,18 +24866,16 @@ pub unsafe fn vsri_n_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { )] fn _vsri_n_s8(a: int8x8_t, b: int8x8_t, n: i32) -> int8x8_t; } - _vsri_n_s8(a, b, N) + unsafe { _vsri_n_s8(a, b, N) } } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sri, N = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vsriq_n_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { +pub fn vsriq_n_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { static_assert!(N >= 1 && N <= 8); unsafe extern "unadjusted" { #[cfg_attr( @@ -27347,18 +24884,16 @@ pub unsafe fn vsriq_n_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t )] fn _vsriq_n_s8(a: int8x16_t, b: int8x16_t, n: i32) -> int8x16_t; } - _vsriq_n_s8(a, b, N) + unsafe { _vsriq_n_s8(a, b, N) } } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sri, N = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vsri_n_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { +pub fn vsri_n_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { static_assert!(N >= 1 && N <= 16); unsafe extern "unadjusted" { #[cfg_attr( @@ -27367,18 +24902,16 @@ pub unsafe fn vsri_n_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t )] fn _vsri_n_s16(a: int16x4_t, b: int16x4_t, n: i32) -> int16x4_t; } - _vsri_n_s16(a, b, N) + unsafe { _vsri_n_s16(a, b, N) } } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sri, N = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vsriq_n_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { +pub fn vsriq_n_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { static_assert!(N >= 1 && N <= 16); unsafe extern "unadjusted" { #[cfg_attr( @@ -27387,18 +24920,16 @@ pub unsafe fn vsriq_n_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t )] fn _vsriq_n_s16(a: int16x8_t, b: int16x8_t, n: i32) -> int16x8_t; } - _vsriq_n_s16(a, b, N) + unsafe { _vsriq_n_s16(a, b, N) } } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sri, N = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vsri_n_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { +pub fn vsri_n_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { static_assert!(N >= 1 && N <= 32); unsafe extern "unadjusted" { #[cfg_attr( @@ -27407,18 +24938,16 @@ pub unsafe fn vsri_n_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t )] fn _vsri_n_s32(a: int32x2_t, b: int32x2_t, n: i32) -> int32x2_t; } - _vsri_n_s32(a, b, N) + unsafe { _vsri_n_s32(a, b, N) } } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sri, N = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vsriq_n_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { +pub fn vsriq_n_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { static_assert!(N >= 1 && N <= 32); unsafe extern "unadjusted" { #[cfg_attr( @@ -27427,18 +24956,16 @@ pub unsafe fn vsriq_n_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t )] fn _vsriq_n_s32(a: int32x4_t, b: int32x4_t, n: i32) -> int32x4_t; } - _vsriq_n_s32(a, b, N) + unsafe { _vsriq_n_s32(a, b, N) } } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sri, N = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vsri_n_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { +pub fn vsri_n_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { static_assert!(N >= 1 && N <= 64); unsafe extern "unadjusted" { #[cfg_attr( @@ -27447,18 +24974,16 @@ pub unsafe fn vsri_n_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t )] fn _vsri_n_s64(a: int64x1_t, b: int64x1_t, n: i32) -> int64x1_t; } - _vsri_n_s64(a, b, N) + unsafe { _vsri_n_s64(a, b, N) } } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sri, N = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vsriq_n_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { +pub fn vsriq_n_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { static_assert!(N >= 1 && N <= 64); unsafe extern "unadjusted" { #[cfg_attr( @@ -27467,215 +24992,183 @@ pub unsafe fn vsriq_n_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t )] fn _vsriq_n_s64(a: int64x2_t, b: int64x2_t, n: i32) -> int64x2_t; } - _vsriq_n_s64(a, b, N) + unsafe { _vsriq_n_s64(a, b, N) } } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sri, N = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vsri_n_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { +pub fn vsri_n_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { static_assert!(N >= 1 && N <= 8); - transmute(vsri_n_s8::(transmute(a), transmute(b))) + unsafe { transmute(vsri_n_s8::(transmute(a), transmute(b))) } } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sri, N = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vsriq_n_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { +pub fn vsriq_n_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { static_assert!(N >= 1 && N <= 8); - transmute(vsriq_n_s8::(transmute(a), transmute(b))) + unsafe { transmute(vsriq_n_s8::(transmute(a), transmute(b))) } } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sri, N = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vsri_n_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { +pub fn vsri_n_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { static_assert!(N >= 1 && N <= 16); - transmute(vsri_n_s16::(transmute(a), transmute(b))) + unsafe { transmute(vsri_n_s16::(transmute(a), transmute(b))) } } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sri, N = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vsriq_n_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { +pub fn vsriq_n_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { static_assert!(N >= 1 && N <= 16); - transmute(vsriq_n_s16::(transmute(a), transmute(b))) + unsafe { transmute(vsriq_n_s16::(transmute(a), transmute(b))) } } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sri, N = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vsri_n_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { +pub fn vsri_n_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { static_assert!(N >= 1 && N <= 32); - transmute(vsri_n_s32::(transmute(a), transmute(b))) + unsafe { transmute(vsri_n_s32::(transmute(a), transmute(b))) } } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sri, N = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vsriq_n_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { +pub fn vsriq_n_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { static_assert!(N >= 1 && N <= 32); - transmute(vsriq_n_s32::(transmute(a), transmute(b))) + unsafe { transmute(vsriq_n_s32::(transmute(a), transmute(b))) } } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sri, N = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vsri_n_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { +pub fn vsri_n_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { static_assert!(N >= 1 && N <= 64); - transmute(vsri_n_s64::(transmute(a), transmute(b))) + unsafe { transmute(vsri_n_s64::(transmute(a), transmute(b))) } } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sri, N = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vsriq_n_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { +pub fn vsriq_n_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { static_assert!(N >= 1 && N <= 64); - transmute(vsriq_n_s64::(transmute(a), transmute(b))) + unsafe { transmute(vsriq_n_s64::(transmute(a), transmute(b))) } } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sri, N = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vsri_n_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { +pub fn vsri_n_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { static_assert!(N >= 1 && N <= 8); - transmute(vsri_n_s8::(transmute(a), transmute(b))) + unsafe { transmute(vsri_n_s8::(transmute(a), transmute(b))) } } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sri, N = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vsriq_n_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { +pub fn vsriq_n_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { static_assert!(N >= 1 && N <= 8); - transmute(vsriq_n_s8::(transmute(a), transmute(b))) + unsafe { transmute(vsriq_n_s8::(transmute(a), transmute(b))) } } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sri, N = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vsri_n_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { +pub fn vsri_n_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { static_assert!(N >= 1 && N <= 16); - transmute(vsri_n_s16::(transmute(a), transmute(b))) + unsafe { transmute(vsri_n_s16::(transmute(a), transmute(b))) } } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sri, N = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vsriq_n_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { +pub fn vsriq_n_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { static_assert!(N >= 1 && N <= 16); - transmute(vsriq_n_s16::(transmute(a), transmute(b))) + unsafe { transmute(vsriq_n_s16::(transmute(a), transmute(b))) } } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(sri, N = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vsri_n_p64(a: poly64x1_t, b: poly64x1_t) -> poly64x1_t { +pub fn vsri_n_p64(a: poly64x1_t, b: poly64x1_t) -> poly64x1_t { static_assert!(N >= 1 && N <= 64); - transmute(vsri_n_s64::(transmute(a), transmute(b))) + unsafe { transmute(vsri_n_s64::(transmute(a), transmute(b))) } } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(sri, N = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vsriq_n_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { +pub fn vsriq_n_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { static_assert!(N >= 1 && N <= 64); - transmute(vsriq_n_s64::(transmute(a), transmute(b))) + unsafe { transmute(vsriq_n_s64::(transmute(a), transmute(b))) } } #[doc = "Shift right and insert"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsrid_n_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[rustc_legacy_const_generics(2)] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sri, N = 2))] -pub unsafe fn vsrid_n_s64(a: i64, b: i64) -> i64 { +pub fn vsrid_n_s64(a: i64, b: i64) -> i64 { static_assert!(N >= 1 && N <= 64); - transmute(vsri_n_s64::(transmute(a), transmute(b))) + unsafe { transmute(vsri_n_s64::(transmute(a), transmute(b))) } } #[doc = "Shift right and insert"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsrid_n_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[rustc_legacy_const_generics(2)] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sri, N = 2))] -pub unsafe fn vsrid_n_u64(a: u64, b: u64) -> u64 { +pub fn vsrid_n_u64(a: u64, b: u64) -> u64 { static_assert!(N >= 1 && N <= 64); - transmute(vsri_n_u64::(transmute(a), transmute(b))) + unsafe { transmute(vsri_n_u64::(transmute(a), transmute(b))) } } #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16)"] @@ -28958,402 +26451,371 @@ pub unsafe fn vst4q_u64(a: *mut u64, b: uint64x2x4_t) { } #[doc = "Subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fsub))] -pub unsafe fn vsub_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { - simd_sub(a, b) +pub fn vsub_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { + unsafe { simd_sub(a, b) } } #[doc = "Subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fsub))] -pub unsafe fn vsubq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { - simd_sub(a, b) +pub fn vsubq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { + unsafe { simd_sub(a, b) } } #[doc = "Subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubd_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vsubd_s64(a: i64, b: i64) -> i64 { +pub fn vsubd_s64(a: i64, b: i64) -> i64 { a.wrapping_sub(b) } #[doc = "Subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubd_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vsubd_u64(a: u64, b: u64) -> u64 { +pub fn vsubd_u64(a: u64, b: u64) -> u64 { a.wrapping_sub(b) } #[doc = "Subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubh_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vsubh_f16(a: f16, b: f16) -> f16 { +pub fn vsubh_f16(a: f16, b: f16) -> f16 { a - b } #[doc = "Signed Subtract Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_high_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ssubl))] -pub unsafe fn vsubl_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t { - let c: int8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); - let d: int16x8_t = simd_cast(c); - let e: int8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); - let f: int16x8_t = simd_cast(e); - simd_sub(d, f) +pub fn vsubl_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t { + unsafe { + let c: int8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); + let d: int16x8_t = simd_cast(c); + let e: int8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); + let f: int16x8_t = simd_cast(e); + simd_sub(d, f) + } } #[doc = "Signed Subtract Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_high_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ssubl))] -pub unsafe fn vsubl_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t { - let c: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); - let d: int32x4_t = simd_cast(c); - let e: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); - let f: int32x4_t = simd_cast(e); - simd_sub(d, f) +pub fn vsubl_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t { + unsafe { + let c: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); + let d: int32x4_t = simd_cast(c); + let e: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); + let f: int32x4_t = simd_cast(e); + simd_sub(d, f) + } } #[doc = "Signed Subtract Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_high_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ssubl))] -pub unsafe fn vsubl_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t { - let c: int32x2_t = simd_shuffle!(a, a, [2, 3]); - let d: int64x2_t = simd_cast(c); - let e: int32x2_t = simd_shuffle!(b, b, [2, 3]); - let f: int64x2_t = simd_cast(e); - simd_sub(d, f) +pub fn vsubl_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t { + unsafe { + let c: int32x2_t = simd_shuffle!(a, a, [2, 3]); + let d: int64x2_t = simd_cast(c); + let e: int32x2_t = simd_shuffle!(b, b, [2, 3]); + let f: int64x2_t = simd_cast(e); + simd_sub(d, f) + } } #[doc = "Unsigned Subtract Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_high_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(usubl))] -pub unsafe fn vsubl_high_u8(a: uint8x16_t, b: uint8x16_t) -> uint16x8_t { - let c: uint8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); - let d: uint16x8_t = simd_cast(c); - let e: uint8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); - let f: uint16x8_t = simd_cast(e); - simd_sub(d, f) +pub fn vsubl_high_u8(a: uint8x16_t, b: uint8x16_t) -> uint16x8_t { + unsafe { + let c: uint8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); + let d: uint16x8_t = simd_cast(c); + let e: uint8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); + let f: uint16x8_t = simd_cast(e); + simd_sub(d, f) + } } #[doc = "Unsigned Subtract Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_high_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(usubl))] -pub unsafe fn vsubl_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t { - let c: uint16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); - let d: uint32x4_t = simd_cast(c); - let e: uint16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); - let f: uint32x4_t = simd_cast(e); - simd_sub(d, f) +pub fn vsubl_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t { + unsafe { + let c: uint16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); + let d: uint32x4_t = simd_cast(c); + let e: uint16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); + let f: uint32x4_t = simd_cast(e); + simd_sub(d, f) + } } #[doc = "Unsigned Subtract Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_high_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(usubl))] -pub unsafe fn vsubl_high_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t { - let c: uint32x2_t = simd_shuffle!(a, a, [2, 3]); - let d: uint64x2_t = simd_cast(c); - let e: uint32x2_t = simd_shuffle!(b, b, [2, 3]); - let f: uint64x2_t = simd_cast(e); - simd_sub(d, f) +pub fn vsubl_high_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t { + unsafe { + let c: uint32x2_t = simd_shuffle!(a, a, [2, 3]); + let d: uint64x2_t = simd_cast(c); + let e: uint32x2_t = simd_shuffle!(b, b, [2, 3]); + let f: uint64x2_t = simd_cast(e); + simd_sub(d, f) + } } #[doc = "Signed Subtract Wide"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_high_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ssubw))] -pub unsafe fn vsubw_high_s8(a: int16x8_t, b: int8x16_t) -> int16x8_t { - let c: int8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); - simd_sub(a, simd_cast(c)) +pub fn vsubw_high_s8(a: int16x8_t, b: int8x16_t) -> int16x8_t { + unsafe { + let c: int8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); + simd_sub(a, simd_cast(c)) + } } #[doc = "Signed Subtract Wide"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_high_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ssubw))] -pub unsafe fn vsubw_high_s16(a: int32x4_t, b: int16x8_t) -> int32x4_t { - let c: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); - simd_sub(a, simd_cast(c)) +pub fn vsubw_high_s16(a: int32x4_t, b: int16x8_t) -> int32x4_t { + unsafe { + let c: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); + simd_sub(a, simd_cast(c)) + } } #[doc = "Signed Subtract Wide"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_high_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ssubw))] -pub unsafe fn vsubw_high_s32(a: int64x2_t, b: int32x4_t) -> int64x2_t { - let c: int32x2_t = simd_shuffle!(b, b, [2, 3]); - simd_sub(a, simd_cast(c)) +pub fn vsubw_high_s32(a: int64x2_t, b: int32x4_t) -> int64x2_t { + unsafe { + let c: int32x2_t = simd_shuffle!(b, b, [2, 3]); + simd_sub(a, simd_cast(c)) + } } #[doc = "Unsigned Subtract Wide"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_high_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(usubw))] -pub unsafe fn vsubw_high_u8(a: uint16x8_t, b: uint8x16_t) -> uint16x8_t { - let c: uint8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); - simd_sub(a, simd_cast(c)) +pub fn vsubw_high_u8(a: uint16x8_t, b: uint8x16_t) -> uint16x8_t { + unsafe { + let c: uint8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); + simd_sub(a, simd_cast(c)) + } } #[doc = "Unsigned Subtract Wide"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_high_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(usubw))] -pub unsafe fn vsubw_high_u16(a: uint32x4_t, b: uint16x8_t) -> uint32x4_t { - let c: uint16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); - simd_sub(a, simd_cast(c)) +pub fn vsubw_high_u16(a: uint32x4_t, b: uint16x8_t) -> uint32x4_t { + unsafe { + let c: uint16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); + simd_sub(a, simd_cast(c)) + } } #[doc = "Unsigned Subtract Wide"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_high_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(usubw))] -pub unsafe fn vsubw_high_u32(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t { - let c: uint32x2_t = simd_shuffle!(b, b, [2, 3]); - simd_sub(a, simd_cast(c)) +pub fn vsubw_high_u32(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t { + unsafe { + let c: uint32x2_t = simd_shuffle!(b, b, [2, 3]); + simd_sub(a, simd_cast(c)) + } } #[doc = "Dot product index form with signed and unsigned integers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudot_laneq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,i8mm")] #[cfg_attr(test, assert_instr(sudot, LANE = 3))] #[rustc_legacy_const_generics(3)] #[unstable(feature = "stdarch_neon_i8mm", issue = "117223")] -pub unsafe fn vsudot_laneq_s32( - a: int32x2_t, - b: int8x8_t, - c: uint8x16_t, -) -> int32x2_t { +pub fn vsudot_laneq_s32(a: int32x2_t, b: int8x8_t, c: uint8x16_t) -> int32x2_t { static_assert_uimm_bits!(LANE, 2); - let c: uint32x4_t = transmute(c); - let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); - vusdot_s32(a, transmute(c), b) + unsafe { + let c: uint32x4_t = transmute(c); + let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); + vusdot_s32(a, transmute(c), b) + } } #[doc = "Dot product index form with signed and unsigned integers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudotq_laneq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,i8mm")] #[cfg_attr(test, assert_instr(sudot, LANE = 3))] #[rustc_legacy_const_generics(3)] #[unstable(feature = "stdarch_neon_i8mm", issue = "117223")] -pub unsafe fn vsudotq_laneq_s32( - a: int32x4_t, - b: int8x16_t, - c: uint8x16_t, -) -> int32x4_t { +pub fn vsudotq_laneq_s32(a: int32x4_t, b: int8x16_t, c: uint8x16_t) -> int32x4_t { static_assert_uimm_bits!(LANE, 2); - let c: uint32x4_t = transmute(c); - let c: uint32x4_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vusdotq_s32(a, transmute(c), b) + unsafe { + let c: uint32x4_t = transmute(c); + let c: uint32x4_t = + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); + vusdotq_s32(a, transmute(c), b) + } } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vtbl1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { - vqtbl1_s8(vcombine_s8(a, crate::mem::zeroed()), transmute(b)) +pub fn vtbl1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { + vqtbl1_s8(vcombine_s8(a, unsafe { crate::mem::zeroed() }), unsafe { + { + transmute(b) + } + }) } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vtbl1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { - vqtbl1_u8(vcombine_u8(a, crate::mem::zeroed()), b) +pub fn vtbl1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + vqtbl1_u8(vcombine_u8(a, unsafe { crate::mem::zeroed() }), b) } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vtbl1_p8(a: poly8x8_t, b: uint8x8_t) -> poly8x8_t { - vqtbl1_p8(vcombine_p8(a, crate::mem::zeroed()), b) +pub fn vtbl1_p8(a: poly8x8_t, b: uint8x8_t) -> poly8x8_t { + vqtbl1_p8(vcombine_p8(a, unsafe { crate::mem::zeroed() }), b) } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vtbl2_s8(a: int8x8x2_t, b: int8x8_t) -> int8x8_t { - vqtbl1(transmute(vcombine_s8(a.0, a.1)), transmute(b)) +pub fn vtbl2_s8(a: int8x8x2_t, b: int8x8_t) -> int8x8_t { + unsafe { vqtbl1(transmute(vcombine_s8(a.0, a.1)), transmute(b)) } } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vtbl2_u8(a: uint8x8x2_t, b: uint8x8_t) -> uint8x8_t { - transmute(vqtbl1(transmute(vcombine_u8(a.0, a.1)), b)) +pub fn vtbl2_u8(a: uint8x8x2_t, b: uint8x8_t) -> uint8x8_t { + unsafe { transmute(vqtbl1(transmute(vcombine_u8(a.0, a.1)), b)) } } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vtbl2_u8(a: uint8x8x2_t, b: uint8x8_t) -> uint8x8_t { +pub fn vtbl2_u8(a: uint8x8x2_t, b: uint8x8_t) -> uint8x8_t { let mut a: uint8x8x2_t = a; a.0 = simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]); a.1 = simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]); let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: uint8x8_t = transmute(vqtbl1(transmute(vcombine_u8(a.0, a.1)), b)); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: uint8x8_t = transmute(vqtbl1(transmute(vcombine_u8(a.0, a.1)), b)); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vtbl2_p8(a: poly8x8x2_t, b: uint8x8_t) -> poly8x8_t { - transmute(vqtbl1(transmute(vcombine_p8(a.0, a.1)), b)) +pub fn vtbl2_p8(a: poly8x8x2_t, b: uint8x8_t) -> poly8x8_t { + unsafe { transmute(vqtbl1(transmute(vcombine_p8(a.0, a.1)), b)) } } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vtbl2_p8(a: poly8x8x2_t, b: uint8x8_t) -> poly8x8_t { +pub fn vtbl2_p8(a: poly8x8x2_t, b: uint8x8_t) -> poly8x8_t { let mut a: poly8x8x2_t = a; a.0 = simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]); a.1 = simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]); let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: poly8x8_t = transmute(vqtbl1(transmute(vcombine_p8(a.0, a.1)), b)); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: poly8x8_t = transmute(vqtbl1(transmute(vcombine_p8(a.0, a.1)), b)); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vtbl3_s8(a: int8x8x3_t, b: int8x8_t) -> int8x8_t { +pub fn vtbl3_s8(a: int8x8x3_t, b: int8x8_t) -> int8x8_t { let x = int8x16x2_t( vcombine_s8(a.0, a.1), - vcombine_s8(a.2, crate::mem::zeroed()), + vcombine_s8(a.2, unsafe { crate::mem::zeroed() }), ); - transmute(vqtbl2(transmute(x.0), transmute(x.1), transmute(b))) + unsafe { transmute(vqtbl2(transmute(x.0), transmute(x.1), transmute(b))) } } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vtbl3_u8(a: uint8x8x3_t, b: uint8x8_t) -> uint8x8_t { +pub fn vtbl3_u8(a: uint8x8x3_t, b: uint8x8_t) -> uint8x8_t { let x = uint8x16x2_t( vcombine_u8(a.0, a.1), - vcombine_u8(a.2, crate::mem::zeroed()), + vcombine_u8(a.2, unsafe { crate::mem::zeroed() }), ); - transmute(vqtbl2(transmute(x.0), transmute(x.1), b)) + unsafe { transmute(vqtbl2(transmute(x.0), transmute(x.1), b)) } } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vtbl3_u8(a: uint8x8x3_t, b: uint8x8_t) -> uint8x8_t { +pub fn vtbl3_u8(a: uint8x8x3_t, b: uint8x8_t) -> uint8x8_t { let mut a: uint8x8x3_t = a; a.0 = simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]); a.1 = simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]); @@ -29361,37 +26823,35 @@ pub unsafe fn vtbl3_u8(a: uint8x8x3_t, b: uint8x8_t) -> uint8x8_t { let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); let x = uint8x16x2_t( vcombine_u8(a.0, a.1), - vcombine_u8(a.2, crate::mem::zeroed()), + vcombine_u8(a.2, unsafe { crate::mem::zeroed() }), ); - let ret_val: uint8x8_t = transmute(vqtbl2(transmute(x.0), transmute(x.1), b)); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: uint8x8_t = transmute(vqtbl2(transmute(x.0), transmute(x.1), b)); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vtbl3_p8(a: poly8x8x3_t, b: uint8x8_t) -> poly8x8_t { +pub fn vtbl3_p8(a: poly8x8x3_t, b: uint8x8_t) -> poly8x8_t { let x = poly8x16x2_t( vcombine_p8(a.0, a.1), - vcombine_p8(a.2, crate::mem::zeroed()), + vcombine_p8(a.2, unsafe { crate::mem::zeroed() }), ); - transmute(vqtbl2(transmute(x.0), transmute(x.1), b)) + unsafe { transmute(vqtbl2(transmute(x.0), transmute(x.1), b)) } } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vtbl3_p8(a: poly8x8x3_t, b: uint8x8_t) -> poly8x8_t { +pub fn vtbl3_p8(a: poly8x8x3_t, b: uint8x8_t) -> poly8x8_t { let mut a: poly8x8x3_t = a; a.0 = simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]); a.1 = simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]); @@ -29399,46 +26859,42 @@ pub unsafe fn vtbl3_p8(a: poly8x8x3_t, b: uint8x8_t) -> poly8x8_t { let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); let x = poly8x16x2_t( vcombine_p8(a.0, a.1), - vcombine_p8(a.2, crate::mem::zeroed()), + vcombine_p8(a.2, unsafe { crate::mem::zeroed() }), ); - let ret_val: poly8x8_t = transmute(vqtbl2(transmute(x.0), transmute(x.1), b)); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: poly8x8_t = transmute(vqtbl2(transmute(x.0), transmute(x.1), b)); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vtbl4_s8(a: int8x8x4_t, b: int8x8_t) -> int8x8_t { +pub fn vtbl4_s8(a: int8x8x4_t, b: int8x8_t) -> int8x8_t { let x = int8x16x2_t(vcombine_s8(a.0, a.1), vcombine_s8(a.2, a.3)); - transmute(vqtbl2(transmute(x.0), transmute(x.1), transmute(b))) + unsafe { transmute(vqtbl2(transmute(x.0), transmute(x.1), transmute(b))) } } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vtbl4_u8(a: uint8x8x4_t, b: uint8x8_t) -> uint8x8_t { +pub fn vtbl4_u8(a: uint8x8x4_t, b: uint8x8_t) -> uint8x8_t { let x = uint8x16x2_t(vcombine_u8(a.0, a.1), vcombine_u8(a.2, a.3)); - transmute(vqtbl2(transmute(x.0), transmute(x.1), b)) + unsafe { transmute(vqtbl2(transmute(x.0), transmute(x.1), b)) } } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vtbl4_u8(a: uint8x8x4_t, b: uint8x8_t) -> uint8x8_t { +pub fn vtbl4_u8(a: uint8x8x4_t, b: uint8x8_t) -> uint8x8_t { let mut a: uint8x8x4_t = a; a.0 = simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]); a.1 = simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]); @@ -29446,32 +26902,30 @@ pub unsafe fn vtbl4_u8(a: uint8x8x4_t, b: uint8x8_t) -> uint8x8_t { a.3 = simd_shuffle!(a.3, a.3, [7, 6, 5, 4, 3, 2, 1, 0]); let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); let x = uint8x16x2_t(vcombine_u8(a.0, a.1), vcombine_u8(a.2, a.3)); - let ret_val: uint8x8_t = transmute(vqtbl2(transmute(x.0), transmute(x.1), b)); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: uint8x8_t = transmute(vqtbl2(transmute(x.0), transmute(x.1), b)); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vtbl4_p8(a: poly8x8x4_t, b: uint8x8_t) -> poly8x8_t { +pub fn vtbl4_p8(a: poly8x8x4_t, b: uint8x8_t) -> poly8x8_t { let x = poly8x16x2_t(vcombine_p8(a.0, a.1), vcombine_p8(a.2, a.3)); - transmute(vqtbl2(transmute(x.0), transmute(x.1), b)) + unsafe { transmute(vqtbl2(transmute(x.0), transmute(x.1), b)) } } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vtbl4_p8(a: poly8x8x4_t, b: uint8x8_t) -> poly8x8_t { +pub fn vtbl4_p8(a: poly8x8x4_t, b: uint8x8_t) -> poly8x8_t { let mut a: poly8x8x4_t = a; a.0 = simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]); a.1 = simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]); @@ -29479,191 +26933,187 @@ pub unsafe fn vtbl4_p8(a: poly8x8x4_t, b: uint8x8_t) -> poly8x8_t { a.3 = simd_shuffle!(a.3, a.3, [7, 6, 5, 4, 3, 2, 1, 0]); let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); let x = poly8x16x2_t(vcombine_p8(a.0, a.1), vcombine_p8(a.2, a.3)); - let ret_val: poly8x8_t = transmute(vqtbl2(transmute(x.0), transmute(x.1), b)); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: poly8x8_t = transmute(vqtbl2(transmute(x.0), transmute(x.1), b)); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vtbx1_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t { - simd_select( - simd_lt::(c, transmute(i8x8::splat(8))), - transmute(vqtbx1( - transmute(a), - transmute(vcombine_s8(b, crate::mem::zeroed())), - transmute(c), - )), - a, - ) +pub fn vtbx1_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t { + unsafe { + simd_select( + simd_lt::(c, transmute(i8x8::splat(8))), + transmute(vqtbx1( + transmute(a), + transmute(vcombine_s8(b, crate::mem::zeroed())), + transmute(c), + )), + a, + ) + } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vtbx1_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t { - simd_select( - simd_lt::(c, transmute(u8x8::splat(8))), - transmute(vqtbx1( - transmute(a), - transmute(vcombine_u8(b, crate::mem::zeroed())), - c, - )), - a, - ) +pub fn vtbx1_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t { + unsafe { + simd_select( + simd_lt::(c, transmute(u8x8::splat(8))), + transmute(vqtbx1( + transmute(a), + transmute(vcombine_u8(b, crate::mem::zeroed())), + c, + )), + a, + ) + } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vtbx1_p8(a: poly8x8_t, b: poly8x8_t, c: uint8x8_t) -> poly8x8_t { - simd_select( - simd_lt::(c, transmute(u8x8::splat(8))), - transmute(vqtbx1( - transmute(a), - transmute(vcombine_p8(b, crate::mem::zeroed())), - c, - )), - a, - ) +pub fn vtbx1_p8(a: poly8x8_t, b: poly8x8_t, c: uint8x8_t) -> poly8x8_t { + unsafe { + simd_select( + simd_lt::(c, transmute(u8x8::splat(8))), + transmute(vqtbx1( + transmute(a), + transmute(vcombine_p8(b, crate::mem::zeroed())), + c, + )), + a, + ) + } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vtbx2_s8(a: int8x8_t, b: int8x8x2_t, c: int8x8_t) -> int8x8_t { - vqtbx1(transmute(a), transmute(vcombine_s8(b.0, b.1)), transmute(c)) +pub fn vtbx2_s8(a: int8x8_t, b: int8x8x2_t, c: int8x8_t) -> int8x8_t { + unsafe { vqtbx1(transmute(a), transmute(vcombine_s8(b.0, b.1)), transmute(c)) } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vtbx2_u8(a: uint8x8_t, b: uint8x8x2_t, c: uint8x8_t) -> uint8x8_t { - transmute(vqtbx1(transmute(a), transmute(vcombine_u8(b.0, b.1)), c)) +pub fn vtbx2_u8(a: uint8x8_t, b: uint8x8x2_t, c: uint8x8_t) -> uint8x8_t { + unsafe { transmute(vqtbx1(transmute(a), transmute(vcombine_u8(b.0, b.1)), c)) } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vtbx2_u8(a: uint8x8_t, b: uint8x8x2_t, c: uint8x8_t) -> uint8x8_t { +pub fn vtbx2_u8(a: uint8x8_t, b: uint8x8x2_t, c: uint8x8_t) -> uint8x8_t { let mut b: uint8x8x2_t = b; let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); b.0 = simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]); b.1 = simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]); let c: uint8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: uint8x8_t = transmute(vqtbx1(transmute(a), transmute(vcombine_u8(b.0, b.1)), c)); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: uint8x8_t = + transmute(vqtbx1(transmute(a), transmute(vcombine_u8(b.0, b.1)), c)); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vtbx2_p8(a: poly8x8_t, b: poly8x8x2_t, c: uint8x8_t) -> poly8x8_t { - transmute(vqtbx1(transmute(a), transmute(vcombine_p8(b.0, b.1)), c)) +pub fn vtbx2_p8(a: poly8x8_t, b: poly8x8x2_t, c: uint8x8_t) -> poly8x8_t { + unsafe { transmute(vqtbx1(transmute(a), transmute(vcombine_p8(b.0, b.1)), c)) } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vtbx2_p8(a: poly8x8_t, b: poly8x8x2_t, c: uint8x8_t) -> poly8x8_t { +pub fn vtbx2_p8(a: poly8x8_t, b: poly8x8x2_t, c: uint8x8_t) -> poly8x8_t { let mut b: poly8x8x2_t = b; let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); b.0 = simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]); b.1 = simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]); let c: uint8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: poly8x8_t = transmute(vqtbx1(transmute(a), transmute(vcombine_p8(b.0, b.1)), c)); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: poly8x8_t = + transmute(vqtbx1(transmute(a), transmute(vcombine_p8(b.0, b.1)), c)); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vtbx3_s8(a: int8x8_t, b: int8x8x3_t, c: int8x8_t) -> int8x8_t { +pub fn vtbx3_s8(a: int8x8_t, b: int8x8x3_t, c: int8x8_t) -> int8x8_t { let x = int8x16x2_t( vcombine_s8(b.0, b.1), - vcombine_s8(b.2, crate::mem::zeroed()), + vcombine_s8(b.2, unsafe { crate::mem::zeroed() }), ); - transmute(simd_select( - simd_lt::(transmute(c), transmute(i8x8::splat(24))), - transmute(vqtbx2( - transmute(a), - transmute(x.0), - transmute(x.1), - transmute(c), - )), - a, - )) + unsafe { + transmute(simd_select( + simd_lt::(transmute(c), transmute(i8x8::splat(24))), + transmute(vqtbx2( + transmute(a), + transmute(x.0), + transmute(x.1), + transmute(c), + )), + a, + )) + } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vtbx3_u8(a: uint8x8_t, b: uint8x8x3_t, c: uint8x8_t) -> uint8x8_t { +pub fn vtbx3_u8(a: uint8x8_t, b: uint8x8x3_t, c: uint8x8_t) -> uint8x8_t { let x = uint8x16x2_t( vcombine_u8(b.0, b.1), - vcombine_u8(b.2, crate::mem::zeroed()), + vcombine_u8(b.2, unsafe { crate::mem::zeroed() }), ); - transmute(simd_select( - simd_lt::(transmute(c), transmute(u8x8::splat(24))), - transmute(vqtbx2(transmute(a), transmute(x.0), transmute(x.1), c)), - a, - )) + unsafe { + transmute(simd_select( + simd_lt::(transmute(c), transmute(u8x8::splat(24))), + transmute(vqtbx2(transmute(a), transmute(x.0), transmute(x.1), c)), + a, + )) + } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vtbx3_u8(a: uint8x8_t, b: uint8x8x3_t, c: uint8x8_t) -> uint8x8_t { +pub fn vtbx3_u8(a: uint8x8_t, b: uint8x8x3_t, c: uint8x8_t) -> uint8x8_t { let mut b: uint8x8x3_t = b; let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); b.0 = simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]); @@ -29672,45 +27122,45 @@ pub unsafe fn vtbx3_u8(a: uint8x8_t, b: uint8x8x3_t, c: uint8x8_t) -> uint8x8_t let c: uint8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]); let x = uint8x16x2_t( vcombine_u8(b.0, b.1), - vcombine_u8(b.2, crate::mem::zeroed()), + vcombine_u8(b.2, unsafe { crate::mem::zeroed() }), ); - let ret_val: uint8x8_t = transmute(simd_select( - simd_lt::(transmute(c), transmute(u8x8::splat(24))), - transmute(vqtbx2(transmute(a), transmute(x.0), transmute(x.1), c)), - a, - )); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: uint8x8_t = transmute(simd_select( + simd_lt::(transmute(c), transmute(u8x8::splat(24))), + transmute(vqtbx2(transmute(a), transmute(x.0), transmute(x.1), c)), + a, + )); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vtbx3_p8(a: poly8x8_t, b: poly8x8x3_t, c: uint8x8_t) -> poly8x8_t { +pub fn vtbx3_p8(a: poly8x8_t, b: poly8x8x3_t, c: uint8x8_t) -> poly8x8_t { let x = poly8x16x2_t( vcombine_p8(b.0, b.1), - vcombine_p8(b.2, crate::mem::zeroed()), + vcombine_p8(b.2, unsafe { crate::mem::zeroed() }), ); - transmute(simd_select( - simd_lt::(transmute(c), transmute(u8x8::splat(24))), - transmute(vqtbx2(transmute(a), transmute(x.0), transmute(x.1), c)), - a, - )) + unsafe { + transmute(simd_select( + simd_lt::(transmute(c), transmute(u8x8::splat(24))), + transmute(vqtbx2(transmute(a), transmute(x.0), transmute(x.1), c)), + a, + )) + } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vtbx3_p8(a: poly8x8_t, b: poly8x8x3_t, c: uint8x8_t) -> poly8x8_t { +pub fn vtbx3_p8(a: poly8x8_t, b: poly8x8x3_t, c: uint8x8_t) -> poly8x8_t { let mut b: poly8x8x3_t = b; let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); b.0 = simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]); @@ -29719,58 +27169,58 @@ pub unsafe fn vtbx3_p8(a: poly8x8_t, b: poly8x8x3_t, c: uint8x8_t) -> poly8x8_t let c: uint8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]); let x = poly8x16x2_t( vcombine_p8(b.0, b.1), - vcombine_p8(b.2, crate::mem::zeroed()), + vcombine_p8(b.2, unsafe { crate::mem::zeroed() }), ); - let ret_val: poly8x8_t = transmute(simd_select( - simd_lt::(transmute(c), transmute(u8x8::splat(24))), - transmute(vqtbx2(transmute(a), transmute(x.0), transmute(x.1), c)), - a, - )); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: poly8x8_t = transmute(simd_select( + simd_lt::(transmute(c), transmute(u8x8::splat(24))), + transmute(vqtbx2(transmute(a), transmute(x.0), transmute(x.1), c)), + a, + )); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vtbx4_s8(a: int8x8_t, b: int8x8x4_t, c: int8x8_t) -> int8x8_t { - vqtbx2( - transmute(a), - transmute(vcombine_s8(b.0, b.1)), - transmute(vcombine_s8(b.2, b.3)), - transmute(c), - ) +pub fn vtbx4_s8(a: int8x8_t, b: int8x8x4_t, c: int8x8_t) -> int8x8_t { + unsafe { + vqtbx2( + transmute(a), + transmute(vcombine_s8(b.0, b.1)), + transmute(vcombine_s8(b.2, b.3)), + transmute(c), + ) + } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vtbx4_u8(a: uint8x8_t, b: uint8x8x4_t, c: uint8x8_t) -> uint8x8_t { - transmute(vqtbx2( - transmute(a), - transmute(vcombine_u8(b.0, b.1)), - transmute(vcombine_u8(b.2, b.3)), - c, - )) +pub fn vtbx4_u8(a: uint8x8_t, b: uint8x8x4_t, c: uint8x8_t) -> uint8x8_t { + unsafe { + transmute(vqtbx2( + transmute(a), + transmute(vcombine_u8(b.0, b.1)), + transmute(vcombine_u8(b.2, b.3)), + c, + )) + } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vtbx4_u8(a: uint8x8_t, b: uint8x8x4_t, c: uint8x8_t) -> uint8x8_t { +pub fn vtbx4_u8(a: uint8x8_t, b: uint8x8x4_t, c: uint8x8_t) -> uint8x8_t { let mut b: uint8x8x4_t = b; let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); b.0 = simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]); @@ -29778,41 +27228,41 @@ pub unsafe fn vtbx4_u8(a: uint8x8_t, b: uint8x8x4_t, c: uint8x8_t) -> uint8x8_t b.2 = simd_shuffle!(b.2, b.2, [7, 6, 5, 4, 3, 2, 1, 0]); b.3 = simd_shuffle!(b.3, b.3, [7, 6, 5, 4, 3, 2, 1, 0]); let c: uint8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: uint8x8_t = transmute(vqtbx2( - transmute(a), - transmute(vcombine_u8(b.0, b.1)), - transmute(vcombine_u8(b.2, b.3)), - c, - )); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: uint8x8_t = transmute(vqtbx2( + transmute(a), + transmute(vcombine_u8(b.0, b.1)), + transmute(vcombine_u8(b.2, b.3)), + c, + )); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vtbx4_p8(a: poly8x8_t, b: poly8x8x4_t, c: uint8x8_t) -> poly8x8_t { - transmute(vqtbx2( - transmute(a), - transmute(vcombine_p8(b.0, b.1)), - transmute(vcombine_p8(b.2, b.3)), - c, - )) +pub fn vtbx4_p8(a: poly8x8_t, b: poly8x8x4_t, c: uint8x8_t) -> poly8x8_t { + unsafe { + transmute(vqtbx2( + transmute(a), + transmute(vcombine_p8(b.0, b.1)), + transmute(vcombine_p8(b.2, b.3)), + c, + )) + } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vtbx4_p8(a: poly8x8_t, b: poly8x8x4_t, c: uint8x8_t) -> poly8x8_t { +pub fn vtbx4_p8(a: poly8x8_t, b: poly8x8x4_t, c: uint8x8_t) -> poly8x8_t { let mut b: poly8x8x4_t = b; let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); b.0 = simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]); @@ -29820,675 +27270,587 @@ pub unsafe fn vtbx4_p8(a: poly8x8_t, b: poly8x8x4_t, c: uint8x8_t) -> poly8x8_t b.2 = simd_shuffle!(b.2, b.2, [7, 6, 5, 4, 3, 2, 1, 0]); b.3 = simd_shuffle!(b.3, b.3, [7, 6, 5, 4, 3, 2, 1, 0]); let c: uint8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: poly8x8_t = transmute(vqtbx2( - transmute(a), - transmute(vcombine_p8(b.0, b.1)), - transmute(vcombine_p8(b.2, b.3)), - c, - )); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: poly8x8_t = transmute(vqtbx2( + transmute(a), + transmute(vcombine_p8(b.0, b.1)), + transmute(vcombine_p8(b.2, b.3)), + c, + )); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] -pub unsafe fn vtrn1_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { - simd_shuffle!(a, b, [0, 4, 2, 6]) +pub fn vtrn1_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { + unsafe { simd_shuffle!(a, b, [0, 4, 2, 6]) } } #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] -pub unsafe fn vtrn1q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { - simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]) +pub fn vtrn1q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { + unsafe { simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]) } } #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] -pub unsafe fn vtrn1_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { - simd_shuffle!(a, b, [0, 2]) +pub fn vtrn1_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { + unsafe { simd_shuffle!(a, b, [0, 2]) } } #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] -pub unsafe fn vtrn1q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { - simd_shuffle!(a, b, [0, 2]) +pub fn vtrn1q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { + unsafe { simd_shuffle!(a, b, [0, 2]) } } #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] -pub unsafe fn vtrn1_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { - simd_shuffle!(a, b, [0, 2]) +pub fn vtrn1_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + unsafe { simd_shuffle!(a, b, [0, 2]) } } #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] -pub unsafe fn vtrn1q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { - simd_shuffle!(a, b, [0, 2]) +pub fn vtrn1q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { + unsafe { simd_shuffle!(a, b, [0, 2]) } } #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] -pub unsafe fn vtrn1_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { - simd_shuffle!(a, b, [0, 2]) +pub fn vtrn1_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + unsafe { simd_shuffle!(a, b, [0, 2]) } } #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] -pub unsafe fn vtrn1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { - simd_shuffle!(a, b, [0, 2]) +pub fn vtrn1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { + unsafe { simd_shuffle!(a, b, [0, 2]) } } #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] -pub unsafe fn vtrn1q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { - simd_shuffle!(a, b, [0, 2]) +pub fn vtrn1q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { + unsafe { simd_shuffle!(a, b, [0, 2]) } } #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] -pub unsafe fn vtrn1q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { - simd_shuffle!(a, b, [0, 4, 2, 6]) +pub fn vtrn1q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { + unsafe { simd_shuffle!(a, b, [0, 4, 2, 6]) } } #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] -pub unsafe fn vtrn1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { - simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]) +pub fn vtrn1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { + unsafe { simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]) } } #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] -pub unsafe fn vtrn1q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { - simd_shuffle!( - a, - b, - [0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30] - ) +pub fn vtrn1q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { + unsafe { + simd_shuffle!( + a, + b, + [0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30] + ) + } } #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] -pub unsafe fn vtrn1_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { - simd_shuffle!(a, b, [0, 4, 2, 6]) +pub fn vtrn1_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + unsafe { simd_shuffle!(a, b, [0, 4, 2, 6]) } } #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] -pub unsafe fn vtrn1q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { - simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]) +pub fn vtrn1q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + unsafe { simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]) } } #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] -pub unsafe fn vtrn1q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { - simd_shuffle!(a, b, [0, 4, 2, 6]) +pub fn vtrn1q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + unsafe { simd_shuffle!(a, b, [0, 4, 2, 6]) } } #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] -pub unsafe fn vtrn1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { - simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]) +pub fn vtrn1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + unsafe { simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]) } } #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] -pub unsafe fn vtrn1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { - simd_shuffle!( - a, - b, - [0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30] - ) +pub fn vtrn1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + unsafe { + simd_shuffle!( + a, + b, + [0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30] + ) + } } #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] -pub unsafe fn vtrn1_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { - simd_shuffle!(a, b, [0, 4, 2, 6]) +pub fn vtrn1_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + unsafe { simd_shuffle!(a, b, [0, 4, 2, 6]) } } #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] -pub unsafe fn vtrn1q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { - simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]) +pub fn vtrn1q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + unsafe { simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]) } } #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] -pub unsafe fn vtrn1q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { - simd_shuffle!(a, b, [0, 4, 2, 6]) +pub fn vtrn1q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + unsafe { simd_shuffle!(a, b, [0, 4, 2, 6]) } } #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] -pub unsafe fn vtrn1_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { - simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]) +pub fn vtrn1_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { + unsafe { simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]) } } #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] -pub unsafe fn vtrn1q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { - simd_shuffle!( - a, - b, - [0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30] - ) +pub fn vtrn1q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { + unsafe { + simd_shuffle!( + a, + b, + [0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30] + ) + } } #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] -pub unsafe fn vtrn1_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { - simd_shuffle!(a, b, [0, 4, 2, 6]) +pub fn vtrn1_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { + unsafe { simd_shuffle!(a, b, [0, 4, 2, 6]) } } #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] -pub unsafe fn vtrn1q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { - simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]) +pub fn vtrn1q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { + unsafe { simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]) } } #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] -pub unsafe fn vtrn2_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { - simd_shuffle!(a, b, [1, 5, 3, 7]) +pub fn vtrn2_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { + unsafe { simd_shuffle!(a, b, [1, 5, 3, 7]) } } #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] -pub unsafe fn vtrn2q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { - simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]) +pub fn vtrn2q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { + unsafe { simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]) } } #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] -pub unsafe fn vtrn2_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { - simd_shuffle!(a, b, [1, 3]) +pub fn vtrn2_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { + unsafe { simd_shuffle!(a, b, [1, 3]) } } #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] -pub unsafe fn vtrn2q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { - simd_shuffle!(a, b, [1, 3]) +pub fn vtrn2q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { + unsafe { simd_shuffle!(a, b, [1, 3]) } } #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] -pub unsafe fn vtrn2_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { - simd_shuffle!(a, b, [1, 3]) +pub fn vtrn2_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + unsafe { simd_shuffle!(a, b, [1, 3]) } } #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] -pub unsafe fn vtrn2q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { - simd_shuffle!(a, b, [1, 3]) +pub fn vtrn2q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { + unsafe { simd_shuffle!(a, b, [1, 3]) } } #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] -pub unsafe fn vtrn2_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { - simd_shuffle!(a, b, [1, 3]) +pub fn vtrn2_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + unsafe { simd_shuffle!(a, b, [1, 3]) } } #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] -pub unsafe fn vtrn2q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { - simd_shuffle!(a, b, [1, 3]) +pub fn vtrn2q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { + unsafe { simd_shuffle!(a, b, [1, 3]) } } #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] -pub unsafe fn vtrn2q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { - simd_shuffle!(a, b, [1, 3]) +pub fn vtrn2q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { + unsafe { simd_shuffle!(a, b, [1, 3]) } } #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] -pub unsafe fn vtrn2q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { - simd_shuffle!(a, b, [1, 5, 3, 7]) +pub fn vtrn2q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { + unsafe { simd_shuffle!(a, b, [1, 5, 3, 7]) } } #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] -pub unsafe fn vtrn2_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { - simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]) +pub fn vtrn2_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { + unsafe { simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]) } } #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] -pub unsafe fn vtrn2q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { - simd_shuffle!( - a, - b, - [1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31] - ) +pub fn vtrn2q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { + unsafe { + simd_shuffle!( + a, + b, + [1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31] + ) + } } #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] -pub unsafe fn vtrn2_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { - simd_shuffle!(a, b, [1, 5, 3, 7]) +pub fn vtrn2_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + unsafe { simd_shuffle!(a, b, [1, 5, 3, 7]) } } #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] -pub unsafe fn vtrn2q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { - simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]) +pub fn vtrn2q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + unsafe { simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]) } } #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] -pub unsafe fn vtrn2q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { - simd_shuffle!(a, b, [1, 5, 3, 7]) +pub fn vtrn2q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + unsafe { simd_shuffle!(a, b, [1, 5, 3, 7]) } } #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] -pub unsafe fn vtrn2_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { - simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]) +pub fn vtrn2_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + unsafe { simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]) } } #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] -pub unsafe fn vtrn2q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { - simd_shuffle!( - a, - b, - [1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31] - ) +pub fn vtrn2q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + unsafe { + simd_shuffle!( + a, + b, + [1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31] + ) + } } #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] -pub unsafe fn vtrn2_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { - simd_shuffle!(a, b, [1, 5, 3, 7]) +pub fn vtrn2_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + unsafe { simd_shuffle!(a, b, [1, 5, 3, 7]) } } #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] -pub unsafe fn vtrn2q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { - simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]) +pub fn vtrn2q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + unsafe { simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]) } } #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] -pub unsafe fn vtrn2q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { - simd_shuffle!(a, b, [1, 5, 3, 7]) +pub fn vtrn2q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + unsafe { simd_shuffle!(a, b, [1, 5, 3, 7]) } } #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] -pub unsafe fn vtrn2_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { - simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]) +pub fn vtrn2_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { + unsafe { simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]) } } #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] -pub unsafe fn vtrn2q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { - simd_shuffle!( - a, - b, - [1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31] - ) +pub fn vtrn2q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { + unsafe { + simd_shuffle!( + a, + b, + [1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31] + ) + } } #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] -pub unsafe fn vtrn2_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { - simd_shuffle!(a, b, [1, 5, 3, 7]) +pub fn vtrn2_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { + unsafe { simd_shuffle!(a, b, [1, 5, 3, 7]) } } #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] -pub unsafe fn vtrn2q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { - simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]) +pub fn vtrn2q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { + unsafe { simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]) } } #[doc = "Signed compare bitwise Test bits nonzero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmtst))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vtst_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t { - let c: int64x1_t = simd_and(a, b); - let d: i64x1 = i64x1::new(0); - simd_ne(c, transmute(d)) +pub fn vtst_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t { + unsafe { + let c: int64x1_t = simd_and(a, b); + let d: i64x1 = i64x1::new(0); + simd_ne(c, transmute(d)) + } } #[doc = "Signed compare bitwise Test bits nonzero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmtst))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vtstq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t { - let c: int64x2_t = simd_and(a, b); - let d: i64x2 = i64x2::new(0, 0); - simd_ne(c, transmute(d)) +pub fn vtstq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t { + unsafe { + let c: int64x2_t = simd_and(a, b); + let d: i64x2 = i64x2::new(0, 0); + simd_ne(c, transmute(d)) + } } #[doc = "Signed compare bitwise Test bits nonzero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmtst))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vtst_p64(a: poly64x1_t, b: poly64x1_t) -> uint64x1_t { - let c: poly64x1_t = simd_and(a, b); - let d: i64x1 = i64x1::new(0); - simd_ne(c, transmute(d)) +pub fn vtst_p64(a: poly64x1_t, b: poly64x1_t) -> uint64x1_t { + unsafe { + let c: poly64x1_t = simd_and(a, b); + let d: i64x1 = i64x1::new(0); + simd_ne(c, transmute(d)) + } } #[doc = "Signed compare bitwise Test bits nonzero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmtst))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vtstq_p64(a: poly64x2_t, b: poly64x2_t) -> uint64x2_t { - let c: poly64x2_t = simd_and(a, b); - let d: i64x2 = i64x2::new(0, 0); - simd_ne(c, transmute(d)) +pub fn vtstq_p64(a: poly64x2_t, b: poly64x2_t) -> uint64x2_t { + unsafe { + let c: poly64x2_t = simd_and(a, b); + let d: i64x2 = i64x2::new(0, 0); + simd_ne(c, transmute(d)) + } } #[doc = "Unsigned compare bitwise Test bits nonzero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmtst))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vtst_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { - let c: uint64x1_t = simd_and(a, b); - let d: u64x1 = u64x1::new(0); - simd_ne(c, transmute(d)) +pub fn vtst_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { + unsafe { + let c: uint64x1_t = simd_and(a, b); + let d: u64x1 = u64x1::new(0); + simd_ne(c, transmute(d)) + } } #[doc = "Unsigned compare bitwise Test bits nonzero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmtst))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vtstq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { - let c: uint64x2_t = simd_and(a, b); - let d: u64x2 = u64x2::new(0, 0); - simd_ne(c, transmute(d)) +pub fn vtstq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { + unsafe { + let c: uint64x2_t = simd_and(a, b); + let d: u64x2 = u64x2::new(0, 0); + simd_ne(c, transmute(d)) + } } #[doc = "Compare bitwise test bits nonzero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstd_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tst))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vtstd_s64(a: i64, b: i64) -> u64 { - transmute(vtst_s64(transmute(a), transmute(b))) +pub fn vtstd_s64(a: i64, b: i64) -> u64 { + unsafe { transmute(vtst_s64(transmute(a), transmute(b))) } } #[doc = "Compare bitwise test bits nonzero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstd_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tst))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vtstd_u64(a: u64, b: u64) -> u64 { - transmute(vtst_u64(transmute(a), transmute(b))) +pub fn vtstd_u64(a: u64, b: u64) -> u64 { + unsafe { transmute(vtst_u64(transmute(a), transmute(b))) } } #[doc = "Signed saturating Accumulate of Unsigned value."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqadd_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(suqadd))] -pub unsafe fn vuqadd_s8(a: int8x8_t, b: uint8x8_t) -> int8x8_t { +pub fn vuqadd_s8(a: int8x8_t, b: uint8x8_t) -> int8x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -30496,17 +27858,15 @@ pub unsafe fn vuqadd_s8(a: int8x8_t, b: uint8x8_t) -> int8x8_t { )] fn _vuqadd_s8(a: int8x8_t, b: uint8x8_t) -> int8x8_t; } - _vuqadd_s8(a, b) + unsafe { _vuqadd_s8(a, b) } } #[doc = "Signed saturating Accumulate of Unsigned value."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqaddq_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(suqadd))] -pub unsafe fn vuqaddq_s8(a: int8x16_t, b: uint8x16_t) -> int8x16_t { +pub fn vuqaddq_s8(a: int8x16_t, b: uint8x16_t) -> int8x16_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -30514,17 +27874,15 @@ pub unsafe fn vuqaddq_s8(a: int8x16_t, b: uint8x16_t) -> int8x16_t { )] fn _vuqaddq_s8(a: int8x16_t, b: uint8x16_t) -> int8x16_t; } - _vuqaddq_s8(a, b) + unsafe { _vuqaddq_s8(a, b) } } #[doc = "Signed saturating Accumulate of Unsigned value."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqadd_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(suqadd))] -pub unsafe fn vuqadd_s16(a: int16x4_t, b: uint16x4_t) -> int16x4_t { +pub fn vuqadd_s16(a: int16x4_t, b: uint16x4_t) -> int16x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -30532,17 +27890,15 @@ pub unsafe fn vuqadd_s16(a: int16x4_t, b: uint16x4_t) -> int16x4_t { )] fn _vuqadd_s16(a: int16x4_t, b: uint16x4_t) -> int16x4_t; } - _vuqadd_s16(a, b) + unsafe { _vuqadd_s16(a, b) } } #[doc = "Signed saturating Accumulate of Unsigned value."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqaddq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(suqadd))] -pub unsafe fn vuqaddq_s16(a: int16x8_t, b: uint16x8_t) -> int16x8_t { +pub fn vuqaddq_s16(a: int16x8_t, b: uint16x8_t) -> int16x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -30550,17 +27906,15 @@ pub unsafe fn vuqaddq_s16(a: int16x8_t, b: uint16x8_t) -> int16x8_t { )] fn _vuqaddq_s16(a: int16x8_t, b: uint16x8_t) -> int16x8_t; } - _vuqaddq_s16(a, b) + unsafe { _vuqaddq_s16(a, b) } } #[doc = "Signed saturating Accumulate of Unsigned value."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqadd_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(suqadd))] -pub unsafe fn vuqadd_s32(a: int32x2_t, b: uint32x2_t) -> int32x2_t { +pub fn vuqadd_s32(a: int32x2_t, b: uint32x2_t) -> int32x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -30568,17 +27922,15 @@ pub unsafe fn vuqadd_s32(a: int32x2_t, b: uint32x2_t) -> int32x2_t { )] fn _vuqadd_s32(a: int32x2_t, b: uint32x2_t) -> int32x2_t; } - _vuqadd_s32(a, b) + unsafe { _vuqadd_s32(a, b) } } #[doc = "Signed saturating Accumulate of Unsigned value."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqaddq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(suqadd))] -pub unsafe fn vuqaddq_s32(a: int32x4_t, b: uint32x4_t) -> int32x4_t { +pub fn vuqaddq_s32(a: int32x4_t, b: uint32x4_t) -> int32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -30586,17 +27938,15 @@ pub unsafe fn vuqaddq_s32(a: int32x4_t, b: uint32x4_t) -> int32x4_t { )] fn _vuqaddq_s32(a: int32x4_t, b: uint32x4_t) -> int32x4_t; } - _vuqaddq_s32(a, b) + unsafe { _vuqaddq_s32(a, b) } } #[doc = "Signed saturating Accumulate of Unsigned value."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqadd_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(suqadd))] -pub unsafe fn vuqadd_s64(a: int64x1_t, b: uint64x1_t) -> int64x1_t { +pub fn vuqadd_s64(a: int64x1_t, b: uint64x1_t) -> int64x1_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -30604,17 +27954,15 @@ pub unsafe fn vuqadd_s64(a: int64x1_t, b: uint64x1_t) -> int64x1_t { )] fn _vuqadd_s64(a: int64x1_t, b: uint64x1_t) -> int64x1_t; } - _vuqadd_s64(a, b) + unsafe { _vuqadd_s64(a, b) } } #[doc = "Signed saturating Accumulate of Unsigned value."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqaddq_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(suqadd))] -pub unsafe fn vuqaddq_s64(a: int64x2_t, b: uint64x2_t) -> int64x2_t { +pub fn vuqaddq_s64(a: int64x2_t, b: uint64x2_t) -> int64x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -30622,39 +27970,33 @@ pub unsafe fn vuqaddq_s64(a: int64x2_t, b: uint64x2_t) -> int64x2_t { )] fn _vuqaddq_s64(a: int64x2_t, b: uint64x2_t) -> int64x2_t; } - _vuqaddq_s64(a, b) + unsafe { _vuqaddq_s64(a, b) } } #[doc = "Signed saturating accumulate of unsigned value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqaddb_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(suqadd))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vuqaddb_s8(a: i8, b: u8) -> i8 { - simd_extract!(vuqadd_s8(vdup_n_s8(a), vdup_n_u8(b)), 0) +pub fn vuqaddb_s8(a: i8, b: u8) -> i8 { + unsafe { simd_extract!(vuqadd_s8(vdup_n_s8(a), vdup_n_u8(b)), 0) } } #[doc = "Signed saturating accumulate of unsigned value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqaddh_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(suqadd))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vuqaddh_s16(a: i16, b: u16) -> i16 { - simd_extract!(vuqadd_s16(vdup_n_s16(a), vdup_n_u16(b)), 0) +pub fn vuqaddh_s16(a: i16, b: u16) -> i16 { + unsafe { simd_extract!(vuqadd_s16(vdup_n_s16(a), vdup_n_u16(b)), 0) } } #[doc = "Signed saturating accumulate of unsigned value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqaddd_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(suqadd))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vuqaddd_s64(a: i64, b: u64) -> i64 { +pub fn vuqaddd_s64(a: i64, b: u64) -> i64 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -30662,17 +28004,15 @@ pub unsafe fn vuqaddd_s64(a: i64, b: u64) -> i64 { )] fn _vuqaddd_s64(a: i64, b: u64) -> i64; } - _vuqaddd_s64(a, b) + unsafe { _vuqaddd_s64(a, b) } } #[doc = "Signed saturating accumulate of unsigned value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqadds_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(suqadd))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vuqadds_s32(a: i32, b: u32) -> i32 { +pub fn vuqadds_s32(a: i32, b: u32) -> i32 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -30680,608 +28020,515 @@ pub unsafe fn vuqadds_s32(a: i32, b: u32) -> i32 { )] fn _vuqadds_s32(a: i32, b: u32) -> i32; } - _vuqadds_s32(a, b) + unsafe { _vuqadds_s32(a, b) } } #[doc = "Dot product index form with unsigned and signed integers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdot_laneq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,i8mm")] #[cfg_attr(test, assert_instr(usdot, LANE = 3))] #[rustc_legacy_const_generics(3)] #[unstable(feature = "stdarch_neon_i8mm", issue = "117223")] -pub unsafe fn vusdot_laneq_s32( - a: int32x2_t, - b: uint8x8_t, - c: int8x16_t, -) -> int32x2_t { +pub fn vusdot_laneq_s32(a: int32x2_t, b: uint8x8_t, c: int8x16_t) -> int32x2_t { static_assert_uimm_bits!(LANE, 2); - let c: int32x4_t = transmute(c); - let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); - vusdot_s32(a, b, transmute(c)) + unsafe { + let c: int32x4_t = transmute(c); + let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); + vusdot_s32(a, b, transmute(c)) + } } #[doc = "Dot product index form with unsigned and signed integers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdotq_laneq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,i8mm")] #[cfg_attr(test, assert_instr(usdot, LANE = 3))] #[rustc_legacy_const_generics(3)] #[unstable(feature = "stdarch_neon_i8mm", issue = "117223")] -pub unsafe fn vusdotq_laneq_s32( - a: int32x4_t, - b: uint8x16_t, - c: int8x16_t, -) -> int32x4_t { +pub fn vusdotq_laneq_s32(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t { static_assert_uimm_bits!(LANE, 2); - let c: int32x4_t = transmute(c); - let c: int32x4_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vusdotq_s32(a, b, transmute(c)) + unsafe { + let c: int32x4_t = transmute(c); + let c: int32x4_t = + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); + vusdotq_s32(a, b, transmute(c)) + } } #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] -pub unsafe fn vuzp1_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { - simd_shuffle!(a, b, [0, 2, 4, 6]) +pub fn vuzp1_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { + unsafe { simd_shuffle!(a, b, [0, 2, 4, 6]) } } #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] -pub unsafe fn vuzp1q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { - simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]) +pub fn vuzp1q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { + unsafe { simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]) } } #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] -pub unsafe fn vuzp1_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { - simd_shuffle!(a, b, [0, 2]) +pub fn vuzp1_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { + unsafe { simd_shuffle!(a, b, [0, 2]) } } #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] -pub unsafe fn vuzp1q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { - simd_shuffle!(a, b, [0, 2]) +pub fn vuzp1q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { + unsafe { simd_shuffle!(a, b, [0, 2]) } } #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] -pub unsafe fn vuzp1_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { - simd_shuffle!(a, b, [0, 2]) +pub fn vuzp1_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + unsafe { simd_shuffle!(a, b, [0, 2]) } } #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] -pub unsafe fn vuzp1q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { - simd_shuffle!(a, b, [0, 2]) +pub fn vuzp1q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { + unsafe { simd_shuffle!(a, b, [0, 2]) } } #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] -pub unsafe fn vuzp1_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { - simd_shuffle!(a, b, [0, 2]) +pub fn vuzp1_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + unsafe { simd_shuffle!(a, b, [0, 2]) } } #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] -pub unsafe fn vuzp1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { - simd_shuffle!(a, b, [0, 2]) +pub fn vuzp1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { + unsafe { simd_shuffle!(a, b, [0, 2]) } } #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] -pub unsafe fn vuzp1q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { - simd_shuffle!(a, b, [0, 2]) +pub fn vuzp1q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { + unsafe { simd_shuffle!(a, b, [0, 2]) } } #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] -pub unsafe fn vuzp1q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { - simd_shuffle!(a, b, [0, 2, 4, 6]) +pub fn vuzp1q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { + unsafe { simd_shuffle!(a, b, [0, 2, 4, 6]) } } #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] -pub unsafe fn vuzp1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { - simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]) +pub fn vuzp1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { + unsafe { simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]) } } #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] -pub unsafe fn vuzp1q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { - simd_shuffle!( - a, - b, - [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30] - ) +pub fn vuzp1q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { + unsafe { + simd_shuffle!( + a, + b, + [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30] + ) + } } #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] -pub unsafe fn vuzp1_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { - simd_shuffle!(a, b, [0, 2, 4, 6]) +pub fn vuzp1_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + unsafe { simd_shuffle!(a, b, [0, 2, 4, 6]) } } #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] -pub unsafe fn vuzp1q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { - simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]) +pub fn vuzp1q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + unsafe { simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]) } } #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] -pub unsafe fn vuzp1q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { - simd_shuffle!(a, b, [0, 2, 4, 6]) +pub fn vuzp1q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + unsafe { simd_shuffle!(a, b, [0, 2, 4, 6]) } } #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] -pub unsafe fn vuzp1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { - simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]) +pub fn vuzp1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + unsafe { simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]) } } #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] -pub unsafe fn vuzp1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { - simd_shuffle!( - a, - b, - [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30] - ) +pub fn vuzp1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + unsafe { + simd_shuffle!( + a, + b, + [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30] + ) + } } #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] -pub unsafe fn vuzp1_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { - simd_shuffle!(a, b, [0, 2, 4, 6]) +pub fn vuzp1_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + unsafe { simd_shuffle!(a, b, [0, 2, 4, 6]) } } #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] -pub unsafe fn vuzp1q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { - simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]) +pub fn vuzp1q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + unsafe { simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]) } } #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] -pub unsafe fn vuzp1q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { - simd_shuffle!(a, b, [0, 2, 4, 6]) +pub fn vuzp1q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + unsafe { simd_shuffle!(a, b, [0, 2, 4, 6]) } } #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] -pub unsafe fn vuzp1_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { - simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]) +pub fn vuzp1_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { + unsafe { simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]) } } #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] -pub unsafe fn vuzp1q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { - simd_shuffle!( - a, - b, - [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30] - ) +pub fn vuzp1q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { + unsafe { + simd_shuffle!( + a, + b, + [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30] + ) + } } #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] -pub unsafe fn vuzp1_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { - simd_shuffle!(a, b, [0, 2, 4, 6]) +pub fn vuzp1_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { + unsafe { simd_shuffle!(a, b, [0, 2, 4, 6]) } } #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] -pub unsafe fn vuzp1q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { - simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]) +pub fn vuzp1q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { + unsafe { simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]) } } #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] -pub unsafe fn vuzp2_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { - simd_shuffle!(a, b, [1, 3, 5, 7]) +pub fn vuzp2_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { + unsafe { simd_shuffle!(a, b, [1, 3, 5, 7]) } } #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] -pub unsafe fn vuzp2q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { - simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]) +pub fn vuzp2q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { + unsafe { simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]) } } #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] -pub unsafe fn vuzp2_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { - simd_shuffle!(a, b, [1, 3]) +pub fn vuzp2_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { + unsafe { simd_shuffle!(a, b, [1, 3]) } } #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] -pub unsafe fn vuzp2q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { - simd_shuffle!(a, b, [1, 3]) +pub fn vuzp2q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { + unsafe { simd_shuffle!(a, b, [1, 3]) } } #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] -pub unsafe fn vuzp2_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { - simd_shuffle!(a, b, [1, 3]) +pub fn vuzp2_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + unsafe { simd_shuffle!(a, b, [1, 3]) } } #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] -pub unsafe fn vuzp2q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { - simd_shuffle!(a, b, [1, 3]) +pub fn vuzp2q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { + unsafe { simd_shuffle!(a, b, [1, 3]) } } #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] -pub unsafe fn vuzp2_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { - simd_shuffle!(a, b, [1, 3]) +pub fn vuzp2_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + unsafe { simd_shuffle!(a, b, [1, 3]) } } #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] -pub unsafe fn vuzp2q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { - simd_shuffle!(a, b, [1, 3]) +pub fn vuzp2q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { + unsafe { simd_shuffle!(a, b, [1, 3]) } } #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] -pub unsafe fn vuzp2q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { - simd_shuffle!(a, b, [1, 3]) +pub fn vuzp2q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { + unsafe { simd_shuffle!(a, b, [1, 3]) } } #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] -pub unsafe fn vuzp2q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { - simd_shuffle!(a, b, [1, 3, 5, 7]) +pub fn vuzp2q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { + unsafe { simd_shuffle!(a, b, [1, 3, 5, 7]) } } #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] -pub unsafe fn vuzp2_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { - simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]) +pub fn vuzp2_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { + unsafe { simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]) } } #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] -pub unsafe fn vuzp2q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { - simd_shuffle!( - a, - b, - [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31] - ) +pub fn vuzp2q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { + unsafe { + simd_shuffle!( + a, + b, + [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31] + ) + } } #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] -pub unsafe fn vuzp2_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { - simd_shuffle!(a, b, [1, 3, 5, 7]) +pub fn vuzp2_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + unsafe { simd_shuffle!(a, b, [1, 3, 5, 7]) } } #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] -pub unsafe fn vuzp2q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { - simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]) +pub fn vuzp2q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + unsafe { simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]) } } #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] -pub unsafe fn vuzp2q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { - simd_shuffle!(a, b, [1, 3, 5, 7]) +pub fn vuzp2q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + unsafe { simd_shuffle!(a, b, [1, 3, 5, 7]) } } #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] -pub unsafe fn vuzp2_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { - simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]) +pub fn vuzp2_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + unsafe { simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]) } } #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] -pub unsafe fn vuzp2q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { - simd_shuffle!( - a, - b, - [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31] - ) +pub fn vuzp2q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + unsafe { + simd_shuffle!( + a, + b, + [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31] + ) + } } #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] -pub unsafe fn vuzp2_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { - simd_shuffle!(a, b, [1, 3, 5, 7]) +pub fn vuzp2_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + unsafe { simd_shuffle!(a, b, [1, 3, 5, 7]) } } #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] -pub unsafe fn vuzp2q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { - simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]) +pub fn vuzp2q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + unsafe { simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]) } } #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] -pub unsafe fn vuzp2q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { - simd_shuffle!(a, b, [1, 3, 5, 7]) +pub fn vuzp2q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + unsafe { simd_shuffle!(a, b, [1, 3, 5, 7]) } } #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] -pub unsafe fn vuzp2_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { - simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]) +pub fn vuzp2_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { + unsafe { simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]) } } #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] -pub unsafe fn vuzp2q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { - simd_shuffle!( - a, - b, - [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31] - ) +pub fn vuzp2q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { + unsafe { + simd_shuffle!( + a, + b, + [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31] + ) + } } #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] -pub unsafe fn vuzp2_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { - simd_shuffle!(a, b, [1, 3, 5, 7]) +pub fn vuzp2_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { + unsafe { simd_shuffle!(a, b, [1, 3, 5, 7]) } } #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] -pub unsafe fn vuzp2q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { - simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]) +pub fn vuzp2q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { + unsafe { simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]) } } #[doc = "Exclusive OR and rotate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vxarq_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,sha3")] #[cfg_attr(test, assert_instr(xar, IMM6 = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] -pub unsafe fn vxarq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { +pub fn vxarq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { static_assert_uimm_bits!(IMM6, 6); unsafe extern "unadjusted" { #[cfg_attr( @@ -31290,557 +28537,473 @@ pub unsafe fn vxarq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64 )] fn _vxarq_u64(a: uint64x2_t, b: uint64x2_t, n: i64) -> uint64x2_t; } - _vxarq_u64(a, b, IMM6 as i64) + unsafe { _vxarq_u64(a, b, IMM6 as i64) } } #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] -pub unsafe fn vzip1_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { - simd_shuffle!(a, b, [0, 4, 1, 5]) +pub fn vzip1_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { + unsafe { simd_shuffle!(a, b, [0, 4, 1, 5]) } } #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] -pub unsafe fn vzip1q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { - simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]) +pub fn vzip1q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { + unsafe { simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]) } } #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] -pub unsafe fn vzip1_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { - simd_shuffle!(a, b, [0, 2]) +pub fn vzip1_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { + unsafe { simd_shuffle!(a, b, [0, 2]) } } #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] -pub unsafe fn vzip1q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { - simd_shuffle!(a, b, [0, 4, 1, 5]) +pub fn vzip1q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { + unsafe { simd_shuffle!(a, b, [0, 4, 1, 5]) } } #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] -pub unsafe fn vzip1q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { - simd_shuffle!(a, b, [0, 2]) +pub fn vzip1q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { + unsafe { simd_shuffle!(a, b, [0, 2]) } } #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] -pub unsafe fn vzip1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { - simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]) +pub fn vzip1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { + unsafe { simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]) } } #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] -pub unsafe fn vzip1q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { - simd_shuffle!( - a, - b, - [0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23] - ) +pub fn vzip1q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { + unsafe { + simd_shuffle!( + a, + b, + [0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23] + ) + } } #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] -pub unsafe fn vzip1_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { - simd_shuffle!(a, b, [0, 4, 1, 5]) +pub fn vzip1_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + unsafe { simd_shuffle!(a, b, [0, 4, 1, 5]) } } #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] -pub unsafe fn vzip1q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { - simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]) +pub fn vzip1q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + unsafe { simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]) } } #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] -pub unsafe fn vzip1_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { - simd_shuffle!(a, b, [0, 2]) +pub fn vzip1_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + unsafe { simd_shuffle!(a, b, [0, 2]) } } #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] -pub unsafe fn vzip1q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { - simd_shuffle!(a, b, [0, 4, 1, 5]) +pub fn vzip1q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + unsafe { simd_shuffle!(a, b, [0, 4, 1, 5]) } } #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] -pub unsafe fn vzip1q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { - simd_shuffle!(a, b, [0, 2]) +pub fn vzip1q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { + unsafe { simd_shuffle!(a, b, [0, 2]) } } #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] -pub unsafe fn vzip1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { - simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]) +pub fn vzip1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + unsafe { simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]) } } #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] -pub unsafe fn vzip1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { - simd_shuffle!( - a, - b, - [0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23] - ) +pub fn vzip1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + unsafe { + simd_shuffle!( + a, + b, + [0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23] + ) + } } #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] -pub unsafe fn vzip1_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { - simd_shuffle!(a, b, [0, 4, 1, 5]) +pub fn vzip1_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + unsafe { simd_shuffle!(a, b, [0, 4, 1, 5]) } } #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] -pub unsafe fn vzip1q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { - simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]) +pub fn vzip1q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + unsafe { simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]) } } #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] -pub unsafe fn vzip1_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { - simd_shuffle!(a, b, [0, 2]) +pub fn vzip1_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + unsafe { simd_shuffle!(a, b, [0, 2]) } } #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] -pub unsafe fn vzip1q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { - simd_shuffle!(a, b, [0, 4, 1, 5]) +pub fn vzip1q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + unsafe { simd_shuffle!(a, b, [0, 4, 1, 5]) } } #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] -pub unsafe fn vzip1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { - simd_shuffle!(a, b, [0, 2]) +pub fn vzip1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { + unsafe { simd_shuffle!(a, b, [0, 2]) } } #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] -pub unsafe fn vzip1_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { - simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]) +pub fn vzip1_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { + unsafe { simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]) } } #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] -pub unsafe fn vzip1q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { - simd_shuffle!( - a, - b, - [0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23] - ) +pub fn vzip1q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { + unsafe { + simd_shuffle!( + a, + b, + [0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23] + ) + } } #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] -pub unsafe fn vzip1_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { - simd_shuffle!(a, b, [0, 4, 1, 5]) +pub fn vzip1_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { + unsafe { simd_shuffle!(a, b, [0, 4, 1, 5]) } } #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] -pub unsafe fn vzip1q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { - simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]) +pub fn vzip1q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { + unsafe { simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]) } } #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] -pub unsafe fn vzip1q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { - simd_shuffle!(a, b, [0, 2]) +pub fn vzip1q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { + unsafe { simd_shuffle!(a, b, [0, 2]) } } #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] -pub unsafe fn vzip2_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { - simd_shuffle!(a, b, [2, 6, 3, 7]) +pub fn vzip2_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { + unsafe { simd_shuffle!(a, b, [2, 6, 3, 7]) } } #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] -pub unsafe fn vzip2q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { - simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]) +pub fn vzip2q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { + unsafe { simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]) } } #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] -pub unsafe fn vzip2_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { - simd_shuffle!(a, b, [1, 3]) +pub fn vzip2_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { + unsafe { simd_shuffle!(a, b, [1, 3]) } } #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] -pub unsafe fn vzip2q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { - simd_shuffle!(a, b, [2, 6, 3, 7]) +pub fn vzip2q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { + unsafe { simd_shuffle!(a, b, [2, 6, 3, 7]) } } #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_f64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] -pub unsafe fn vzip2q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { - simd_shuffle!(a, b, [1, 3]) +pub fn vzip2q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { + unsafe { simd_shuffle!(a, b, [1, 3]) } } #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] -pub unsafe fn vzip2_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { - simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]) +pub fn vzip2_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { + unsafe { simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]) } } #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] -pub unsafe fn vzip2q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { - simd_shuffle!( - a, - b, - [8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31] - ) +pub fn vzip2q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { + unsafe { + simd_shuffle!( + a, + b, + [8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31] + ) + } } #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] -pub unsafe fn vzip2_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { - simd_shuffle!(a, b, [2, 6, 3, 7]) +pub fn vzip2_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + unsafe { simd_shuffle!(a, b, [2, 6, 3, 7]) } } #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] -pub unsafe fn vzip2q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { - simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]) +pub fn vzip2q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + unsafe { simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]) } } #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] -pub unsafe fn vzip2_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { - simd_shuffle!(a, b, [1, 3]) +pub fn vzip2_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + unsafe { simd_shuffle!(a, b, [1, 3]) } } #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] -pub unsafe fn vzip2q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { - simd_shuffle!(a, b, [2, 6, 3, 7]) +pub fn vzip2q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + unsafe { simd_shuffle!(a, b, [2, 6, 3, 7]) } } #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] -pub unsafe fn vzip2q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { - simd_shuffle!(a, b, [1, 3]) +pub fn vzip2q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { + unsafe { simd_shuffle!(a, b, [1, 3]) } } #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] -pub unsafe fn vzip2_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { - simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]) +pub fn vzip2_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + unsafe { simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]) } } #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] -pub unsafe fn vzip2q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { - simd_shuffle!( - a, - b, - [8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31] - ) +pub fn vzip2q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + unsafe { + simd_shuffle!( + a, + b, + [8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31] + ) + } } #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] -pub unsafe fn vzip2_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { - simd_shuffle!(a, b, [2, 6, 3, 7]) +pub fn vzip2_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + unsafe { simd_shuffle!(a, b, [2, 6, 3, 7]) } } #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] -pub unsafe fn vzip2q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { - simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]) +pub fn vzip2q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + unsafe { simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]) } } #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] -pub unsafe fn vzip2_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { - simd_shuffle!(a, b, [1, 3]) +pub fn vzip2_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + unsafe { simd_shuffle!(a, b, [1, 3]) } } #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] -pub unsafe fn vzip2q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { - simd_shuffle!(a, b, [2, 6, 3, 7]) +pub fn vzip2q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + unsafe { simd_shuffle!(a, b, [2, 6, 3, 7]) } } #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] -pub unsafe fn vzip2q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { - simd_shuffle!(a, b, [1, 3]) +pub fn vzip2q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { + unsafe { simd_shuffle!(a, b, [1, 3]) } } #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] -pub unsafe fn vzip2_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { - simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]) +pub fn vzip2_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { + unsafe { simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]) } } #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] -pub unsafe fn vzip2q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { - simd_shuffle!( - a, - b, - [8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31] - ) +pub fn vzip2q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { + unsafe { + simd_shuffle!( + a, + b, + [8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31] + ) + } } #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] -pub unsafe fn vzip2_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { - simd_shuffle!(a, b, [2, 6, 3, 7]) +pub fn vzip2_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { + unsafe { simd_shuffle!(a, b, [2, 6, 3, 7]) } } #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] -pub unsafe fn vzip2q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { - simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]) +pub fn vzip2q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { + unsafe { simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]) } } #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] -pub unsafe fn vzip2q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { - simd_shuffle!(a, b, [1, 3]) +pub fn vzip2q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { + unsafe { simd_shuffle!(a, b, [1, 3]) } } diff --git a/crates/core_arch/src/aarch64/neon/mod.rs b/crates/core_arch/src/aarch64/neon/mod.rs index 961f950215..1c61414a9d 100644 --- a/crates/core_arch/src/aarch64/neon/mod.rs +++ b/crates/core_arch/src/aarch64/neon/mod.rs @@ -76,10 +76,7 @@ pub struct float64x2x4_t( #[cfg_attr(test, assert_instr(nop, N1 = 0, N2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopy_lane_s64( - _a: int64x1_t, - b: int64x1_t, -) -> int64x1_t { +pub fn vcopy_lane_s64(_a: int64x1_t, b: int64x1_t) -> int64x1_t { static_assert!(N1 == 0); static_assert!(N2 == 0); b @@ -91,10 +88,7 @@ pub unsafe fn vcopy_lane_s64( #[cfg_attr(test, assert_instr(nop, N1 = 0, N2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopy_lane_u64( - _a: uint64x1_t, - b: uint64x1_t, -) -> uint64x1_t { +pub fn vcopy_lane_u64(_a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { static_assert!(N1 == 0); static_assert!(N2 == 0); b @@ -106,10 +100,7 @@ pub unsafe fn vcopy_lane_u64( #[cfg_attr(test, assert_instr(nop, N1 = 0, N2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopy_lane_p64( - _a: poly64x1_t, - b: poly64x1_t, -) -> poly64x1_t { +pub fn vcopy_lane_p64(_a: poly64x1_t, b: poly64x1_t) -> poly64x1_t { static_assert!(N1 == 0); static_assert!(N2 == 0); b @@ -121,7 +112,7 @@ pub unsafe fn vcopy_lane_p64( #[cfg_attr(test, assert_instr(nop, N1 = 0, N2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopy_lane_f64( +pub fn vcopy_lane_f64( _a: float64x1_t, b: float64x1_t, ) -> float64x1_t { @@ -136,13 +127,13 @@ pub unsafe fn vcopy_lane_f64( #[cfg_attr(test, assert_instr(nop, LANE1 = 0, LANE2 = 1))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopy_laneq_s64( +pub fn vcopy_laneq_s64( _a: int64x1_t, b: int64x2_t, ) -> int64x1_t { static_assert!(LANE1 == 0); static_assert_uimm_bits!(LANE2, 1); - transmute::(simd_extract!(b, LANE2 as u32)) + unsafe { transmute::(simd_extract!(b, LANE2 as u32)) } } /// Duplicate vector element to vector or scalar @@ -151,13 +142,13 @@ pub unsafe fn vcopy_laneq_s64( #[cfg_attr(test, assert_instr(nop, LANE1 = 0, LANE2 = 1))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopy_laneq_u64( +pub fn vcopy_laneq_u64( _a: uint64x1_t, b: uint64x2_t, ) -> uint64x1_t { static_assert!(LANE1 == 0); static_assert_uimm_bits!(LANE2, 1); - transmute::(simd_extract!(b, LANE2 as u32)) + unsafe { transmute::(simd_extract!(b, LANE2 as u32)) } } /// Duplicate vector element to vector or scalar @@ -166,13 +157,13 @@ pub unsafe fn vcopy_laneq_u64( #[cfg_attr(test, assert_instr(nop, LANE1 = 0, LANE2 = 1))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopy_laneq_p64( +pub fn vcopy_laneq_p64( _a: poly64x1_t, b: poly64x2_t, ) -> poly64x1_t { static_assert!(LANE1 == 0); static_assert_uimm_bits!(LANE2, 1); - transmute::(simd_extract!(b, LANE2 as u32)) + unsafe { transmute::(simd_extract!(b, LANE2 as u32)) } } /// Duplicate vector element to vector or scalar @@ -181,13 +172,13 @@ pub unsafe fn vcopy_laneq_p64( #[cfg_attr(test, assert_instr(nop, LANE1 = 0, LANE2 = 1))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopy_laneq_f64( +pub fn vcopy_laneq_f64( _a: float64x1_t, b: float64x2_t, ) -> float64x1_t { static_assert!(LANE1 == 0); static_assert_uimm_bits!(LANE2, 1); - transmute::(simd_extract!(b, LANE2 as u32)) + unsafe { transmute::(simd_extract!(b, LANE2 as u32)) } } /// Load multiple single-element structures to one, two, three, or four registers @@ -238,42 +229,46 @@ pub unsafe fn vld1q_lane_f64(ptr: *const f64, src: float64x2_t) #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(bsl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vbsl_f64(a: uint64x1_t, b: float64x1_t, c: float64x1_t) -> float64x1_t { +pub fn vbsl_f64(a: uint64x1_t, b: float64x1_t, c: float64x1_t) -> float64x1_t { let not = int64x1_t::splat(-1); - transmute(simd_or( - simd_and(a, transmute(b)), - simd_and(simd_xor(a, transmute(not)), transmute(c)), - )) + unsafe { + transmute(simd_or( + simd_and(a, transmute(b)), + simd_and(simd_xor(a, transmute(not)), transmute(c)), + )) + } } /// Bitwise Select. #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(bsl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vbsl_p64(a: poly64x1_t, b: poly64x1_t, c: poly64x1_t) -> poly64x1_t { +pub fn vbsl_p64(a: poly64x1_t, b: poly64x1_t, c: poly64x1_t) -> poly64x1_t { let not = int64x1_t::splat(-1); - simd_or(simd_and(a, b), simd_and(simd_xor(a, transmute(not)), c)) + unsafe { simd_or(simd_and(a, b), simd_and(simd_xor(a, transmute(not)), c)) } } /// Bitwise Select. (128-bit) #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(bsl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vbslq_f64(a: uint64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t { +pub fn vbslq_f64(a: uint64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t { let not = int64x2_t::splat(-1); - transmute(simd_or( - simd_and(a, transmute(b)), - simd_and(simd_xor(a, transmute(not)), transmute(c)), - )) + unsafe { + transmute(simd_or( + simd_and(a, transmute(b)), + simd_and(simd_xor(a, transmute(not)), transmute(c)), + )) + } } /// Bitwise Select. (128-bit) #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(bsl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vbslq_p64(a: poly64x2_t, b: poly64x2_t, c: poly64x2_t) -> poly64x2_t { +pub fn vbslq_p64(a: poly64x2_t, b: poly64x2_t, c: poly64x2_t) -> poly64x2_t { let not = int64x2_t::splat(-1); - simd_or(simd_and(a, b), simd_and(simd_xor(a, transmute(not)), c)) + unsafe { simd_or(simd_and(a, b), simd_and(simd_xor(a, transmute(not)), c)) } } /// Vector add. @@ -281,8 +276,8 @@ pub unsafe fn vbslq_p64(a: poly64x2_t, b: poly64x2_t, c: poly64x2_t) -> poly64x2 #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fadd))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vadd_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { - simd_add(a, b) +pub fn vadd_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { + unsafe { simd_add(a, b) } } /// Vector add. @@ -290,8 +285,8 @@ pub unsafe fn vadd_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fadd))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vaddq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { - simd_add(a, b) +pub fn vaddq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { + unsafe { simd_add(a, b) } } /// Vector add. @@ -299,8 +294,8 @@ pub unsafe fn vaddq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(add))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vadd_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { - simd_add(a, b) +pub fn vadd_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { + unsafe { simd_add(a, b) } } /// Vector add. @@ -308,8 +303,8 @@ pub unsafe fn vadd_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(add))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vadd_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { - simd_add(a, b) +pub fn vadd_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { + unsafe { simd_add(a, b) } } /// Vector add. @@ -317,7 +312,7 @@ pub unsafe fn vadd_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(add))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vaddd_s64(a: i64, b: i64) -> i64 { +pub fn vaddd_s64(a: i64, b: i64) -> i64 { a.wrapping_add(b) } @@ -326,7 +321,7 @@ pub unsafe fn vaddd_s64(a: i64, b: i64) -> i64 { #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(add))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vaddd_u64(a: u64, b: u64) -> u64 { +pub fn vaddd_u64(a: u64, b: u64) -> u64 { a.wrapping_add(b) } @@ -336,7 +331,7 @@ pub unsafe fn vaddd_u64(a: u64, b: u64) -> u64 { #[cfg_attr(test, assert_instr(nop, N = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vext_p64(a: poly64x1_t, _b: poly64x1_t) -> poly64x1_t { +pub fn vext_p64(a: poly64x1_t, _b: poly64x1_t) -> poly64x1_t { static_assert!(N == 0); a } @@ -347,7 +342,7 @@ pub unsafe fn vext_p64(a: poly64x1_t, _b: poly64x1_t) -> poly64x1_ #[cfg_attr(test, assert_instr(nop, N = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vext_f64(a: float64x1_t, _b: float64x1_t) -> float64x1_t { +pub fn vext_f64(a: float64x1_t, _b: float64x1_t) -> float64x1_t { static_assert!(N == 0); a } @@ -357,8 +352,8 @@ pub unsafe fn vext_f64(a: float64x1_t, _b: float64x1_t) -> float64 #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmov))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vdup_n_p64(value: p64) -> poly64x1_t { - transmute(u64x1::new(value)) +pub fn vdup_n_p64(value: p64) -> poly64x1_t { + unsafe { transmute(u64x1::new(value)) } } /// Duplicate vector element to vector or scalar @@ -366,7 +361,7 @@ pub unsafe fn vdup_n_p64(value: p64) -> poly64x1_t { #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vdup_n_f64(value: f64) -> float64x1_t { +pub fn vdup_n_f64(value: f64) -> float64x1_t { float64x1_t::splat(value) } @@ -375,8 +370,8 @@ pub unsafe fn vdup_n_f64(value: f64) -> float64x1_t { #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(dup))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vdupq_n_p64(value: p64) -> poly64x2_t { - transmute(u64x2::new(value, value)) +pub fn vdupq_n_p64(value: p64) -> poly64x2_t { + unsafe { transmute(u64x2::new(value, value)) } } /// Duplicate vector element to vector or scalar @@ -384,7 +379,7 @@ pub unsafe fn vdupq_n_p64(value: p64) -> poly64x2_t { #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(dup))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vdupq_n_f64(value: f64) -> float64x2_t { +pub fn vdupq_n_f64(value: f64) -> float64x2_t { float64x2_t::splat(value) } @@ -393,7 +388,7 @@ pub unsafe fn vdupq_n_f64(value: f64) -> float64x2_t { #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fmov))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmov_n_p64(value: p64) -> poly64x1_t { +pub fn vmov_n_p64(value: p64) -> poly64x1_t { vdup_n_p64(value) } @@ -402,7 +397,7 @@ pub unsafe fn vmov_n_p64(value: p64) -> poly64x1_t { #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmov_n_f64(value: f64) -> float64x1_t { +pub fn vmov_n_f64(value: f64) -> float64x1_t { vdup_n_f64(value) } @@ -411,7 +406,7 @@ pub unsafe fn vmov_n_f64(value: f64) -> float64x1_t { #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(dup))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmovq_n_p64(value: p64) -> poly64x2_t { +pub fn vmovq_n_p64(value: p64) -> poly64x2_t { vdupq_n_p64(value) } @@ -420,7 +415,7 @@ pub unsafe fn vmovq_n_p64(value: p64) -> poly64x2_t { #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(dup))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmovq_n_f64(value: f64) -> float64x2_t { +pub fn vmovq_n_f64(value: f64) -> float64x2_t { vdupq_n_f64(value) } @@ -430,8 +425,8 @@ pub unsafe fn vmovq_n_f64(value: f64) -> float64x2_t { #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(mov))] #[cfg_attr(all(test, target_env = "msvc"), assert_instr(dup))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vget_high_f64(a: float64x2_t) -> float64x1_t { - float64x1_t([simd_extract!(a, 1)]) +pub fn vget_high_f64(a: float64x2_t) -> float64x1_t { + unsafe { float64x1_t([simd_extract!(a, 1)]) } } /// Duplicate vector element to vector or scalar @@ -439,8 +434,8 @@ pub unsafe fn vget_high_f64(a: float64x2_t) -> float64x1_t { #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ext))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vget_high_p64(a: poly64x2_t) -> poly64x1_t { - transmute(u64x1::new(simd_extract!(a, 1))) +pub fn vget_high_p64(a: poly64x2_t) -> poly64x1_t { + unsafe { transmute(u64x1::new(simd_extract!(a, 1))) } } /// Duplicate vector element to vector or scalar @@ -448,8 +443,8 @@ pub unsafe fn vget_high_p64(a: poly64x2_t) -> poly64x1_t { #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vget_low_f64(a: float64x2_t) -> float64x1_t { - float64x1_t([simd_extract!(a, 0)]) +pub fn vget_low_f64(a: float64x2_t) -> float64x1_t { + unsafe { float64x1_t([simd_extract!(a, 0)]) } } /// Duplicate vector element to vector or scalar @@ -457,8 +452,8 @@ pub unsafe fn vget_low_f64(a: float64x2_t) -> float64x1_t { #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vget_low_p64(a: poly64x2_t) -> poly64x1_t { - transmute(u64x1::new(simd_extract!(a, 0))) +pub fn vget_low_p64(a: poly64x2_t) -> poly64x1_t { + unsafe { transmute(u64x1::new(simd_extract!(a, 0))) } } /// Duplicate vector element to vector or scalar @@ -470,9 +465,9 @@ pub unsafe fn vget_low_p64(a: poly64x2_t) -> poly64x1_t { all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop, IMM5 = 0) )] -pub unsafe fn vget_lane_f64(v: float64x1_t) -> f64 { +pub fn vget_lane_f64(v: float64x1_t) -> f64 { static_assert!(IMM5 == 0); - simd_extract!(v, IMM5 as u32) + unsafe { simd_extract!(v, IMM5 as u32) } } /// Duplicate vector element to vector or scalar @@ -484,9 +479,9 @@ pub unsafe fn vget_lane_f64(v: float64x1_t) -> f64 { all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop, IMM5 = 0) )] -pub unsafe fn vgetq_lane_f64(v: float64x2_t) -> f64 { +pub fn vgetq_lane_f64(v: float64x2_t) -> f64 { static_assert_uimm_bits!(IMM5, 1); - simd_extract!(v, IMM5 as u32) + unsafe { simd_extract!(v, IMM5 as u32) } } /// Vector combine @@ -494,8 +489,8 @@ pub unsafe fn vgetq_lane_f64(v: float64x2_t) -> f64 { #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(mov))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcombine_f64(low: float64x1_t, high: float64x1_t) -> float64x2_t { - simd_shuffle!(low, high, [0, 1]) +pub fn vcombine_f64(low: float64x1_t, high: float64x1_t) -> float64x2_t { + unsafe { simd_shuffle!(low, high, [0, 1]) } } /// Shift left @@ -504,7 +499,7 @@ pub unsafe fn vcombine_f64(low: float64x1_t, high: float64x1_t) -> float64x2_t { #[cfg_attr(test, assert_instr(nop, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vshld_n_s64(a: i64) -> i64 { +pub fn vshld_n_s64(a: i64) -> i64 { static_assert_uimm_bits!(N, 6); a << N } @@ -515,7 +510,7 @@ pub unsafe fn vshld_n_s64(a: i64) -> i64 { #[cfg_attr(test, assert_instr(nop, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vshld_n_u64(a: u64) -> u64 { +pub fn vshld_n_u64(a: u64) -> u64 { static_assert_uimm_bits!(N, 6); a << N } @@ -526,7 +521,7 @@ pub unsafe fn vshld_n_u64(a: u64) -> u64 { #[cfg_attr(test, assert_instr(nop, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vshrd_n_s64(a: i64) -> i64 { +pub fn vshrd_n_s64(a: i64) -> i64 { static_assert!(N >= 1 && N <= 64); let n: i32 = if N == 64 { 63 } else { N }; a >> n @@ -538,7 +533,7 @@ pub unsafe fn vshrd_n_s64(a: i64) -> i64 { #[cfg_attr(test, assert_instr(nop, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vshrd_n_u64(a: u64) -> u64 { +pub fn vshrd_n_u64(a: u64) -> u64 { static_assert!(N >= 1 && N <= 64); let n: i32 = if N == 64 { return 0; @@ -554,7 +549,7 @@ pub unsafe fn vshrd_n_u64(a: u64) -> u64 { #[cfg_attr(test, assert_instr(nop, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vsrad_n_s64(a: i64, b: i64) -> i64 { +pub fn vsrad_n_s64(a: i64, b: i64) -> i64 { static_assert!(N >= 1 && N <= 64); a.wrapping_add(vshrd_n_s64::(b)) } @@ -565,7 +560,7 @@ pub unsafe fn vsrad_n_s64(a: i64, b: i64) -> i64 { #[cfg_attr(test, assert_instr(nop, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vsrad_n_u64(a: u64, b: u64) -> u64 { +pub fn vsrad_n_u64(a: u64, b: u64) -> u64 { static_assert!(N >= 1 && N <= 64); a.wrapping_add(vshrd_n_u64::(b)) } diff --git a/crates/core_arch/src/arm_shared/neon/generated.rs b/crates/core_arch/src/arm_shared/neon/generated.rs index abe7c5c59e..a877233565 100644 --- a/crates/core_arch/src/arm_shared/neon/generated.rs +++ b/crates/core_arch/src/arm_shared/neon/generated.rs @@ -14,8 +14,6 @@ use super::*; #[doc = "CRC32 single round checksum for bytes (8 bits)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32b)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "crc")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] @@ -28,7 +26,7 @@ use super::*; not(target_arch = "arm"), stable(feature = "stdarch_aarch64_crc32", since = "1.80.0") )] -pub unsafe fn __crc32b(crc: u32, data: u8) -> u32 { +pub fn __crc32b(crc: u32, data: u8) -> u32 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -37,12 +35,10 @@ pub unsafe fn __crc32b(crc: u32, data: u8) -> u32 { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32b")] fn ___crc32b(crc: u32, data: u32) -> u32; } - ___crc32b(crc, data as u32) + unsafe { ___crc32b(crc, data as u32) } } #[doc = "CRC32-C single round checksum for bytes (8 bits)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32cb)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "crc")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] @@ -55,7 +51,7 @@ pub unsafe fn __crc32b(crc: u32, data: u8) -> u32 { not(target_arch = "arm"), stable(feature = "stdarch_aarch64_crc32", since = "1.80.0") )] -pub unsafe fn __crc32cb(crc: u32, data: u8) -> u32 { +pub fn __crc32cb(crc: u32, data: u8) -> u32 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -64,12 +60,10 @@ pub unsafe fn __crc32cb(crc: u32, data: u8) -> u32 { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32cb")] fn ___crc32cb(crc: u32, data: u32) -> u32; } - ___crc32cb(crc, data as u32) + unsafe { ___crc32cb(crc, data as u32) } } #[doc = "CRC32-C single round checksum for quad words (64 bits)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32cd)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "crc")] #[cfg(target_arch = "arm")] @@ -78,19 +72,17 @@ pub unsafe fn __crc32cb(crc: u32, data: u8) -> u32 { target_arch = "arm", unstable(feature = "stdarch_aarch32_crc32", issue = "125085") )] -pub unsafe fn __crc32cd(crc: u32, data: u64) -> u32 { +pub fn __crc32cd(crc: u32, data: u64) -> u32 { let b: u32 = (data & 0xFFFFFFFF) as u32; let c: u32 = (data >> 32) as u32; unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32cw")] fn ___crc32cw(crc: u32, data: u32) -> u32; } - ___crc32cw(___crc32cw(crc, b), c) + unsafe { ___crc32cw(___crc32cw(crc, b), c) } } #[doc = "CRC32-C single round checksum for bytes (16 bits)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32ch)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "crc")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] @@ -103,7 +95,7 @@ pub unsafe fn __crc32cd(crc: u32, data: u64) -> u32 { not(target_arch = "arm"), stable(feature = "stdarch_aarch64_crc32", since = "1.80.0") )] -pub unsafe fn __crc32ch(crc: u32, data: u16) -> u32 { +pub fn __crc32ch(crc: u32, data: u16) -> u32 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -112,12 +104,10 @@ pub unsafe fn __crc32ch(crc: u32, data: u16) -> u32 { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32ch")] fn ___crc32ch(crc: u32, data: u32) -> u32; } - ___crc32ch(crc, data as u32) + unsafe { ___crc32ch(crc, data as u32) } } #[doc = "CRC32-C single round checksum for bytes (32 bits)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32cw)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "crc")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] @@ -130,7 +120,7 @@ pub unsafe fn __crc32ch(crc: u32, data: u16) -> u32 { not(target_arch = "arm"), stable(feature = "stdarch_aarch64_crc32", since = "1.80.0") )] -pub unsafe fn __crc32cw(crc: u32, data: u32) -> u32 { +pub fn __crc32cw(crc: u32, data: u32) -> u32 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -139,12 +129,10 @@ pub unsafe fn __crc32cw(crc: u32, data: u32) -> u32 { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32cw")] fn ___crc32cw(crc: u32, data: u32) -> u32; } - ___crc32cw(crc, data) + unsafe { ___crc32cw(crc, data) } } #[doc = "CRC32 single round checksum for quad words (64 bits)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32d)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "crc")] #[cfg(target_arch = "arm")] @@ -153,19 +141,17 @@ pub unsafe fn __crc32cw(crc: u32, data: u32) -> u32 { target_arch = "arm", unstable(feature = "stdarch_aarch32_crc32", issue = "125085") )] -pub unsafe fn __crc32d(crc: u32, data: u64) -> u32 { +pub fn __crc32d(crc: u32, data: u64) -> u32 { let b: u32 = (data & 0xFFFFFFFF) as u32; let c: u32 = (data >> 32) as u32; unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32w")] fn ___crc32w(crc: u32, data: u32) -> u32; } - ___crc32w(___crc32w(crc, b), c) + unsafe { ___crc32w(___crc32w(crc, b), c) } } #[doc = "CRC32 single round checksum for bytes (16 bits)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32h)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "crc")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] @@ -178,7 +164,7 @@ pub unsafe fn __crc32d(crc: u32, data: u64) -> u32 { not(target_arch = "arm"), stable(feature = "stdarch_aarch64_crc32", since = "1.80.0") )] -pub unsafe fn __crc32h(crc: u32, data: u16) -> u32 { +pub fn __crc32h(crc: u32, data: u16) -> u32 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -187,12 +173,10 @@ pub unsafe fn __crc32h(crc: u32, data: u16) -> u32 { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32h")] fn ___crc32h(crc: u32, data: u32) -> u32; } - ___crc32h(crc, data as u32) + unsafe { ___crc32h(crc, data as u32) } } #[doc = "CRC32 single round checksum for bytes (32 bits)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32w)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "crc")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] @@ -205,7 +189,7 @@ pub unsafe fn __crc32h(crc: u32, data: u16) -> u32 { not(target_arch = "arm"), stable(feature = "stdarch_aarch64_crc32", since = "1.80.0") )] -pub unsafe fn __crc32w(crc: u32, data: u32) -> u32 { +pub fn __crc32w(crc: u32, data: u32) -> u32 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -214,12 +198,10 @@ pub unsafe fn __crc32w(crc: u32, data: u32) -> u32 { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32w")] fn ___crc32w(crc: u32, data: u32) -> u32; } - ___crc32w(crc, data) + unsafe { ___crc32w(crc, data) } } #[doc = "Signed Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadal_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -228,17 +210,15 @@ pub unsafe fn __crc32w(crc: u32, data: u32) -> u32 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -unsafe fn priv_vpadal_s8(a: int16x4_t, b: int8x8_t) -> int16x4_t { +fn priv_vpadal_s8(a: int16x4_t, b: int8x8_t) -> int16x4_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadals.v4i16.v8i8")] fn _priv_vpadal_s8(a: int16x4_t, b: int8x8_t) -> int16x4_t; } - _priv_vpadal_s8(a, b) + unsafe { _priv_vpadal_s8(a, b) } } #[doc = "Signed Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadalq_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -247,17 +227,15 @@ unsafe fn priv_vpadal_s8(a: int16x4_t, b: int8x8_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -unsafe fn priv_vpadalq_s8(a: int16x8_t, b: int8x16_t) -> int16x8_t { +fn priv_vpadalq_s8(a: int16x8_t, b: int8x16_t) -> int16x8_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadals.v8i16.v16i8")] fn _priv_vpadalq_s8(a: int16x8_t, b: int8x16_t) -> int16x8_t; } - _priv_vpadalq_s8(a, b) + unsafe { _priv_vpadalq_s8(a, b) } } #[doc = "Signed Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadal_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -266,17 +244,15 @@ unsafe fn priv_vpadalq_s8(a: int16x8_t, b: int8x16_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -unsafe fn priv_vpadal_s16(a: int32x2_t, b: int16x4_t) -> int32x2_t { +fn priv_vpadal_s16(a: int32x2_t, b: int16x4_t) -> int32x2_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadals.v2i32.v4i16")] fn _priv_vpadal_s16(a: int32x2_t, b: int16x4_t) -> int32x2_t; } - _priv_vpadal_s16(a, b) + unsafe { _priv_vpadal_s16(a, b) } } #[doc = "Signed Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadalq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -285,17 +261,15 @@ unsafe fn priv_vpadal_s16(a: int32x2_t, b: int16x4_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -unsafe fn priv_vpadalq_s16(a: int32x4_t, b: int16x8_t) -> int32x4_t { +fn priv_vpadalq_s16(a: int32x4_t, b: int16x8_t) -> int32x4_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadals.v4i32.v8i16")] fn _priv_vpadalq_s16(a: int32x4_t, b: int16x8_t) -> int32x4_t; } - _priv_vpadalq_s16(a, b) + unsafe { _priv_vpadalq_s16(a, b) } } #[doc = "Signed Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadal_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -304,17 +278,15 @@ unsafe fn priv_vpadalq_s16(a: int32x4_t, b: int16x8_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -unsafe fn priv_vpadal_s32(a: int64x1_t, b: int32x2_t) -> int64x1_t { +fn priv_vpadal_s32(a: int64x1_t, b: int32x2_t) -> int64x1_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadals.v1i64.v2i32")] fn _priv_vpadal_s32(a: int64x1_t, b: int32x2_t) -> int64x1_t; } - _priv_vpadal_s32(a, b) + unsafe { _priv_vpadal_s32(a, b) } } #[doc = "Signed Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadalq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -323,17 +295,15 @@ unsafe fn priv_vpadal_s32(a: int64x1_t, b: int32x2_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -unsafe fn priv_vpadalq_s32(a: int64x2_t, b: int32x4_t) -> int64x2_t { +fn priv_vpadalq_s32(a: int64x2_t, b: int32x4_t) -> int64x2_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadals.v2i64.v4i32")] fn _priv_vpadalq_s32(a: int64x2_t, b: int32x4_t) -> int64x2_t; } - _priv_vpadalq_s32(a, b) + unsafe { _priv_vpadalq_s32(a, b) } } #[doc = "Signed Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadal_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -342,17 +312,15 @@ unsafe fn priv_vpadalq_s32(a: int64x2_t, b: int32x4_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -unsafe fn priv_vpadal_u8(a: uint16x4_t, b: uint8x8_t) -> uint16x4_t { +fn priv_vpadal_u8(a: uint16x4_t, b: uint8x8_t) -> uint16x4_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadalu.v4i16.v8i8")] fn _priv_vpadal_u8(a: uint16x4_t, b: uint8x8_t) -> uint16x4_t; } - _priv_vpadal_u8(a, b) + unsafe { _priv_vpadal_u8(a, b) } } #[doc = "Signed Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadalq_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -361,17 +329,15 @@ unsafe fn priv_vpadal_u8(a: uint16x4_t, b: uint8x8_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -unsafe fn priv_vpadalq_u8(a: uint16x8_t, b: uint8x16_t) -> uint16x8_t { +fn priv_vpadalq_u8(a: uint16x8_t, b: uint8x16_t) -> uint16x8_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadalu.v8i16.v16i8")] fn _priv_vpadalq_u8(a: uint16x8_t, b: uint8x16_t) -> uint16x8_t; } - _priv_vpadalq_u8(a, b) + unsafe { _priv_vpadalq_u8(a, b) } } #[doc = "Signed Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadal_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -380,17 +346,15 @@ unsafe fn priv_vpadalq_u8(a: uint16x8_t, b: uint8x16_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -unsafe fn priv_vpadal_u16(a: uint32x2_t, b: uint16x4_t) -> uint32x2_t { +fn priv_vpadal_u16(a: uint32x2_t, b: uint16x4_t) -> uint32x2_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadalu.v2i32.v4i16")] fn _priv_vpadal_u16(a: uint32x2_t, b: uint16x4_t) -> uint32x2_t; } - _priv_vpadal_u16(a, b) + unsafe { _priv_vpadal_u16(a, b) } } #[doc = "Signed Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadalq_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -399,17 +363,15 @@ unsafe fn priv_vpadal_u16(a: uint32x2_t, b: uint16x4_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -unsafe fn priv_vpadalq_u16(a: uint32x4_t, b: uint16x8_t) -> uint32x4_t { +fn priv_vpadalq_u16(a: uint32x4_t, b: uint16x8_t) -> uint32x4_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadalu.v4i32.v8i16")] fn _priv_vpadalq_u16(a: uint32x4_t, b: uint16x8_t) -> uint32x4_t; } - _priv_vpadalq_u16(a, b) + unsafe { _priv_vpadalq_u16(a, b) } } #[doc = "Signed Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadal_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -418,17 +380,15 @@ unsafe fn priv_vpadalq_u16(a: uint32x4_t, b: uint16x8_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -unsafe fn priv_vpadal_u32(a: uint64x1_t, b: uint32x2_t) -> uint64x1_t { +fn priv_vpadal_u32(a: uint64x1_t, b: uint32x2_t) -> uint64x1_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadalu.v1i64.v2i32")] fn _priv_vpadal_u32(a: uint64x1_t, b: uint32x2_t) -> uint64x1_t; } - _priv_vpadal_u32(a, b) + unsafe { _priv_vpadal_u32(a, b) } } #[doc = "Signed Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadalq_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -437,17 +397,15 @@ unsafe fn priv_vpadal_u32(a: uint64x1_t, b: uint32x2_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -unsafe fn priv_vpadalq_u32(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t { +fn priv_vpadalq_u32(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadalu.v2i64.v4i32")] fn _priv_vpadalq_u32(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t; } - _priv_vpadalq_u32(a, b) + unsafe { _priv_vpadalq_u32(a, b) } } #[doc = "Signed Absolute difference and Accumulate Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -464,15 +422,15 @@ unsafe fn priv_vpadalq_u32(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vabal_s8(a: int16x8_t, b: int8x8_t, c: int8x8_t) -> int16x8_t { +pub fn vabal_s8(a: int16x8_t, b: int8x8_t, c: int8x8_t) -> int16x8_t { let d: int8x8_t = vabd_s8(b, c); - let e: uint8x8_t = simd_cast(d); - simd_add(a, simd_cast(e)) + unsafe { + let e: uint8x8_t = simd_cast(d); + simd_add(a, simd_cast(e)) + } } #[doc = "Signed Absolute difference and Accumulate Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -489,15 +447,15 @@ pub unsafe fn vabal_s8(a: int16x8_t, b: int8x8_t, c: int8x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vabal_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t { +pub fn vabal_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t { let d: int16x4_t = vabd_s16(b, c); - let e: uint16x4_t = simd_cast(d); - simd_add(a, simd_cast(e)) + unsafe { + let e: uint16x4_t = simd_cast(d); + simd_add(a, simd_cast(e)) + } } #[doc = "Signed Absolute difference and Accumulate Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -514,15 +472,15 @@ pub unsafe fn vabal_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vabal_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t { +pub fn vabal_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t { let d: int32x2_t = vabd_s32(b, c); - let e: uint32x2_t = simd_cast(d); - simd_add(a, simd_cast(e)) + unsafe { + let e: uint32x2_t = simd_cast(d); + simd_add(a, simd_cast(e)) + } } #[doc = "Unsigned Absolute difference and Accumulate Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -539,14 +497,12 @@ pub unsafe fn vabal_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vabal_u8(a: uint16x8_t, b: uint8x8_t, c: uint8x8_t) -> uint16x8_t { +pub fn vabal_u8(a: uint16x8_t, b: uint8x8_t, c: uint8x8_t) -> uint16x8_t { let d: uint8x8_t = vabd_u8(b, c); - simd_add(a, simd_cast(d)) + unsafe { simd_add(a, simd_cast(d)) } } #[doc = "Unsigned Absolute difference and Accumulate Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -563,14 +519,12 @@ pub unsafe fn vabal_u8(a: uint16x8_t, b: uint8x8_t, c: uint8x8_t) -> uint16x8_t target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vabal_u16(a: uint32x4_t, b: uint16x4_t, c: uint16x4_t) -> uint32x4_t { +pub fn vabal_u16(a: uint32x4_t, b: uint16x4_t, c: uint16x4_t) -> uint32x4_t { let d: uint16x4_t = vabd_u16(b, c); - simd_add(a, simd_cast(d)) + unsafe { simd_add(a, simd_cast(d)) } } #[doc = "Unsigned Absolute difference and Accumulate Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -587,14 +541,12 @@ pub unsafe fn vabal_u16(a: uint32x4_t, b: uint16x4_t, c: uint16x4_t) -> uint32x4 target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vabal_u32(a: uint64x2_t, b: uint32x2_t, c: uint32x2_t) -> uint64x2_t { +pub fn vabal_u32(a: uint64x2_t, b: uint32x2_t, c: uint32x2_t) -> uint64x2_t { let d: uint32x2_t = vabd_u32(b, c); - simd_add(a, simd_cast(d)) + unsafe { simd_add(a, simd_cast(d)) } } #[doc = "Absolute difference between the arguments of Floating"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.f16"))] @@ -604,7 +556,7 @@ pub unsafe fn vabal_u32(a: uint64x2_t, b: uint32x2_t, c: uint32x2_t) -> uint64x2 )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vabd_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { +pub fn vabd_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabds.v4f16")] #[cfg_attr( @@ -613,12 +565,10 @@ pub unsafe fn vabd_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { )] fn _vabd_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t; } - _vabd_f16(a, b) + unsafe { _vabd_f16(a, b) } } #[doc = "Absolute difference between the arguments of Floating"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.f16"))] @@ -628,7 +578,7 @@ pub unsafe fn vabd_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vabdq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { +pub fn vabdq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabds.v8f16")] #[cfg_attr( @@ -637,12 +587,10 @@ pub unsafe fn vabdq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { )] fn _vabdq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t; } - _vabdq_f16(a, b) + unsafe { _vabdq_f16(a, b) } } #[doc = "Absolute difference between the arguments of Floating"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -659,7 +607,7 @@ pub unsafe fn vabdq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vabd_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { +pub fn vabd_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabds.v2f32")] #[cfg_attr( @@ -668,12 +616,10 @@ pub unsafe fn vabd_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { )] fn _vabd_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t; } - _vabd_f32(a, b) + unsafe { _vabd_f32(a, b) } } #[doc = "Absolute difference between the arguments of Floating"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -690,7 +636,7 @@ pub unsafe fn vabd_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vabdq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { +pub fn vabdq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabds.v4f32")] #[cfg_attr( @@ -699,12 +645,10 @@ pub unsafe fn vabdq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { )] fn _vabdq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t; } - _vabdq_f32(a, b) + unsafe { _vabdq_f32(a, b) } } #[doc = "Absolute difference between the arguments"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -721,7 +665,7 @@ pub unsafe fn vabdq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vabd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { +pub fn vabd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -730,12 +674,10 @@ pub unsafe fn vabd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabds.v8i8")] fn _vabd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t; } - _vabd_s8(a, b) + unsafe { _vabd_s8(a, b) } } #[doc = "Absolute difference between the arguments"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -752,7 +694,7 @@ pub unsafe fn vabd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vabdq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { +pub fn vabdq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -761,12 +703,10 @@ pub unsafe fn vabdq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabds.v16i8")] fn _vabdq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t; } - _vabdq_s8(a, b) + unsafe { _vabdq_s8(a, b) } } #[doc = "Absolute difference between the arguments"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -783,7 +723,7 @@ pub unsafe fn vabdq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vabd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { +pub fn vabd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -792,12 +732,10 @@ pub unsafe fn vabd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabds.v4i16")] fn _vabd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t; } - _vabd_s16(a, b) + unsafe { _vabd_s16(a, b) } } #[doc = "Absolute difference between the arguments"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -814,7 +752,7 @@ pub unsafe fn vabd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vabdq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { +pub fn vabdq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -823,12 +761,10 @@ pub unsafe fn vabdq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabds.v8i16")] fn _vabdq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t; } - _vabdq_s16(a, b) + unsafe { _vabdq_s16(a, b) } } #[doc = "Absolute difference between the arguments"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -845,7 +781,7 @@ pub unsafe fn vabdq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vabd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { +pub fn vabd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -854,12 +790,10 @@ pub unsafe fn vabd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabds.v2i32")] fn _vabd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t; } - _vabd_s32(a, b) + unsafe { _vabd_s32(a, b) } } #[doc = "Absolute difference between the arguments"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -876,7 +810,7 @@ pub unsafe fn vabd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vabdq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { +pub fn vabdq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -885,12 +819,10 @@ pub unsafe fn vabdq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabds.v4i32")] fn _vabdq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t; } - _vabdq_s32(a, b) + unsafe { _vabdq_s32(a, b) } } #[doc = "Absolute difference between the arguments"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -907,7 +839,7 @@ pub unsafe fn vabdq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vabd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { +pub fn vabd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -916,12 +848,10 @@ pub unsafe fn vabd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabdu.v8i8")] fn _vabd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t; } - _vabd_u8(a, b) + unsafe { _vabd_u8(a, b) } } #[doc = "Absolute difference between the arguments"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -938,7 +868,7 @@ pub unsafe fn vabd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vabdq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { +pub fn vabdq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -947,12 +877,10 @@ pub unsafe fn vabdq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabdu.v16i8")] fn _vabdq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t; } - _vabdq_u8(a, b) + unsafe { _vabdq_u8(a, b) } } #[doc = "Absolute difference between the arguments"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -969,7 +897,7 @@ pub unsafe fn vabdq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vabd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { +pub fn vabd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -978,12 +906,10 @@ pub unsafe fn vabd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabdu.v4i16")] fn _vabd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t; } - _vabd_u16(a, b) + unsafe { _vabd_u16(a, b) } } #[doc = "Absolute difference between the arguments"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -1000,7 +926,7 @@ pub unsafe fn vabd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vabdq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { +pub fn vabdq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -1009,12 +935,10 @@ pub unsafe fn vabdq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabdu.v8i16")] fn _vabdq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t; } - _vabdq_u16(a, b) + unsafe { _vabdq_u16(a, b) } } #[doc = "Absolute difference between the arguments"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -1031,7 +955,7 @@ pub unsafe fn vabdq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vabd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { +pub fn vabd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -1040,12 +964,10 @@ pub unsafe fn vabd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabdu.v2i32")] fn _vabd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t; } - _vabd_u32(a, b) + unsafe { _vabd_u32(a, b) } } #[doc = "Absolute difference between the arguments"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -1062,7 +984,7 @@ pub unsafe fn vabd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vabdq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { +pub fn vabdq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -1071,12 +993,10 @@ pub unsafe fn vabdq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabdu.v4i32")] fn _vabdq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t; } - _vabdq_u32(a, b) + unsafe { _vabdq_u32(a, b) } } #[doc = "Signed Absolute difference Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -1093,14 +1013,14 @@ pub unsafe fn vabdq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vabdl_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t { - let c: uint8x8_t = simd_cast(vabd_s8(a, b)); - simd_cast(c) +pub fn vabdl_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t { + unsafe { + let c: uint8x8_t = simd_cast(vabd_s8(a, b)); + simd_cast(c) + } } #[doc = "Signed Absolute difference Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -1117,14 +1037,14 @@ pub unsafe fn vabdl_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vabdl_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t { - let c: uint16x4_t = simd_cast(vabd_s16(a, b)); - simd_cast(c) +pub fn vabdl_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t { + unsafe { + let c: uint16x4_t = simd_cast(vabd_s16(a, b)); + simd_cast(c) + } } #[doc = "Signed Absolute difference Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -1141,14 +1061,14 @@ pub unsafe fn vabdl_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vabdl_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t { - let c: uint32x2_t = simd_cast(vabd_s32(a, b)); - simd_cast(c) +pub fn vabdl_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t { + unsafe { + let c: uint32x2_t = simd_cast(vabd_s32(a, b)); + simd_cast(c) + } } #[doc = "Unsigned Absolute difference Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -1165,13 +1085,11 @@ pub unsafe fn vabdl_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vabdl_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t { - simd_cast(vabd_u8(a, b)) +pub fn vabdl_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t { + unsafe { simd_cast(vabd_u8(a, b)) } } #[doc = "Unsigned Absolute difference Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -1188,13 +1106,11 @@ pub unsafe fn vabdl_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vabdl_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t { - simd_cast(vabd_u16(a, b)) +pub fn vabdl_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t { + unsafe { simd_cast(vabd_u16(a, b)) } } #[doc = "Unsigned Absolute difference Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -1211,13 +1127,11 @@ pub unsafe fn vabdl_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vabdl_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t { - simd_cast(vabd_u32(a, b)) +pub fn vabdl_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t { + unsafe { simd_cast(vabd_u32(a, b)) } } #[doc = "Floating-point absolute value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))] @@ -1227,13 +1141,11 @@ pub unsafe fn vabdl_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vabs_f16(a: float16x4_t) -> float16x4_t { - simd_fabs(a) +pub fn vabs_f16(a: float16x4_t) -> float16x4_t { + unsafe { simd_fabs(a) } } #[doc = "Floating-point absolute value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))] @@ -1243,13 +1155,11 @@ pub unsafe fn vabs_f16(a: float16x4_t) -> float16x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vabsq_f16(a: float16x8_t) -> float16x8_t { - simd_fabs(a) +pub fn vabsq_f16(a: float16x8_t) -> float16x8_t { + unsafe { simd_fabs(a) } } #[doc = "Floating-point absolute value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -1266,13 +1176,11 @@ pub unsafe fn vabsq_f16(a: float16x8_t) -> float16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vabs_f32(a: float32x2_t) -> float32x2_t { - simd_fabs(a) +pub fn vabs_f32(a: float32x2_t) -> float32x2_t { + unsafe { simd_fabs(a) } } #[doc = "Floating-point absolute value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -1289,13 +1197,11 @@ pub unsafe fn vabs_f32(a: float32x2_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vabsq_f32(a: float32x4_t) -> float32x4_t { - simd_fabs(a) +pub fn vabsq_f32(a: float32x4_t) -> float32x4_t { + unsafe { simd_fabs(a) } } #[doc = "Absolute value (wrapping)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -1312,7 +1218,7 @@ pub unsafe fn vabsq_f32(a: float32x4_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vabs_s8(a: int8x8_t) -> int8x8_t { +pub fn vabs_s8(a: int8x8_t) -> int8x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -1321,12 +1227,10 @@ pub unsafe fn vabs_s8(a: int8x8_t) -> int8x8_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabs.v8i8")] fn _vabs_s8(a: int8x8_t) -> int8x8_t; } - _vabs_s8(a) + unsafe { _vabs_s8(a) } } #[doc = "Absolute value (wrapping)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -1343,7 +1247,7 @@ pub unsafe fn vabs_s8(a: int8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vabsq_s8(a: int8x16_t) -> int8x16_t { +pub fn vabsq_s8(a: int8x16_t) -> int8x16_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -1352,12 +1256,10 @@ pub unsafe fn vabsq_s8(a: int8x16_t) -> int8x16_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabs.v16i8")] fn _vabsq_s8(a: int8x16_t) -> int8x16_t; } - _vabsq_s8(a) + unsafe { _vabsq_s8(a) } } #[doc = "Absolute value (wrapping)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -1374,7 +1276,7 @@ pub unsafe fn vabsq_s8(a: int8x16_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vabs_s16(a: int16x4_t) -> int16x4_t { +pub fn vabs_s16(a: int16x4_t) -> int16x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -1383,12 +1285,10 @@ pub unsafe fn vabs_s16(a: int16x4_t) -> int16x4_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabs.v4i16")] fn _vabs_s16(a: int16x4_t) -> int16x4_t; } - _vabs_s16(a) + unsafe { _vabs_s16(a) } } #[doc = "Absolute value (wrapping)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -1405,7 +1305,7 @@ pub unsafe fn vabs_s16(a: int16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vabsq_s16(a: int16x8_t) -> int16x8_t { +pub fn vabsq_s16(a: int16x8_t) -> int16x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -1414,12 +1314,10 @@ pub unsafe fn vabsq_s16(a: int16x8_t) -> int16x8_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabs.v8i16")] fn _vabsq_s16(a: int16x8_t) -> int16x8_t; } - _vabsq_s16(a) + unsafe { _vabsq_s16(a) } } #[doc = "Absolute value (wrapping)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -1436,7 +1334,7 @@ pub unsafe fn vabsq_s16(a: int16x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vabs_s32(a: int32x2_t) -> int32x2_t { +pub fn vabs_s32(a: int32x2_t) -> int32x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -1445,12 +1343,10 @@ pub unsafe fn vabs_s32(a: int32x2_t) -> int32x2_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabs.v2i32")] fn _vabs_s32(a: int32x2_t) -> int32x2_t; } - _vabs_s32(a) + unsafe { _vabs_s32(a) } } #[doc = "Absolute value (wrapping)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -1467,7 +1363,7 @@ pub unsafe fn vabs_s32(a: int32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vabsq_s32(a: int32x4_t) -> int32x4_t { +pub fn vabsq_s32(a: int32x4_t) -> int32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -1476,12 +1372,10 @@ pub unsafe fn vabsq_s32(a: int32x4_t) -> int32x4_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabs.v4i32")] fn _vabsq_s32(a: int32x4_t) -> int32x4_t; } - _vabsq_s32(a) + unsafe { _vabsq_s32(a) } } #[doc = "Floating-point absolute value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsh_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))] @@ -1491,13 +1385,11 @@ pub unsafe fn vabsq_s32(a: int32x4_t) -> int32x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vabsh_f16(a: f16) -> f16 { - simd_extract!(vabs_f16(vdup_n_f16(a)), 0) +pub fn vabsh_f16(a: f16) -> f16 { + unsafe { simd_extract!(vabs_f16(vdup_n_f16(a)), 0) } } #[doc = "Floating-point Add (vector)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vadd.f16"))] @@ -1507,13 +1399,11 @@ pub unsafe fn vabsh_f16(a: f16) -> f16 { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vadd_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { - simd_add(a, b) +pub fn vadd_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { + unsafe { simd_add(a, b) } } #[doc = "Floating-point Add (vector)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vadd.f16"))] @@ -1523,13 +1413,11 @@ pub unsafe fn vadd_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vaddq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { - simd_add(a, b) +pub fn vaddq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { + unsafe { simd_add(a, b) } } #[doc = "Bitwise exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -1546,13 +1434,11 @@ pub unsafe fn vaddq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vadd_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { - simd_xor(a, b) +pub fn vadd_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { + unsafe { simd_xor(a, b) } } #[doc = "Bitwise exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -1569,13 +1455,11 @@ pub unsafe fn vadd_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vaddq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { - simd_xor(a, b) +pub fn vaddq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { + unsafe { simd_xor(a, b) } } #[doc = "Bitwise exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -1592,13 +1476,11 @@ pub unsafe fn vaddq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vadd_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { - simd_xor(a, b) +pub fn vadd_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { + unsafe { simd_xor(a, b) } } #[doc = "Bitwise exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -1615,13 +1497,11 @@ pub unsafe fn vadd_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vaddq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { - simd_xor(a, b) +pub fn vaddq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { + unsafe { simd_xor(a, b) } } #[doc = "Bitwise exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -1638,13 +1518,11 @@ pub unsafe fn vaddq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vadd_p64(a: poly64x1_t, b: poly64x1_t) -> poly64x1_t { - simd_xor(a, b) +pub fn vadd_p64(a: poly64x1_t, b: poly64x1_t) -> poly64x1_t { + unsafe { simd_xor(a, b) } } #[doc = "Bitwise exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -1661,13 +1539,11 @@ pub unsafe fn vadd_p64(a: poly64x1_t, b: poly64x1_t) -> poly64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vaddq_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { - simd_xor(a, b) +pub fn vaddq_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { + unsafe { simd_xor(a, b) } } #[doc = "Add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddh_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vadd.f16"))] @@ -1677,13 +1553,11 @@ pub unsafe fn vaddq_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vaddh_f16(a: f16, b: f16) -> f16 { +pub fn vaddh_f16(a: f16, b: f16) -> f16 { a + b } #[doc = "Bitwise exclusive OR"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_p128)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -1700,13 +1574,11 @@ pub unsafe fn vaddh_f16(a: f16, b: f16) -> f16 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vaddq_p128(a: p128, b: p128) -> p128 { +pub fn vaddq_p128(a: p128, b: p128) -> p128 { a ^ b } #[doc = "AES single round encryption."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaesdq_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] @@ -1719,7 +1591,7 @@ pub unsafe fn vaddq_p128(a: p128, b: p128) -> p128 { not(target_arch = "arm"), stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0") )] -pub unsafe fn vaesdq_u8(data: uint8x16_t, key: uint8x16_t) -> uint8x16_t { +pub fn vaesdq_u8(data: uint8x16_t, key: uint8x16_t) -> uint8x16_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -1728,12 +1600,10 @@ pub unsafe fn vaesdq_u8(data: uint8x16_t, key: uint8x16_t) -> uint8x16_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.aesd")] fn _vaesdq_u8(data: uint8x16_t, key: uint8x16_t) -> uint8x16_t; } - _vaesdq_u8(data, key) + unsafe { _vaesdq_u8(data, key) } } #[doc = "AES single round encryption."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaeseq_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] @@ -1746,7 +1616,7 @@ pub unsafe fn vaesdq_u8(data: uint8x16_t, key: uint8x16_t) -> uint8x16_t { not(target_arch = "arm"), stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0") )] -pub unsafe fn vaeseq_u8(data: uint8x16_t, key: uint8x16_t) -> uint8x16_t { +pub fn vaeseq_u8(data: uint8x16_t, key: uint8x16_t) -> uint8x16_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -1755,12 +1625,10 @@ pub unsafe fn vaeseq_u8(data: uint8x16_t, key: uint8x16_t) -> uint8x16_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.aese")] fn _vaeseq_u8(data: uint8x16_t, key: uint8x16_t) -> uint8x16_t; } - _vaeseq_u8(data, key) + unsafe { _vaeseq_u8(data, key) } } #[doc = "AES inverse mix columns."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaesimcq_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] @@ -1773,7 +1641,7 @@ pub unsafe fn vaeseq_u8(data: uint8x16_t, key: uint8x16_t) -> uint8x16_t { not(target_arch = "arm"), stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0") )] -pub unsafe fn vaesimcq_u8(data: uint8x16_t) -> uint8x16_t { +pub fn vaesimcq_u8(data: uint8x16_t) -> uint8x16_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -1782,12 +1650,10 @@ pub unsafe fn vaesimcq_u8(data: uint8x16_t) -> uint8x16_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.aesimc")] fn _vaesimcq_u8(data: uint8x16_t) -> uint8x16_t; } - _vaesimcq_u8(data) + unsafe { _vaesimcq_u8(data) } } #[doc = "AES mix columns."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaesmcq_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] @@ -1800,7 +1666,7 @@ pub unsafe fn vaesimcq_u8(data: uint8x16_t) -> uint8x16_t { not(target_arch = "arm"), stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0") )] -pub unsafe fn vaesmcq_u8(data: uint8x16_t) -> uint8x16_t { +pub fn vaesmcq_u8(data: uint8x16_t) -> uint8x16_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -1809,12 +1675,10 @@ pub unsafe fn vaesmcq_u8(data: uint8x16_t) -> uint8x16_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.aesmc")] fn _vaesmcq_u8(data: uint8x16_t) -> uint8x16_t; } - _vaesmcq_u8(data) + unsafe { _vaesmcq_u8(data) } } #[doc = "Vector bitwise and"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -1831,13 +1695,11 @@ pub unsafe fn vaesmcq_u8(data: uint8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vand_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { - simd_and(a, b) +pub fn vand_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { + unsafe { simd_and(a, b) } } #[doc = "Vector bitwise and"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -1854,13 +1716,11 @@ pub unsafe fn vand_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vandq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { - simd_and(a, b) +pub fn vandq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { + unsafe { simd_and(a, b) } } #[doc = "Vector bitwise and"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -1877,13 +1737,11 @@ pub unsafe fn vandq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vand_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { - simd_and(a, b) +pub fn vand_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + unsafe { simd_and(a, b) } } #[doc = "Vector bitwise and"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -1900,13 +1758,11 @@ pub unsafe fn vand_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vandq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { - simd_and(a, b) +pub fn vandq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + unsafe { simd_and(a, b) } } #[doc = "Vector bitwise and"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -1923,13 +1779,11 @@ pub unsafe fn vandq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vand_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { - simd_and(a, b) +pub fn vand_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + unsafe { simd_and(a, b) } } #[doc = "Vector bitwise and"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -1946,13 +1800,11 @@ pub unsafe fn vand_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vandq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { - simd_and(a, b) +pub fn vandq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + unsafe { simd_and(a, b) } } #[doc = "Vector bitwise and"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -1969,13 +1821,11 @@ pub unsafe fn vandq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vand_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { - simd_and(a, b) +pub fn vand_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { + unsafe { simd_and(a, b) } } #[doc = "Vector bitwise and"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -1992,13 +1842,11 @@ pub unsafe fn vand_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vandq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { - simd_and(a, b) +pub fn vandq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { + unsafe { simd_and(a, b) } } #[doc = "Vector bitwise and"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -2015,13 +1863,11 @@ pub unsafe fn vandq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vand_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { - simd_and(a, b) +pub fn vand_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + unsafe { simd_and(a, b) } } #[doc = "Vector bitwise and"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -2038,13 +1884,11 @@ pub unsafe fn vand_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vandq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { - simd_and(a, b) +pub fn vandq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + unsafe { simd_and(a, b) } } #[doc = "Vector bitwise and"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -2061,13 +1905,11 @@ pub unsafe fn vandq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vand_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { - simd_and(a, b) +pub fn vand_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + unsafe { simd_and(a, b) } } #[doc = "Vector bitwise and"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -2084,13 +1926,11 @@ pub unsafe fn vand_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vandq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { - simd_and(a, b) +pub fn vandq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + unsafe { simd_and(a, b) } } #[doc = "Vector bitwise and"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -2107,13 +1947,11 @@ pub unsafe fn vandq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vand_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { - simd_and(a, b) +pub fn vand_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + unsafe { simd_and(a, b) } } #[doc = "Vector bitwise and"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -2130,13 +1968,11 @@ pub unsafe fn vand_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vandq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { - simd_and(a, b) +pub fn vandq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + unsafe { simd_and(a, b) } } #[doc = "Vector bitwise and"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -2153,13 +1989,11 @@ pub unsafe fn vandq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vand_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { - simd_and(a, b) +pub fn vand_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { + unsafe { simd_and(a, b) } } #[doc = "Vector bitwise and"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -2176,13 +2010,11 @@ pub unsafe fn vand_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vandq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { - simd_and(a, b) +pub fn vandq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { + unsafe { simd_and(a, b) } } #[doc = "Floating-point absolute compare greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcage_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f16"))] @@ -2192,7 +2024,7 @@ pub unsafe fn vandq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcage_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t { +pub fn vcage_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vacge.v4i16.v4f16")] #[cfg_attr( @@ -2201,12 +2033,10 @@ pub unsafe fn vcage_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t { )] fn _vcage_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t; } - _vcage_f16(a, b) + unsafe { _vcage_f16(a, b) } } #[doc = "Floating-point absolute compare greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcageq_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f16"))] @@ -2216,7 +2046,7 @@ pub unsafe fn vcage_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcageq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t { +pub fn vcageq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vacge.v8i16.v8f16")] #[cfg_attr( @@ -2225,12 +2055,10 @@ pub unsafe fn vcageq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t { )] fn _vcageq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t; } - _vcageq_f16(a, b) + unsafe { _vcageq_f16(a, b) } } #[doc = "Floating-point absolute compare greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcage_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -2247,7 +2075,7 @@ pub unsafe fn vcageq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcage_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t { +pub fn vcage_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vacge.v2i32.v2f32")] #[cfg_attr( @@ -2256,12 +2084,10 @@ pub unsafe fn vcage_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t { )] fn _vcage_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t; } - _vcage_f32(a, b) + unsafe { _vcage_f32(a, b) } } #[doc = "Floating-point absolute compare greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcageq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -2278,7 +2104,7 @@ pub unsafe fn vcage_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcageq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { +pub fn vcageq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vacge.v4i32.v4f32")] #[cfg_attr( @@ -2287,12 +2113,10 @@ pub unsafe fn vcageq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { )] fn _vcageq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t; } - _vcageq_f32(a, b) + unsafe { _vcageq_f32(a, b) } } #[doc = "Floating-point absolute compare greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagt_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f16"))] @@ -2302,7 +2126,7 @@ pub unsafe fn vcageq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcagt_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t { +pub fn vcagt_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vacgt.v4i16.v4f16")] #[cfg_attr( @@ -2311,12 +2135,10 @@ pub unsafe fn vcagt_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t { )] fn _vcagt_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t; } - _vcagt_f16(a, b) + unsafe { _vcagt_f16(a, b) } } #[doc = "Floating-point absolute compare greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagtq_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f16"))] @@ -2326,7 +2148,7 @@ pub unsafe fn vcagt_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcagtq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t { +pub fn vcagtq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vacgt.v8i16.v8f16")] #[cfg_attr( @@ -2335,12 +2157,10 @@ pub unsafe fn vcagtq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t { )] fn _vcagtq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t; } - _vcagtq_f16(a, b) + unsafe { _vcagtq_f16(a, b) } } #[doc = "Floating-point absolute compare greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagt_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -2357,7 +2177,7 @@ pub unsafe fn vcagtq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcagt_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t { +pub fn vcagt_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vacgt.v2i32.v2f32")] #[cfg_attr( @@ -2366,12 +2186,10 @@ pub unsafe fn vcagt_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t { )] fn _vcagt_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t; } - _vcagt_f32(a, b) + unsafe { _vcagt_f32(a, b) } } #[doc = "Floating-point absolute compare greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagtq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -2388,7 +2206,7 @@ pub unsafe fn vcagt_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcagtq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { +pub fn vcagtq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vacgt.v4i32.v4f32")] #[cfg_attr( @@ -2397,12 +2215,10 @@ pub unsafe fn vcagtq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { )] fn _vcagtq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t; } - _vcagtq_f32(a, b) + unsafe { _vcagtq_f32(a, b) } } #[doc = "Floating-point absolute compare less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcale_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f16"))] @@ -2412,13 +2228,11 @@ pub unsafe fn vcagtq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcale_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t { +pub fn vcale_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t { vcage_f16(b, a) } #[doc = "Floating-point absolute compare less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaleq_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f16"))] @@ -2428,13 +2242,11 @@ pub unsafe fn vcale_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcaleq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t { +pub fn vcaleq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t { vcageq_f16(b, a) } #[doc = "Floating-point absolute compare less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcale_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -2451,13 +2263,11 @@ pub unsafe fn vcaleq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcale_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t { +pub fn vcale_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t { vcage_f32(b, a) } #[doc = "Floating-point absolute compare less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaleq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -2474,13 +2284,11 @@ pub unsafe fn vcale_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcaleq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { +pub fn vcaleq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { vcageq_f32(b, a) } #[doc = "Floating-point absolute compare less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcalt_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f16"))] @@ -2490,13 +2298,11 @@ pub unsafe fn vcaleq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcalt_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t { +pub fn vcalt_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t { vcagt_f16(b, a) } #[doc = "Floating-point absolute compare less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaltq_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f16"))] @@ -2506,13 +2312,11 @@ pub unsafe fn vcalt_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcaltq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t { +pub fn vcaltq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t { vcagtq_f16(b, a) } #[doc = "Floating-point absolute compare less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcalt_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -2529,13 +2333,11 @@ pub unsafe fn vcaltq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcalt_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t { +pub fn vcalt_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t { vcagt_f32(b, a) } #[doc = "Floating-point absolute compare less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaltq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -2552,13 +2354,11 @@ pub unsafe fn vcalt_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcaltq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { +pub fn vcaltq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { vcagtq_f32(b, a) } #[doc = "Floating-point compare equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.f16"))] @@ -2568,13 +2368,11 @@ pub unsafe fn vcaltq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vceq_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t { - simd_eq(a, b) +pub fn vceq_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t { + unsafe { simd_eq(a, b) } } #[doc = "Floating-point compare equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.f16"))] @@ -2584,13 +2382,11 @@ pub unsafe fn vceq_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vceqq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t { - simd_eq(a, b) +pub fn vceqq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t { + unsafe { simd_eq(a, b) } } #[doc = "Floating-point compare equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -2607,13 +2403,11 @@ pub unsafe fn vceqq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vceq_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t { - simd_eq(a, b) +pub fn vceq_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t { + unsafe { simd_eq(a, b) } } #[doc = "Floating-point compare equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -2630,13 +2424,11 @@ pub unsafe fn vceq_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vceqq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { - simd_eq(a, b) +pub fn vceqq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { + unsafe { simd_eq(a, b) } } #[doc = "Compare bitwise Equal (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -2653,13 +2445,11 @@ pub unsafe fn vceqq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vceq_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t { - simd_eq(a, b) +pub fn vceq_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t { + unsafe { simd_eq(a, b) } } #[doc = "Compare bitwise Equal (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -2676,13 +2466,11 @@ pub unsafe fn vceq_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vceqq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t { - simd_eq(a, b) +pub fn vceqq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t { + unsafe { simd_eq(a, b) } } #[doc = "Compare bitwise Equal (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -2699,13 +2487,11 @@ pub unsafe fn vceqq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vceq_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t { - simd_eq(a, b) +pub fn vceq_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t { + unsafe { simd_eq(a, b) } } #[doc = "Compare bitwise Equal (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -2722,13 +2508,11 @@ pub unsafe fn vceq_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vceqq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t { - simd_eq(a, b) +pub fn vceqq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t { + unsafe { simd_eq(a, b) } } #[doc = "Compare bitwise Equal (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -2745,13 +2529,11 @@ pub unsafe fn vceqq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vceq_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t { - simd_eq(a, b) +pub fn vceq_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t { + unsafe { simd_eq(a, b) } } #[doc = "Compare bitwise Equal (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -2768,13 +2550,11 @@ pub unsafe fn vceq_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vceqq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t { - simd_eq(a, b) +pub fn vceqq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t { + unsafe { simd_eq(a, b) } } #[doc = "Compare bitwise Equal (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -2791,13 +2571,11 @@ pub unsafe fn vceqq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vceq_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { - simd_eq(a, b) +pub fn vceq_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + unsafe { simd_eq(a, b) } } #[doc = "Compare bitwise Equal (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -2814,13 +2592,11 @@ pub unsafe fn vceq_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vceqq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { - simd_eq(a, b) +pub fn vceqq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + unsafe { simd_eq(a, b) } } #[doc = "Compare bitwise Equal (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -2837,13 +2613,11 @@ pub unsafe fn vceqq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vceq_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { - simd_eq(a, b) +pub fn vceq_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + unsafe { simd_eq(a, b) } } #[doc = "Compare bitwise Equal (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -2860,13 +2634,11 @@ pub unsafe fn vceq_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vceqq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { - simd_eq(a, b) +pub fn vceqq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + unsafe { simd_eq(a, b) } } #[doc = "Compare bitwise Equal (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -2883,13 +2655,11 @@ pub unsafe fn vceqq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vceq_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { - simd_eq(a, b) +pub fn vceq_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + unsafe { simd_eq(a, b) } } #[doc = "Compare bitwise Equal (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -2906,13 +2676,11 @@ pub unsafe fn vceq_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vceqq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { - simd_eq(a, b) +pub fn vceqq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + unsafe { simd_eq(a, b) } } #[doc = "Compare bitwise Equal (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -2929,13 +2697,11 @@ pub unsafe fn vceqq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vceq_p8(a: poly8x8_t, b: poly8x8_t) -> uint8x8_t { - simd_eq(a, b) +pub fn vceq_p8(a: poly8x8_t, b: poly8x8_t) -> uint8x8_t { + unsafe { simd_eq(a, b) } } #[doc = "Compare bitwise Equal (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -2952,13 +2718,11 @@ pub unsafe fn vceq_p8(a: poly8x8_t, b: poly8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vceqq_p8(a: poly8x16_t, b: poly8x16_t) -> uint8x16_t { - simd_eq(a, b) +pub fn vceqq_p8(a: poly8x16_t, b: poly8x16_t) -> uint8x16_t { + unsafe { simd_eq(a, b) } } #[doc = "Floating-point compare greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f16"))] @@ -2968,13 +2732,11 @@ pub unsafe fn vceqq_p8(a: poly8x16_t, b: poly8x16_t) -> uint8x16_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcge_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t { - simd_ge(a, b) +pub fn vcge_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t { + unsafe { simd_ge(a, b) } } #[doc = "Floating-point compare greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f16"))] @@ -2984,13 +2746,11 @@ pub unsafe fn vcge_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcgeq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t { - simd_ge(a, b) +pub fn vcgeq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t { + unsafe { simd_ge(a, b) } } #[doc = "Floating-point compare greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -3007,13 +2767,11 @@ pub unsafe fn vcgeq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcge_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t { - simd_ge(a, b) +pub fn vcge_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t { + unsafe { simd_ge(a, b) } } #[doc = "Floating-point compare greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -3030,13 +2788,11 @@ pub unsafe fn vcge_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcgeq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { - simd_ge(a, b) +pub fn vcgeq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { + unsafe { simd_ge(a, b) } } #[doc = "Compare signed greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -3053,13 +2809,11 @@ pub unsafe fn vcgeq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcge_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t { - simd_ge(a, b) +pub fn vcge_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t { + unsafe { simd_ge(a, b) } } #[doc = "Compare signed greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -3076,13 +2830,11 @@ pub unsafe fn vcge_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcgeq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t { - simd_ge(a, b) +pub fn vcgeq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t { + unsafe { simd_ge(a, b) } } #[doc = "Compare signed greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -3099,13 +2851,11 @@ pub unsafe fn vcgeq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcge_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t { - simd_ge(a, b) +pub fn vcge_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t { + unsafe { simd_ge(a, b) } } #[doc = "Compare signed greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -3122,13 +2872,11 @@ pub unsafe fn vcge_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcgeq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t { - simd_ge(a, b) +pub fn vcgeq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t { + unsafe { simd_ge(a, b) } } #[doc = "Compare signed greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -3145,13 +2893,11 @@ pub unsafe fn vcgeq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcge_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t { - simd_ge(a, b) +pub fn vcge_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t { + unsafe { simd_ge(a, b) } } #[doc = "Compare signed greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -3168,13 +2914,11 @@ pub unsafe fn vcge_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcgeq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t { - simd_ge(a, b) +pub fn vcgeq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t { + unsafe { simd_ge(a, b) } } #[doc = "Compare unsigned greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -3191,13 +2935,11 @@ pub unsafe fn vcgeq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcge_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { - simd_ge(a, b) +pub fn vcge_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + unsafe { simd_ge(a, b) } } #[doc = "Compare unsigned greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -3214,13 +2956,11 @@ pub unsafe fn vcge_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcgeq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { - simd_ge(a, b) +pub fn vcgeq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + unsafe { simd_ge(a, b) } } #[doc = "Compare unsigned greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -3237,13 +2977,11 @@ pub unsafe fn vcgeq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcge_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { - simd_ge(a, b) +pub fn vcge_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + unsafe { simd_ge(a, b) } } #[doc = "Compare unsigned greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -3260,13 +2998,11 @@ pub unsafe fn vcge_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcgeq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { - simd_ge(a, b) +pub fn vcgeq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + unsafe { simd_ge(a, b) } } #[doc = "Compare unsigned greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -3283,13 +3019,11 @@ pub unsafe fn vcgeq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcge_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { - simd_ge(a, b) +pub fn vcge_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + unsafe { simd_ge(a, b) } } #[doc = "Compare unsigned greater than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -3306,13 +3040,11 @@ pub unsafe fn vcge_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcgeq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { - simd_ge(a, b) +pub fn vcgeq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + unsafe { simd_ge(a, b) } } #[doc = "Floating-point compare greater than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgez_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f16"))] @@ -3322,14 +3054,12 @@ pub unsafe fn vcgeq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcgez_f16(a: float16x4_t) -> uint16x4_t { +pub fn vcgez_f16(a: float16x4_t) -> uint16x4_t { let b: f16x4 = f16x4::new(0.0, 0.0, 0.0, 0.0); - simd_ge(a, transmute(b)) + unsafe { simd_ge(a, transmute(b)) } } #[doc = "Floating-point compare greater than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezq_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f16"))] @@ -3339,14 +3069,12 @@ pub unsafe fn vcgez_f16(a: float16x4_t) -> uint16x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcgezq_f16(a: float16x8_t) -> uint16x8_t { +pub fn vcgezq_f16(a: float16x8_t) -> uint16x8_t { let b: f16x8 = f16x8::new(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0); - simd_ge(a, transmute(b)) + unsafe { simd_ge(a, transmute(b)) } } #[doc = "Floating-point compare greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f16"))] @@ -3356,13 +3084,11 @@ pub unsafe fn vcgezq_f16(a: float16x8_t) -> uint16x8_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcgt_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t { - simd_gt(a, b) +pub fn vcgt_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t { + unsafe { simd_gt(a, b) } } #[doc = "Floating-point compare greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f16"))] @@ -3372,13 +3098,11 @@ pub unsafe fn vcgt_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcgtq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t { - simd_gt(a, b) +pub fn vcgtq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t { + unsafe { simd_gt(a, b) } } #[doc = "Floating-point compare greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -3395,13 +3119,11 @@ pub unsafe fn vcgtq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcgt_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t { - simd_gt(a, b) +pub fn vcgt_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t { + unsafe { simd_gt(a, b) } } #[doc = "Floating-point compare greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -3418,13 +3140,11 @@ pub unsafe fn vcgt_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcgtq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { - simd_gt(a, b) +pub fn vcgtq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { + unsafe { simd_gt(a, b) } } #[doc = "Compare signed greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -3441,13 +3161,11 @@ pub unsafe fn vcgtq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcgt_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t { - simd_gt(a, b) +pub fn vcgt_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t { + unsafe { simd_gt(a, b) } } #[doc = "Compare signed greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -3464,13 +3182,11 @@ pub unsafe fn vcgt_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcgtq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t { - simd_gt(a, b) +pub fn vcgtq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t { + unsafe { simd_gt(a, b) } } #[doc = "Compare signed greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -3487,13 +3203,11 @@ pub unsafe fn vcgtq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcgt_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t { - simd_gt(a, b) +pub fn vcgt_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t { + unsafe { simd_gt(a, b) } } #[doc = "Compare signed greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -3510,13 +3224,11 @@ pub unsafe fn vcgt_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcgtq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t { - simd_gt(a, b) +pub fn vcgtq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t { + unsafe { simd_gt(a, b) } } #[doc = "Compare signed greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -3533,13 +3245,11 @@ pub unsafe fn vcgtq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcgt_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t { - simd_gt(a, b) +pub fn vcgt_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t { + unsafe { simd_gt(a, b) } } #[doc = "Compare signed greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -3556,13 +3266,11 @@ pub unsafe fn vcgt_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcgtq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t { - simd_gt(a, b) +pub fn vcgtq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t { + unsafe { simd_gt(a, b) } } #[doc = "Compare unsigned greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -3579,13 +3287,11 @@ pub unsafe fn vcgtq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcgt_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { - simd_gt(a, b) +pub fn vcgt_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + unsafe { simd_gt(a, b) } } #[doc = "Compare unsigned greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -3602,13 +3308,11 @@ pub unsafe fn vcgt_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcgtq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { - simd_gt(a, b) +pub fn vcgtq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + unsafe { simd_gt(a, b) } } #[doc = "Compare unsigned greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -3625,13 +3329,11 @@ pub unsafe fn vcgtq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcgt_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { - simd_gt(a, b) +pub fn vcgt_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + unsafe { simd_gt(a, b) } } #[doc = "Compare unsigned greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -3648,13 +3350,11 @@ pub unsafe fn vcgt_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcgtq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { - simd_gt(a, b) +pub fn vcgtq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + unsafe { simd_gt(a, b) } } #[doc = "Compare unsigned greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -3671,13 +3371,11 @@ pub unsafe fn vcgtq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcgt_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { - simd_gt(a, b) +pub fn vcgt_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + unsafe { simd_gt(a, b) } } #[doc = "Compare unsigned greater than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -3694,13 +3392,11 @@ pub unsafe fn vcgt_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcgtq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { - simd_gt(a, b) +pub fn vcgtq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + unsafe { simd_gt(a, b) } } #[doc = "Floating-point compare greater than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtz_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f16"))] @@ -3710,14 +3406,12 @@ pub unsafe fn vcgtq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcgtz_f16(a: float16x4_t) -> uint16x4_t { +pub fn vcgtz_f16(a: float16x4_t) -> uint16x4_t { let b: f16x4 = f16x4::new(0.0, 0.0, 0.0, 0.0); - simd_gt(a, transmute(b)) + unsafe { simd_gt(a, transmute(b)) } } #[doc = "Floating-point compare greater than zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzq_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f16"))] @@ -3727,14 +3421,12 @@ pub unsafe fn vcgtz_f16(a: float16x4_t) -> uint16x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcgtzq_f16(a: float16x8_t) -> uint16x8_t { +pub fn vcgtzq_f16(a: float16x8_t) -> uint16x8_t { let b: f16x8 = f16x8::new(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0); - simd_gt(a, transmute(b)) + unsafe { simd_gt(a, transmute(b)) } } #[doc = "Floating-point compare less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f16"))] @@ -3744,13 +3436,11 @@ pub unsafe fn vcgtzq_f16(a: float16x8_t) -> uint16x8_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcle_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t { - simd_le(a, b) +pub fn vcle_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t { + unsafe { simd_le(a, b) } } #[doc = "Floating-point compare less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f16"))] @@ -3760,13 +3450,11 @@ pub unsafe fn vcle_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcleq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t { - simd_le(a, b) +pub fn vcleq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t { + unsafe { simd_le(a, b) } } #[doc = "Floating-point compare less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -3783,13 +3471,11 @@ pub unsafe fn vcleq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcle_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t { - simd_le(a, b) +pub fn vcle_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t { + unsafe { simd_le(a, b) } } #[doc = "Floating-point compare less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -3806,13 +3492,11 @@ pub unsafe fn vcle_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcleq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { - simd_le(a, b) +pub fn vcleq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { + unsafe { simd_le(a, b) } } #[doc = "Compare signed less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -3829,13 +3513,11 @@ pub unsafe fn vcleq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcle_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t { - simd_le(a, b) +pub fn vcle_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t { + unsafe { simd_le(a, b) } } #[doc = "Compare signed less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -3852,13 +3534,11 @@ pub unsafe fn vcle_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcleq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t { - simd_le(a, b) +pub fn vcleq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t { + unsafe { simd_le(a, b) } } #[doc = "Compare signed less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -3875,13 +3555,11 @@ pub unsafe fn vcleq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcle_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t { - simd_le(a, b) +pub fn vcle_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t { + unsafe { simd_le(a, b) } } #[doc = "Compare signed less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -3898,13 +3576,11 @@ pub unsafe fn vcle_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcleq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t { - simd_le(a, b) +pub fn vcleq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t { + unsafe { simd_le(a, b) } } #[doc = "Compare signed less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -3921,13 +3597,11 @@ pub unsafe fn vcleq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcle_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t { - simd_le(a, b) +pub fn vcle_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t { + unsafe { simd_le(a, b) } } #[doc = "Compare signed less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -3944,13 +3618,11 @@ pub unsafe fn vcle_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcleq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t { - simd_le(a, b) +pub fn vcleq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t { + unsafe { simd_le(a, b) } } #[doc = "Compare unsigned less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -3967,13 +3639,11 @@ pub unsafe fn vcleq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcle_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { - simd_le(a, b) +pub fn vcle_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + unsafe { simd_le(a, b) } } #[doc = "Compare unsigned less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -3990,13 +3660,11 @@ pub unsafe fn vcle_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcleq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { - simd_le(a, b) +pub fn vcleq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + unsafe { simd_le(a, b) } } #[doc = "Compare unsigned less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -4013,13 +3681,11 @@ pub unsafe fn vcleq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcle_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { - simd_le(a, b) +pub fn vcle_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + unsafe { simd_le(a, b) } } #[doc = "Compare unsigned less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -4036,13 +3702,11 @@ pub unsafe fn vcle_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcleq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { - simd_le(a, b) +pub fn vcleq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + unsafe { simd_le(a, b) } } #[doc = "Compare unsigned less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -4059,13 +3723,11 @@ pub unsafe fn vcleq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcle_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { - simd_le(a, b) +pub fn vcle_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + unsafe { simd_le(a, b) } } #[doc = "Compare unsigned less than or equal"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -4082,13 +3744,11 @@ pub unsafe fn vcle_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcleq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { - simd_le(a, b) +pub fn vcleq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + unsafe { simd_le(a, b) } } #[doc = "Floating-point compare less than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclez_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcle.f16"))] @@ -4098,14 +3758,12 @@ pub unsafe fn vcleq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vclez_f16(a: float16x4_t) -> uint16x4_t { +pub fn vclez_f16(a: float16x4_t) -> uint16x4_t { let b: f16x4 = f16x4::new(0.0, 0.0, 0.0, 0.0); - simd_le(a, transmute(b)) + unsafe { simd_le(a, transmute(b)) } } #[doc = "Floating-point compare less than or equal to zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezq_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcle.f16"))] @@ -4115,14 +3773,12 @@ pub unsafe fn vclez_f16(a: float16x4_t) -> uint16x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vclezq_f16(a: float16x8_t) -> uint16x8_t { +pub fn vclezq_f16(a: float16x8_t) -> uint16x8_t { let b: f16x8 = f16x8::new(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0); - simd_le(a, transmute(b)) + unsafe { simd_le(a, transmute(b)) } } #[doc = "Count leading sign bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -4139,7 +3795,7 @@ pub unsafe fn vclezq_f16(a: float16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcls_s8(a: int8x8_t) -> int8x8_t { +pub fn vcls_s8(a: int8x8_t) -> int8x8_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vcls.v8i8")] #[cfg_attr( @@ -4148,12 +3804,10 @@ pub unsafe fn vcls_s8(a: int8x8_t) -> int8x8_t { )] fn _vcls_s8(a: int8x8_t) -> int8x8_t; } - _vcls_s8(a) + unsafe { _vcls_s8(a) } } #[doc = "Count leading sign bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -4170,7 +3824,7 @@ pub unsafe fn vcls_s8(a: int8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vclsq_s8(a: int8x16_t) -> int8x16_t { +pub fn vclsq_s8(a: int8x16_t) -> int8x16_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vcls.v16i8")] #[cfg_attr( @@ -4179,12 +3833,10 @@ pub unsafe fn vclsq_s8(a: int8x16_t) -> int8x16_t { )] fn _vclsq_s8(a: int8x16_t) -> int8x16_t; } - _vclsq_s8(a) + unsafe { _vclsq_s8(a) } } #[doc = "Count leading sign bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -4201,7 +3853,7 @@ pub unsafe fn vclsq_s8(a: int8x16_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcls_s16(a: int16x4_t) -> int16x4_t { +pub fn vcls_s16(a: int16x4_t) -> int16x4_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vcls.v4i16")] #[cfg_attr( @@ -4210,12 +3862,10 @@ pub unsafe fn vcls_s16(a: int16x4_t) -> int16x4_t { )] fn _vcls_s16(a: int16x4_t) -> int16x4_t; } - _vcls_s16(a) + unsafe { _vcls_s16(a) } } #[doc = "Count leading sign bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -4232,7 +3882,7 @@ pub unsafe fn vcls_s16(a: int16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vclsq_s16(a: int16x8_t) -> int16x8_t { +pub fn vclsq_s16(a: int16x8_t) -> int16x8_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vcls.v8i16")] #[cfg_attr( @@ -4241,12 +3891,10 @@ pub unsafe fn vclsq_s16(a: int16x8_t) -> int16x8_t { )] fn _vclsq_s16(a: int16x8_t) -> int16x8_t; } - _vclsq_s16(a) + unsafe { _vclsq_s16(a) } } #[doc = "Count leading sign bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -4263,7 +3911,7 @@ pub unsafe fn vclsq_s16(a: int16x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcls_s32(a: int32x2_t) -> int32x2_t { +pub fn vcls_s32(a: int32x2_t) -> int32x2_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vcls.v2i32")] #[cfg_attr( @@ -4272,12 +3920,10 @@ pub unsafe fn vcls_s32(a: int32x2_t) -> int32x2_t { )] fn _vcls_s32(a: int32x2_t) -> int32x2_t; } - _vcls_s32(a) + unsafe { _vcls_s32(a) } } #[doc = "Count leading sign bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -4294,7 +3940,7 @@ pub unsafe fn vcls_s32(a: int32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vclsq_s32(a: int32x4_t) -> int32x4_t { +pub fn vclsq_s32(a: int32x4_t) -> int32x4_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vcls.v4i32")] #[cfg_attr( @@ -4303,12 +3949,10 @@ pub unsafe fn vclsq_s32(a: int32x4_t) -> int32x4_t { )] fn _vclsq_s32(a: int32x4_t) -> int32x4_t; } - _vclsq_s32(a) + unsafe { _vclsq_s32(a) } } #[doc = "Count leading sign bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -4325,13 +3969,11 @@ pub unsafe fn vclsq_s32(a: int32x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcls_u8(a: uint8x8_t) -> int8x8_t { - vcls_s8(transmute(a)) +pub fn vcls_u8(a: uint8x8_t) -> int8x8_t { + unsafe { vcls_s8(transmute(a)) } } #[doc = "Count leading sign bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -4348,13 +3990,11 @@ pub unsafe fn vcls_u8(a: uint8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vclsq_u8(a: uint8x16_t) -> int8x16_t { - vclsq_s8(transmute(a)) +pub fn vclsq_u8(a: uint8x16_t) -> int8x16_t { + unsafe { vclsq_s8(transmute(a)) } } #[doc = "Count leading sign bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -4371,13 +4011,11 @@ pub unsafe fn vclsq_u8(a: uint8x16_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcls_u16(a: uint16x4_t) -> int16x4_t { - vcls_s16(transmute(a)) +pub fn vcls_u16(a: uint16x4_t) -> int16x4_t { + unsafe { vcls_s16(transmute(a)) } } #[doc = "Count leading sign bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -4394,13 +4032,11 @@ pub unsafe fn vcls_u16(a: uint16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vclsq_u16(a: uint16x8_t) -> int16x8_t { - vclsq_s16(transmute(a)) +pub fn vclsq_u16(a: uint16x8_t) -> int16x8_t { + unsafe { vclsq_s16(transmute(a)) } } #[doc = "Count leading sign bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -4417,13 +4053,11 @@ pub unsafe fn vclsq_u16(a: uint16x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcls_u32(a: uint32x2_t) -> int32x2_t { - vcls_s32(transmute(a)) +pub fn vcls_u32(a: uint32x2_t) -> int32x2_t { + unsafe { vcls_s32(transmute(a)) } } #[doc = "Count leading sign bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -4440,13 +4074,11 @@ pub unsafe fn vcls_u32(a: uint32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vclsq_u32(a: uint32x4_t) -> int32x4_t { - vclsq_s32(transmute(a)) +pub fn vclsq_u32(a: uint32x4_t) -> int32x4_t { + unsafe { vclsq_s32(transmute(a)) } } #[doc = "Floating-point compare less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f16"))] @@ -4456,13 +4088,11 @@ pub unsafe fn vclsq_u32(a: uint32x4_t) -> int32x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vclt_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t { - simd_lt(a, b) +pub fn vclt_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t { + unsafe { simd_lt(a, b) } } #[doc = "Floating-point compare less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f16"))] @@ -4472,13 +4102,11 @@ pub unsafe fn vclt_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcltq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t { - simd_lt(a, b) +pub fn vcltq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t { + unsafe { simd_lt(a, b) } } #[doc = "Floating-point compare less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -4495,13 +4123,11 @@ pub unsafe fn vcltq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vclt_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t { - simd_lt(a, b) +pub fn vclt_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t { + unsafe { simd_lt(a, b) } } #[doc = "Floating-point compare less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -4518,13 +4144,11 @@ pub unsafe fn vclt_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcltq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { - simd_lt(a, b) +pub fn vcltq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { + unsafe { simd_lt(a, b) } } #[doc = "Compare signed less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -4541,13 +4165,11 @@ pub unsafe fn vcltq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vclt_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t { - simd_lt(a, b) +pub fn vclt_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t { + unsafe { simd_lt(a, b) } } #[doc = "Compare signed less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -4564,13 +4186,11 @@ pub unsafe fn vclt_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcltq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t { - simd_lt(a, b) +pub fn vcltq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t { + unsafe { simd_lt(a, b) } } #[doc = "Compare signed less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -4587,13 +4207,11 @@ pub unsafe fn vcltq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vclt_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t { - simd_lt(a, b) +pub fn vclt_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t { + unsafe { simd_lt(a, b) } } #[doc = "Compare signed less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -4610,13 +4228,11 @@ pub unsafe fn vclt_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcltq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t { - simd_lt(a, b) +pub fn vcltq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t { + unsafe { simd_lt(a, b) } } #[doc = "Compare signed less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -4633,13 +4249,11 @@ pub unsafe fn vcltq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vclt_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t { - simd_lt(a, b) +pub fn vclt_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t { + unsafe { simd_lt(a, b) } } #[doc = "Compare signed less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -4656,13 +4270,11 @@ pub unsafe fn vclt_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcltq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t { - simd_lt(a, b) +pub fn vcltq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t { + unsafe { simd_lt(a, b) } } #[doc = "Compare unsigned less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -4679,13 +4291,11 @@ pub unsafe fn vcltq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vclt_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { - simd_lt(a, b) +pub fn vclt_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + unsafe { simd_lt(a, b) } } #[doc = "Compare unsigned less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -4702,13 +4312,11 @@ pub unsafe fn vclt_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcltq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { - simd_lt(a, b) +pub fn vcltq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + unsafe { simd_lt(a, b) } } #[doc = "Compare unsigned less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -4725,13 +4333,11 @@ pub unsafe fn vcltq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vclt_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { - simd_lt(a, b) +pub fn vclt_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + unsafe { simd_lt(a, b) } } #[doc = "Compare unsigned less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -4748,13 +4354,11 @@ pub unsafe fn vclt_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcltq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { - simd_lt(a, b) +pub fn vcltq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + unsafe { simd_lt(a, b) } } #[doc = "Compare unsigned less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -4771,13 +4375,11 @@ pub unsafe fn vcltq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vclt_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { - simd_lt(a, b) +pub fn vclt_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + unsafe { simd_lt(a, b) } } #[doc = "Compare unsigned less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -4794,13 +4396,11 @@ pub unsafe fn vclt_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcltq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { - simd_lt(a, b) +pub fn vcltq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + unsafe { simd_lt(a, b) } } #[doc = "Floating-point compare less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltz_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclt.f16"))] @@ -4810,14 +4410,12 @@ pub unsafe fn vcltq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcltz_f16(a: float16x4_t) -> uint16x4_t { +pub fn vcltz_f16(a: float16x4_t) -> uint16x4_t { let b: f16x4 = f16x4::new(0.0, 0.0, 0.0, 0.0); - simd_lt(a, transmute(b)) + unsafe { simd_lt(a, transmute(b)) } } #[doc = "Floating-point compare less than"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzq_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclt.f16"))] @@ -4827,14 +4425,12 @@ pub unsafe fn vcltz_f16(a: float16x4_t) -> uint16x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcltzq_f16(a: float16x8_t) -> uint16x8_t { +pub fn vcltzq_f16(a: float16x8_t) -> uint16x8_t { let b: f16x8 = f16x8::new(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0); - simd_lt(a, transmute(b)) + unsafe { simd_lt(a, transmute(b)) } } #[doc = "Count leading zero bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -4851,7 +4447,7 @@ pub unsafe fn vcltzq_f16(a: float16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vclz_s8(a: int8x8_t) -> int8x8_t { +pub fn vclz_s8(a: int8x8_t) -> int8x8_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.ctlz.v8i8")] #[cfg_attr( @@ -4860,12 +4456,10 @@ pub unsafe fn vclz_s8(a: int8x8_t) -> int8x8_t { )] fn _vclz_s8(a: int8x8_t) -> int8x8_t; } - _vclz_s8(a) + unsafe { _vclz_s8(a) } } #[doc = "Count leading zero bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -4882,7 +4476,7 @@ pub unsafe fn vclz_s8(a: int8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vclzq_s8(a: int8x16_t) -> int8x16_t { +pub fn vclzq_s8(a: int8x16_t) -> int8x16_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.ctlz.v16i8")] #[cfg_attr( @@ -4891,12 +4485,10 @@ pub unsafe fn vclzq_s8(a: int8x16_t) -> int8x16_t { )] fn _vclzq_s8(a: int8x16_t) -> int8x16_t; } - _vclzq_s8(a) + unsafe { _vclzq_s8(a) } } #[doc = "Count leading zero bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -4913,7 +4505,7 @@ pub unsafe fn vclzq_s8(a: int8x16_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vclz_s16(a: int16x4_t) -> int16x4_t { +pub fn vclz_s16(a: int16x4_t) -> int16x4_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.ctlz.v4i16")] #[cfg_attr( @@ -4922,12 +4514,10 @@ pub unsafe fn vclz_s16(a: int16x4_t) -> int16x4_t { )] fn _vclz_s16(a: int16x4_t) -> int16x4_t; } - _vclz_s16(a) + unsafe { _vclz_s16(a) } } #[doc = "Count leading zero bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -4944,7 +4534,7 @@ pub unsafe fn vclz_s16(a: int16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vclzq_s16(a: int16x8_t) -> int16x8_t { +pub fn vclzq_s16(a: int16x8_t) -> int16x8_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.ctlz.v8i16")] #[cfg_attr( @@ -4953,12 +4543,10 @@ pub unsafe fn vclzq_s16(a: int16x8_t) -> int16x8_t { )] fn _vclzq_s16(a: int16x8_t) -> int16x8_t; } - _vclzq_s16(a) + unsafe { _vclzq_s16(a) } } #[doc = "Count leading zero bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -4975,7 +4563,7 @@ pub unsafe fn vclzq_s16(a: int16x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vclz_s32(a: int32x2_t) -> int32x2_t { +pub fn vclz_s32(a: int32x2_t) -> int32x2_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.ctlz.v2i32")] #[cfg_attr( @@ -4984,12 +4572,10 @@ pub unsafe fn vclz_s32(a: int32x2_t) -> int32x2_t { )] fn _vclz_s32(a: int32x2_t) -> int32x2_t; } - _vclz_s32(a) + unsafe { _vclz_s32(a) } } #[doc = "Count leading zero bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -5006,7 +4592,7 @@ pub unsafe fn vclz_s32(a: int32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vclzq_s32(a: int32x4_t) -> int32x4_t { +pub fn vclzq_s32(a: int32x4_t) -> int32x4_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.ctlz.v4i32")] #[cfg_attr( @@ -5015,12 +4601,10 @@ pub unsafe fn vclzq_s32(a: int32x4_t) -> int32x4_t { )] fn _vclzq_s32(a: int32x4_t) -> int32x4_t; } - _vclzq_s32(a) + unsafe { _vclzq_s32(a) } } #[doc = "Count leading zero bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -5038,13 +4622,11 @@ pub unsafe fn vclzq_s32(a: int32x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vclz_u16(a: uint16x4_t) -> uint16x4_t { - transmute(vclz_s16(transmute(a))) +pub fn vclz_u16(a: uint16x4_t) -> uint16x4_t { + unsafe { transmute(vclz_s16(transmute(a))) } } #[doc = "Count leading zero bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -5062,15 +4644,15 @@ pub unsafe fn vclz_u16(a: uint16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vclz_u16(a: uint16x4_t) -> uint16x4_t { +pub fn vclz_u16(a: uint16x4_t) -> uint16x4_t { let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - let ret_val: uint16x4_t = transmute(vclz_s16(transmute(a))); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + unsafe { + let ret_val: uint16x4_t = transmute(vclz_s16(transmute(a))); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Count leading zero bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -5088,13 +4670,11 @@ pub unsafe fn vclz_u16(a: uint16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vclzq_u16(a: uint16x8_t) -> uint16x8_t { - transmute(vclzq_s16(transmute(a))) +pub fn vclzq_u16(a: uint16x8_t) -> uint16x8_t { + unsafe { transmute(vclzq_s16(transmute(a))) } } #[doc = "Count leading zero bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -5112,15 +4692,15 @@ pub unsafe fn vclzq_u16(a: uint16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vclzq_u16(a: uint16x8_t) -> uint16x8_t { +pub fn vclzq_u16(a: uint16x8_t) -> uint16x8_t { let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: uint16x8_t = transmute(vclzq_s16(transmute(a))); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: uint16x8_t = transmute(vclzq_s16(transmute(a))); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Count leading zero bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -5138,13 +4718,11 @@ pub unsafe fn vclzq_u16(a: uint16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vclz_u32(a: uint32x2_t) -> uint32x2_t { - transmute(vclz_s32(transmute(a))) +pub fn vclz_u32(a: uint32x2_t) -> uint32x2_t { + unsafe { transmute(vclz_s32(transmute(a))) } } #[doc = "Count leading zero bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -5162,15 +4740,15 @@ pub unsafe fn vclz_u32(a: uint32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vclz_u32(a: uint32x2_t) -> uint32x2_t { +pub fn vclz_u32(a: uint32x2_t) -> uint32x2_t { let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]); - let ret_val: uint32x2_t = transmute(vclz_s32(transmute(a))); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: uint32x2_t = transmute(vclz_s32(transmute(a))); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Count leading zero bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -5188,13 +4766,11 @@ pub unsafe fn vclz_u32(a: uint32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vclzq_u32(a: uint32x4_t) -> uint32x4_t { - transmute(vclzq_s32(transmute(a))) +pub fn vclzq_u32(a: uint32x4_t) -> uint32x4_t { + unsafe { transmute(vclzq_s32(transmute(a))) } } #[doc = "Count leading zero bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -5212,15 +4788,15 @@ pub unsafe fn vclzq_u32(a: uint32x4_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vclzq_u32(a: uint32x4_t) -> uint32x4_t { +pub fn vclzq_u32(a: uint32x4_t) -> uint32x4_t { let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - let ret_val: uint32x4_t = transmute(vclzq_s32(transmute(a))); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + unsafe { + let ret_val: uint32x4_t = transmute(vclzq_s32(transmute(a))); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Count leading zero bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -5238,13 +4814,11 @@ pub unsafe fn vclzq_u32(a: uint32x4_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vclz_u8(a: uint8x8_t) -> uint8x8_t { - transmute(vclz_s8(transmute(a))) +pub fn vclz_u8(a: uint8x8_t) -> uint8x8_t { + unsafe { transmute(vclz_s8(transmute(a))) } } #[doc = "Count leading zero bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -5262,15 +4836,15 @@ pub unsafe fn vclz_u8(a: uint8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vclz_u8(a: uint8x8_t) -> uint8x8_t { +pub fn vclz_u8(a: uint8x8_t) -> uint8x8_t { let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: uint8x8_t = transmute(vclz_s8(transmute(a))); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: uint8x8_t = transmute(vclz_s8(transmute(a))); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Count leading zero bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -5288,13 +4862,11 @@ pub unsafe fn vclz_u8(a: uint8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vclzq_u8(a: uint8x16_t) -> uint8x16_t { - transmute(vclzq_s8(transmute(a))) +pub fn vclzq_u8(a: uint8x16_t) -> uint8x16_t { + unsafe { transmute(vclzq_s8(transmute(a))) } } #[doc = "Count leading zero bits"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -5312,19 +4884,19 @@ pub unsafe fn vclzq_u8(a: uint8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vclzq_u8(a: uint8x16_t) -> uint8x16_t { +pub fn vclzq_u8(a: uint8x16_t) -> uint8x16_t { let a: uint8x16_t = simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: uint8x16_t = transmute(vclzq_s8(transmute(a))); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) + unsafe { + let ret_val: uint8x16_t = transmute(vclzq_s8(transmute(a))); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } #[doc = "Population count per byte."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcnt_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -5341,7 +4913,7 @@ pub unsafe fn vclzq_u8(a: uint8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcnt_s8(a: int8x8_t) -> int8x8_t { +pub fn vcnt_s8(a: int8x8_t) -> int8x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -5350,12 +4922,10 @@ pub unsafe fn vcnt_s8(a: int8x8_t) -> int8x8_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.ctpop.v8i8")] fn _vcnt_s8(a: int8x8_t) -> int8x8_t; } - _vcnt_s8(a) + unsafe { _vcnt_s8(a) } } #[doc = "Population count per byte."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcntq_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -5372,7 +4942,7 @@ pub unsafe fn vcnt_s8(a: int8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcntq_s8(a: int8x16_t) -> int8x16_t { +pub fn vcntq_s8(a: int8x16_t) -> int8x16_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -5381,12 +4951,10 @@ pub unsafe fn vcntq_s8(a: int8x16_t) -> int8x16_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.ctpop.v16i8")] fn _vcntq_s8(a: int8x16_t) -> int8x16_t; } - _vcntq_s8(a) + unsafe { _vcntq_s8(a) } } #[doc = "Population count per byte."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcnt_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -5404,13 +4972,11 @@ pub unsafe fn vcntq_s8(a: int8x16_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcnt_u8(a: uint8x8_t) -> uint8x8_t { - transmute(vcnt_s8(transmute(a))) +pub fn vcnt_u8(a: uint8x8_t) -> uint8x8_t { + unsafe { transmute(vcnt_s8(transmute(a))) } } #[doc = "Population count per byte."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcnt_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -5428,15 +4994,15 @@ pub unsafe fn vcnt_u8(a: uint8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcnt_u8(a: uint8x8_t) -> uint8x8_t { +pub fn vcnt_u8(a: uint8x8_t) -> uint8x8_t { let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: uint8x8_t = transmute(vcnt_s8(transmute(a))); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: uint8x8_t = transmute(vcnt_s8(transmute(a))); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Population count per byte."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcntq_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -5454,13 +5020,11 @@ pub unsafe fn vcnt_u8(a: uint8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcntq_u8(a: uint8x16_t) -> uint8x16_t { - transmute(vcntq_s8(transmute(a))) +pub fn vcntq_u8(a: uint8x16_t) -> uint8x16_t { + unsafe { transmute(vcntq_s8(transmute(a))) } } #[doc = "Population count per byte."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcntq_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -5478,19 +5042,19 @@ pub unsafe fn vcntq_u8(a: uint8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcntq_u8(a: uint8x16_t) -> uint8x16_t { +pub fn vcntq_u8(a: uint8x16_t) -> uint8x16_t { let a: uint8x16_t = simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: uint8x16_t = transmute(vcntq_s8(transmute(a))); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) + unsafe { + let ret_val: uint8x16_t = transmute(vcntq_s8(transmute(a))); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } #[doc = "Population count per byte."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcnt_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -5508,13 +5072,11 @@ pub unsafe fn vcntq_u8(a: uint8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcnt_p8(a: poly8x8_t) -> poly8x8_t { - transmute(vcnt_s8(transmute(a))) +pub fn vcnt_p8(a: poly8x8_t) -> poly8x8_t { + unsafe { transmute(vcnt_s8(transmute(a))) } } #[doc = "Population count per byte."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcnt_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -5532,15 +5094,15 @@ pub unsafe fn vcnt_p8(a: poly8x8_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcnt_p8(a: poly8x8_t) -> poly8x8_t { +pub fn vcnt_p8(a: poly8x8_t) -> poly8x8_t { let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: poly8x8_t = transmute(vcnt_s8(transmute(a))); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: poly8x8_t = transmute(vcnt_s8(transmute(a))); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Population count per byte."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcntq_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -5558,13 +5120,11 @@ pub unsafe fn vcnt_p8(a: poly8x8_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcntq_p8(a: poly8x16_t) -> poly8x16_t { - transmute(vcntq_s8(transmute(a))) +pub fn vcntq_p8(a: poly8x16_t) -> poly8x16_t { + unsafe { transmute(vcntq_s8(transmute(a))) } } #[doc = "Population count per byte."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcntq_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -5582,31 +5142,29 @@ pub unsafe fn vcntq_p8(a: poly8x16_t) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcntq_p8(a: poly8x16_t) -> poly8x16_t { +pub fn vcntq_p8(a: poly8x16_t) -> poly8x16_t { let a: poly8x16_t = simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: poly8x16_t = transmute(vcntq_s8(transmute(a))); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) + unsafe { + let ret_val: poly8x16_t = transmute(vcntq_s8(transmute(a))); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } #[doc = "Join two smaller vectors into a single larger vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vcombine_f16(a: float16x4_t, b: float16x4_t) -> float16x8_t { - simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]) +pub fn vcombine_f16(a: float16x4_t, b: float16x4_t) -> float16x8_t { + unsafe { simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]) } } #[doc = "Join two smaller vectors into a single larger vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -5619,13 +5177,11 @@ pub unsafe fn vcombine_f16(a: float16x4_t, b: float16x4_t) -> float16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcombine_f32(a: float32x2_t, b: float32x2_t) -> float32x4_t { - simd_shuffle!(a, b, [0, 1, 2, 3]) +pub fn vcombine_f32(a: float32x2_t, b: float32x2_t) -> float32x4_t { + unsafe { simd_shuffle!(a, b, [0, 1, 2, 3]) } } #[doc = "Join two smaller vectors into a single larger vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -5638,13 +5194,11 @@ pub unsafe fn vcombine_f32(a: float32x2_t, b: float32x2_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcombine_s8(a: int8x8_t, b: int8x8_t) -> int8x16_t { - simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) +pub fn vcombine_s8(a: int8x8_t, b: int8x8_t) -> int8x16_t { + unsafe { simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) } } #[doc = "Join two smaller vectors into a single larger vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -5657,13 +5211,11 @@ pub unsafe fn vcombine_s8(a: int8x8_t, b: int8x8_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcombine_s16(a: int16x4_t, b: int16x4_t) -> int16x8_t { - simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]) +pub fn vcombine_s16(a: int16x4_t, b: int16x4_t) -> int16x8_t { + unsafe { simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]) } } #[doc = "Join two smaller vectors into a single larger vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -5676,13 +5228,11 @@ pub unsafe fn vcombine_s16(a: int16x4_t, b: int16x4_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcombine_s32(a: int32x2_t, b: int32x2_t) -> int32x4_t { - simd_shuffle!(a, b, [0, 1, 2, 3]) +pub fn vcombine_s32(a: int32x2_t, b: int32x2_t) -> int32x4_t { + unsafe { simd_shuffle!(a, b, [0, 1, 2, 3]) } } #[doc = "Join two smaller vectors into a single larger vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -5695,13 +5245,11 @@ pub unsafe fn vcombine_s32(a: int32x2_t, b: int32x2_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcombine_s64(a: int64x1_t, b: int64x1_t) -> int64x2_t { - simd_shuffle!(a, b, [0, 1]) +pub fn vcombine_s64(a: int64x1_t, b: int64x1_t) -> int64x2_t { + unsafe { simd_shuffle!(a, b, [0, 1]) } } #[doc = "Join two smaller vectors into a single larger vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -5714,13 +5262,11 @@ pub unsafe fn vcombine_s64(a: int64x1_t, b: int64x1_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcombine_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x16_t { - simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) +pub fn vcombine_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x16_t { + unsafe { simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) } } #[doc = "Join two smaller vectors into a single larger vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -5733,13 +5279,11 @@ pub unsafe fn vcombine_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcombine_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x8_t { - simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]) +pub fn vcombine_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x8_t { + unsafe { simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]) } } #[doc = "Join two smaller vectors into a single larger vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -5752,13 +5296,11 @@ pub unsafe fn vcombine_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcombine_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x4_t { - simd_shuffle!(a, b, [0, 1, 2, 3]) +pub fn vcombine_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x4_t { + unsafe { simd_shuffle!(a, b, [0, 1, 2, 3]) } } #[doc = "Join two smaller vectors into a single larger vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -5771,13 +5313,11 @@ pub unsafe fn vcombine_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcombine_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x2_t { - simd_shuffle!(a, b, [0, 1]) +pub fn vcombine_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x2_t { + unsafe { simd_shuffle!(a, b, [0, 1]) } } #[doc = "Join two smaller vectors into a single larger vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -5790,13 +5330,11 @@ pub unsafe fn vcombine_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcombine_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x16_t { - simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) +pub fn vcombine_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x16_t { + unsafe { simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) } } #[doc = "Join two smaller vectors into a single larger vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -5809,13 +5347,11 @@ pub unsafe fn vcombine_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcombine_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x8_t { - simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]) +pub fn vcombine_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x8_t { + unsafe { simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]) } } #[doc = "Join two smaller vectors into a single larger vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -5828,13 +5364,11 @@ pub unsafe fn vcombine_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcombine_p64(a: poly64x1_t, b: poly64x1_t) -> poly64x2_t { - simd_shuffle!(a, b, [0, 1]) +pub fn vcombine_p64(a: poly64x1_t, b: poly64x1_t) -> poly64x2_t { + unsafe { simd_shuffle!(a, b, [0, 1]) } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -5845,13 +5379,11 @@ pub unsafe fn vcombine_p64(a: poly64x1_t, b: poly64x1_t) -> poly64x2_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcreate_f16(a: u64) -> float16x4_t { - transmute(a) +pub fn vcreate_f16(a: u64) -> float16x4_t { + unsafe { transmute(a) } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -5862,14 +5394,14 @@ pub unsafe fn vcreate_f16(a: u64) -> float16x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcreate_f16(a: u64) -> float16x4_t { - let ret_val: float16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) +pub fn vcreate_f16(a: u64) -> float16x4_t { + unsafe { + let ret_val: float16x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -5887,13 +5419,11 @@ pub unsafe fn vcreate_f16(a: u64) -> float16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcreate_f32(a: u64) -> float32x2_t { - transmute(a) +pub fn vcreate_f32(a: u64) -> float32x2_t { + unsafe { transmute(a) } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -5911,14 +5441,14 @@ pub unsafe fn vcreate_f32(a: u64) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcreate_f32(a: u64) -> float32x2_t { - let ret_val: float32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) +pub fn vcreate_f32(a: u64) -> float32x2_t { + unsafe { + let ret_val: float32x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -5936,13 +5466,11 @@ pub unsafe fn vcreate_f32(a: u64) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcreate_s8(a: u64) -> int8x8_t { - transmute(a) +pub fn vcreate_s8(a: u64) -> int8x8_t { + unsafe { transmute(a) } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -5960,14 +5488,14 @@ pub unsafe fn vcreate_s8(a: u64) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcreate_s8(a: u64) -> int8x8_t { - let ret_val: int8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) +pub fn vcreate_s8(a: u64) -> int8x8_t { + unsafe { + let ret_val: int8x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -5985,13 +5513,11 @@ pub unsafe fn vcreate_s8(a: u64) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcreate_s16(a: u64) -> int16x4_t { - transmute(a) +pub fn vcreate_s16(a: u64) -> int16x4_t { + unsafe { transmute(a) } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -6009,14 +5535,14 @@ pub unsafe fn vcreate_s16(a: u64) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcreate_s16(a: u64) -> int16x4_t { - let ret_val: int16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) +pub fn vcreate_s16(a: u64) -> int16x4_t { + unsafe { + let ret_val: int16x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -6034,13 +5560,11 @@ pub unsafe fn vcreate_s16(a: u64) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcreate_s32(a: u64) -> int32x2_t { - transmute(a) +pub fn vcreate_s32(a: u64) -> int32x2_t { + unsafe { transmute(a) } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -6058,14 +5582,14 @@ pub unsafe fn vcreate_s32(a: u64) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcreate_s32(a: u64) -> int32x2_t { - let ret_val: int32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) +pub fn vcreate_s32(a: u64) -> int32x2_t { + unsafe { + let ret_val: int32x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -6082,13 +5606,11 @@ pub unsafe fn vcreate_s32(a: u64) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcreate_s64(a: u64) -> int64x1_t { - transmute(a) +pub fn vcreate_s64(a: u64) -> int64x1_t { + unsafe { transmute(a) } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -6106,13 +5628,11 @@ pub unsafe fn vcreate_s64(a: u64) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcreate_u8(a: u64) -> uint8x8_t { - transmute(a) +pub fn vcreate_u8(a: u64) -> uint8x8_t { + unsafe { transmute(a) } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -6130,14 +5650,14 @@ pub unsafe fn vcreate_u8(a: u64) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcreate_u8(a: u64) -> uint8x8_t { - let ret_val: uint8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) +pub fn vcreate_u8(a: u64) -> uint8x8_t { + unsafe { + let ret_val: uint8x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -6155,13 +5675,11 @@ pub unsafe fn vcreate_u8(a: u64) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcreate_u16(a: u64) -> uint16x4_t { - transmute(a) +pub fn vcreate_u16(a: u64) -> uint16x4_t { + unsafe { transmute(a) } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -6179,14 +5697,14 @@ pub unsafe fn vcreate_u16(a: u64) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcreate_u16(a: u64) -> uint16x4_t { - let ret_val: uint16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) +pub fn vcreate_u16(a: u64) -> uint16x4_t { + unsafe { + let ret_val: uint16x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -6204,13 +5722,11 @@ pub unsafe fn vcreate_u16(a: u64) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcreate_u32(a: u64) -> uint32x2_t { - transmute(a) +pub fn vcreate_u32(a: u64) -> uint32x2_t { + unsafe { transmute(a) } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -6228,14 +5744,14 @@ pub unsafe fn vcreate_u32(a: u64) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcreate_u32(a: u64) -> uint32x2_t { - let ret_val: uint32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) +pub fn vcreate_u32(a: u64) -> uint32x2_t { + unsafe { + let ret_val: uint32x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -6252,13 +5768,11 @@ pub unsafe fn vcreate_u32(a: u64) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcreate_u64(a: u64) -> uint64x1_t { - transmute(a) +pub fn vcreate_u64(a: u64) -> uint64x1_t { + unsafe { transmute(a) } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -6276,13 +5790,11 @@ pub unsafe fn vcreate_u64(a: u64) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcreate_p8(a: u64) -> poly8x8_t { - transmute(a) +pub fn vcreate_p8(a: u64) -> poly8x8_t { + unsafe { transmute(a) } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -6300,14 +5812,14 @@ pub unsafe fn vcreate_p8(a: u64) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcreate_p8(a: u64) -> poly8x8_t { - let ret_val: poly8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) +pub fn vcreate_p8(a: u64) -> poly8x8_t { + unsafe { + let ret_val: poly8x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -6325,13 +5837,11 @@ pub unsafe fn vcreate_p8(a: u64) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcreate_p16(a: u64) -> poly16x4_t { - transmute(a) +pub fn vcreate_p16(a: u64) -> poly16x4_t { + unsafe { transmute(a) } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -6349,14 +5859,14 @@ pub unsafe fn vcreate_p16(a: u64) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcreate_p16(a: u64) -> poly16x4_t { - let ret_val: poly16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) +pub fn vcreate_p16(a: u64) -> poly16x4_t { + unsafe { + let ret_val: poly16x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] @@ -6373,13 +5883,11 @@ pub unsafe fn vcreate_p16(a: u64) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcreate_p64(a: u64) -> poly64x1_t { - transmute(a) +pub fn vcreate_p64(a: u64) -> poly64x1_t { + unsafe { transmute(a) } } #[doc = "Floating-point convert to lower precision narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f16_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] # [cfg_attr (all (test , target_arch = "arm") , assert_instr (vcvt . f16 . f32))] @@ -6389,13 +5897,11 @@ pub unsafe fn vcreate_p64(a: u64) -> poly64x1_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvt_f16_f32(a: float32x4_t) -> float16x4_t { - simd_cast(a) +pub fn vcvt_f16_f32(a: float32x4_t) -> float16x4_t { + unsafe { simd_cast(a) } } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f16_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))] @@ -6405,13 +5911,11 @@ pub unsafe fn vcvt_f16_f32(a: float32x4_t) -> float16x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvt_f16_s16(a: int16x4_t) -> float16x4_t { - simd_cast(a) +pub fn vcvt_f16_s16(a: int16x4_t) -> float16x4_t { + unsafe { simd_cast(a) } } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_f16_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))] @@ -6421,13 +5925,11 @@ pub unsafe fn vcvt_f16_s16(a: int16x4_t) -> float16x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvtq_f16_s16(a: int16x8_t) -> float16x8_t { - simd_cast(a) +pub fn vcvtq_f16_s16(a: int16x8_t) -> float16x8_t { + unsafe { simd_cast(a) } } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f16_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))] @@ -6437,13 +5939,11 @@ pub unsafe fn vcvtq_f16_s16(a: int16x8_t) -> float16x8_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvt_f16_u16(a: uint16x4_t) -> float16x4_t { - simd_cast(a) +pub fn vcvt_f16_u16(a: uint16x4_t) -> float16x4_t { + unsafe { simd_cast(a) } } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_f16_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))] @@ -6453,13 +5953,11 @@ pub unsafe fn vcvt_f16_u16(a: uint16x4_t) -> float16x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvtq_f16_u16(a: uint16x8_t) -> float16x8_t { - simd_cast(a) +pub fn vcvtq_f16_u16(a: uint16x8_t) -> float16x8_t { + unsafe { simd_cast(a) } } #[doc = "Floating-point convert to higher precision long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f32_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))] @@ -6469,13 +5967,11 @@ pub unsafe fn vcvtq_f16_u16(a: uint16x8_t) -> float16x8_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvt_f32_f16(a: float16x4_t) -> float32x4_t { - simd_cast(a) +pub fn vcvt_f32_f16(a: float16x4_t) -> float32x4_t { + unsafe { simd_cast(a) } } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f32_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -6492,13 +5988,11 @@ pub unsafe fn vcvt_f32_f16(a: float16x4_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcvt_f32_s32(a: int32x2_t) -> float32x2_t { - simd_cast(a) +pub fn vcvt_f32_s32(a: int32x2_t) -> float32x2_t { + unsafe { simd_cast(a) } } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_f32_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -6515,13 +6009,11 @@ pub unsafe fn vcvt_f32_s32(a: int32x2_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcvtq_f32_s32(a: int32x4_t) -> float32x4_t { - simd_cast(a) +pub fn vcvtq_f32_s32(a: int32x4_t) -> float32x4_t { + unsafe { simd_cast(a) } } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f32_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -6538,13 +6030,11 @@ pub unsafe fn vcvtq_f32_s32(a: int32x4_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcvt_f32_u32(a: uint32x2_t) -> float32x2_t { - simd_cast(a) +pub fn vcvt_f32_u32(a: uint32x2_t) -> float32x2_t { + unsafe { simd_cast(a) } } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_f32_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -6561,13 +6051,11 @@ pub unsafe fn vcvt_f32_u32(a: uint32x2_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcvtq_f32_u32(a: uint32x4_t) -> float32x4_t { - simd_cast(a) +pub fn vcvtq_f32_u32(a: uint32x4_t) -> float32x4_t { + unsafe { simd_cast(a) } } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f16_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))] @@ -6578,7 +6066,7 @@ pub unsafe fn vcvtq_f32_u32(a: uint32x4_t) -> float32x4_t { #[rustc_legacy_const_generics(1)] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvt_n_f16_s16(a: int16x4_t) -> float16x4_t { +pub fn vcvt_n_f16_s16(a: int16x4_t) -> float16x4_t { static_assert!(N >= 1 && N <= 16); unsafe extern "unadjusted" { #[cfg_attr( @@ -6591,12 +6079,10 @@ pub unsafe fn vcvt_n_f16_s16(a: int16x4_t) -> float16x4_t { )] fn _vcvt_n_f16_s16(a: int16x4_t, n: i32) -> float16x4_t; } - _vcvt_n_f16_s16(a, N) + unsafe { _vcvt_n_f16_s16(a, N) } } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f16_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))] @@ -6607,7 +6093,7 @@ pub unsafe fn vcvt_n_f16_s16(a: int16x4_t) -> float16x4_t { #[rustc_legacy_const_generics(1)] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvtq_n_f16_s16(a: int16x8_t) -> float16x8_t { +pub fn vcvtq_n_f16_s16(a: int16x8_t) -> float16x8_t { static_assert!(N >= 1 && N <= 16); unsafe extern "unadjusted" { #[cfg_attr( @@ -6620,12 +6106,10 @@ pub unsafe fn vcvtq_n_f16_s16(a: int16x8_t) -> float16x8_t { )] fn _vcvtq_n_f16_s16(a: int16x8_t, n: i32) -> float16x8_t; } - _vcvtq_n_f16_s16(a, N) + unsafe { _vcvtq_n_f16_s16(a, N) } } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f16_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))] @@ -6636,7 +6120,7 @@ pub unsafe fn vcvtq_n_f16_s16(a: int16x8_t) -> float16x8_t { #[rustc_legacy_const_generics(1)] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvt_n_f16_u16(a: uint16x4_t) -> float16x4_t { +pub fn vcvt_n_f16_u16(a: uint16x4_t) -> float16x4_t { static_assert!(N >= 1 && N <= 16); unsafe extern "unadjusted" { #[cfg_attr( @@ -6649,12 +6133,10 @@ pub unsafe fn vcvt_n_f16_u16(a: uint16x4_t) -> float16x4_t { )] fn _vcvt_n_f16_u16(a: uint16x4_t, n: i32) -> float16x4_t; } - _vcvt_n_f16_u16(a, N) + unsafe { _vcvt_n_f16_u16(a, N) } } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f16_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))] @@ -6665,7 +6147,7 @@ pub unsafe fn vcvt_n_f16_u16(a: uint16x4_t) -> float16x4_t { #[rustc_legacy_const_generics(1)] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvtq_n_f16_u16(a: uint16x8_t) -> float16x8_t { +pub fn vcvtq_n_f16_u16(a: uint16x8_t) -> float16x8_t { static_assert!(N >= 1 && N <= 16); unsafe extern "unadjusted" { #[cfg_attr( @@ -6678,19 +6160,17 @@ pub unsafe fn vcvtq_n_f16_u16(a: uint16x8_t) -> float16x8_t { )] fn _vcvtq_n_f16_u16(a: uint16x8_t, n: i32) -> float16x8_t; } - _vcvtq_n_f16_u16(a, N) + unsafe { _vcvtq_n_f16_u16(a, N) } } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f32_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vcvt, N = 2))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vcvt_n_f32_s32(a: int32x2_t) -> float32x2_t { +pub fn vcvt_n_f32_s32(a: int32x2_t) -> float32x2_t { static_assert!(N >= 1 && N <= 32); unsafe extern "unadjusted" { #[cfg_attr( @@ -6699,19 +6179,17 @@ pub unsafe fn vcvt_n_f32_s32(a: int32x2_t) -> float32x2_t { )] fn _vcvt_n_f32_s32(a: int32x2_t, n: i32) -> float32x2_t; } - _vcvt_n_f32_s32(a, N) + unsafe { _vcvt_n_f32_s32(a, N) } } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f32_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vcvt, N = 2))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vcvtq_n_f32_s32(a: int32x4_t) -> float32x4_t { +pub fn vcvtq_n_f32_s32(a: int32x4_t) -> float32x4_t { static_assert!(N >= 1 && N <= 32); unsafe extern "unadjusted" { #[cfg_attr( @@ -6720,19 +6198,17 @@ pub unsafe fn vcvtq_n_f32_s32(a: int32x4_t) -> float32x4_t { )] fn _vcvtq_n_f32_s32(a: int32x4_t, n: i32) -> float32x4_t; } - _vcvtq_n_f32_s32(a, N) + unsafe { _vcvtq_n_f32_s32(a, N) } } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f32_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(scvtf, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvt_n_f32_s32(a: int32x2_t) -> float32x2_t { +pub fn vcvt_n_f32_s32(a: int32x2_t) -> float32x2_t { static_assert!(N >= 1 && N <= 32); unsafe extern "unadjusted" { #[cfg_attr( @@ -6741,19 +6217,17 @@ pub unsafe fn vcvt_n_f32_s32(a: int32x2_t) -> float32x2_t { )] fn _vcvt_n_f32_s32(a: int32x2_t, n: i32) -> float32x2_t; } - _vcvt_n_f32_s32(a, N) + unsafe { _vcvt_n_f32_s32(a, N) } } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f32_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(scvtf, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtq_n_f32_s32(a: int32x4_t) -> float32x4_t { +pub fn vcvtq_n_f32_s32(a: int32x4_t) -> float32x4_t { static_assert!(N >= 1 && N <= 32); unsafe extern "unadjusted" { #[cfg_attr( @@ -6762,19 +6236,17 @@ pub unsafe fn vcvtq_n_f32_s32(a: int32x4_t) -> float32x4_t { )] fn _vcvtq_n_f32_s32(a: int32x4_t, n: i32) -> float32x4_t; } - _vcvtq_n_f32_s32(a, N) + unsafe { _vcvtq_n_f32_s32(a, N) } } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f32_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vcvt, N = 2))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vcvt_n_f32_u32(a: uint32x2_t) -> float32x2_t { +pub fn vcvt_n_f32_u32(a: uint32x2_t) -> float32x2_t { static_assert!(N >= 1 && N <= 32); unsafe extern "unadjusted" { #[cfg_attr( @@ -6783,19 +6255,17 @@ pub unsafe fn vcvt_n_f32_u32(a: uint32x2_t) -> float32x2_t { )] fn _vcvt_n_f32_u32(a: uint32x2_t, n: i32) -> float32x2_t; } - _vcvt_n_f32_u32(a, N) + unsafe { _vcvt_n_f32_u32(a, N) } } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f32_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vcvt, N = 2))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vcvtq_n_f32_u32(a: uint32x4_t) -> float32x4_t { +pub fn vcvtq_n_f32_u32(a: uint32x4_t) -> float32x4_t { static_assert!(N >= 1 && N <= 32); unsafe extern "unadjusted" { #[cfg_attr( @@ -6804,19 +6274,17 @@ pub unsafe fn vcvtq_n_f32_u32(a: uint32x4_t) -> float32x4_t { )] fn _vcvtq_n_f32_u32(a: uint32x4_t, n: i32) -> float32x4_t; } - _vcvtq_n_f32_u32(a, N) + unsafe { _vcvtq_n_f32_u32(a, N) } } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f32_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(ucvtf, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvt_n_f32_u32(a: uint32x2_t) -> float32x2_t { +pub fn vcvt_n_f32_u32(a: uint32x2_t) -> float32x2_t { static_assert!(N >= 1 && N <= 32); unsafe extern "unadjusted" { #[cfg_attr( @@ -6825,19 +6293,17 @@ pub unsafe fn vcvt_n_f32_u32(a: uint32x2_t) -> float32x2_t { )] fn _vcvt_n_f32_u32(a: uint32x2_t, n: i32) -> float32x2_t; } - _vcvt_n_f32_u32(a, N) + unsafe { _vcvt_n_f32_u32(a, N) } } #[doc = "Fixed-point convert to floating-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f32_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(ucvtf, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtq_n_f32_u32(a: uint32x4_t) -> float32x4_t { +pub fn vcvtq_n_f32_u32(a: uint32x4_t) -> float32x4_t { static_assert!(N >= 1 && N <= 32); unsafe extern "unadjusted" { #[cfg_attr( @@ -6846,12 +6312,10 @@ pub unsafe fn vcvtq_n_f32_u32(a: uint32x4_t) -> float32x4_t { )] fn _vcvtq_n_f32_u32(a: uint32x4_t, n: i32) -> float32x4_t; } - _vcvtq_n_f32_u32(a, N) + unsafe { _vcvtq_n_f32_u32(a, N) } } #[doc = "Floating-point convert to signed fixed-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_s16_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))] @@ -6862,7 +6326,7 @@ pub unsafe fn vcvtq_n_f32_u32(a: uint32x4_t) -> float32x4_t { #[rustc_legacy_const_generics(1)] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvt_n_s16_f16(a: float16x4_t) -> int16x4_t { +pub fn vcvt_n_s16_f16(a: float16x4_t) -> int16x4_t { static_assert!(N >= 1 && N <= 16); unsafe extern "unadjusted" { #[cfg_attr( @@ -6875,12 +6339,10 @@ pub unsafe fn vcvt_n_s16_f16(a: float16x4_t) -> int16x4_t { )] fn _vcvt_n_s16_f16(a: float16x4_t, n: i32) -> int16x4_t; } - _vcvt_n_s16_f16(a, N) + unsafe { _vcvt_n_s16_f16(a, N) } } #[doc = "Floating-point convert to signed fixed-point"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_s16_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))] @@ -6891,7 +6353,7 @@ pub unsafe fn vcvt_n_s16_f16(a: float16x4_t) -> int16x4_t { #[rustc_legacy_const_generics(1)] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvtq_n_s16_f16(a: float16x8_t) -> int16x8_t { +pub fn vcvtq_n_s16_f16(a: float16x8_t) -> int16x8_t { static_assert!(N >= 1 && N <= 16); unsafe extern "unadjusted" { #[cfg_attr( @@ -6904,19 +6366,17 @@ pub unsafe fn vcvtq_n_s16_f16(a: float16x8_t) -> int16x8_t { )] fn _vcvtq_n_s16_f16(a: float16x8_t, n: i32) -> int16x8_t; } - _vcvtq_n_s16_f16(a, N) + unsafe { _vcvtq_n_s16_f16(a, N) } } #[doc = "Floating-point convert to fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_s32_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vcvt, N = 2))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vcvt_n_s32_f32(a: float32x2_t) -> int32x2_t { +pub fn vcvt_n_s32_f32(a: float32x2_t) -> int32x2_t { static_assert!(N >= 1 && N <= 32); unsafe extern "unadjusted" { #[cfg_attr( @@ -6925,19 +6385,17 @@ pub unsafe fn vcvt_n_s32_f32(a: float32x2_t) -> int32x2_t { )] fn _vcvt_n_s32_f32(a: float32x2_t, n: i32) -> int32x2_t; } - _vcvt_n_s32_f32(a, N) + unsafe { _vcvt_n_s32_f32(a, N) } } #[doc = "Floating-point convert to fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_s32_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vcvt, N = 2))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vcvtq_n_s32_f32(a: float32x4_t) -> int32x4_t { +pub fn vcvtq_n_s32_f32(a: float32x4_t) -> int32x4_t { static_assert!(N >= 1 && N <= 32); unsafe extern "unadjusted" { #[cfg_attr( @@ -6946,19 +6404,17 @@ pub unsafe fn vcvtq_n_s32_f32(a: float32x4_t) -> int32x4_t { )] fn _vcvtq_n_s32_f32(a: float32x4_t, n: i32) -> int32x4_t; } - _vcvtq_n_s32_f32(a, N) + unsafe { _vcvtq_n_s32_f32(a, N) } } #[doc = "Floating-point convert to fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_s32_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(fcvtzs, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvt_n_s32_f32(a: float32x2_t) -> int32x2_t { +pub fn vcvt_n_s32_f32(a: float32x2_t) -> int32x2_t { static_assert!(N >= 1 && N <= 32); unsafe extern "unadjusted" { #[cfg_attr( @@ -6967,19 +6423,17 @@ pub unsafe fn vcvt_n_s32_f32(a: float32x2_t) -> int32x2_t { )] fn _vcvt_n_s32_f32(a: float32x2_t, n: i32) -> int32x2_t; } - _vcvt_n_s32_f32(a, N) + unsafe { _vcvt_n_s32_f32(a, N) } } #[doc = "Floating-point convert to fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_s32_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(fcvtzs, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtq_n_s32_f32(a: float32x4_t) -> int32x4_t { +pub fn vcvtq_n_s32_f32(a: float32x4_t) -> int32x4_t { static_assert!(N >= 1 && N <= 32); unsafe extern "unadjusted" { #[cfg_attr( @@ -6988,12 +6442,10 @@ pub unsafe fn vcvtq_n_s32_f32(a: float32x4_t) -> int32x4_t { )] fn _vcvtq_n_s32_f32(a: float32x4_t, n: i32) -> int32x4_t; } - _vcvtq_n_s32_f32(a, N) + unsafe { _vcvtq_n_s32_f32(a, N) } } #[doc = "Fixed-point convert to unsigned fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_u16_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))] @@ -7004,7 +6456,7 @@ pub unsafe fn vcvtq_n_s32_f32(a: float32x4_t) -> int32x4_t { #[rustc_legacy_const_generics(1)] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvt_n_u16_f16(a: float16x4_t) -> uint16x4_t { +pub fn vcvt_n_u16_f16(a: float16x4_t) -> uint16x4_t { static_assert!(N >= 1 && N <= 16); unsafe extern "unadjusted" { #[cfg_attr( @@ -7017,12 +6469,10 @@ pub unsafe fn vcvt_n_u16_f16(a: float16x4_t) -> uint16x4_t { )] fn _vcvt_n_u16_f16(a: float16x4_t, n: i32) -> uint16x4_t; } - _vcvt_n_u16_f16(a, N) + unsafe { _vcvt_n_u16_f16(a, N) } } #[doc = "Fixed-point convert to unsigned fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_u16_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))] @@ -7033,7 +6483,7 @@ pub unsafe fn vcvt_n_u16_f16(a: float16x4_t) -> uint16x4_t { #[rustc_legacy_const_generics(1)] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvtq_n_u16_f16(a: float16x8_t) -> uint16x8_t { +pub fn vcvtq_n_u16_f16(a: float16x8_t) -> uint16x8_t { static_assert!(N >= 1 && N <= 16); unsafe extern "unadjusted" { #[cfg_attr( @@ -7046,19 +6496,17 @@ pub unsafe fn vcvtq_n_u16_f16(a: float16x8_t) -> uint16x8_t { )] fn _vcvtq_n_u16_f16(a: float16x8_t, n: i32) -> uint16x8_t; } - _vcvtq_n_u16_f16(a, N) + unsafe { _vcvtq_n_u16_f16(a, N) } } #[doc = "Floating-point convert to fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_u32_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vcvt, N = 2))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vcvt_n_u32_f32(a: float32x2_t) -> uint32x2_t { +pub fn vcvt_n_u32_f32(a: float32x2_t) -> uint32x2_t { static_assert!(N >= 1 && N <= 32); unsafe extern "unadjusted" { #[cfg_attr( @@ -7067,19 +6515,17 @@ pub unsafe fn vcvt_n_u32_f32(a: float32x2_t) -> uint32x2_t { )] fn _vcvt_n_u32_f32(a: float32x2_t, n: i32) -> uint32x2_t; } - _vcvt_n_u32_f32(a, N) + unsafe { _vcvt_n_u32_f32(a, N) } } #[doc = "Floating-point convert to fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_u32_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vcvt, N = 2))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vcvtq_n_u32_f32(a: float32x4_t) -> uint32x4_t { +pub fn vcvtq_n_u32_f32(a: float32x4_t) -> uint32x4_t { static_assert!(N >= 1 && N <= 32); unsafe extern "unadjusted" { #[cfg_attr( @@ -7088,19 +6534,17 @@ pub unsafe fn vcvtq_n_u32_f32(a: float32x4_t) -> uint32x4_t { )] fn _vcvtq_n_u32_f32(a: float32x4_t, n: i32) -> uint32x4_t; } - _vcvtq_n_u32_f32(a, N) + unsafe { _vcvtq_n_u32_f32(a, N) } } #[doc = "Floating-point convert to fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_u32_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(fcvtzu, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvt_n_u32_f32(a: float32x2_t) -> uint32x2_t { +pub fn vcvt_n_u32_f32(a: float32x2_t) -> uint32x2_t { static_assert!(N >= 1 && N <= 32); unsafe extern "unadjusted" { #[cfg_attr( @@ -7109,19 +6553,17 @@ pub unsafe fn vcvt_n_u32_f32(a: float32x2_t) -> uint32x2_t { )] fn _vcvt_n_u32_f32(a: float32x2_t, n: i32) -> uint32x2_t; } - _vcvt_n_u32_f32(a, N) + unsafe { _vcvt_n_u32_f32(a, N) } } #[doc = "Floating-point convert to fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_u32_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(fcvtzu, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtq_n_u32_f32(a: float32x4_t) -> uint32x4_t { +pub fn vcvtq_n_u32_f32(a: float32x4_t) -> uint32x4_t { static_assert!(N >= 1 && N <= 32); unsafe extern "unadjusted" { #[cfg_attr( @@ -7130,12 +6572,10 @@ pub unsafe fn vcvtq_n_u32_f32(a: float32x4_t) -> uint32x4_t { )] fn _vcvtq_n_u32_f32(a: float32x4_t, n: i32) -> uint32x4_t; } - _vcvtq_n_u32_f32(a, N) + unsafe { _vcvtq_n_u32_f32(a, N) } } #[doc = "Floating-point convert to signed fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_s16_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))] @@ -7145,13 +6585,11 @@ pub unsafe fn vcvtq_n_u32_f32(a: float32x4_t) -> uint32x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvt_s16_f16(a: float16x4_t) -> int16x4_t { - simd_cast(a) +pub fn vcvt_s16_f16(a: float16x4_t) -> int16x4_t { + unsafe { simd_cast(a) } } #[doc = "Floating-point convert to signed fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_s16_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))] @@ -7161,13 +6599,11 @@ pub unsafe fn vcvt_s16_f16(a: float16x4_t) -> int16x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvtq_s16_f16(a: float16x8_t) -> int16x8_t { - simd_cast(a) +pub fn vcvtq_s16_f16(a: float16x8_t) -> int16x8_t { + unsafe { simd_cast(a) } } #[doc = "Floating-point convert to signed fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_s32_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -7184,7 +6620,7 @@ pub unsafe fn vcvtq_s16_f16(a: float16x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcvt_s32_f32(a: float32x2_t) -> int32x2_t { +pub fn vcvt_s32_f32(a: float32x2_t) -> int32x2_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.fptosi.sat.v2i32.v2f32")] #[cfg_attr( @@ -7193,12 +6629,10 @@ pub unsafe fn vcvt_s32_f32(a: float32x2_t) -> int32x2_t { )] fn _vcvt_s32_f32(a: float32x2_t) -> int32x2_t; } - _vcvt_s32_f32(a) + unsafe { _vcvt_s32_f32(a) } } #[doc = "Floating-point convert to signed fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_s32_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -7215,7 +6649,7 @@ pub unsafe fn vcvt_s32_f32(a: float32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcvtq_s32_f32(a: float32x4_t) -> int32x4_t { +pub fn vcvtq_s32_f32(a: float32x4_t) -> int32x4_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.fptosi.sat.v4i32.v4f32")] #[cfg_attr( @@ -7224,12 +6658,10 @@ pub unsafe fn vcvtq_s32_f32(a: float32x4_t) -> int32x4_t { )] fn _vcvtq_s32_f32(a: float32x4_t) -> int32x4_t; } - _vcvtq_s32_f32(a) + unsafe { _vcvtq_s32_f32(a) } } #[doc = "Floating-point convert to unsigned fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_u16_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))] @@ -7239,13 +6671,11 @@ pub unsafe fn vcvtq_s32_f32(a: float32x4_t) -> int32x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvt_u16_f16(a: float16x4_t) -> uint16x4_t { - simd_cast(a) +pub fn vcvt_u16_f16(a: float16x4_t) -> uint16x4_t { + unsafe { simd_cast(a) } } #[doc = "Floating-point convert to unsigned fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_u16_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))] @@ -7255,13 +6685,11 @@ pub unsafe fn vcvt_u16_f16(a: float16x4_t) -> uint16x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vcvtq_u16_f16(a: float16x8_t) -> uint16x8_t { - simd_cast(a) +pub fn vcvtq_u16_f16(a: float16x8_t) -> uint16x8_t { + unsafe { simd_cast(a) } } #[doc = "Floating-point convert to unsigned fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_u32_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -7278,7 +6706,7 @@ pub unsafe fn vcvtq_u16_f16(a: float16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcvt_u32_f32(a: float32x2_t) -> uint32x2_t { +pub fn vcvt_u32_f32(a: float32x2_t) -> uint32x2_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.fptoui.sat.v2i32.v2f32")] #[cfg_attr( @@ -7287,12 +6715,10 @@ pub unsafe fn vcvt_u32_f32(a: float32x2_t) -> uint32x2_t { )] fn _vcvt_u32_f32(a: float32x2_t) -> uint32x2_t; } - _vcvt_u32_f32(a) + unsafe { _vcvt_u32_f32(a) } } #[doc = "Floating-point convert to unsigned fixed-point, rounding toward zero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_u32_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -7309,7 +6735,7 @@ pub unsafe fn vcvt_u32_f32(a: float32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vcvtq_u32_f32(a: float32x4_t) -> uint32x4_t { +pub fn vcvtq_u32_f32(a: float32x4_t) -> uint32x4_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.fptoui.sat.v4i32.v4f32")] #[cfg_attr( @@ -7318,12 +6744,10 @@ pub unsafe fn vcvtq_u32_f32(a: float32x4_t) -> uint32x4_t { )] fn _vcvtq_u32_f32(a: float32x4_t) -> uint32x4_t; } - _vcvtq_u32_f32(a) + unsafe { _vcvtq_u32_f32(a) } } #[doc = "Dot product arithmetic (indexed)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_lane_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[target_feature(enable = "neon,dotprod")] @@ -7341,16 +6765,16 @@ pub unsafe fn vcvtq_u32_f32(a: float32x4_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vdot_lane_s32(a: int32x2_t, b: int8x8_t, c: int8x8_t) -> int32x2_t { +pub fn vdot_lane_s32(a: int32x2_t, b: int8x8_t, c: int8x8_t) -> int32x2_t { static_assert_uimm_bits!(LANE, 1); - let c: int32x2_t = transmute(c); - let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); - vdot_s32(a, b, transmute(c)) + unsafe { + let c: int32x2_t = transmute(c); + let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); + vdot_s32(a, b, transmute(c)) + } } #[doc = "Dot product arithmetic (indexed)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_lane_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[target_feature(enable = "neon,dotprod")] @@ -7368,20 +6792,17 @@ pub unsafe fn vdot_lane_s32(a: int32x2_t, b: int8x8_t, c: int8x target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vdotq_lane_s32( - a: int32x4_t, - b: int8x16_t, - c: int8x8_t, -) -> int32x4_t { +pub fn vdotq_lane_s32(a: int32x4_t, b: int8x16_t, c: int8x8_t) -> int32x4_t { static_assert_uimm_bits!(LANE, 1); - let c: int32x2_t = transmute(c); - let c: int32x4_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vdotq_s32(a, b, transmute(c)) + unsafe { + let c: int32x2_t = transmute(c); + let c: int32x4_t = + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); + vdotq_s32(a, b, transmute(c)) + } } #[doc = "Dot product arithmetic (indexed)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_lane_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[target_feature(enable = "neon,dotprod")] @@ -7399,20 +6820,16 @@ pub unsafe fn vdotq_lane_s32( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vdot_lane_u32( - a: uint32x2_t, - b: uint8x8_t, - c: uint8x8_t, -) -> uint32x2_t { +pub fn vdot_lane_u32(a: uint32x2_t, b: uint8x8_t, c: uint8x8_t) -> uint32x2_t { static_assert_uimm_bits!(LANE, 1); - let c: uint32x2_t = transmute(c); - let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); - vdot_u32(a, b, transmute(c)) + unsafe { + let c: uint32x2_t = transmute(c); + let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); + vdot_u32(a, b, transmute(c)) + } } #[doc = "Dot product arithmetic (indexed)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_lane_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[target_feature(enable = "neon,dotprod")] @@ -7430,20 +6847,17 @@ pub unsafe fn vdot_lane_u32( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vdotq_lane_u32( - a: uint32x4_t, - b: uint8x16_t, - c: uint8x8_t, -) -> uint32x4_t { +pub fn vdotq_lane_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x8_t) -> uint32x4_t { static_assert_uimm_bits!(LANE, 1); - let c: uint32x2_t = transmute(c); - let c: uint32x4_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vdotq_u32(a, b, transmute(c)) + unsafe { + let c: uint32x2_t = transmute(c); + let c: uint32x4_t = + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); + vdotq_u32(a, b, transmute(c)) + } } #[doc = "Dot product arithmetic (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[target_feature(enable = "neon,dotprod")] @@ -7460,7 +6874,7 @@ pub unsafe fn vdotq_lane_u32( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vdot_s32(a: int32x2_t, b: int8x8_t, c: int8x8_t) -> int32x2_t { +pub fn vdot_s32(a: int32x2_t, b: int8x8_t, c: int8x8_t) -> int32x2_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sdot.v2i32.v8i8")] #[cfg_attr( @@ -7469,12 +6883,10 @@ pub unsafe fn vdot_s32(a: int32x2_t, b: int8x8_t, c: int8x8_t) -> int32x2_t { )] fn _vdot_s32(a: int32x2_t, b: int8x8_t, c: int8x8_t) -> int32x2_t; } - _vdot_s32(a, b, c) + unsafe { _vdot_s32(a, b, c) } } #[doc = "Dot product arithmetic (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[target_feature(enable = "neon,dotprod")] @@ -7491,7 +6903,7 @@ pub unsafe fn vdot_s32(a: int32x2_t, b: int8x8_t, c: int8x8_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vdotq_s32(a: int32x4_t, b: int8x16_t, c: int8x16_t) -> int32x4_t { +pub fn vdotq_s32(a: int32x4_t, b: int8x16_t, c: int8x16_t) -> int32x4_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sdot.v4i32.v16i8")] #[cfg_attr( @@ -7500,12 +6912,10 @@ pub unsafe fn vdotq_s32(a: int32x4_t, b: int8x16_t, c: int8x16_t) -> int32x4_t { )] fn _vdotq_s32(a: int32x4_t, b: int8x16_t, c: int8x16_t) -> int32x4_t; } - _vdotq_s32(a, b, c) + unsafe { _vdotq_s32(a, b, c) } } #[doc = "Dot product arithmetic (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[target_feature(enable = "neon,dotprod")] @@ -7522,7 +6932,7 @@ pub unsafe fn vdotq_s32(a: int32x4_t, b: int8x16_t, c: int8x16_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vdot_u32(a: uint32x2_t, b: uint8x8_t, c: uint8x8_t) -> uint32x2_t { +pub fn vdot_u32(a: uint32x2_t, b: uint8x8_t, c: uint8x8_t) -> uint32x2_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.udot.v2i32.v8i8")] #[cfg_attr( @@ -7531,12 +6941,10 @@ pub unsafe fn vdot_u32(a: uint32x2_t, b: uint8x8_t, c: uint8x8_t) -> uint32x2_t )] fn _vdot_u32(a: uint32x2_t, b: uint8x8_t, c: uint8x8_t) -> uint32x2_t; } - _vdot_u32(a, b, c) + unsafe { _vdot_u32(a, b, c) } } #[doc = "Dot product arithmetic (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[target_feature(enable = "neon,dotprod")] @@ -7553,7 +6961,7 @@ pub unsafe fn vdot_u32(a: uint32x2_t, b: uint8x8_t, c: uint8x8_t) -> uint32x2_t target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vdotq_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4_t { +pub fn vdotq_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.udot.v4i32.v16i8")] #[cfg_attr( @@ -7562,12 +6970,10 @@ pub unsafe fn vdotq_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4 )] fn _vdotq_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4_t; } - _vdotq_u32(a, b, c) + unsafe { _vdotq_u32(a, b, c) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))] @@ -7578,14 +6984,12 @@ pub unsafe fn vdotq_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4 #[rustc_legacy_const_generics(1)] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vdup_lane_f16(a: float16x4_t) -> float16x4_t { +pub fn vdup_lane_f16(a: float16x4_t) -> float16x4_t { static_assert_uimm_bits!(N, 2); - simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) + unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))] @@ -7596,18 +7000,18 @@ pub unsafe fn vdup_lane_f16(a: float16x4_t) -> float16x4_t { #[rustc_legacy_const_generics(1)] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vdupq_lane_f16(a: float16x4_t) -> float16x8_t { +pub fn vdupq_lane_f16(a: float16x4_t) -> float16x8_t { static_assert_uimm_bits!(N, 2); - simd_shuffle!( - a, - a, - [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32] - ) + unsafe { + simd_shuffle!( + a, + a, + [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32] + ) + } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -7625,14 +7029,12 @@ pub unsafe fn vdupq_lane_f16(a: float16x4_t) -> float16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vdup_lane_f32(a: float32x2_t) -> float32x2_t { +pub fn vdup_lane_f32(a: float32x2_t) -> float32x2_t { static_assert_uimm_bits!(N, 1); - simd_shuffle!(a, a, [N as u32, N as u32]) + unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -7650,14 +7052,12 @@ pub unsafe fn vdup_lane_f32(a: float32x2_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vdup_lane_s32(a: int32x2_t) -> int32x2_t { +pub fn vdup_lane_s32(a: int32x2_t) -> int32x2_t { static_assert_uimm_bits!(N, 1); - simd_shuffle!(a, a, [N as u32, N as u32]) + unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -7675,14 +7075,12 @@ pub unsafe fn vdup_lane_s32(a: int32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vdup_lane_u32(a: uint32x2_t) -> uint32x2_t { +pub fn vdup_lane_u32(a: uint32x2_t) -> uint32x2_t { static_assert_uimm_bits!(N, 1); - simd_shuffle!(a, a, [N as u32, N as u32]) + unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -7700,14 +7098,12 @@ pub unsafe fn vdup_lane_u32(a: uint32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vdupq_lane_f32(a: float32x2_t) -> float32x4_t { +pub fn vdupq_lane_f32(a: float32x2_t) -> float32x4_t { static_assert_uimm_bits!(N, 1); - simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) + unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -7725,14 +7121,12 @@ pub unsafe fn vdupq_lane_f32(a: float32x2_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vdupq_lane_s32(a: int32x2_t) -> int32x4_t { +pub fn vdupq_lane_s32(a: int32x2_t) -> int32x4_t { static_assert_uimm_bits!(N, 1); - simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) + unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -7750,14 +7144,12 @@ pub unsafe fn vdupq_lane_s32(a: int32x2_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vdupq_lane_u32(a: uint32x2_t) -> uint32x4_t { +pub fn vdupq_lane_u32(a: uint32x2_t) -> uint32x4_t { static_assert_uimm_bits!(N, 1); - simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) + unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -7775,14 +7167,12 @@ pub unsafe fn vdupq_lane_u32(a: uint32x2_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vdup_lane_p16(a: poly16x4_t) -> poly16x4_t { +pub fn vdup_lane_p16(a: poly16x4_t) -> poly16x4_t { static_assert_uimm_bits!(N, 2); - simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) + unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -7800,14 +7190,12 @@ pub unsafe fn vdup_lane_p16(a: poly16x4_t) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vdup_lane_s16(a: int16x4_t) -> int16x4_t { +pub fn vdup_lane_s16(a: int16x4_t) -> int16x4_t { static_assert_uimm_bits!(N, 2); - simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) + unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -7825,14 +7213,12 @@ pub unsafe fn vdup_lane_s16(a: int16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vdup_lane_u16(a: uint16x4_t) -> uint16x4_t { +pub fn vdup_lane_u16(a: uint16x4_t) -> uint16x4_t { static_assert_uimm_bits!(N, 2); - simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) + unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -7850,18 +7236,18 @@ pub unsafe fn vdup_lane_u16(a: uint16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vdupq_lane_p16(a: poly16x4_t) -> poly16x8_t { +pub fn vdupq_lane_p16(a: poly16x4_t) -> poly16x8_t { static_assert_uimm_bits!(N, 2); - simd_shuffle!( - a, - a, - [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32] - ) + unsafe { + simd_shuffle!( + a, + a, + [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32] + ) + } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -7879,18 +7265,18 @@ pub unsafe fn vdupq_lane_p16(a: poly16x4_t) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vdupq_lane_s16(a: int16x4_t) -> int16x8_t { +pub fn vdupq_lane_s16(a: int16x4_t) -> int16x8_t { static_assert_uimm_bits!(N, 2); - simd_shuffle!( - a, - a, - [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32] - ) + unsafe { + simd_shuffle!( + a, + a, + [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32] + ) + } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -7908,18 +7294,18 @@ pub unsafe fn vdupq_lane_s16(a: int16x4_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vdupq_lane_u16(a: uint16x4_t) -> uint16x8_t { +pub fn vdupq_lane_u16(a: uint16x4_t) -> uint16x8_t { static_assert_uimm_bits!(N, 2); - simd_shuffle!( - a, - a, - [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32] - ) + unsafe { + simd_shuffle!( + a, + a, + [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32] + ) + } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -7937,18 +7323,18 @@ pub unsafe fn vdupq_lane_u16(a: uint16x4_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vdup_lane_p8(a: poly8x8_t) -> poly8x8_t { +pub fn vdup_lane_p8(a: poly8x8_t) -> poly8x8_t { static_assert_uimm_bits!(N, 3); - simd_shuffle!( - a, - a, - [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32] - ) + unsafe { + simd_shuffle!( + a, + a, + [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32] + ) + } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -7966,18 +7352,18 @@ pub unsafe fn vdup_lane_p8(a: poly8x8_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vdup_lane_s8(a: int8x8_t) -> int8x8_t { +pub fn vdup_lane_s8(a: int8x8_t) -> int8x8_t { static_assert_uimm_bits!(N, 3); - simd_shuffle!( - a, - a, - [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32] - ) + unsafe { + simd_shuffle!( + a, + a, + [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32] + ) + } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -7995,18 +7381,18 @@ pub unsafe fn vdup_lane_s8(a: int8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vdup_lane_u8(a: uint8x8_t) -> uint8x8_t { +pub fn vdup_lane_u8(a: uint8x8_t) -> uint8x8_t { static_assert_uimm_bits!(N, 3); - simd_shuffle!( - a, - a, - [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32] - ) + unsafe { + simd_shuffle!( + a, + a, + [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32] + ) + } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -8024,21 +7410,21 @@ pub unsafe fn vdup_lane_u8(a: uint8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vdupq_lane_p8(a: poly8x8_t) -> poly8x16_t { +pub fn vdupq_lane_p8(a: poly8x8_t) -> poly8x16_t { static_assert_uimm_bits!(N, 3); - simd_shuffle!( - a, - a, - [ - N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, - N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32 - ] - ) + unsafe { + simd_shuffle!( + a, + a, + [ + N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, + N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32 + ] + ) + } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -8056,21 +7442,21 @@ pub unsafe fn vdupq_lane_p8(a: poly8x8_t) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vdupq_lane_s8(a: int8x8_t) -> int8x16_t { +pub fn vdupq_lane_s8(a: int8x8_t) -> int8x16_t { static_assert_uimm_bits!(N, 3); - simd_shuffle!( - a, - a, - [ - N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, - N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32 - ] - ) + unsafe { + simd_shuffle!( + a, + a, + [ + N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, + N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32 + ] + ) + } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -8088,21 +7474,21 @@ pub unsafe fn vdupq_lane_s8(a: int8x8_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vdupq_lane_u8(a: uint8x8_t) -> uint8x16_t { +pub fn vdupq_lane_u8(a: uint8x8_t) -> uint8x16_t { static_assert_uimm_bits!(N, 3); - simd_shuffle!( - a, - a, - [ - N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, - N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32 - ] - ) + unsafe { + simd_shuffle!( + a, + a, + [ + N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, + N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32 + ] + ) + } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -8120,14 +7506,12 @@ pub unsafe fn vdupq_lane_u8(a: uint8x8_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vdup_lane_s64(a: int64x1_t) -> int64x1_t { +pub fn vdup_lane_s64(a: int64x1_t) -> int64x1_t { static_assert!(N == 0); a } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -8145,14 +7529,12 @@ pub unsafe fn vdup_lane_s64(a: int64x1_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vdup_lane_u64(a: uint64x1_t) -> uint64x1_t { +pub fn vdup_lane_u64(a: uint64x1_t) -> uint64x1_t { static_assert!(N == 0); a } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))] @@ -8163,14 +7545,12 @@ pub unsafe fn vdup_lane_u64(a: uint64x1_t) -> uint64x1_t { #[rustc_legacy_const_generics(1)] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vdup_laneq_f16(a: float16x8_t) -> float16x4_t { +pub fn vdup_laneq_f16(a: float16x8_t) -> float16x4_t { static_assert_uimm_bits!(N, 3); - simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) + unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))] @@ -8181,18 +7561,18 @@ pub unsafe fn vdup_laneq_f16(a: float16x8_t) -> float16x4_t { #[rustc_legacy_const_generics(1)] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vdupq_laneq_f16(a: float16x8_t) -> float16x8_t { +pub fn vdupq_laneq_f16(a: float16x8_t) -> float16x8_t { static_assert_uimm_bits!(N, 3); - simd_shuffle!( - a, - a, - [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32] - ) + unsafe { + simd_shuffle!( + a, + a, + [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32] + ) + } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -8210,14 +7590,12 @@ pub unsafe fn vdupq_laneq_f16(a: float16x8_t) -> float16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vdup_laneq_f32(a: float32x4_t) -> float32x2_t { +pub fn vdup_laneq_f32(a: float32x4_t) -> float32x2_t { static_assert_uimm_bits!(N, 2); - simd_shuffle!(a, a, [N as u32, N as u32]) + unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -8235,14 +7613,12 @@ pub unsafe fn vdup_laneq_f32(a: float32x4_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vdup_laneq_s32(a: int32x4_t) -> int32x2_t { +pub fn vdup_laneq_s32(a: int32x4_t) -> int32x2_t { static_assert_uimm_bits!(N, 2); - simd_shuffle!(a, a, [N as u32, N as u32]) + unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -8260,14 +7636,12 @@ pub unsafe fn vdup_laneq_s32(a: int32x4_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vdup_laneq_u32(a: uint32x4_t) -> uint32x2_t { +pub fn vdup_laneq_u32(a: uint32x4_t) -> uint32x2_t { static_assert_uimm_bits!(N, 2); - simd_shuffle!(a, a, [N as u32, N as u32]) + unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -8285,14 +7659,12 @@ pub unsafe fn vdup_laneq_u32(a: uint32x4_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vdupq_laneq_f32(a: float32x4_t) -> float32x4_t { +pub fn vdupq_laneq_f32(a: float32x4_t) -> float32x4_t { static_assert_uimm_bits!(N, 2); - simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) + unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -8310,14 +7682,12 @@ pub unsafe fn vdupq_laneq_f32(a: float32x4_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vdupq_laneq_s32(a: int32x4_t) -> int32x4_t { +pub fn vdupq_laneq_s32(a: int32x4_t) -> int32x4_t { static_assert_uimm_bits!(N, 2); - simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) + unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -8335,14 +7705,12 @@ pub unsafe fn vdupq_laneq_s32(a: int32x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vdupq_laneq_u32(a: uint32x4_t) -> uint32x4_t { +pub fn vdupq_laneq_u32(a: uint32x4_t) -> uint32x4_t { static_assert_uimm_bits!(N, 2); - simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) + unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -8360,14 +7728,12 @@ pub unsafe fn vdupq_laneq_u32(a: uint32x4_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vdup_laneq_p16(a: poly16x8_t) -> poly16x4_t { +pub fn vdup_laneq_p16(a: poly16x8_t) -> poly16x4_t { static_assert_uimm_bits!(N, 3); - simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) + unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -8385,14 +7751,12 @@ pub unsafe fn vdup_laneq_p16(a: poly16x8_t) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vdup_laneq_s16(a: int16x8_t) -> int16x4_t { +pub fn vdup_laneq_s16(a: int16x8_t) -> int16x4_t { static_assert_uimm_bits!(N, 3); - simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) + unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -8410,14 +7774,12 @@ pub unsafe fn vdup_laneq_s16(a: int16x8_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vdup_laneq_u16(a: uint16x8_t) -> uint16x4_t { +pub fn vdup_laneq_u16(a: uint16x8_t) -> uint16x4_t { static_assert_uimm_bits!(N, 3); - simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) + unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -8435,18 +7797,18 @@ pub unsafe fn vdup_laneq_u16(a: uint16x8_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vdupq_laneq_p16(a: poly16x8_t) -> poly16x8_t { +pub fn vdupq_laneq_p16(a: poly16x8_t) -> poly16x8_t { static_assert_uimm_bits!(N, 3); - simd_shuffle!( - a, - a, - [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32] - ) + unsafe { + simd_shuffle!( + a, + a, + [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32] + ) + } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -8464,18 +7826,18 @@ pub unsafe fn vdupq_laneq_p16(a: poly16x8_t) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vdupq_laneq_s16(a: int16x8_t) -> int16x8_t { +pub fn vdupq_laneq_s16(a: int16x8_t) -> int16x8_t { static_assert_uimm_bits!(N, 3); - simd_shuffle!( - a, - a, - [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32] - ) + unsafe { + simd_shuffle!( + a, + a, + [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32] + ) + } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -8493,18 +7855,18 @@ pub unsafe fn vdupq_laneq_s16(a: int16x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vdupq_laneq_u16(a: uint16x8_t) -> uint16x8_t { +pub fn vdupq_laneq_u16(a: uint16x8_t) -> uint16x8_t { static_assert_uimm_bits!(N, 3); - simd_shuffle!( - a, - a, - [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32] - ) + unsafe { + simd_shuffle!( + a, + a, + [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32] + ) + } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -8522,18 +7884,18 @@ pub unsafe fn vdupq_laneq_u16(a: uint16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vdup_laneq_p8(a: poly8x16_t) -> poly8x8_t { +pub fn vdup_laneq_p8(a: poly8x16_t) -> poly8x8_t { static_assert_uimm_bits!(N, 4); - simd_shuffle!( - a, - a, - [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32] - ) + unsafe { + simd_shuffle!( + a, + a, + [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32] + ) + } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -8551,18 +7913,18 @@ pub unsafe fn vdup_laneq_p8(a: poly8x16_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vdup_laneq_s8(a: int8x16_t) -> int8x8_t { +pub fn vdup_laneq_s8(a: int8x16_t) -> int8x8_t { static_assert_uimm_bits!(N, 4); - simd_shuffle!( - a, - a, - [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32] - ) + unsafe { + simd_shuffle!( + a, + a, + [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32] + ) + } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -8580,18 +7942,18 @@ pub unsafe fn vdup_laneq_s8(a: int8x16_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vdup_laneq_u8(a: uint8x16_t) -> uint8x8_t { +pub fn vdup_laneq_u8(a: uint8x16_t) -> uint8x8_t { static_assert_uimm_bits!(N, 4); - simd_shuffle!( - a, - a, - [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32] - ) + unsafe { + simd_shuffle!( + a, + a, + [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32] + ) + } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -8609,21 +7971,21 @@ pub unsafe fn vdup_laneq_u8(a: uint8x16_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vdupq_laneq_p8(a: poly8x16_t) -> poly8x16_t { +pub fn vdupq_laneq_p8(a: poly8x16_t) -> poly8x16_t { static_assert_uimm_bits!(N, 4); - simd_shuffle!( - a, - a, - [ - N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, - N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32 - ] - ) + unsafe { + simd_shuffle!( + a, + a, + [ + N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, + N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32 + ] + ) + } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -8641,21 +8003,21 @@ pub unsafe fn vdupq_laneq_p8(a: poly8x16_t) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vdupq_laneq_s8(a: int8x16_t) -> int8x16_t { +pub fn vdupq_laneq_s8(a: int8x16_t) -> int8x16_t { static_assert_uimm_bits!(N, 4); - simd_shuffle!( - a, - a, - [ - N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, - N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32 - ] - ) + unsafe { + simd_shuffle!( + a, + a, + [ + N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, + N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32 + ] + ) + } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -8673,21 +8035,21 @@ pub unsafe fn vdupq_laneq_s8(a: int8x16_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vdupq_laneq_u8(a: uint8x16_t) -> uint8x16_t { +pub fn vdupq_laneq_u8(a: uint8x16_t) -> uint8x16_t { static_assert_uimm_bits!(N, 4); - simd_shuffle!( - a, - a, - [ - N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, - N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32 - ] - ) + unsafe { + simd_shuffle!( + a, + a, + [ + N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, + N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32 + ] + ) + } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -8705,14 +8067,12 @@ pub unsafe fn vdupq_laneq_u8(a: uint8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vdup_laneq_s64(a: int64x2_t) -> int64x1_t { +pub fn vdup_laneq_s64(a: int64x2_t) -> int64x1_t { static_assert_uimm_bits!(N, 1); - transmute::(simd_extract!(a, N as u32)) + unsafe { transmute::(simd_extract!(a, N as u32)) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -8730,14 +8090,12 @@ pub unsafe fn vdup_laneq_s64(a: int64x2_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vdup_laneq_u64(a: uint64x2_t) -> uint64x1_t { +pub fn vdup_laneq_u64(a: uint64x2_t) -> uint64x1_t { static_assert_uimm_bits!(N, 1); - transmute::(simd_extract!(a, N as u32)) + unsafe { transmute::(simd_extract!(a, N as u32)) } } #[doc = "Create a new vector with all lanes set to a value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))] @@ -8747,13 +8105,11 @@ pub unsafe fn vdup_laneq_u64(a: uint64x2_t) -> uint64x1_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vdup_n_f16(a: f16) -> float16x4_t { +pub fn vdup_n_f16(a: f16) -> float16x4_t { float16x4_t::splat(a) } #[doc = "Create a new vector with all lanes set to a value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))] @@ -8763,13 +8119,11 @@ pub unsafe fn vdup_n_f16(a: f16) -> float16x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vdupq_n_f16(a: f16) -> float16x8_t { +pub fn vdupq_n_f16(a: f16) -> float16x8_t { float16x8_t::splat(a) } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -8787,14 +8141,12 @@ pub unsafe fn vdupq_n_f16(a: f16) -> float16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vdupq_lane_s64(a: int64x1_t) -> int64x2_t { +pub fn vdupq_lane_s64(a: int64x1_t) -> int64x2_t { static_assert!(N == 0); - simd_shuffle!(a, a, [N as u32, N as u32]) + unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -8812,14 +8164,12 @@ pub unsafe fn vdupq_lane_s64(a: int64x1_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vdupq_lane_u64(a: uint64x1_t) -> uint64x2_t { +pub fn vdupq_lane_u64(a: uint64x1_t) -> uint64x2_t { static_assert!(N == 0); - simd_shuffle!(a, a, [N as u32, N as u32]) + unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -8837,14 +8187,12 @@ pub unsafe fn vdupq_lane_u64(a: uint64x1_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vdupq_laneq_s64(a: int64x2_t) -> int64x2_t { +pub fn vdupq_laneq_s64(a: int64x2_t) -> int64x2_t { static_assert_uimm_bits!(N, 1); - simd_shuffle!(a, a, [N as u32, N as u32]) + unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) } } #[doc = "Set all vector lanes to the same value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -8862,14 +8210,12 @@ pub unsafe fn vdupq_laneq_s64(a: int64x2_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vdupq_laneq_u64(a: uint64x2_t) -> uint64x2_t { +pub fn vdupq_laneq_u64(a: uint64x2_t) -> uint64x2_t { static_assert_uimm_bits!(N, 1); - simd_shuffle!(a, a, [N as u32, N as u32]) + unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) } } #[doc = "Vector bitwise exclusive or (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -8886,13 +8232,11 @@ pub unsafe fn vdupq_laneq_u64(a: uint64x2_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn veor_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { - simd_xor(a, b) +pub fn veor_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { + unsafe { simd_xor(a, b) } } #[doc = "Vector bitwise exclusive or (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -8909,13 +8253,11 @@ pub unsafe fn veor_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn veorq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { - simd_xor(a, b) +pub fn veorq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { + unsafe { simd_xor(a, b) } } #[doc = "Vector bitwise exclusive or (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -8932,13 +8274,11 @@ pub unsafe fn veorq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn veor_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { - simd_xor(a, b) +pub fn veor_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + unsafe { simd_xor(a, b) } } #[doc = "Vector bitwise exclusive or (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -8955,13 +8295,11 @@ pub unsafe fn veor_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn veorq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { - simd_xor(a, b) +pub fn veorq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + unsafe { simd_xor(a, b) } } #[doc = "Vector bitwise exclusive or (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -8978,13 +8316,11 @@ pub unsafe fn veorq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn veor_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { - simd_xor(a, b) +pub fn veor_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + unsafe { simd_xor(a, b) } } #[doc = "Vector bitwise exclusive or (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -9001,13 +8337,11 @@ pub unsafe fn veor_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn veorq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { - simd_xor(a, b) +pub fn veorq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + unsafe { simd_xor(a, b) } } #[doc = "Vector bitwise exclusive or (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -9024,13 +8358,11 @@ pub unsafe fn veorq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn veor_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { - simd_xor(a, b) +pub fn veor_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { + unsafe { simd_xor(a, b) } } #[doc = "Vector bitwise exclusive or (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -9047,13 +8379,11 @@ pub unsafe fn veor_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn veorq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { - simd_xor(a, b) +pub fn veorq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { + unsafe { simd_xor(a, b) } } #[doc = "Vector bitwise exclusive or (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -9070,13 +8400,11 @@ pub unsafe fn veorq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn veor_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { - simd_xor(a, b) +pub fn veor_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + unsafe { simd_xor(a, b) } } #[doc = "Vector bitwise exclusive or (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -9093,13 +8421,11 @@ pub unsafe fn veor_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn veorq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { - simd_xor(a, b) +pub fn veorq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + unsafe { simd_xor(a, b) } } #[doc = "Vector bitwise exclusive or (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -9116,13 +8442,11 @@ pub unsafe fn veorq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn veor_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { - simd_xor(a, b) +pub fn veor_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + unsafe { simd_xor(a, b) } } #[doc = "Vector bitwise exclusive or (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -9139,13 +8463,11 @@ pub unsafe fn veor_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn veorq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { - simd_xor(a, b) +pub fn veorq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + unsafe { simd_xor(a, b) } } #[doc = "Vector bitwise exclusive or (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -9162,13 +8484,11 @@ pub unsafe fn veorq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn veor_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { - simd_xor(a, b) +pub fn veor_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + unsafe { simd_xor(a, b) } } #[doc = "Vector bitwise exclusive or (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -9185,13 +8505,11 @@ pub unsafe fn veor_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn veorq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { - simd_xor(a, b) +pub fn veorq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + unsafe { simd_xor(a, b) } } #[doc = "Vector bitwise exclusive or (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -9208,13 +8526,11 @@ pub unsafe fn veorq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn veor_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { - simd_xor(a, b) +pub fn veor_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { + unsafe { simd_xor(a, b) } } #[doc = "Vector bitwise exclusive or (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -9231,13 +8547,11 @@ pub unsafe fn veor_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn veorq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { - simd_xor(a, b) +pub fn veorq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { + unsafe { simd_xor(a, b) } } #[doc = "Extract vector from pair of vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))] @@ -9248,20 +8562,20 @@ pub unsafe fn veorq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { #[rustc_legacy_const_generics(2)] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vext_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { +pub fn vext_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { static_assert_uimm_bits!(N, 2); - match N & 0b11 { - 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), - 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), - 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), - 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), - _ => unreachable_unchecked(), + unsafe { + match N & 0b11 { + 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), + 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), + 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), + 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), + _ => unreachable_unchecked(), + } } } #[doc = "Extract vector from pair of vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -9279,18 +8593,18 @@ pub unsafe fn vext_f16(a: float16x4_t, b: float16x4_t) -> float16x target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vext_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { +pub fn vext_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { static_assert_uimm_bits!(N, 1); - match N & 0b1 { - 0 => simd_shuffle!(a, b, [0, 1]), - 1 => simd_shuffle!(a, b, [1, 2]), - _ => unreachable_unchecked(), + unsafe { + match N & 0b1 { + 0 => simd_shuffle!(a, b, [0, 1]), + 1 => simd_shuffle!(a, b, [1, 2]), + _ => unreachable_unchecked(), + } } } #[doc = "Extract vector from pair of vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -9308,18 +8622,18 @@ pub unsafe fn vext_f32(a: float32x2_t, b: float32x2_t) -> float32x target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vext_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { +pub fn vext_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { static_assert_uimm_bits!(N, 1); - match N & 0b1 { - 0 => simd_shuffle!(a, b, [0, 1]), - 1 => simd_shuffle!(a, b, [1, 2]), - _ => unreachable_unchecked(), + unsafe { + match N & 0b1 { + 0 => simd_shuffle!(a, b, [0, 1]), + 1 => simd_shuffle!(a, b, [1, 2]), + _ => unreachable_unchecked(), + } } } #[doc = "Extract vector from pair of vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -9337,18 +8651,18 @@ pub unsafe fn vext_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vext_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { +pub fn vext_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { static_assert_uimm_bits!(N, 1); - match N & 0b1 { - 0 => simd_shuffle!(a, b, [0, 1]), - 1 => simd_shuffle!(a, b, [1, 2]), - _ => unreachable_unchecked(), + unsafe { + match N & 0b1 { + 0 => simd_shuffle!(a, b, [0, 1]), + 1 => simd_shuffle!(a, b, [1, 2]), + _ => unreachable_unchecked(), + } } } #[doc = "Extract vector from pair of vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -9366,24 +8680,24 @@ pub unsafe fn vext_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vext_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { +pub fn vext_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { static_assert_uimm_bits!(N, 3); - match N & 0b111 { - 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), - 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), - 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), - 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), - 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), - 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), - 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), - 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), - _ => unreachable_unchecked(), + unsafe { + match N & 0b111 { + 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), + 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), + 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), + 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), + 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), + 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), + 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), + 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), + _ => unreachable_unchecked(), + } } } #[doc = "Extract vector from pair of vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -9401,24 +8715,24 @@ pub unsafe fn vext_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vextq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { +pub fn vextq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { static_assert_uimm_bits!(N, 3); - match N & 0b111 { - 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), - 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), - 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), - 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), - 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), - 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), - 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), - 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), - _ => unreachable_unchecked(), + unsafe { + match N & 0b111 { + 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), + 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), + 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), + 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), + 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), + 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), + 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), + 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), + _ => unreachable_unchecked(), + } } } #[doc = "Extract vector from pair of vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -9436,24 +8750,24 @@ pub unsafe fn vextq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vext_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { +pub fn vext_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { static_assert_uimm_bits!(N, 3); - match N & 0b111 { - 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), - 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), - 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), - 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), - 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), - 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), - 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), - 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), - _ => unreachable_unchecked(), + unsafe { + match N & 0b111 { + 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), + 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), + 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), + 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), + 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), + 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), + 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), + 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), + _ => unreachable_unchecked(), + } } } #[doc = "Extract vector from pair of vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -9471,24 +8785,24 @@ pub unsafe fn vext_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vextq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { +pub fn vextq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { static_assert_uimm_bits!(N, 3); - match N & 0b111 { - 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), - 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), - 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), - 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), - 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), - 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), - 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), - 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), - _ => unreachable_unchecked(), + unsafe { + match N & 0b111 { + 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), + 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), + 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), + 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), + 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), + 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), + 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), + 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), + _ => unreachable_unchecked(), + } } } #[doc = "Extract vector from pair of vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -9506,24 +8820,24 @@ pub unsafe fn vextq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_ target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vext_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { +pub fn vext_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { static_assert_uimm_bits!(N, 3); - match N & 0b111 { - 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), - 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), - 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), - 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), - 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), - 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), - 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), - 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), - _ => unreachable_unchecked(), + unsafe { + match N & 0b111 { + 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), + 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), + 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), + 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), + 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), + 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), + 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), + 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), + _ => unreachable_unchecked(), + } } } #[doc = "Extract vector from pair of vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -9541,24 +8855,24 @@ pub unsafe fn vext_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vextq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { +pub fn vextq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { static_assert_uimm_bits!(N, 3); - match N & 0b111 { - 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), - 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), - 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), - 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), - 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), - 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), - 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), - 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), - _ => unreachable_unchecked(), + unsafe { + match N & 0b111 { + 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), + 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), + 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), + 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), + 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), + 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), + 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), + 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), + _ => unreachable_unchecked(), + } } } #[doc = "Extract vector from pair of vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))] @@ -9569,24 +8883,24 @@ pub unsafe fn vextq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_ #[rustc_legacy_const_generics(2)] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vextq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { +pub fn vextq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { static_assert_uimm_bits!(N, 3); - match N & 0b111 { - 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), - 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), - 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), - 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), - 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), - 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), - 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), - 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), - _ => unreachable_unchecked(), + unsafe { + match N & 0b111 { + 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), + 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), + 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), + 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), + 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), + 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), + 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), + 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), + _ => unreachable_unchecked(), + } } } #[doc = "Extract vector from pair of vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -9604,20 +8918,20 @@ pub unsafe fn vextq_f16(a: float16x8_t, b: float16x8_t) -> float16 target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vextq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { +pub fn vextq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { static_assert_uimm_bits!(N, 2); - match N & 0b11 { - 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), - 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), - 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), - 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), - _ => unreachable_unchecked(), + unsafe { + match N & 0b11 { + 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), + 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), + 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), + 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), + _ => unreachable_unchecked(), + } } } #[doc = "Extract vector from pair of vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -9635,20 +8949,20 @@ pub unsafe fn vextq_f32(a: float32x4_t, b: float32x4_t) -> float32 target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vext_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { +pub fn vext_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { static_assert_uimm_bits!(N, 2); - match N & 0b11 { - 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), - 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), - 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), - 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), - _ => unreachable_unchecked(), + unsafe { + match N & 0b11 { + 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), + 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), + 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), + 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), + _ => unreachable_unchecked(), + } } } #[doc = "Extract vector from pair of vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -9666,20 +8980,20 @@ pub unsafe fn vext_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vextq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { +pub fn vextq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { static_assert_uimm_bits!(N, 2); - match N & 0b11 { - 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), - 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), - 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), - 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), - _ => unreachable_unchecked(), + unsafe { + match N & 0b11 { + 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), + 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), + 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), + 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), + _ => unreachable_unchecked(), + } } } #[doc = "Extract vector from pair of vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -9697,20 +9011,20 @@ pub unsafe fn vextq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vext_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { +pub fn vext_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { static_assert_uimm_bits!(N, 2); - match N & 0b11 { - 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), - 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), - 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), - 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), - _ => unreachable_unchecked(), + unsafe { + match N & 0b11 { + 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), + 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), + 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), + 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), + _ => unreachable_unchecked(), + } } } #[doc = "Extract vector from pair of vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -9728,20 +9042,20 @@ pub unsafe fn vext_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vextq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { +pub fn vextq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { static_assert_uimm_bits!(N, 2); - match N & 0b11 { - 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), - 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), - 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), - 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), - _ => unreachable_unchecked(), + unsafe { + match N & 0b11 { + 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), + 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), + 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), + 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), + _ => unreachable_unchecked(), + } } } #[doc = "Extract vector from pair of vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -9759,20 +9073,20 @@ pub unsafe fn vextq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_ target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vext_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { +pub fn vext_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { static_assert_uimm_bits!(N, 2); - match N & 0b11 { - 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), - 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), - 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), - 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), - _ => unreachable_unchecked(), + unsafe { + match N & 0b11 { + 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), + 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), + 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), + 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), + _ => unreachable_unchecked(), + } } } #[doc = "Extract vector from pair of vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -9790,18 +9104,18 @@ pub unsafe fn vext_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vextq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { +pub fn vextq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { static_assert_uimm_bits!(N, 1); - match N & 0b1 { - 0 => simd_shuffle!(a, b, [0, 1]), - 1 => simd_shuffle!(a, b, [1, 2]), - _ => unreachable_unchecked(), + unsafe { + match N & 0b1 { + 0 => simd_shuffle!(a, b, [0, 1]), + 1 => simd_shuffle!(a, b, [1, 2]), + _ => unreachable_unchecked(), + } } } #[doc = "Extract vector from pair of vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -9819,18 +9133,18 @@ pub unsafe fn vextq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vextq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { +pub fn vextq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { static_assert_uimm_bits!(N, 1); - match N & 0b1 { - 0 => simd_shuffle!(a, b, [0, 1]), - 1 => simd_shuffle!(a, b, [1, 2]), - _ => unreachable_unchecked(), + unsafe { + match N & 0b1 { + 0 => simd_shuffle!(a, b, [0, 1]), + 1 => simd_shuffle!(a, b, [1, 2]), + _ => unreachable_unchecked(), + } } } #[doc = "Extract vector from pair of vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -9848,92 +9162,92 @@ pub unsafe fn vextq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_ target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vextq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { +pub fn vextq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { static_assert_uimm_bits!(N, 4); - match N & 0b1111 { - 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), - 1 => simd_shuffle!( - a, - b, - [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16] - ), - 2 => simd_shuffle!( - a, - b, - [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17] - ), - 3 => simd_shuffle!( - a, - b, - [3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18] - ), - 4 => simd_shuffle!( - a, - b, - [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19] - ), - 5 => simd_shuffle!( - a, - b, - [5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20] - ), - 6 => simd_shuffle!( - a, - b, - [6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21] - ), - 7 => simd_shuffle!( - a, - b, - [7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22] - ), - 8 => simd_shuffle!( - a, - b, - [8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23] - ), - 9 => simd_shuffle!( - a, - b, - [9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24] - ), - 10 => simd_shuffle!( - a, - b, - [10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25] - ), - 11 => simd_shuffle!( - a, - b, - [11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26] - ), - 12 => simd_shuffle!( - a, - b, - [12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27] - ), - 13 => simd_shuffle!( - a, - b, - [13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28] - ), - 14 => simd_shuffle!( - a, - b, - [14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29] - ), - 15 => simd_shuffle!( - a, - b, - [15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30] - ), - _ => unreachable_unchecked(), + unsafe { + match N & 0b1111 { + 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), + 1 => simd_shuffle!( + a, + b, + [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16] + ), + 2 => simd_shuffle!( + a, + b, + [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17] + ), + 3 => simd_shuffle!( + a, + b, + [3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18] + ), + 4 => simd_shuffle!( + a, + b, + [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19] + ), + 5 => simd_shuffle!( + a, + b, + [5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20] + ), + 6 => simd_shuffle!( + a, + b, + [6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21] + ), + 7 => simd_shuffle!( + a, + b, + [7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22] + ), + 8 => simd_shuffle!( + a, + b, + [8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23] + ), + 9 => simd_shuffle!( + a, + b, + [9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24] + ), + 10 => simd_shuffle!( + a, + b, + [10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25] + ), + 11 => simd_shuffle!( + a, + b, + [11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26] + ), + 12 => simd_shuffle!( + a, + b, + [12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27] + ), + 13 => simd_shuffle!( + a, + b, + [13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28] + ), + 14 => simd_shuffle!( + a, + b, + [14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29] + ), + 15 => simd_shuffle!( + a, + b, + [15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30] + ), + _ => unreachable_unchecked(), + } } } #[doc = "Extract vector from pair of vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -9951,92 +9265,92 @@ pub unsafe fn vextq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vextq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { +pub fn vextq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { static_assert_uimm_bits!(N, 4); - match N & 0b1111 { - 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), - 1 => simd_shuffle!( - a, - b, - [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16] - ), - 2 => simd_shuffle!( - a, - b, - [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17] - ), - 3 => simd_shuffle!( - a, - b, - [3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18] - ), - 4 => simd_shuffle!( - a, - b, - [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19] - ), - 5 => simd_shuffle!( - a, - b, - [5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20] - ), - 6 => simd_shuffle!( - a, - b, - [6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21] - ), - 7 => simd_shuffle!( - a, - b, - [7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22] - ), - 8 => simd_shuffle!( - a, - b, - [8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23] - ), - 9 => simd_shuffle!( - a, - b, - [9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24] - ), - 10 => simd_shuffle!( - a, - b, - [10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25] - ), - 11 => simd_shuffle!( - a, - b, - [11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26] - ), - 12 => simd_shuffle!( - a, - b, - [12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27] - ), - 13 => simd_shuffle!( - a, - b, - [13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28] - ), - 14 => simd_shuffle!( - a, - b, - [14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29] - ), - 15 => simd_shuffle!( - a, - b, - [15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30] - ), - _ => unreachable_unchecked(), + unsafe { + match N & 0b1111 { + 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), + 1 => simd_shuffle!( + a, + b, + [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16] + ), + 2 => simd_shuffle!( + a, + b, + [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17] + ), + 3 => simd_shuffle!( + a, + b, + [3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18] + ), + 4 => simd_shuffle!( + a, + b, + [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19] + ), + 5 => simd_shuffle!( + a, + b, + [5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20] + ), + 6 => simd_shuffle!( + a, + b, + [6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21] + ), + 7 => simd_shuffle!( + a, + b, + [7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22] + ), + 8 => simd_shuffle!( + a, + b, + [8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23] + ), + 9 => simd_shuffle!( + a, + b, + [9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24] + ), + 10 => simd_shuffle!( + a, + b, + [10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25] + ), + 11 => simd_shuffle!( + a, + b, + [11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26] + ), + 12 => simd_shuffle!( + a, + b, + [12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27] + ), + 13 => simd_shuffle!( + a, + b, + [13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28] + ), + 14 => simd_shuffle!( + a, + b, + [14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29] + ), + 15 => simd_shuffle!( + a, + b, + [15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30] + ), + _ => unreachable_unchecked(), + } } } #[doc = "Extract vector from pair of vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -10054,92 +9368,92 @@ pub unsafe fn vextq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vextq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { +pub fn vextq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { static_assert_uimm_bits!(N, 4); - match N & 0b1111 { - 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), - 1 => simd_shuffle!( - a, - b, - [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16] - ), - 2 => simd_shuffle!( - a, - b, - [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17] - ), - 3 => simd_shuffle!( - a, - b, - [3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18] - ), - 4 => simd_shuffle!( - a, - b, - [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19] - ), - 5 => simd_shuffle!( - a, - b, - [5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20] - ), - 6 => simd_shuffle!( - a, - b, - [6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21] - ), - 7 => simd_shuffle!( - a, - b, - [7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22] - ), - 8 => simd_shuffle!( - a, - b, - [8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23] - ), - 9 => simd_shuffle!( - a, - b, - [9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24] - ), - 10 => simd_shuffle!( - a, - b, - [10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25] - ), - 11 => simd_shuffle!( - a, - b, - [11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26] - ), - 12 => simd_shuffle!( - a, - b, - [12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27] - ), - 13 => simd_shuffle!( - a, - b, - [13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28] - ), - 14 => simd_shuffle!( - a, - b, - [14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29] - ), - 15 => simd_shuffle!( - a, - b, - [15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30] - ), - _ => unreachable_unchecked(), + unsafe { + match N & 0b1111 { + 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), + 1 => simd_shuffle!( + a, + b, + [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16] + ), + 2 => simd_shuffle!( + a, + b, + [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17] + ), + 3 => simd_shuffle!( + a, + b, + [3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18] + ), + 4 => simd_shuffle!( + a, + b, + [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19] + ), + 5 => simd_shuffle!( + a, + b, + [5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20] + ), + 6 => simd_shuffle!( + a, + b, + [6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21] + ), + 7 => simd_shuffle!( + a, + b, + [7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22] + ), + 8 => simd_shuffle!( + a, + b, + [8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23] + ), + 9 => simd_shuffle!( + a, + b, + [9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24] + ), + 10 => simd_shuffle!( + a, + b, + [10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25] + ), + 11 => simd_shuffle!( + a, + b, + [11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26] + ), + 12 => simd_shuffle!( + a, + b, + [12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27] + ), + 13 => simd_shuffle!( + a, + b, + [13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28] + ), + 14 => simd_shuffle!( + a, + b, + [14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29] + ), + 15 => simd_shuffle!( + a, + b, + [15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30] + ), + _ => unreachable_unchecked(), + } } } #[doc = "Floating-point fused Multiply-Add to accumulator (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))] @@ -10149,18 +9463,16 @@ pub unsafe fn vextq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vfma_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t { +pub fn vfma_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "aarch64", link_name = "llvm.fma.v4f16")] #[cfg_attr(target_arch = "arm", link_name = "llvm.fma.v4f16")] fn _vfma_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t; } - _vfma_f16(b, c, a) + unsafe { _vfma_f16(b, c, a) } } #[doc = "Floating-point fused Multiply-Add to accumulator (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))] @@ -10170,18 +9482,16 @@ pub unsafe fn vfma_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float1 )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vfmaq_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t { +pub fn vfmaq_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "aarch64", link_name = "llvm.fma.v8f16")] #[cfg_attr(target_arch = "arm", link_name = "llvm.fma.v8f16")] fn _vfmaq_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t; } - _vfmaq_f16(b, c, a) + unsafe { _vfmaq_f16(b, c, a) } } #[doc = "Floating-point fused Multiply-Add to accumulator(vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] @@ -10198,18 +9508,16 @@ pub unsafe fn vfmaq_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vfma_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t { +pub fn vfma_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "aarch64", link_name = "llvm.fma.v2f32")] #[cfg_attr(target_arch = "arm", link_name = "llvm.fma.v2f32")] fn _vfma_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t; } - _vfma_f32(b, c, a) + unsafe { _vfma_f32(b, c, a) } } #[doc = "Floating-point fused Multiply-Add to accumulator(vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] @@ -10226,18 +9534,16 @@ pub unsafe fn vfma_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float3 target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vfmaq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t { +pub fn vfmaq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "aarch64", link_name = "llvm.fma.v4f32")] #[cfg_attr(target_arch = "arm", link_name = "llvm.fma.v4f32")] fn _vfmaq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t; } - _vfmaq_f32(b, c, a) + unsafe { _vfmaq_f32(b, c, a) } } #[doc = "Floating-point fused Multiply-Add to accumulator(vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_n_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] @@ -10254,13 +9560,11 @@ pub unsafe fn vfmaq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vfma_n_f32(a: float32x2_t, b: float32x2_t, c: f32) -> float32x2_t { +pub fn vfma_n_f32(a: float32x2_t, b: float32x2_t, c: f32) -> float32x2_t { vfma_f32(a, b, vdup_n_f32_vfp4(c)) } #[doc = "Floating-point fused Multiply-Add to accumulator(vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_n_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] @@ -10277,13 +9581,11 @@ pub unsafe fn vfma_n_f32(a: float32x2_t, b: float32x2_t, c: f32) -> float32x2_t target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vfmaq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t { +pub fn vfmaq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t { vfmaq_f32(a, b, vdupq_n_f32_vfp4(c)) } #[doc = "Floating-point fused multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] @@ -10294,14 +9596,14 @@ pub unsafe fn vfmaq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vfms_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t { - let b: float16x4_t = simd_neg(b); - vfma_f16(a, b, c) +pub fn vfms_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t { + unsafe { + let b: float16x4_t = simd_neg(b); + vfma_f16(a, b, c) + } } #[doc = "Floating-point fused multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] @@ -10312,14 +9614,14 @@ pub unsafe fn vfms_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float1 )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vfmsq_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t { - let b: float16x8_t = simd_neg(b); - vfmaq_f16(a, b, c) +pub fn vfmsq_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t { + unsafe { + let b: float16x8_t = simd_neg(b); + vfmaq_f16(a, b, c) + } } #[doc = "Floating-point fused multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] @@ -10336,14 +9638,14 @@ pub unsafe fn vfmsq_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vfms_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t { - let b: float32x2_t = simd_neg(b); - vfma_f32(a, b, c) +pub fn vfms_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t { + unsafe { + let b: float32x2_t = simd_neg(b); + vfma_f32(a, b, c) + } } #[doc = "Floating-point fused multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] @@ -10360,14 +9662,14 @@ pub unsafe fn vfms_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float3 target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vfmsq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t { - let b: float32x4_t = simd_neg(b); - vfmaq_f32(a, b, c) +pub fn vfmsq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t { + unsafe { + let b: float32x4_t = simd_neg(b); + vfmaq_f32(a, b, c) + } } #[doc = "Floating-point fused Multiply-subtract to accumulator(vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_n_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] @@ -10384,13 +9686,11 @@ pub unsafe fn vfmsq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vfms_n_f32(a: float32x2_t, b: float32x2_t, c: f32) -> float32x2_t { +pub fn vfms_n_f32(a: float32x2_t, b: float32x2_t, c: f32) -> float32x2_t { vfms_f32(a, b, vdup_n_f32_vfp4(c)) } #[doc = "Floating-point fused Multiply-subtract to accumulator(vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_n_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] @@ -10407,37 +9707,31 @@ pub unsafe fn vfms_n_f32(a: float32x2_t, b: float32x2_t, c: f32) -> float32x2_t target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vfmsq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t { +pub fn vfmsq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t { vfmsq_f32(a, b, vdupq_n_f32_vfp4(c)) } #[doc = "Duplicate vector element to vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vget_high_f16(a: float16x8_t) -> float16x4_t { - simd_shuffle!(a, a, [4, 5, 6, 7]) +pub fn vget_high_f16(a: float16x8_t) -> float16x4_t { + unsafe { simd_shuffle!(a, a, [4, 5, 6, 7]) } } #[doc = "Duplicate vector element to vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg_attr(test, assert_instr(nop))] -pub unsafe fn vget_low_f16(a: float16x8_t) -> float16x4_t { - simd_shuffle!(a, a, [0, 1, 2, 3]) +pub fn vget_low_f16(a: float16x8_t) -> float16x4_t { + unsafe { simd_shuffle!(a, a, [0, 1, 2, 3]) } } #[doc = "Duplicate vector element to scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[target_feature(enable = "neon,fp16")] @@ -10448,14 +9742,12 @@ pub unsafe fn vget_low_f16(a: float16x8_t) -> float16x4_t { )] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vget_lane_f16(a: float16x4_t) -> f16 { +pub fn vget_lane_f16(a: float16x4_t) -> f16 { static_assert_uimm_bits!(LANE, 2); - simd_extract!(a, LANE as u32) + unsafe { simd_extract!(a, LANE as u32) } } #[doc = "Duplicate vector element to scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[target_feature(enable = "neon,fp16")] @@ -10466,14 +9758,12 @@ pub unsafe fn vget_lane_f16(a: float16x4_t) -> f16 { )] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vgetq_lane_f16(a: float16x8_t) -> f16 { +pub fn vgetq_lane_f16(a: float16x8_t) -> f16 { static_assert_uimm_bits!(LANE, 3); - simd_extract!(a, LANE as u32) + unsafe { simd_extract!(a, LANE as u32) } } #[doc = "Halving add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -10490,7 +9780,7 @@ pub unsafe fn vgetq_lane_f16(a: float16x8_t) -> f16 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vhadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { +pub fn vhadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -10499,12 +9789,10 @@ pub unsafe fn vhadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhadds.v8i8")] fn _vhadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t; } - _vhadd_s8(a, b) + unsafe { _vhadd_s8(a, b) } } #[doc = "Halving add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -10521,7 +9809,7 @@ pub unsafe fn vhadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vhaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { +pub fn vhaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -10530,12 +9818,10 @@ pub unsafe fn vhaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhadds.v16i8")] fn _vhaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t; } - _vhaddq_s8(a, b) + unsafe { _vhaddq_s8(a, b) } } #[doc = "Halving add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -10552,7 +9838,7 @@ pub unsafe fn vhaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vhadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { +pub fn vhadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -10561,12 +9847,10 @@ pub unsafe fn vhadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhadds.v4i16")] fn _vhadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t; } - _vhadd_s16(a, b) + unsafe { _vhadd_s16(a, b) } } #[doc = "Halving add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -10583,7 +9867,7 @@ pub unsafe fn vhadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vhaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { +pub fn vhaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -10592,12 +9876,10 @@ pub unsafe fn vhaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhadds.v8i16")] fn _vhaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t; } - _vhaddq_s16(a, b) + unsafe { _vhaddq_s16(a, b) } } #[doc = "Halving add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -10614,7 +9896,7 @@ pub unsafe fn vhaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vhadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { +pub fn vhadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -10623,12 +9905,10 @@ pub unsafe fn vhadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhadds.v2i32")] fn _vhadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t; } - _vhadd_s32(a, b) + unsafe { _vhadd_s32(a, b) } } #[doc = "Halving add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -10645,7 +9925,7 @@ pub unsafe fn vhadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vhaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { +pub fn vhaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -10654,12 +9934,10 @@ pub unsafe fn vhaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhadds.v4i32")] fn _vhaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t; } - _vhaddq_s32(a, b) + unsafe { _vhaddq_s32(a, b) } } #[doc = "Halving add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -10676,7 +9954,7 @@ pub unsafe fn vhaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vhadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { +pub fn vhadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -10685,12 +9963,10 @@ pub unsafe fn vhadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhaddu.v8i8")] fn _vhadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t; } - _vhadd_u8(a, b) + unsafe { _vhadd_u8(a, b) } } #[doc = "Halving add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -10707,7 +9983,7 @@ pub unsafe fn vhadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vhaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { +pub fn vhaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -10716,12 +9992,10 @@ pub unsafe fn vhaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhaddu.v16i8")] fn _vhaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t; } - _vhaddq_u8(a, b) + unsafe { _vhaddq_u8(a, b) } } #[doc = "Halving add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -10738,7 +10012,7 @@ pub unsafe fn vhaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vhadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { +pub fn vhadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -10747,12 +10021,10 @@ pub unsafe fn vhadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhaddu.v4i16")] fn _vhadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t; } - _vhadd_u16(a, b) + unsafe { _vhadd_u16(a, b) } } #[doc = "Halving add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -10769,7 +10041,7 @@ pub unsafe fn vhadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vhaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { +pub fn vhaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -10778,12 +10050,10 @@ pub unsafe fn vhaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhaddu.v8i16")] fn _vhaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t; } - _vhaddq_u16(a, b) + unsafe { _vhaddq_u16(a, b) } } #[doc = "Halving add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -10800,7 +10070,7 @@ pub unsafe fn vhaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vhadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { +pub fn vhadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -10809,12 +10079,10 @@ pub unsafe fn vhadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhaddu.v2i32")] fn _vhadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t; } - _vhadd_u32(a, b) + unsafe { _vhadd_u32(a, b) } } #[doc = "Halving add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -10831,7 +10099,7 @@ pub unsafe fn vhadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vhaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { +pub fn vhaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -10840,12 +10108,10 @@ pub unsafe fn vhaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhaddu.v4i32")] fn _vhaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t; } - _vhaddq_u32(a, b) + unsafe { _vhaddq_u32(a, b) } } #[doc = "Signed halving subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -10862,7 +10128,7 @@ pub unsafe fn vhaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vhsub_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { +pub fn vhsub_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -10871,12 +10137,10 @@ pub unsafe fn vhsub_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubs.v4i16")] fn _vhsub_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t; } - _vhsub_s16(a, b) + unsafe { _vhsub_s16(a, b) } } #[doc = "Signed halving subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -10893,7 +10157,7 @@ pub unsafe fn vhsub_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vhsubq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { +pub fn vhsubq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -10902,12 +10166,10 @@ pub unsafe fn vhsubq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubs.v8i16")] fn _vhsubq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t; } - _vhsubq_s16(a, b) + unsafe { _vhsubq_s16(a, b) } } #[doc = "Signed halving subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -10924,7 +10186,7 @@ pub unsafe fn vhsubq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vhsub_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { +pub fn vhsub_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -10933,12 +10195,10 @@ pub unsafe fn vhsub_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubs.v2i32")] fn _vhsub_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t; } - _vhsub_s32(a, b) + unsafe { _vhsub_s32(a, b) } } #[doc = "Signed halving subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -10955,7 +10215,7 @@ pub unsafe fn vhsub_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vhsubq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { +pub fn vhsubq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -10964,12 +10224,10 @@ pub unsafe fn vhsubq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubs.v4i32")] fn _vhsubq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t; } - _vhsubq_s32(a, b) + unsafe { _vhsubq_s32(a, b) } } #[doc = "Signed halving subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -10986,7 +10244,7 @@ pub unsafe fn vhsubq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vhsub_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { +pub fn vhsub_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -10995,12 +10253,10 @@ pub unsafe fn vhsub_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubs.v8i8")] fn _vhsub_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t; } - _vhsub_s8(a, b) + unsafe { _vhsub_s8(a, b) } } #[doc = "Signed halving subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -11017,7 +10273,7 @@ pub unsafe fn vhsub_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vhsubq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { +pub fn vhsubq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -11026,12 +10282,10 @@ pub unsafe fn vhsubq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubs.v16i8")] fn _vhsubq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t; } - _vhsubq_s8(a, b) + unsafe { _vhsubq_s8(a, b) } } #[doc = "Signed halving subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -11048,7 +10302,7 @@ pub unsafe fn vhsubq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vhsub_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { +pub fn vhsub_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -11057,12 +10311,10 @@ pub unsafe fn vhsub_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubu.v8i8")] fn _vhsub_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t; } - _vhsub_u8(a, b) + unsafe { _vhsub_u8(a, b) } } #[doc = "Signed halving subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -11079,7 +10331,7 @@ pub unsafe fn vhsub_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vhsubq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { +pub fn vhsubq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -11088,12 +10340,10 @@ pub unsafe fn vhsubq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubu.v16i8")] fn _vhsubq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t; } - _vhsubq_u8(a, b) + unsafe { _vhsubq_u8(a, b) } } #[doc = "Signed halving subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -11110,7 +10360,7 @@ pub unsafe fn vhsubq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vhsub_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { +pub fn vhsub_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -11119,12 +10369,10 @@ pub unsafe fn vhsub_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubu.v4i16")] fn _vhsub_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t; } - _vhsub_u16(a, b) + unsafe { _vhsub_u16(a, b) } } #[doc = "Signed halving subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -11141,7 +10389,7 @@ pub unsafe fn vhsub_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vhsubq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { +pub fn vhsubq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -11150,12 +10398,10 @@ pub unsafe fn vhsubq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubu.v8i16")] fn _vhsubq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t; } - _vhsubq_u16(a, b) + unsafe { _vhsubq_u16(a, b) } } #[doc = "Signed halving subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -11172,7 +10418,7 @@ pub unsafe fn vhsubq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vhsub_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { +pub fn vhsub_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -11181,12 +10427,10 @@ pub unsafe fn vhsub_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubu.v2i32")] fn _vhsub_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t; } - _vhsub_u32(a, b) + unsafe { _vhsub_u32(a, b) } } #[doc = "Signed halving subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -11203,7 +10447,7 @@ pub unsafe fn vhsub_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vhsubq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { +pub fn vhsubq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -11212,7 +10456,7 @@ pub unsafe fn vhsubq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubu.v4i32")] fn _vhsubq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t; } - _vhsubq_u32(a, b) + unsafe { _vhsubq_u32(a, b) } } #[doc = "Load one single-element structure and replicate to all lanes of one register"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_f16)"] @@ -23178,8 +22422,6 @@ pub unsafe fn vld4q_p16(a: *const p16) -> poly16x8x4_t { } #[doc = "Maximum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] @@ -23189,7 +22431,7 @@ pub unsafe fn vld4q_p16(a: *const p16) -> poly16x8x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vmax_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { +pub fn vmax_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v4f16")] #[cfg_attr( @@ -23198,12 +22440,10 @@ pub unsafe fn vmax_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { )] fn _vmax_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t; } - _vmax_f16(a, b) + unsafe { _vmax_f16(a, b) } } #[doc = "Maximum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] @@ -23213,7 +22453,7 @@ pub unsafe fn vmax_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vmaxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { +pub fn vmaxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v8f16")] #[cfg_attr( @@ -23222,12 +22462,10 @@ pub unsafe fn vmaxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { )] fn _vmaxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t; } - _vmaxq_f16(a, b) + unsafe { _vmaxq_f16(a, b) } } #[doc = "Maximum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -23244,7 +22482,7 @@ pub unsafe fn vmaxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmax_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { +pub fn vmax_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v2f32")] #[cfg_attr( @@ -23253,12 +22491,10 @@ pub unsafe fn vmax_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { )] fn _vmax_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t; } - _vmax_f32(a, b) + unsafe { _vmax_f32(a, b) } } #[doc = "Maximum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -23275,7 +22511,7 @@ pub unsafe fn vmax_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmaxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { +pub fn vmaxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v4f32")] #[cfg_attr( @@ -23284,12 +22520,10 @@ pub unsafe fn vmaxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { )] fn _vmaxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t; } - _vmaxq_f32(a, b) + unsafe { _vmaxq_f32(a, b) } } #[doc = "Maximum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -23306,7 +22540,7 @@ pub unsafe fn vmaxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmax_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { +pub fn vmax_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v8i8")] #[cfg_attr( @@ -23315,12 +22549,10 @@ pub unsafe fn vmax_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { )] fn _vmax_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t; } - _vmax_s8(a, b) + unsafe { _vmax_s8(a, b) } } #[doc = "Maximum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -23337,7 +22569,7 @@ pub unsafe fn vmax_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmaxq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { +pub fn vmaxq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v16i8")] #[cfg_attr( @@ -23346,12 +22578,10 @@ pub unsafe fn vmaxq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { )] fn _vmaxq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t; } - _vmaxq_s8(a, b) + unsafe { _vmaxq_s8(a, b) } } #[doc = "Maximum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -23368,7 +22598,7 @@ pub unsafe fn vmaxq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmax_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { +pub fn vmax_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v4i16")] #[cfg_attr( @@ -23377,12 +22607,10 @@ pub unsafe fn vmax_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { )] fn _vmax_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t; } - _vmax_s16(a, b) + unsafe { _vmax_s16(a, b) } } #[doc = "Maximum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -23399,7 +22627,7 @@ pub unsafe fn vmax_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmaxq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { +pub fn vmaxq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v8i16")] #[cfg_attr( @@ -23408,12 +22636,10 @@ pub unsafe fn vmaxq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { )] fn _vmaxq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t; } - _vmaxq_s16(a, b) + unsafe { _vmaxq_s16(a, b) } } #[doc = "Maximum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -23430,7 +22656,7 @@ pub unsafe fn vmaxq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmax_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { +pub fn vmax_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v2i32")] #[cfg_attr( @@ -23439,12 +22665,10 @@ pub unsafe fn vmax_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { )] fn _vmax_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t; } - _vmax_s32(a, b) + unsafe { _vmax_s32(a, b) } } #[doc = "Maximum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -23461,7 +22685,7 @@ pub unsafe fn vmax_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmaxq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { +pub fn vmaxq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v4i32")] #[cfg_attr( @@ -23470,12 +22694,10 @@ pub unsafe fn vmaxq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { )] fn _vmaxq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t; } - _vmaxq_s32(a, b) + unsafe { _vmaxq_s32(a, b) } } #[doc = "Maximum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -23492,7 +22714,7 @@ pub unsafe fn vmaxq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmax_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { +pub fn vmax_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxu.v8i8")] #[cfg_attr( @@ -23501,12 +22723,10 @@ pub unsafe fn vmax_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { )] fn _vmax_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t; } - _vmax_u8(a, b) + unsafe { _vmax_u8(a, b) } } #[doc = "Maximum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -23523,7 +22743,7 @@ pub unsafe fn vmax_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmaxq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { +pub fn vmaxq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxu.v16i8")] #[cfg_attr( @@ -23532,12 +22752,10 @@ pub unsafe fn vmaxq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { )] fn _vmaxq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t; } - _vmaxq_u8(a, b) + unsafe { _vmaxq_u8(a, b) } } #[doc = "Maximum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -23554,7 +22772,7 @@ pub unsafe fn vmaxq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmax_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { +pub fn vmax_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxu.v4i16")] #[cfg_attr( @@ -23563,12 +22781,10 @@ pub unsafe fn vmax_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { )] fn _vmax_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t; } - _vmax_u16(a, b) + unsafe { _vmax_u16(a, b) } } #[doc = "Maximum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -23585,7 +22801,7 @@ pub unsafe fn vmax_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmaxq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { +pub fn vmaxq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxu.v8i16")] #[cfg_attr( @@ -23594,12 +22810,10 @@ pub unsafe fn vmaxq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { )] fn _vmaxq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t; } - _vmaxq_u16(a, b) + unsafe { _vmaxq_u16(a, b) } } #[doc = "Maximum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -23616,7 +22830,7 @@ pub unsafe fn vmaxq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmax_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { +pub fn vmax_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxu.v2i32")] #[cfg_attr( @@ -23625,12 +22839,10 @@ pub unsafe fn vmax_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { )] fn _vmax_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t; } - _vmax_u32(a, b) + unsafe { _vmax_u32(a, b) } } #[doc = "Maximum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -23647,7 +22859,7 @@ pub unsafe fn vmax_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmaxq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { +pub fn vmaxq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxu.v4i32")] #[cfg_attr( @@ -23656,12 +22868,10 @@ pub unsafe fn vmaxq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { )] fn _vmaxq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t; } - _vmaxq_u32(a, b) + unsafe { _vmaxq_u32(a, b) } } #[doc = "Floating-point Maximum Number (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnm_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmaxnm))] @@ -23671,7 +22881,7 @@ pub unsafe fn vmaxq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vmaxnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { +pub fn vmaxnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxnm.v4f16")] #[cfg_attr( @@ -23680,12 +22890,10 @@ pub unsafe fn vmaxnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { )] fn _vmaxnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t; } - _vmaxnm_f16(a, b) + unsafe { _vmaxnm_f16(a, b) } } #[doc = "Floating-point Maximum Number (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmq_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmaxnm))] @@ -23695,7 +22903,7 @@ pub unsafe fn vmaxnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vmaxnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { +pub fn vmaxnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxnm.v8f16")] #[cfg_attr( @@ -23704,12 +22912,10 @@ pub unsafe fn vmaxnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { )] fn _vmaxnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t; } - _vmaxnmq_f16(a, b) + unsafe { _vmaxnmq_f16(a, b) } } #[doc = "Floating-point Maximum Number (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnm_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))] @@ -23726,7 +22932,7 @@ pub unsafe fn vmaxnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmaxnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { +pub fn vmaxnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxnm.v2f32")] #[cfg_attr( @@ -23735,12 +22941,10 @@ pub unsafe fn vmaxnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { )] fn _vmaxnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t; } - _vmaxnm_f32(a, b) + unsafe { _vmaxnm_f32(a, b) } } #[doc = "Floating-point Maximum Number (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))] @@ -23757,7 +22961,7 @@ pub unsafe fn vmaxnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmaxnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { +pub fn vmaxnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxnm.v4f32")] #[cfg_attr( @@ -23766,12 +22970,10 @@ pub unsafe fn vmaxnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { )] fn _vmaxnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t; } - _vmaxnmq_f32(a, b) + unsafe { _vmaxnmq_f32(a, b) } } #[doc = "Minimum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] @@ -23781,7 +22983,7 @@ pub unsafe fn vmaxnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vmin_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { +pub fn vmin_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v4f16")] #[cfg_attr( @@ -23790,12 +22992,10 @@ pub unsafe fn vmin_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { )] fn _vmin_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t; } - _vmin_f16(a, b) + unsafe { _vmin_f16(a, b) } } #[doc = "Minimum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] @@ -23805,7 +23005,7 @@ pub unsafe fn vmin_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vminq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { +pub fn vminq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v8f16")] #[cfg_attr( @@ -23814,12 +23014,10 @@ pub unsafe fn vminq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { )] fn _vminq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t; } - _vminq_f16(a, b) + unsafe { _vminq_f16(a, b) } } #[doc = "Minimum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -23836,7 +23034,7 @@ pub unsafe fn vminq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmin_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { +pub fn vmin_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v2f32")] #[cfg_attr( @@ -23845,12 +23043,10 @@ pub unsafe fn vmin_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { )] fn _vmin_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t; } - _vmin_f32(a, b) + unsafe { _vmin_f32(a, b) } } #[doc = "Minimum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -23867,7 +23063,7 @@ pub unsafe fn vmin_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vminq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { +pub fn vminq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v4f32")] #[cfg_attr( @@ -23876,12 +23072,10 @@ pub unsafe fn vminq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { )] fn _vminq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t; } - _vminq_f32(a, b) + unsafe { _vminq_f32(a, b) } } #[doc = "Minimum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -23898,7 +23092,7 @@ pub unsafe fn vminq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmin_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { +pub fn vmin_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v8i8")] #[cfg_attr( @@ -23907,12 +23101,10 @@ pub unsafe fn vmin_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { )] fn _vmin_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t; } - _vmin_s8(a, b) + unsafe { _vmin_s8(a, b) } } #[doc = "Minimum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -23929,7 +23121,7 @@ pub unsafe fn vmin_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vminq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { +pub fn vminq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v16i8")] #[cfg_attr( @@ -23938,12 +23130,10 @@ pub unsafe fn vminq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { )] fn _vminq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t; } - _vminq_s8(a, b) + unsafe { _vminq_s8(a, b) } } #[doc = "Minimum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -23960,7 +23150,7 @@ pub unsafe fn vminq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmin_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { +pub fn vmin_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v4i16")] #[cfg_attr( @@ -23969,12 +23159,10 @@ pub unsafe fn vmin_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { )] fn _vmin_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t; } - _vmin_s16(a, b) + unsafe { _vmin_s16(a, b) } } #[doc = "Minimum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -23991,7 +23179,7 @@ pub unsafe fn vmin_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vminq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { +pub fn vminq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v8i16")] #[cfg_attr( @@ -24000,12 +23188,10 @@ pub unsafe fn vminq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { )] fn _vminq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t; } - _vminq_s16(a, b) + unsafe { _vminq_s16(a, b) } } #[doc = "Minimum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -24022,7 +23208,7 @@ pub unsafe fn vminq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmin_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { +pub fn vmin_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v2i32")] #[cfg_attr( @@ -24031,12 +23217,10 @@ pub unsafe fn vmin_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { )] fn _vmin_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t; } - _vmin_s32(a, b) + unsafe { _vmin_s32(a, b) } } #[doc = "Minimum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -24053,7 +23237,7 @@ pub unsafe fn vmin_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vminq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { +pub fn vminq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v4i32")] #[cfg_attr( @@ -24062,12 +23246,10 @@ pub unsafe fn vminq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { )] fn _vminq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t; } - _vminq_s32(a, b) + unsafe { _vminq_s32(a, b) } } #[doc = "Minimum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -24084,7 +23266,7 @@ pub unsafe fn vminq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmin_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { +pub fn vmin_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminu.v8i8")] #[cfg_attr( @@ -24093,12 +23275,10 @@ pub unsafe fn vmin_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { )] fn _vmin_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t; } - _vmin_u8(a, b) + unsafe { _vmin_u8(a, b) } } #[doc = "Minimum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -24115,7 +23295,7 @@ pub unsafe fn vmin_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vminq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { +pub fn vminq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminu.v16i8")] #[cfg_attr( @@ -24124,12 +23304,10 @@ pub unsafe fn vminq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { )] fn _vminq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t; } - _vminq_u8(a, b) + unsafe { _vminq_u8(a, b) } } #[doc = "Minimum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -24146,7 +23324,7 @@ pub unsafe fn vminq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmin_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { +pub fn vmin_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminu.v4i16")] #[cfg_attr( @@ -24155,12 +23333,10 @@ pub unsafe fn vmin_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { )] fn _vmin_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t; } - _vmin_u16(a, b) + unsafe { _vmin_u16(a, b) } } #[doc = "Minimum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -24177,7 +23353,7 @@ pub unsafe fn vmin_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vminq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { +pub fn vminq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminu.v8i16")] #[cfg_attr( @@ -24186,12 +23362,10 @@ pub unsafe fn vminq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { )] fn _vminq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t; } - _vminq_u16(a, b) + unsafe { _vminq_u16(a, b) } } #[doc = "Minimum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -24208,7 +23382,7 @@ pub unsafe fn vminq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmin_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { +pub fn vmin_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminu.v2i32")] #[cfg_attr( @@ -24217,12 +23391,10 @@ pub unsafe fn vmin_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { )] fn _vmin_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t; } - _vmin_u32(a, b) + unsafe { _vmin_u32(a, b) } } #[doc = "Minimum (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -24239,7 +23411,7 @@ pub unsafe fn vmin_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vminq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { +pub fn vminq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminu.v4i32")] #[cfg_attr( @@ -24248,12 +23420,10 @@ pub unsafe fn vminq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { )] fn _vminq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t; } - _vminq_u32(a, b) + unsafe { _vminq_u32(a, b) } } #[doc = "Floating-point Minimum Number (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnm_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vminnm))] @@ -24263,7 +23433,7 @@ pub unsafe fn vminq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vminnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { +pub fn vminnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminnm.v4f16")] #[cfg_attr( @@ -24272,12 +23442,10 @@ pub unsafe fn vminnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { )] fn _vminnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t; } - _vminnm_f16(a, b) + unsafe { _vminnm_f16(a, b) } } #[doc = "Floating-point Minimum Number (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmq_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vminnm))] @@ -24287,7 +23455,7 @@ pub unsafe fn vminnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vminnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { +pub fn vminnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminnm.v8f16")] #[cfg_attr( @@ -24296,12 +23464,10 @@ pub unsafe fn vminnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { )] fn _vminnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t; } - _vminnmq_f16(a, b) + unsafe { _vminnmq_f16(a, b) } } #[doc = "Floating-point Minimum Number (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnm_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))] @@ -24318,7 +23484,7 @@ pub unsafe fn vminnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vminnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { +pub fn vminnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminnm.v2f32")] #[cfg_attr( @@ -24327,12 +23493,10 @@ pub unsafe fn vminnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { )] fn _vminnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t; } - _vminnm_f32(a, b) + unsafe { _vminnm_f32(a, b) } } #[doc = "Floating-point Minimum Number (vector)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))] @@ -24349,7 +23513,7 @@ pub unsafe fn vminnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vminnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { +pub fn vminnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminnm.v4f32")] #[cfg_attr( @@ -24358,12 +23522,10 @@ pub unsafe fn vminnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { )] fn _vminnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t; } - _vminnmq_f32(a, b) + unsafe { _vminnmq_f32(a, b) } } #[doc = "Floating-point multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -24380,13 +23542,11 @@ pub unsafe fn vminnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmla_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t { - simd_add(a, simd_mul(b, c)) +pub fn vmla_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t { + unsafe { simd_add(a, simd_mul(b, c)) } } #[doc = "Floating-point multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -24403,13 +23563,11 @@ pub unsafe fn vmla_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float3 target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmlaq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t { - simd_add(a, simd_mul(b, c)) +pub fn vmlaq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t { + unsafe { simd_add(a, simd_mul(b, c)) } } #[doc = "Vector multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -24427,18 +23585,16 @@ pub unsafe fn vmlaq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmla_lane_f32( +pub fn vmla_lane_f32( a: float32x2_t, b: float32x2_t, c: float32x2_t, ) -> float32x2_t { static_assert_uimm_bits!(LANE, 1); - vmla_f32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) + unsafe { vmla_f32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } } #[doc = "Vector multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -24456,18 +23612,16 @@ pub unsafe fn vmla_lane_f32( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmla_laneq_f32( +pub fn vmla_laneq_f32( a: float32x2_t, b: float32x2_t, c: float32x4_t, ) -> float32x2_t { static_assert_uimm_bits!(LANE, 2); - vmla_f32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) + unsafe { vmla_f32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } } #[doc = "Vector multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -24485,22 +23639,22 @@ pub unsafe fn vmla_laneq_f32( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmlaq_lane_f32( +pub fn vmlaq_lane_f32( a: float32x4_t, b: float32x4_t, c: float32x2_t, ) -> float32x4_t { static_assert_uimm_bits!(LANE, 1); - vmlaq_f32( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) + unsafe { + vmlaq_f32( + a, + b, + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) + } } #[doc = "Vector multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -24518,22 +23672,22 @@ pub unsafe fn vmlaq_lane_f32( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmlaq_laneq_f32( +pub fn vmlaq_laneq_f32( a: float32x4_t, b: float32x4_t, c: float32x4_t, ) -> float32x4_t { static_assert_uimm_bits!(LANE, 2); - vmlaq_f32( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) + unsafe { + vmlaq_f32( + a, + b, + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) + } } #[doc = "Vector multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -24551,22 +23705,18 @@ pub unsafe fn vmlaq_laneq_f32( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmla_lane_s16( - a: int16x4_t, - b: int16x4_t, - c: int16x4_t, -) -> int16x4_t { +pub fn vmla_lane_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t { static_assert_uimm_bits!(LANE, 2); - vmla_s16( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) + unsafe { + vmla_s16( + a, + b, + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) + } } #[doc = "Vector multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -24584,22 +23734,18 @@ pub unsafe fn vmla_lane_s16( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmla_lane_u16( - a: uint16x4_t, - b: uint16x4_t, - c: uint16x4_t, -) -> uint16x4_t { +pub fn vmla_lane_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_t { static_assert_uimm_bits!(LANE, 2); - vmla_u16( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) + unsafe { + vmla_u16( + a, + b, + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) + } } #[doc = "Vector multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -24617,22 +23763,18 @@ pub unsafe fn vmla_lane_u16( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmla_laneq_s16( - a: int16x4_t, - b: int16x4_t, - c: int16x8_t, -) -> int16x4_t { +pub fn vmla_laneq_s16(a: int16x4_t, b: int16x4_t, c: int16x8_t) -> int16x4_t { static_assert_uimm_bits!(LANE, 3); - vmla_s16( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) + unsafe { + vmla_s16( + a, + b, + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) + } } #[doc = "Vector multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -24650,22 +23792,18 @@ pub unsafe fn vmla_laneq_s16( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmla_laneq_u16( - a: uint16x4_t, - b: uint16x4_t, - c: uint16x8_t, -) -> uint16x4_t { +pub fn vmla_laneq_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x8_t) -> uint16x4_t { static_assert_uimm_bits!(LANE, 3); - vmla_u16( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) + unsafe { + vmla_u16( + a, + b, + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) + } } #[doc = "Vector multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -24683,35 +23821,31 @@ pub unsafe fn vmla_laneq_u16( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmlaq_lane_s16( - a: int16x8_t, - b: int16x8_t, - c: int16x4_t, -) -> int16x8_t { +pub fn vmlaq_lane_s16(a: int16x8_t, b: int16x8_t, c: int16x4_t) -> int16x8_t { static_assert_uimm_bits!(LANE, 2); - vmlaq_s16( - a, - b, - simd_shuffle!( - c, - c, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) + unsafe { + vmlaq_s16( + a, + b, + simd_shuffle!( + c, + c, + [ + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32 + ] + ), + ) + } } #[doc = "Vector multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -24729,35 +23863,31 @@ pub unsafe fn vmlaq_lane_s16( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmlaq_lane_u16( - a: uint16x8_t, - b: uint16x8_t, - c: uint16x4_t, -) -> uint16x8_t { +pub fn vmlaq_lane_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x4_t) -> uint16x8_t { static_assert_uimm_bits!(LANE, 2); - vmlaq_u16( - a, - b, - simd_shuffle!( - c, - c, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) + unsafe { + vmlaq_u16( + a, + b, + simd_shuffle!( + c, + c, + [ + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32 + ] + ), + ) + } } #[doc = "Vector multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -24775,35 +23905,31 @@ pub unsafe fn vmlaq_lane_u16( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmlaq_laneq_s16( - a: int16x8_t, - b: int16x8_t, - c: int16x8_t, -) -> int16x8_t { +pub fn vmlaq_laneq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t { static_assert_uimm_bits!(LANE, 3); - vmlaq_s16( - a, - b, - simd_shuffle!( - c, - c, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) + unsafe { + vmlaq_s16( + a, + b, + simd_shuffle!( + c, + c, + [ + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32 + ] + ), + ) + } } #[doc = "Vector multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -24821,35 +23947,31 @@ pub unsafe fn vmlaq_laneq_s16( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmlaq_laneq_u16( - a: uint16x8_t, - b: uint16x8_t, - c: uint16x8_t, -) -> uint16x8_t { +pub fn vmlaq_laneq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t { static_assert_uimm_bits!(LANE, 3); - vmlaq_u16( - a, - b, - simd_shuffle!( - c, - c, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) + unsafe { + vmlaq_u16( + a, + b, + simd_shuffle!( + c, + c, + [ + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32 + ] + ), + ) + } } #[doc = "Vector multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -24867,18 +23989,12 @@ pub unsafe fn vmlaq_laneq_u16( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmla_lane_s32( - a: int32x2_t, - b: int32x2_t, - c: int32x2_t, -) -> int32x2_t { +pub fn vmla_lane_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t { static_assert_uimm_bits!(LANE, 1); - vmla_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) + unsafe { vmla_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } } #[doc = "Vector multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -24896,18 +24012,12 @@ pub unsafe fn vmla_lane_s32( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmla_lane_u32( - a: uint32x2_t, - b: uint32x2_t, - c: uint32x2_t, -) -> uint32x2_t { +pub fn vmla_lane_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_t { static_assert_uimm_bits!(LANE, 1); - vmla_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) + unsafe { vmla_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } } #[doc = "Vector multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -24925,18 +24035,12 @@ pub unsafe fn vmla_lane_u32( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmla_laneq_s32( - a: int32x2_t, - b: int32x2_t, - c: int32x4_t, -) -> int32x2_t { +pub fn vmla_laneq_s32(a: int32x2_t, b: int32x2_t, c: int32x4_t) -> int32x2_t { static_assert_uimm_bits!(LANE, 2); - vmla_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) + unsafe { vmla_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } } #[doc = "Vector multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -24954,18 +24058,12 @@ pub unsafe fn vmla_laneq_s32( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmla_laneq_u32( - a: uint32x2_t, - b: uint32x2_t, - c: uint32x4_t, -) -> uint32x2_t { +pub fn vmla_laneq_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x4_t) -> uint32x2_t { static_assert_uimm_bits!(LANE, 2); - vmla_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) + unsafe { vmla_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } } #[doc = "Vector multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -24983,22 +24081,18 @@ pub unsafe fn vmla_laneq_u32( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmlaq_lane_s32( - a: int32x4_t, - b: int32x4_t, - c: int32x2_t, -) -> int32x4_t { +pub fn vmlaq_lane_s32(a: int32x4_t, b: int32x4_t, c: int32x2_t) -> int32x4_t { static_assert_uimm_bits!(LANE, 1); - vmlaq_s32( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) + unsafe { + vmlaq_s32( + a, + b, + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) + } } #[doc = "Vector multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -25016,22 +24110,18 @@ pub unsafe fn vmlaq_lane_s32( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmlaq_lane_u32( - a: uint32x4_t, - b: uint32x4_t, - c: uint32x2_t, -) -> uint32x4_t { +pub fn vmlaq_lane_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x2_t) -> uint32x4_t { static_assert_uimm_bits!(LANE, 1); - vmlaq_u32( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) + unsafe { + vmlaq_u32( + a, + b, + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) + } } #[doc = "Vector multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -25049,22 +24139,18 @@ pub unsafe fn vmlaq_lane_u32( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmlaq_laneq_s32( - a: int32x4_t, - b: int32x4_t, - c: int32x4_t, -) -> int32x4_t { +pub fn vmlaq_laneq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t { static_assert_uimm_bits!(LANE, 2); - vmlaq_s32( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) + unsafe { + vmlaq_s32( + a, + b, + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) + } } #[doc = "Vector multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -25082,22 +24168,18 @@ pub unsafe fn vmlaq_laneq_s32( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmlaq_laneq_u32( - a: uint32x4_t, - b: uint32x4_t, - c: uint32x4_t, -) -> uint32x4_t { +pub fn vmlaq_laneq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t { static_assert_uimm_bits!(LANE, 2); - vmlaq_u32( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) + unsafe { + vmlaq_u32( + a, + b, + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) + } } #[doc = "Vector multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -25114,13 +24196,11 @@ pub unsafe fn vmlaq_laneq_u32( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmla_n_f32(a: float32x2_t, b: float32x2_t, c: f32) -> float32x2_t { +pub fn vmla_n_f32(a: float32x2_t, b: float32x2_t, c: f32) -> float32x2_t { vmla_f32(a, b, vdup_n_f32(c)) } #[doc = "Vector multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -25137,13 +24217,11 @@ pub unsafe fn vmla_n_f32(a: float32x2_t, b: float32x2_t, c: f32) -> float32x2_t target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmlaq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t { +pub fn vmlaq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t { vmlaq_f32(a, b, vdupq_n_f32(c)) } #[doc = "Vector multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -25160,13 +24238,11 @@ pub unsafe fn vmlaq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmla_n_s16(a: int16x4_t, b: int16x4_t, c: i16) -> int16x4_t { +pub fn vmla_n_s16(a: int16x4_t, b: int16x4_t, c: i16) -> int16x4_t { vmla_s16(a, b, vdup_n_s16(c)) } #[doc = "Vector multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -25183,13 +24259,11 @@ pub unsafe fn vmla_n_s16(a: int16x4_t, b: int16x4_t, c: i16) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmlaq_n_s16(a: int16x8_t, b: int16x8_t, c: i16) -> int16x8_t { +pub fn vmlaq_n_s16(a: int16x8_t, b: int16x8_t, c: i16) -> int16x8_t { vmlaq_s16(a, b, vdupq_n_s16(c)) } #[doc = "Vector multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -25206,13 +24280,11 @@ pub unsafe fn vmlaq_n_s16(a: int16x8_t, b: int16x8_t, c: i16) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmla_n_u16(a: uint16x4_t, b: uint16x4_t, c: u16) -> uint16x4_t { +pub fn vmla_n_u16(a: uint16x4_t, b: uint16x4_t, c: u16) -> uint16x4_t { vmla_u16(a, b, vdup_n_u16(c)) } #[doc = "Vector multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -25229,13 +24301,11 @@ pub unsafe fn vmla_n_u16(a: uint16x4_t, b: uint16x4_t, c: u16) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmlaq_n_u16(a: uint16x8_t, b: uint16x8_t, c: u16) -> uint16x8_t { +pub fn vmlaq_n_u16(a: uint16x8_t, b: uint16x8_t, c: u16) -> uint16x8_t { vmlaq_u16(a, b, vdupq_n_u16(c)) } #[doc = "Vector multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -25252,13 +24322,11 @@ pub unsafe fn vmlaq_n_u16(a: uint16x8_t, b: uint16x8_t, c: u16) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmla_n_s32(a: int32x2_t, b: int32x2_t, c: i32) -> int32x2_t { +pub fn vmla_n_s32(a: int32x2_t, b: int32x2_t, c: i32) -> int32x2_t { vmla_s32(a, b, vdup_n_s32(c)) } #[doc = "Vector multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -25275,13 +24343,11 @@ pub unsafe fn vmla_n_s32(a: int32x2_t, b: int32x2_t, c: i32) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmlaq_n_s32(a: int32x4_t, b: int32x4_t, c: i32) -> int32x4_t { +pub fn vmlaq_n_s32(a: int32x4_t, b: int32x4_t, c: i32) -> int32x4_t { vmlaq_s32(a, b, vdupq_n_s32(c)) } #[doc = "Vector multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -25298,13 +24364,11 @@ pub unsafe fn vmlaq_n_s32(a: int32x4_t, b: int32x4_t, c: i32) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmla_n_u32(a: uint32x2_t, b: uint32x2_t, c: u32) -> uint32x2_t { +pub fn vmla_n_u32(a: uint32x2_t, b: uint32x2_t, c: u32) -> uint32x2_t { vmla_u32(a, b, vdup_n_u32(c)) } #[doc = "Vector multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -25321,13 +24385,11 @@ pub unsafe fn vmla_n_u32(a: uint32x2_t, b: uint32x2_t, c: u32) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmlaq_n_u32(a: uint32x4_t, b: uint32x4_t, c: u32) -> uint32x4_t { +pub fn vmlaq_n_u32(a: uint32x4_t, b: uint32x4_t, c: u32) -> uint32x4_t { vmlaq_u32(a, b, vdupq_n_u32(c)) } #[doc = "Multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -25344,13 +24406,11 @@ pub unsafe fn vmlaq_n_u32(a: uint32x4_t, b: uint32x4_t, c: u32) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmla_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t { - simd_add(a, simd_mul(b, c)) +pub fn vmla_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t { + unsafe { simd_add(a, simd_mul(b, c)) } } #[doc = "Multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -25367,13 +24427,11 @@ pub unsafe fn vmla_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmlaq_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t { - simd_add(a, simd_mul(b, c)) +pub fn vmlaq_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t { + unsafe { simd_add(a, simd_mul(b, c)) } } #[doc = "Multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -25390,13 +24448,11 @@ pub unsafe fn vmlaq_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmla_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t { - simd_add(a, simd_mul(b, c)) +pub fn vmla_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t { + unsafe { simd_add(a, simd_mul(b, c)) } } #[doc = "Multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -25413,13 +24469,11 @@ pub unsafe fn vmla_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmlaq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t { - simd_add(a, simd_mul(b, c)) +pub fn vmlaq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t { + unsafe { simd_add(a, simd_mul(b, c)) } } #[doc = "Multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -25436,13 +24490,11 @@ pub unsafe fn vmlaq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmla_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t { - simd_add(a, simd_mul(b, c)) +pub fn vmla_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t { + unsafe { simd_add(a, simd_mul(b, c)) } } #[doc = "Multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -25459,13 +24511,11 @@ pub unsafe fn vmla_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmlaq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t { - simd_add(a, simd_mul(b, c)) +pub fn vmlaq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t { + unsafe { simd_add(a, simd_mul(b, c)) } } #[doc = "Multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -25482,13 +24532,11 @@ pub unsafe fn vmlaq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmla_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t { - simd_add(a, simd_mul(b, c)) +pub fn vmla_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t { + unsafe { simd_add(a, simd_mul(b, c)) } } #[doc = "Multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -25505,13 +24553,11 @@ pub unsafe fn vmla_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmlaq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t { - simd_add(a, simd_mul(b, c)) +pub fn vmlaq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t { + unsafe { simd_add(a, simd_mul(b, c)) } } #[doc = "Multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -25528,13 +24574,11 @@ pub unsafe fn vmlaq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_ target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmla_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_t { - simd_add(a, simd_mul(b, c)) +pub fn vmla_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_t { + unsafe { simd_add(a, simd_mul(b, c)) } } #[doc = "Multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -25551,13 +24595,11 @@ pub unsafe fn vmla_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_ target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmlaq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t { - simd_add(a, simd_mul(b, c)) +pub fn vmlaq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t { + unsafe { simd_add(a, simd_mul(b, c)) } } #[doc = "Multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -25574,13 +24616,11 @@ pub unsafe fn vmlaq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8 target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmla_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_t { - simd_add(a, simd_mul(b, c)) +pub fn vmla_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_t { + unsafe { simd_add(a, simd_mul(b, c)) } } #[doc = "Multiply-add to accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -25597,13 +24637,11 @@ pub unsafe fn vmla_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_ target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmlaq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t { - simd_add(a, simd_mul(b, c)) +pub fn vmlaq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t { + unsafe { simd_add(a, simd_mul(b, c)) } } #[doc = "Vector widening multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_lane_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -25621,22 +24659,18 @@ pub unsafe fn vmlaq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4 target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmlal_lane_s16( - a: int32x4_t, - b: int16x4_t, - c: int16x4_t, -) -> int32x4_t { +pub fn vmlal_lane_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t { static_assert_uimm_bits!(LANE, 2); - vmlal_s16( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) + unsafe { + vmlal_s16( + a, + b, + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) + } } #[doc = "Vector widening multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_laneq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -25654,22 +24688,18 @@ pub unsafe fn vmlal_lane_s16( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmlal_laneq_s16( - a: int32x4_t, - b: int16x4_t, - c: int16x8_t, -) -> int32x4_t { +pub fn vmlal_laneq_s16(a: int32x4_t, b: int16x4_t, c: int16x8_t) -> int32x4_t { static_assert_uimm_bits!(LANE, 3); - vmlal_s16( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) + unsafe { + vmlal_s16( + a, + b, + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) + } } #[doc = "Vector widening multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_lane_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -25687,18 +24717,12 @@ pub unsafe fn vmlal_laneq_s16( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmlal_lane_s32( - a: int64x2_t, - b: int32x2_t, - c: int32x2_t, -) -> int64x2_t { +pub fn vmlal_lane_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t { static_assert_uimm_bits!(LANE, 1); - vmlal_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) + unsafe { vmlal_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } } #[doc = "Vector widening multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_laneq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -25716,18 +24740,12 @@ pub unsafe fn vmlal_lane_s32( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmlal_laneq_s32( - a: int64x2_t, - b: int32x2_t, - c: int32x4_t, -) -> int64x2_t { +pub fn vmlal_laneq_s32(a: int64x2_t, b: int32x2_t, c: int32x4_t) -> int64x2_t { static_assert_uimm_bits!(LANE, 2); - vmlal_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) + unsafe { vmlal_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } } #[doc = "Vector widening multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_lane_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -25745,22 +24763,18 @@ pub unsafe fn vmlal_laneq_s32( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmlal_lane_u16( - a: uint32x4_t, - b: uint16x4_t, - c: uint16x4_t, -) -> uint32x4_t { +pub fn vmlal_lane_u16(a: uint32x4_t, b: uint16x4_t, c: uint16x4_t) -> uint32x4_t { static_assert_uimm_bits!(LANE, 2); - vmlal_u16( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) + unsafe { + vmlal_u16( + a, + b, + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) + } } #[doc = "Vector widening multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_laneq_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -25778,22 +24792,18 @@ pub unsafe fn vmlal_lane_u16( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmlal_laneq_u16( - a: uint32x4_t, - b: uint16x4_t, - c: uint16x8_t, -) -> uint32x4_t { +pub fn vmlal_laneq_u16(a: uint32x4_t, b: uint16x4_t, c: uint16x8_t) -> uint32x4_t { static_assert_uimm_bits!(LANE, 3); - vmlal_u16( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) + unsafe { + vmlal_u16( + a, + b, + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) + } } #[doc = "Vector widening multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_lane_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -25811,18 +24821,12 @@ pub unsafe fn vmlal_laneq_u16( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmlal_lane_u32( - a: uint64x2_t, - b: uint32x2_t, - c: uint32x2_t, -) -> uint64x2_t { +pub fn vmlal_lane_u32(a: uint64x2_t, b: uint32x2_t, c: uint32x2_t) -> uint64x2_t { static_assert_uimm_bits!(LANE, 1); - vmlal_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) + unsafe { vmlal_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } } #[doc = "Vector widening multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_laneq_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -25840,18 +24844,12 @@ pub unsafe fn vmlal_lane_u32( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmlal_laneq_u32( - a: uint64x2_t, - b: uint32x2_t, - c: uint32x4_t, -) -> uint64x2_t { +pub fn vmlal_laneq_u32(a: uint64x2_t, b: uint32x2_t, c: uint32x4_t) -> uint64x2_t { static_assert_uimm_bits!(LANE, 2); - vmlal_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) + unsafe { vmlal_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } } #[doc = "Vector widening multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_n_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -25868,13 +24866,11 @@ pub unsafe fn vmlal_laneq_u32( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmlal_n_s16(a: int32x4_t, b: int16x4_t, c: i16) -> int32x4_t { +pub fn vmlal_n_s16(a: int32x4_t, b: int16x4_t, c: i16) -> int32x4_t { vmlal_s16(a, b, vdup_n_s16(c)) } #[doc = "Vector widening multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_n_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -25891,13 +24887,11 @@ pub unsafe fn vmlal_n_s16(a: int32x4_t, b: int16x4_t, c: i16) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmlal_n_s32(a: int64x2_t, b: int32x2_t, c: i32) -> int64x2_t { +pub fn vmlal_n_s32(a: int64x2_t, b: int32x2_t, c: i32) -> int64x2_t { vmlal_s32(a, b, vdup_n_s32(c)) } #[doc = "Vector widening multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_n_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -25914,13 +24908,11 @@ pub unsafe fn vmlal_n_s32(a: int64x2_t, b: int32x2_t, c: i32) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmlal_n_u16(a: uint32x4_t, b: uint16x4_t, c: u16) -> uint32x4_t { +pub fn vmlal_n_u16(a: uint32x4_t, b: uint16x4_t, c: u16) -> uint32x4_t { vmlal_u16(a, b, vdup_n_u16(c)) } #[doc = "Vector widening multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_n_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -25937,13 +24929,11 @@ pub unsafe fn vmlal_n_u16(a: uint32x4_t, b: uint16x4_t, c: u16) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmlal_n_u32(a: uint64x2_t, b: uint32x2_t, c: u32) -> uint64x2_t { +pub fn vmlal_n_u32(a: uint64x2_t, b: uint32x2_t, c: u32) -> uint64x2_t { vmlal_u32(a, b, vdup_n_u32(c)) } #[doc = "Signed multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -25960,13 +24950,11 @@ pub unsafe fn vmlal_n_u32(a: uint64x2_t, b: uint32x2_t, c: u32) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmlal_s8(a: int16x8_t, b: int8x8_t, c: int8x8_t) -> int16x8_t { - simd_add(a, vmull_s8(b, c)) +pub fn vmlal_s8(a: int16x8_t, b: int8x8_t, c: int8x8_t) -> int16x8_t { + unsafe { simd_add(a, vmull_s8(b, c)) } } #[doc = "Signed multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -25983,13 +24971,11 @@ pub unsafe fn vmlal_s8(a: int16x8_t, b: int8x8_t, c: int8x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmlal_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t { - simd_add(a, vmull_s16(b, c)) +pub fn vmlal_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t { + unsafe { simd_add(a, vmull_s16(b, c)) } } #[doc = "Signed multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -26006,13 +24992,11 @@ pub unsafe fn vmlal_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmlal_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t { - simd_add(a, vmull_s32(b, c)) +pub fn vmlal_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t { + unsafe { simd_add(a, vmull_s32(b, c)) } } #[doc = "Unsigned multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -26029,13 +25013,11 @@ pub unsafe fn vmlal_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmlal_u8(a: uint16x8_t, b: uint8x8_t, c: uint8x8_t) -> uint16x8_t { - simd_add(a, vmull_u8(b, c)) +pub fn vmlal_u8(a: uint16x8_t, b: uint8x8_t, c: uint8x8_t) -> uint16x8_t { + unsafe { simd_add(a, vmull_u8(b, c)) } } #[doc = "Unsigned multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -26052,13 +25034,11 @@ pub unsafe fn vmlal_u8(a: uint16x8_t, b: uint8x8_t, c: uint8x8_t) -> uint16x8_t target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmlal_u16(a: uint32x4_t, b: uint16x4_t, c: uint16x4_t) -> uint32x4_t { - simd_add(a, vmull_u16(b, c)) +pub fn vmlal_u16(a: uint32x4_t, b: uint16x4_t, c: uint16x4_t) -> uint32x4_t { + unsafe { simd_add(a, vmull_u16(b, c)) } } #[doc = "Unsigned multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -26075,13 +25055,11 @@ pub unsafe fn vmlal_u16(a: uint32x4_t, b: uint16x4_t, c: uint16x4_t) -> uint32x4 target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmlal_u32(a: uint64x2_t, b: uint32x2_t, c: uint32x2_t) -> uint64x2_t { - simd_add(a, vmull_u32(b, c)) +pub fn vmlal_u32(a: uint64x2_t, b: uint32x2_t, c: uint32x2_t) -> uint64x2_t { + unsafe { simd_add(a, vmull_u32(b, c)) } } #[doc = "Floating-point multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -26098,13 +25076,11 @@ pub unsafe fn vmlal_u32(a: uint64x2_t, b: uint32x2_t, c: uint32x2_t) -> uint64x2 target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmls_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t { - simd_sub(a, simd_mul(b, c)) +pub fn vmls_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t { + unsafe { simd_sub(a, simd_mul(b, c)) } } #[doc = "Floating-point multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -26121,13 +25097,11 @@ pub unsafe fn vmls_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float3 target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmlsq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t { - simd_sub(a, simd_mul(b, c)) +pub fn vmlsq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t { + unsafe { simd_sub(a, simd_mul(b, c)) } } #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -26145,18 +25119,16 @@ pub unsafe fn vmlsq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmls_lane_f32( +pub fn vmls_lane_f32( a: float32x2_t, b: float32x2_t, c: float32x2_t, ) -> float32x2_t { static_assert_uimm_bits!(LANE, 1); - vmls_f32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) + unsafe { vmls_f32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } } #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -26174,18 +25146,16 @@ pub unsafe fn vmls_lane_f32( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmls_laneq_f32( +pub fn vmls_laneq_f32( a: float32x2_t, b: float32x2_t, c: float32x4_t, ) -> float32x2_t { static_assert_uimm_bits!(LANE, 2); - vmls_f32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) + unsafe { vmls_f32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } } #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -26203,22 +25173,22 @@ pub unsafe fn vmls_laneq_f32( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmlsq_lane_f32( +pub fn vmlsq_lane_f32( a: float32x4_t, b: float32x4_t, c: float32x2_t, ) -> float32x4_t { static_assert_uimm_bits!(LANE, 1); - vmlsq_f32( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) + unsafe { + vmlsq_f32( + a, + b, + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) + } } #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -26236,22 +25206,22 @@ pub unsafe fn vmlsq_lane_f32( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmlsq_laneq_f32( +pub fn vmlsq_laneq_f32( a: float32x4_t, b: float32x4_t, c: float32x4_t, ) -> float32x4_t { static_assert_uimm_bits!(LANE, 2); - vmlsq_f32( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) + unsafe { + vmlsq_f32( + a, + b, + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) + } } #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -26269,22 +25239,18 @@ pub unsafe fn vmlsq_laneq_f32( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmls_lane_s16( - a: int16x4_t, - b: int16x4_t, - c: int16x4_t, -) -> int16x4_t { +pub fn vmls_lane_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t { static_assert_uimm_bits!(LANE, 2); - vmls_s16( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) + unsafe { + vmls_s16( + a, + b, + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) + } } #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -26302,22 +25268,18 @@ pub unsafe fn vmls_lane_s16( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmls_lane_u16( - a: uint16x4_t, - b: uint16x4_t, - c: uint16x4_t, -) -> uint16x4_t { +pub fn vmls_lane_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_t { static_assert_uimm_bits!(LANE, 2); - vmls_u16( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) + unsafe { + vmls_u16( + a, + b, + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) + } } #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -26335,22 +25297,18 @@ pub unsafe fn vmls_lane_u16( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmls_laneq_s16( - a: int16x4_t, - b: int16x4_t, - c: int16x8_t, -) -> int16x4_t { +pub fn vmls_laneq_s16(a: int16x4_t, b: int16x4_t, c: int16x8_t) -> int16x4_t { static_assert_uimm_bits!(LANE, 3); - vmls_s16( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) + unsafe { + vmls_s16( + a, + b, + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) + } } #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -26368,22 +25326,18 @@ pub unsafe fn vmls_laneq_s16( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmls_laneq_u16( - a: uint16x4_t, - b: uint16x4_t, - c: uint16x8_t, -) -> uint16x4_t { +pub fn vmls_laneq_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x8_t) -> uint16x4_t { static_assert_uimm_bits!(LANE, 3); - vmls_u16( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) + unsafe { + vmls_u16( + a, + b, + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) + } } #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -26401,35 +25355,31 @@ pub unsafe fn vmls_laneq_u16( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmlsq_lane_s16( - a: int16x8_t, - b: int16x8_t, - c: int16x4_t, -) -> int16x8_t { +pub fn vmlsq_lane_s16(a: int16x8_t, b: int16x8_t, c: int16x4_t) -> int16x8_t { static_assert_uimm_bits!(LANE, 2); - vmlsq_s16( - a, - b, - simd_shuffle!( - c, - c, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) + unsafe { + vmlsq_s16( + a, + b, + simd_shuffle!( + c, + c, + [ + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32 + ] + ), + ) + } } #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -26447,35 +25397,31 @@ pub unsafe fn vmlsq_lane_s16( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmlsq_lane_u16( - a: uint16x8_t, - b: uint16x8_t, - c: uint16x4_t, -) -> uint16x8_t { +pub fn vmlsq_lane_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x4_t) -> uint16x8_t { static_assert_uimm_bits!(LANE, 2); - vmlsq_u16( - a, - b, - simd_shuffle!( - c, - c, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) + unsafe { + vmlsq_u16( + a, + b, + simd_shuffle!( + c, + c, + [ + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32 + ] + ), + ) + } } #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -26493,35 +25439,31 @@ pub unsafe fn vmlsq_lane_u16( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmlsq_laneq_s16( - a: int16x8_t, - b: int16x8_t, - c: int16x8_t, -) -> int16x8_t { +pub fn vmlsq_laneq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t { static_assert_uimm_bits!(LANE, 3); - vmlsq_s16( - a, - b, - simd_shuffle!( - c, - c, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) + unsafe { + vmlsq_s16( + a, + b, + simd_shuffle!( + c, + c, + [ + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32 + ] + ), + ) + } } #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -26539,35 +25481,31 @@ pub unsafe fn vmlsq_laneq_s16( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmlsq_laneq_u16( - a: uint16x8_t, - b: uint16x8_t, - c: uint16x8_t, -) -> uint16x8_t { +pub fn vmlsq_laneq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t { static_assert_uimm_bits!(LANE, 3); - vmlsq_u16( - a, - b, - simd_shuffle!( - c, - c, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) + unsafe { + vmlsq_u16( + a, + b, + simd_shuffle!( + c, + c, + [ + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32 + ] + ), + ) + } } #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -26585,18 +25523,12 @@ pub unsafe fn vmlsq_laneq_u16( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmls_lane_s32( - a: int32x2_t, - b: int32x2_t, - c: int32x2_t, -) -> int32x2_t { +pub fn vmls_lane_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t { static_assert_uimm_bits!(LANE, 1); - vmls_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) + unsafe { vmls_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } } #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -26614,18 +25546,12 @@ pub unsafe fn vmls_lane_s32( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmls_lane_u32( - a: uint32x2_t, - b: uint32x2_t, - c: uint32x2_t, -) -> uint32x2_t { +pub fn vmls_lane_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_t { static_assert_uimm_bits!(LANE, 1); - vmls_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) + unsafe { vmls_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } } #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -26643,18 +25569,12 @@ pub unsafe fn vmls_lane_u32( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmls_laneq_s32( - a: int32x2_t, - b: int32x2_t, - c: int32x4_t, -) -> int32x2_t { +pub fn vmls_laneq_s32(a: int32x2_t, b: int32x2_t, c: int32x4_t) -> int32x2_t { static_assert_uimm_bits!(LANE, 2); - vmls_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) + unsafe { vmls_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } } #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -26672,18 +25592,12 @@ pub unsafe fn vmls_laneq_s32( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmls_laneq_u32( - a: uint32x2_t, - b: uint32x2_t, - c: uint32x4_t, -) -> uint32x2_t { +pub fn vmls_laneq_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x4_t) -> uint32x2_t { static_assert_uimm_bits!(LANE, 2); - vmls_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) + unsafe { vmls_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } } #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -26701,22 +25615,18 @@ pub unsafe fn vmls_laneq_u32( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmlsq_lane_s32( - a: int32x4_t, - b: int32x4_t, - c: int32x2_t, -) -> int32x4_t { +pub fn vmlsq_lane_s32(a: int32x4_t, b: int32x4_t, c: int32x2_t) -> int32x4_t { static_assert_uimm_bits!(LANE, 1); - vmlsq_s32( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) + unsafe { + vmlsq_s32( + a, + b, + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) + } } #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -26734,22 +25644,18 @@ pub unsafe fn vmlsq_lane_s32( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmlsq_lane_u32( - a: uint32x4_t, - b: uint32x4_t, - c: uint32x2_t, -) -> uint32x4_t { +pub fn vmlsq_lane_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x2_t) -> uint32x4_t { static_assert_uimm_bits!(LANE, 1); - vmlsq_u32( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) + unsafe { + vmlsq_u32( + a, + b, + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) + } } #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -26767,22 +25673,18 @@ pub unsafe fn vmlsq_lane_u32( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmlsq_laneq_s32( - a: int32x4_t, - b: int32x4_t, - c: int32x4_t, -) -> int32x4_t { +pub fn vmlsq_laneq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t { static_assert_uimm_bits!(LANE, 2); - vmlsq_s32( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) + unsafe { + vmlsq_s32( + a, + b, + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) + } } #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -26800,22 +25702,18 @@ pub unsafe fn vmlsq_laneq_s32( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmlsq_laneq_u32( - a: uint32x4_t, - b: uint32x4_t, - c: uint32x4_t, -) -> uint32x4_t { +pub fn vmlsq_laneq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t { static_assert_uimm_bits!(LANE, 2); - vmlsq_u32( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) + unsafe { + vmlsq_u32( + a, + b, + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) + } } #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -26832,13 +25730,11 @@ pub unsafe fn vmlsq_laneq_u32( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmls_n_f32(a: float32x2_t, b: float32x2_t, c: f32) -> float32x2_t { +pub fn vmls_n_f32(a: float32x2_t, b: float32x2_t, c: f32) -> float32x2_t { vmls_f32(a, b, vdup_n_f32(c)) } #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -26855,13 +25751,11 @@ pub unsafe fn vmls_n_f32(a: float32x2_t, b: float32x2_t, c: f32) -> float32x2_t target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmlsq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t { +pub fn vmlsq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t { vmlsq_f32(a, b, vdupq_n_f32(c)) } #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -26878,13 +25772,11 @@ pub unsafe fn vmlsq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmls_n_s16(a: int16x4_t, b: int16x4_t, c: i16) -> int16x4_t { +pub fn vmls_n_s16(a: int16x4_t, b: int16x4_t, c: i16) -> int16x4_t { vmls_s16(a, b, vdup_n_s16(c)) } #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -26901,13 +25793,11 @@ pub unsafe fn vmls_n_s16(a: int16x4_t, b: int16x4_t, c: i16) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmlsq_n_s16(a: int16x8_t, b: int16x8_t, c: i16) -> int16x8_t { +pub fn vmlsq_n_s16(a: int16x8_t, b: int16x8_t, c: i16) -> int16x8_t { vmlsq_s16(a, b, vdupq_n_s16(c)) } #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -26924,13 +25814,11 @@ pub unsafe fn vmlsq_n_s16(a: int16x8_t, b: int16x8_t, c: i16) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmls_n_u16(a: uint16x4_t, b: uint16x4_t, c: u16) -> uint16x4_t { +pub fn vmls_n_u16(a: uint16x4_t, b: uint16x4_t, c: u16) -> uint16x4_t { vmls_u16(a, b, vdup_n_u16(c)) } #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -26947,13 +25835,11 @@ pub unsafe fn vmls_n_u16(a: uint16x4_t, b: uint16x4_t, c: u16) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmlsq_n_u16(a: uint16x8_t, b: uint16x8_t, c: u16) -> uint16x8_t { +pub fn vmlsq_n_u16(a: uint16x8_t, b: uint16x8_t, c: u16) -> uint16x8_t { vmlsq_u16(a, b, vdupq_n_u16(c)) } #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -26970,13 +25856,11 @@ pub unsafe fn vmlsq_n_u16(a: uint16x8_t, b: uint16x8_t, c: u16) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmls_n_s32(a: int32x2_t, b: int32x2_t, c: i32) -> int32x2_t { +pub fn vmls_n_s32(a: int32x2_t, b: int32x2_t, c: i32) -> int32x2_t { vmls_s32(a, b, vdup_n_s32(c)) } #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -26993,13 +25877,11 @@ pub unsafe fn vmls_n_s32(a: int32x2_t, b: int32x2_t, c: i32) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmlsq_n_s32(a: int32x4_t, b: int32x4_t, c: i32) -> int32x4_t { +pub fn vmlsq_n_s32(a: int32x4_t, b: int32x4_t, c: i32) -> int32x4_t { vmlsq_s32(a, b, vdupq_n_s32(c)) } #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -27016,13 +25898,11 @@ pub unsafe fn vmlsq_n_s32(a: int32x4_t, b: int32x4_t, c: i32) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmls_n_u32(a: uint32x2_t, b: uint32x2_t, c: u32) -> uint32x2_t { +pub fn vmls_n_u32(a: uint32x2_t, b: uint32x2_t, c: u32) -> uint32x2_t { vmls_u32(a, b, vdup_n_u32(c)) } #[doc = "Vector multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -27039,13 +25919,11 @@ pub unsafe fn vmls_n_u32(a: uint32x2_t, b: uint32x2_t, c: u32) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmlsq_n_u32(a: uint32x4_t, b: uint32x4_t, c: u32) -> uint32x4_t { +pub fn vmlsq_n_u32(a: uint32x4_t, b: uint32x4_t, c: u32) -> uint32x4_t { vmlsq_u32(a, b, vdupq_n_u32(c)) } #[doc = "Multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -27062,13 +25940,11 @@ pub unsafe fn vmlsq_n_u32(a: uint32x4_t, b: uint32x4_t, c: u32) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmls_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t { - simd_sub(a, simd_mul(b, c)) +pub fn vmls_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t { + unsafe { simd_sub(a, simd_mul(b, c)) } } #[doc = "Multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -27085,13 +25961,11 @@ pub unsafe fn vmls_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmlsq_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t { - simd_sub(a, simd_mul(b, c)) +pub fn vmlsq_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t { + unsafe { simd_sub(a, simd_mul(b, c)) } } #[doc = "Multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -27108,13 +25982,11 @@ pub unsafe fn vmlsq_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmls_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t { - simd_sub(a, simd_mul(b, c)) +pub fn vmls_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t { + unsafe { simd_sub(a, simd_mul(b, c)) } } #[doc = "Multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -27131,13 +26003,11 @@ pub unsafe fn vmls_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmlsq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t { - simd_sub(a, simd_mul(b, c)) +pub fn vmlsq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t { + unsafe { simd_sub(a, simd_mul(b, c)) } } #[doc = "Multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -27154,13 +26024,11 @@ pub unsafe fn vmlsq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmls_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t { - simd_sub(a, simd_mul(b, c)) +pub fn vmls_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t { + unsafe { simd_sub(a, simd_mul(b, c)) } } #[doc = "Multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -27177,13 +26045,11 @@ pub unsafe fn vmls_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmlsq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t { - simd_sub(a, simd_mul(b, c)) +pub fn vmlsq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t { + unsafe { simd_sub(a, simd_mul(b, c)) } } #[doc = "Multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -27200,13 +26066,11 @@ pub unsafe fn vmlsq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmls_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t { - simd_sub(a, simd_mul(b, c)) +pub fn vmls_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t { + unsafe { simd_sub(a, simd_mul(b, c)) } } #[doc = "Multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -27223,13 +26087,11 @@ pub unsafe fn vmls_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmlsq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t { - simd_sub(a, simd_mul(b, c)) +pub fn vmlsq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t { + unsafe { simd_sub(a, simd_mul(b, c)) } } #[doc = "Multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -27246,13 +26108,11 @@ pub unsafe fn vmlsq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_ target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmls_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_t { - simd_sub(a, simd_mul(b, c)) +pub fn vmls_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_t { + unsafe { simd_sub(a, simd_mul(b, c)) } } #[doc = "Multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -27269,13 +26129,11 @@ pub unsafe fn vmls_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_ target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmlsq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t { - simd_sub(a, simd_mul(b, c)) +pub fn vmlsq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t { + unsafe { simd_sub(a, simd_mul(b, c)) } } #[doc = "Multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -27292,13 +26150,11 @@ pub unsafe fn vmlsq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8 target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmls_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_t { - simd_sub(a, simd_mul(b, c)) +pub fn vmls_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_t { + unsafe { simd_sub(a, simd_mul(b, c)) } } #[doc = "Multiply-subtract from accumulator"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -27315,13 +26171,11 @@ pub unsafe fn vmls_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_ target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmlsq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t { - simd_sub(a, simd_mul(b, c)) +pub fn vmlsq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t { + unsafe { simd_sub(a, simd_mul(b, c)) } } #[doc = "Vector widening multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_lane_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -27339,22 +26193,18 @@ pub unsafe fn vmlsq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4 target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmlsl_lane_s16( - a: int32x4_t, - b: int16x4_t, - c: int16x4_t, -) -> int32x4_t { +pub fn vmlsl_lane_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t { static_assert_uimm_bits!(LANE, 2); - vmlsl_s16( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) + unsafe { + vmlsl_s16( + a, + b, + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) + } } #[doc = "Vector widening multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_laneq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -27372,22 +26222,18 @@ pub unsafe fn vmlsl_lane_s16( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmlsl_laneq_s16( - a: int32x4_t, - b: int16x4_t, - c: int16x8_t, -) -> int32x4_t { +pub fn vmlsl_laneq_s16(a: int32x4_t, b: int16x4_t, c: int16x8_t) -> int32x4_t { static_assert_uimm_bits!(LANE, 3); - vmlsl_s16( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) + unsafe { + vmlsl_s16( + a, + b, + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) + } } #[doc = "Vector widening multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_lane_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -27405,18 +26251,12 @@ pub unsafe fn vmlsl_laneq_s16( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmlsl_lane_s32( - a: int64x2_t, - b: int32x2_t, - c: int32x2_t, -) -> int64x2_t { +pub fn vmlsl_lane_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t { static_assert_uimm_bits!(LANE, 1); - vmlsl_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) + unsafe { vmlsl_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } } #[doc = "Vector widening multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_laneq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -27434,18 +26274,12 @@ pub unsafe fn vmlsl_lane_s32( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmlsl_laneq_s32( - a: int64x2_t, - b: int32x2_t, - c: int32x4_t, -) -> int64x2_t { +pub fn vmlsl_laneq_s32(a: int64x2_t, b: int32x2_t, c: int32x4_t) -> int64x2_t { static_assert_uimm_bits!(LANE, 2); - vmlsl_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) + unsafe { vmlsl_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } } #[doc = "Vector widening multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_lane_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -27463,22 +26297,18 @@ pub unsafe fn vmlsl_laneq_s32( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmlsl_lane_u16( - a: uint32x4_t, - b: uint16x4_t, - c: uint16x4_t, -) -> uint32x4_t { +pub fn vmlsl_lane_u16(a: uint32x4_t, b: uint16x4_t, c: uint16x4_t) -> uint32x4_t { static_assert_uimm_bits!(LANE, 2); - vmlsl_u16( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) + unsafe { + vmlsl_u16( + a, + b, + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) + } } #[doc = "Vector widening multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_laneq_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -27496,22 +26326,18 @@ pub unsafe fn vmlsl_lane_u16( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmlsl_laneq_u16( - a: uint32x4_t, - b: uint16x4_t, - c: uint16x8_t, -) -> uint32x4_t { +pub fn vmlsl_laneq_u16(a: uint32x4_t, b: uint16x4_t, c: uint16x8_t) -> uint32x4_t { static_assert_uimm_bits!(LANE, 3); - vmlsl_u16( - a, - b, - simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) + unsafe { + vmlsl_u16( + a, + b, + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) + } } #[doc = "Vector widening multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_lane_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -27529,18 +26355,12 @@ pub unsafe fn vmlsl_laneq_u16( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmlsl_lane_u32( - a: uint64x2_t, - b: uint32x2_t, - c: uint32x2_t, -) -> uint64x2_t { +pub fn vmlsl_lane_u32(a: uint64x2_t, b: uint32x2_t, c: uint32x2_t) -> uint64x2_t { static_assert_uimm_bits!(LANE, 1); - vmlsl_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) + unsafe { vmlsl_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } } #[doc = "Vector widening multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_laneq_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -27558,18 +26378,12 @@ pub unsafe fn vmlsl_lane_u32( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmlsl_laneq_u32( - a: uint64x2_t, - b: uint32x2_t, - c: uint32x4_t, -) -> uint64x2_t { +pub fn vmlsl_laneq_u32(a: uint64x2_t, b: uint32x2_t, c: uint32x4_t) -> uint64x2_t { static_assert_uimm_bits!(LANE, 2); - vmlsl_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) + unsafe { vmlsl_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } } #[doc = "Vector widening multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_n_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -27586,13 +26400,11 @@ pub unsafe fn vmlsl_laneq_u32( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmlsl_n_s16(a: int32x4_t, b: int16x4_t, c: i16) -> int32x4_t { +pub fn vmlsl_n_s16(a: int32x4_t, b: int16x4_t, c: i16) -> int32x4_t { vmlsl_s16(a, b, vdup_n_s16(c)) } #[doc = "Vector widening multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_n_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -27609,13 +26421,11 @@ pub unsafe fn vmlsl_n_s16(a: int32x4_t, b: int16x4_t, c: i16) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmlsl_n_s32(a: int64x2_t, b: int32x2_t, c: i32) -> int64x2_t { +pub fn vmlsl_n_s32(a: int64x2_t, b: int32x2_t, c: i32) -> int64x2_t { vmlsl_s32(a, b, vdup_n_s32(c)) } #[doc = "Vector widening multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_n_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -27632,13 +26442,11 @@ pub unsafe fn vmlsl_n_s32(a: int64x2_t, b: int32x2_t, c: i32) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmlsl_n_u16(a: uint32x4_t, b: uint16x4_t, c: u16) -> uint32x4_t { +pub fn vmlsl_n_u16(a: uint32x4_t, b: uint16x4_t, c: u16) -> uint32x4_t { vmlsl_u16(a, b, vdup_n_u16(c)) } #[doc = "Vector widening multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_n_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -27655,13 +26463,11 @@ pub unsafe fn vmlsl_n_u16(a: uint32x4_t, b: uint16x4_t, c: u16) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmlsl_n_u32(a: uint64x2_t, b: uint32x2_t, c: u32) -> uint64x2_t { +pub fn vmlsl_n_u32(a: uint64x2_t, b: uint32x2_t, c: u32) -> uint64x2_t { vmlsl_u32(a, b, vdup_n_u32(c)) } #[doc = "Signed multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -27678,13 +26484,11 @@ pub unsafe fn vmlsl_n_u32(a: uint64x2_t, b: uint32x2_t, c: u32) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmlsl_s8(a: int16x8_t, b: int8x8_t, c: int8x8_t) -> int16x8_t { - simd_sub(a, vmull_s8(b, c)) +pub fn vmlsl_s8(a: int16x8_t, b: int8x8_t, c: int8x8_t) -> int16x8_t { + unsafe { simd_sub(a, vmull_s8(b, c)) } } #[doc = "Signed multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -27701,13 +26505,11 @@ pub unsafe fn vmlsl_s8(a: int16x8_t, b: int8x8_t, c: int8x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmlsl_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t { - simd_sub(a, vmull_s16(b, c)) +pub fn vmlsl_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t { + unsafe { simd_sub(a, vmull_s16(b, c)) } } #[doc = "Signed multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -27724,13 +26526,11 @@ pub unsafe fn vmlsl_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmlsl_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t { - simd_sub(a, vmull_s32(b, c)) +pub fn vmlsl_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t { + unsafe { simd_sub(a, vmull_s32(b, c)) } } #[doc = "Unsigned multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -27747,13 +26547,11 @@ pub unsafe fn vmlsl_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmlsl_u8(a: uint16x8_t, b: uint8x8_t, c: uint8x8_t) -> uint16x8_t { - simd_sub(a, vmull_u8(b, c)) +pub fn vmlsl_u8(a: uint16x8_t, b: uint8x8_t, c: uint8x8_t) -> uint16x8_t { + unsafe { simd_sub(a, vmull_u8(b, c)) } } #[doc = "Unsigned multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -27770,13 +26568,11 @@ pub unsafe fn vmlsl_u8(a: uint16x8_t, b: uint8x8_t, c: uint8x8_t) -> uint16x8_t target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmlsl_u16(a: uint32x4_t, b: uint16x4_t, c: uint16x4_t) -> uint32x4_t { - simd_sub(a, vmull_u16(b, c)) +pub fn vmlsl_u16(a: uint32x4_t, b: uint16x4_t, c: uint16x4_t) -> uint32x4_t { + unsafe { simd_sub(a, vmull_u16(b, c)) } } #[doc = "Unsigned multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -27793,13 +26589,11 @@ pub unsafe fn vmlsl_u16(a: uint32x4_t, b: uint16x4_t, c: uint16x4_t) -> uint32x4 target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmlsl_u32(a: uint64x2_t, b: uint32x2_t, c: uint32x2_t) -> uint64x2_t { - simd_sub(a, vmull_u32(b, c)) +pub fn vmlsl_u32(a: uint64x2_t, b: uint32x2_t, c: uint32x2_t) -> uint64x2_t { + unsafe { simd_sub(a, vmull_u32(b, c)) } } #[doc = "8-bit integer matrix multiply-accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmmlaq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,i8mm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] @@ -27816,7 +26610,7 @@ pub unsafe fn vmlsl_u32(a: uint64x2_t, b: uint32x2_t, c: uint32x2_t) -> uint64x2 target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmmlaq_s32(a: int32x4_t, b: int8x16_t, c: int8x16_t) -> int32x4_t { +pub fn vmmlaq_s32(a: int32x4_t, b: int8x16_t, c: int8x16_t) -> int32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -27825,12 +26619,10 @@ pub unsafe fn vmmlaq_s32(a: int32x4_t, b: int8x16_t, c: int8x16_t) -> int32x4_t #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.smmla.v4i32.v16i8")] fn _vmmlaq_s32(a: int32x4_t, b: int8x16_t, c: int8x16_t) -> int32x4_t; } - _vmmlaq_s32(a, b, c) + unsafe { _vmmlaq_s32(a, b, c) } } #[doc = "8-bit integer matrix multiply-accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmmlaq_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,i8mm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] @@ -27847,7 +26639,7 @@ pub unsafe fn vmmlaq_s32(a: int32x4_t, b: int8x16_t, c: int8x16_t) -> int32x4_t target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmmlaq_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4_t { +pub fn vmmlaq_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -27856,12 +26648,10 @@ pub unsafe fn vmmlaq_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.ummla.v4i32.v16i8")] fn _vmmlaq_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4_t; } - _vmmlaq_u32(a, b, c) + unsafe { _vmmlaq_u32(a, b, c) } } #[doc = "Duplicate element to vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))] @@ -27871,13 +26661,11 @@ pub unsafe fn vmmlaq_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vmov_n_f16(a: f16) -> float16x4_t { +pub fn vmov_n_f16(a: f16) -> float16x4_t { vdup_n_f16(a) } #[doc = "Duplicate element to vector"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))] @@ -27887,13 +26675,11 @@ pub unsafe fn vmov_n_f16(a: f16) -> float16x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vmovq_n_f16(a: f16) -> float16x8_t { +pub fn vmovq_n_f16(a: f16) -> float16x8_t { vdupq_n_f16(a) } #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.f16"))] @@ -27903,13 +26689,11 @@ pub unsafe fn vmovq_n_f16(a: f16) -> float16x8_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vmul_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { - simd_mul(a, b) +pub fn vmul_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { + unsafe { simd_mul(a, b) } } #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.f16"))] @@ -27919,13 +26703,11 @@ pub unsafe fn vmul_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vmulq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { - simd_mul(a, b) +pub fn vmulq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { + unsafe { simd_mul(a, b) } } #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -27942,13 +26724,11 @@ pub unsafe fn vmulq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmul_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { - simd_mul(a, b) +pub fn vmul_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { + unsafe { simd_mul(a, b) } } #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -27965,13 +26745,11 @@ pub unsafe fn vmul_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmulq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { - simd_mul(a, b) +pub fn vmulq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { + unsafe { simd_mul(a, b) } } #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] @@ -27982,17 +26760,17 @@ pub unsafe fn vmulq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { #[rustc_legacy_const_generics(2)] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vmul_lane_f16(a: float16x4_t, v: float16x4_t) -> float16x4_t { +pub fn vmul_lane_f16(a: float16x4_t, v: float16x4_t) -> float16x4_t { static_assert_uimm_bits!(LANE, 2); - simd_mul( - a, - simd_shuffle!(v, v, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) + unsafe { + simd_mul( + a, + simd_shuffle!(v, v, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) + } } #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] @@ -28003,30 +26781,30 @@ pub unsafe fn vmul_lane_f16(a: float16x4_t, v: float16x4_t) -> #[rustc_legacy_const_generics(2)] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vmulq_lane_f16(a: float16x8_t, v: float16x4_t) -> float16x8_t { +pub fn vmulq_lane_f16(a: float16x8_t, v: float16x4_t) -> float16x8_t { static_assert_uimm_bits!(LANE, 2); - simd_mul( - a, - simd_shuffle!( - v, - v, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) + unsafe { + simd_mul( + a, + simd_shuffle!( + v, + v, + [ + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32 + ] + ), + ) + } } #[doc = "Floating-point multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -28044,14 +26822,12 @@ pub unsafe fn vmulq_lane_f16(a: float16x8_t, v: float16x4_t) -> target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmul_lane_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { +pub fn vmul_lane_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { static_assert_uimm_bits!(LANE, 1); - simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) + unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) } } #[doc = "Floating-point multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -28069,14 +26845,12 @@ pub unsafe fn vmul_lane_f32(a: float32x2_t, b: float32x2_t) -> target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmul_laneq_f32(a: float32x2_t, b: float32x4_t) -> float32x2_t { +pub fn vmul_laneq_f32(a: float32x2_t, b: float32x4_t) -> float32x2_t { static_assert_uimm_bits!(LANE, 2); - simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) + unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) } } #[doc = "Floating-point multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -28094,17 +26868,17 @@ pub unsafe fn vmul_laneq_f32(a: float32x2_t, b: float32x4_t) -> target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmulq_lane_f32(a: float32x4_t, b: float32x2_t) -> float32x4_t { +pub fn vmulq_lane_f32(a: float32x4_t, b: float32x2_t) -> float32x4_t { static_assert_uimm_bits!(LANE, 1); - simd_mul( - a, - simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) + unsafe { + simd_mul( + a, + simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) + } } #[doc = "Floating-point multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -28122,17 +26896,17 @@ pub unsafe fn vmulq_lane_f32(a: float32x4_t, b: float32x2_t) -> target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmulq_laneq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { +pub fn vmulq_laneq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { static_assert_uimm_bits!(LANE, 2); - simd_mul( - a, - simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) + unsafe { + simd_mul( + a, + simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) + } } #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -28150,17 +26924,17 @@ pub unsafe fn vmulq_laneq_f32(a: float32x4_t, b: float32x4_t) - target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmul_lane_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { +pub fn vmul_lane_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { static_assert_uimm_bits!(LANE, 2); - simd_mul( - a, - simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) + unsafe { + simd_mul( + a, + simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) + } } #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -28178,30 +26952,30 @@ pub unsafe fn vmul_lane_s16(a: int16x4_t, b: int16x4_t) -> int1 target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmulq_lane_s16(a: int16x8_t, b: int16x4_t) -> int16x8_t { +pub fn vmulq_lane_s16(a: int16x8_t, b: int16x4_t) -> int16x8_t { static_assert_uimm_bits!(LANE, 2); - simd_mul( - a, - simd_shuffle!( - b, - b, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) + unsafe { + simd_mul( + a, + simd_shuffle!( + b, + b, + [ + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32 + ] + ), + ) + } } #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -28219,14 +26993,12 @@ pub unsafe fn vmulq_lane_s16(a: int16x8_t, b: int16x4_t) -> int target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmul_lane_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { +pub fn vmul_lane_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { static_assert_uimm_bits!(LANE, 1); - simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) + unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) } } #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -28244,17 +27016,17 @@ pub unsafe fn vmul_lane_s32(a: int32x2_t, b: int32x2_t) -> int3 target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmulq_lane_s32(a: int32x4_t, b: int32x2_t) -> int32x4_t { +pub fn vmulq_lane_s32(a: int32x4_t, b: int32x2_t) -> int32x4_t { static_assert_uimm_bits!(LANE, 1); - simd_mul( - a, - simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) + unsafe { + simd_mul( + a, + simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) + } } #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -28272,17 +27044,17 @@ pub unsafe fn vmulq_lane_s32(a: int32x4_t, b: int32x2_t) -> int target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmul_lane_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { +pub fn vmul_lane_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { static_assert_uimm_bits!(LANE, 2); - simd_mul( - a, - simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) + unsafe { + simd_mul( + a, + simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) + } } #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -28300,30 +27072,30 @@ pub unsafe fn vmul_lane_u16(a: uint16x4_t, b: uint16x4_t) -> ui target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmulq_lane_u16(a: uint16x8_t, b: uint16x4_t) -> uint16x8_t { +pub fn vmulq_lane_u16(a: uint16x8_t, b: uint16x4_t) -> uint16x8_t { static_assert_uimm_bits!(LANE, 2); - simd_mul( - a, - simd_shuffle!( - b, - b, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) + unsafe { + simd_mul( + a, + simd_shuffle!( + b, + b, + [ + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32 + ] + ), + ) + } } #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -28341,14 +27113,12 @@ pub unsafe fn vmulq_lane_u16(a: uint16x8_t, b: uint16x4_t) -> u target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmul_lane_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { +pub fn vmul_lane_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { static_assert_uimm_bits!(LANE, 1); - simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) + unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) } } #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -28366,17 +27136,17 @@ pub unsafe fn vmul_lane_u32(a: uint32x2_t, b: uint32x2_t) -> ui target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmulq_lane_u32(a: uint32x4_t, b: uint32x2_t) -> uint32x4_t { +pub fn vmulq_lane_u32(a: uint32x4_t, b: uint32x2_t) -> uint32x4_t { static_assert_uimm_bits!(LANE, 1); - simd_mul( - a, - simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) + unsafe { + simd_mul( + a, + simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) + } } #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -28394,17 +27164,17 @@ pub unsafe fn vmulq_lane_u32(a: uint32x4_t, b: uint32x2_t) -> u target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmul_laneq_s16(a: int16x4_t, b: int16x8_t) -> int16x4_t { +pub fn vmul_laneq_s16(a: int16x4_t, b: int16x8_t) -> int16x4_t { static_assert_uimm_bits!(LANE, 3); - simd_mul( - a, - simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) + unsafe { + simd_mul( + a, + simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) + } } #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -28422,30 +27192,30 @@ pub unsafe fn vmul_laneq_s16(a: int16x4_t, b: int16x8_t) -> int target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmulq_laneq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { +pub fn vmulq_laneq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { static_assert_uimm_bits!(LANE, 3); - simd_mul( - a, - simd_shuffle!( - b, - b, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) + unsafe { + simd_mul( + a, + simd_shuffle!( + b, + b, + [ + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32 + ] + ), + ) + } } #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -28463,14 +27233,12 @@ pub unsafe fn vmulq_laneq_s16(a: int16x8_t, b: int16x8_t) -> in target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmul_laneq_s32(a: int32x2_t, b: int32x4_t) -> int32x2_t { +pub fn vmul_laneq_s32(a: int32x2_t, b: int32x4_t) -> int32x2_t { static_assert_uimm_bits!(LANE, 2); - simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) + unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) } } #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -28488,17 +27256,17 @@ pub unsafe fn vmul_laneq_s32(a: int32x2_t, b: int32x4_t) -> int target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmulq_laneq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { +pub fn vmulq_laneq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { static_assert_uimm_bits!(LANE, 2); - simd_mul( - a, - simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) + unsafe { + simd_mul( + a, + simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) + } } #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -28516,17 +27284,17 @@ pub unsafe fn vmulq_laneq_s32(a: int32x4_t, b: int32x4_t) -> in target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmul_laneq_u16(a: uint16x4_t, b: uint16x8_t) -> uint16x4_t { +pub fn vmul_laneq_u16(a: uint16x4_t, b: uint16x8_t) -> uint16x4_t { static_assert_uimm_bits!(LANE, 3); - simd_mul( - a, - simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) + unsafe { + simd_mul( + a, + simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) + } } #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -28544,30 +27312,30 @@ pub unsafe fn vmul_laneq_u16(a: uint16x4_t, b: uint16x8_t) -> u target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmulq_laneq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { +pub fn vmulq_laneq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { static_assert_uimm_bits!(LANE, 3); - simd_mul( - a, - simd_shuffle!( - b, - b, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ), - ) + unsafe { + simd_mul( + a, + simd_shuffle!( + b, + b, + [ + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32 + ] + ), + ) + } } #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -28585,14 +27353,12 @@ pub unsafe fn vmulq_laneq_u16(a: uint16x8_t, b: uint16x8_t) -> target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmul_laneq_u32(a: uint32x2_t, b: uint32x4_t) -> uint32x2_t { +pub fn vmul_laneq_u32(a: uint32x2_t, b: uint32x4_t) -> uint32x2_t { static_assert_uimm_bits!(LANE, 2); - simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) + unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) } } #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -28610,17 +27376,17 @@ pub unsafe fn vmul_laneq_u32(a: uint32x2_t, b: uint32x4_t) -> u target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmulq_laneq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { +pub fn vmulq_laneq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { static_assert_uimm_bits!(LANE, 2); - simd_mul( - a, - simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) + unsafe { + simd_mul( + a, + simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) + } } #[doc = "Vector multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))] @@ -28630,13 +27396,11 @@ pub unsafe fn vmulq_laneq_u32(a: uint32x4_t, b: uint32x4_t) -> )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vmul_n_f16(a: float16x4_t, b: f16) -> float16x4_t { - simd_mul(a, vdup_n_f16(b)) +pub fn vmul_n_f16(a: float16x4_t, b: f16) -> float16x4_t { + unsafe { simd_mul(a, vdup_n_f16(b)) } } #[doc = "Vector multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))] @@ -28646,13 +27410,11 @@ pub unsafe fn vmul_n_f16(a: float16x4_t, b: f16) -> float16x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vmulq_n_f16(a: float16x8_t, b: f16) -> float16x8_t { - simd_mul(a, vdupq_n_f16(b)) +pub fn vmulq_n_f16(a: float16x8_t, b: f16) -> float16x8_t { + unsafe { simd_mul(a, vdupq_n_f16(b)) } } #[doc = "Vector multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -28669,13 +27431,11 @@ pub unsafe fn vmulq_n_f16(a: float16x8_t, b: f16) -> float16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmul_n_f32(a: float32x2_t, b: f32) -> float32x2_t { - simd_mul(a, vdup_n_f32(b)) +pub fn vmul_n_f32(a: float32x2_t, b: f32) -> float32x2_t { + unsafe { simd_mul(a, vdup_n_f32(b)) } } #[doc = "Vector multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -28692,13 +27452,11 @@ pub unsafe fn vmul_n_f32(a: float32x2_t, b: f32) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmulq_n_f32(a: float32x4_t, b: f32) -> float32x4_t { - simd_mul(a, vdupq_n_f32(b)) +pub fn vmulq_n_f32(a: float32x4_t, b: f32) -> float32x4_t { + unsafe { simd_mul(a, vdupq_n_f32(b)) } } #[doc = "Vector multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -28715,13 +27473,11 @@ pub unsafe fn vmulq_n_f32(a: float32x4_t, b: f32) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmul_n_s16(a: int16x4_t, b: i16) -> int16x4_t { - simd_mul(a, vdup_n_s16(b)) +pub fn vmul_n_s16(a: int16x4_t, b: i16) -> int16x4_t { + unsafe { simd_mul(a, vdup_n_s16(b)) } } #[doc = "Vector multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -28738,13 +27494,11 @@ pub unsafe fn vmul_n_s16(a: int16x4_t, b: i16) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmulq_n_s16(a: int16x8_t, b: i16) -> int16x8_t { - simd_mul(a, vdupq_n_s16(b)) +pub fn vmulq_n_s16(a: int16x8_t, b: i16) -> int16x8_t { + unsafe { simd_mul(a, vdupq_n_s16(b)) } } #[doc = "Vector multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -28761,13 +27515,11 @@ pub unsafe fn vmulq_n_s16(a: int16x8_t, b: i16) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmul_n_s32(a: int32x2_t, b: i32) -> int32x2_t { - simd_mul(a, vdup_n_s32(b)) +pub fn vmul_n_s32(a: int32x2_t, b: i32) -> int32x2_t { + unsafe { simd_mul(a, vdup_n_s32(b)) } } #[doc = "Vector multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -28784,13 +27536,11 @@ pub unsafe fn vmul_n_s32(a: int32x2_t, b: i32) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmulq_n_s32(a: int32x4_t, b: i32) -> int32x4_t { - simd_mul(a, vdupq_n_s32(b)) +pub fn vmulq_n_s32(a: int32x4_t, b: i32) -> int32x4_t { + unsafe { simd_mul(a, vdupq_n_s32(b)) } } #[doc = "Vector multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -28807,13 +27557,11 @@ pub unsafe fn vmulq_n_s32(a: int32x4_t, b: i32) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmul_n_u16(a: uint16x4_t, b: u16) -> uint16x4_t { - simd_mul(a, vdup_n_u16(b)) +pub fn vmul_n_u16(a: uint16x4_t, b: u16) -> uint16x4_t { + unsafe { simd_mul(a, vdup_n_u16(b)) } } #[doc = "Vector multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -28830,13 +27578,11 @@ pub unsafe fn vmul_n_u16(a: uint16x4_t, b: u16) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmulq_n_u16(a: uint16x8_t, b: u16) -> uint16x8_t { - simd_mul(a, vdupq_n_u16(b)) +pub fn vmulq_n_u16(a: uint16x8_t, b: u16) -> uint16x8_t { + unsafe { simd_mul(a, vdupq_n_u16(b)) } } #[doc = "Vector multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -28853,13 +27599,11 @@ pub unsafe fn vmulq_n_u16(a: uint16x8_t, b: u16) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmul_n_u32(a: uint32x2_t, b: u32) -> uint32x2_t { - simd_mul(a, vdup_n_u32(b)) +pub fn vmul_n_u32(a: uint32x2_t, b: u32) -> uint32x2_t { + unsafe { simd_mul(a, vdup_n_u32(b)) } } #[doc = "Vector multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -28876,13 +27620,11 @@ pub unsafe fn vmul_n_u32(a: uint32x2_t, b: u32) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmulq_n_u32(a: uint32x4_t, b: u32) -> uint32x4_t { - simd_mul(a, vdupq_n_u32(b)) +pub fn vmulq_n_u32(a: uint32x4_t, b: u32) -> uint32x4_t { + unsafe { simd_mul(a, vdupq_n_u32(b)) } } #[doc = "Polynomial multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -28899,7 +27641,7 @@ pub unsafe fn vmulq_n_u32(a: uint32x4_t, b: u32) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmul_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { +pub fn vmul_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmulp.v8i8")] #[cfg_attr( @@ -28908,12 +27650,10 @@ pub unsafe fn vmul_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { )] fn _vmul_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t; } - _vmul_p8(a, b) + unsafe { _vmul_p8(a, b) } } #[doc = "Polynomial multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -28930,7 +27670,7 @@ pub unsafe fn vmul_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmulq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { +pub fn vmulq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmulp.v16i8")] #[cfg_attr( @@ -28939,12 +27679,10 @@ pub unsafe fn vmulq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { )] fn _vmulq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t; } - _vmulq_p8(a, b) + unsafe { _vmulq_p8(a, b) } } #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -28961,13 +27699,11 @@ pub unsafe fn vmulq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmul_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { - simd_mul(a, b) +pub fn vmul_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + unsafe { simd_mul(a, b) } } #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -28984,13 +27720,11 @@ pub unsafe fn vmul_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmulq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { - simd_mul(a, b) +pub fn vmulq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + unsafe { simd_mul(a, b) } } #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -29007,13 +27741,11 @@ pub unsafe fn vmulq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmul_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { - simd_mul(a, b) +pub fn vmul_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + unsafe { simd_mul(a, b) } } #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -29030,13 +27762,11 @@ pub unsafe fn vmul_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmulq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { - simd_mul(a, b) +pub fn vmulq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + unsafe { simd_mul(a, b) } } #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -29053,13 +27783,11 @@ pub unsafe fn vmulq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmul_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { - simd_mul(a, b) +pub fn vmul_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + unsafe { simd_mul(a, b) } } #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -29076,13 +27804,11 @@ pub unsafe fn vmul_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmulq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { - simd_mul(a, b) +pub fn vmulq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + unsafe { simd_mul(a, b) } } #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -29099,13 +27825,11 @@ pub unsafe fn vmulq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmul_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { - simd_mul(a, b) +pub fn vmul_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + unsafe { simd_mul(a, b) } } #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -29122,13 +27846,11 @@ pub unsafe fn vmul_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmulq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { - simd_mul(a, b) +pub fn vmulq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + unsafe { simd_mul(a, b) } } #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -29145,13 +27867,11 @@ pub unsafe fn vmulq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmul_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { - simd_mul(a, b) +pub fn vmul_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { + unsafe { simd_mul(a, b) } } #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -29168,13 +27888,11 @@ pub unsafe fn vmul_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmulq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { - simd_mul(a, b) +pub fn vmulq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { + unsafe { simd_mul(a, b) } } #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -29191,13 +27909,11 @@ pub unsafe fn vmulq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmul_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { - simd_mul(a, b) +pub fn vmul_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + unsafe { simd_mul(a, b) } } #[doc = "Multiply"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -29214,13 +27930,11 @@ pub unsafe fn vmul_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmulq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { - simd_mul(a, b) +pub fn vmulq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + unsafe { simd_mul(a, b) } } #[doc = "Vector long multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_lane_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -29238,17 +27952,17 @@ pub unsafe fn vmulq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmull_lane_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t { +pub fn vmull_lane_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t { static_assert_uimm_bits!(LANE, 2); - vmull_s16( - a, - simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) + unsafe { + vmull_s16( + a, + simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) + } } #[doc = "Vector long multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_laneq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -29266,17 +27980,17 @@ pub unsafe fn vmull_lane_s16(a: int16x4_t, b: int16x4_t) -> int target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmull_laneq_s16(a: int16x4_t, b: int16x8_t) -> int32x4_t { +pub fn vmull_laneq_s16(a: int16x4_t, b: int16x8_t) -> int32x4_t { static_assert_uimm_bits!(LANE, 3); - vmull_s16( - a, - simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) + unsafe { + vmull_s16( + a, + simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) + } } #[doc = "Vector long multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_lane_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -29294,14 +28008,12 @@ pub unsafe fn vmull_laneq_s16(a: int16x4_t, b: int16x8_t) -> in target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmull_lane_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t { +pub fn vmull_lane_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t { static_assert_uimm_bits!(LANE, 1); - vmull_s32(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) + unsafe { vmull_s32(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) } } #[doc = "Vector long multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_laneq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -29319,14 +28031,12 @@ pub unsafe fn vmull_lane_s32(a: int32x2_t, b: int32x2_t) -> int target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmull_laneq_s32(a: int32x2_t, b: int32x4_t) -> int64x2_t { +pub fn vmull_laneq_s32(a: int32x2_t, b: int32x4_t) -> int64x2_t { static_assert_uimm_bits!(LANE, 2); - vmull_s32(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) + unsafe { vmull_s32(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) } } #[doc = "Vector long multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_lane_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -29344,17 +28054,17 @@ pub unsafe fn vmull_laneq_s32(a: int32x2_t, b: int32x4_t) -> in target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmull_lane_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t { +pub fn vmull_lane_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t { static_assert_uimm_bits!(LANE, 2); - vmull_u16( - a, - simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) + unsafe { + vmull_u16( + a, + simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) + } } #[doc = "Vector long multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_laneq_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -29372,17 +28082,17 @@ pub unsafe fn vmull_lane_u16(a: uint16x4_t, b: uint16x4_t) -> u target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmull_laneq_u16(a: uint16x4_t, b: uint16x8_t) -> uint32x4_t { +pub fn vmull_laneq_u16(a: uint16x4_t, b: uint16x8_t) -> uint32x4_t { static_assert_uimm_bits!(LANE, 3); - vmull_u16( - a, - simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), - ) + unsafe { + vmull_u16( + a, + simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) + } } #[doc = "Vector long multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_lane_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -29400,14 +28110,12 @@ pub unsafe fn vmull_laneq_u16(a: uint16x4_t, b: uint16x8_t) -> target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmull_lane_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t { +pub fn vmull_lane_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t { static_assert_uimm_bits!(LANE, 1); - vmull_u32(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) + unsafe { vmull_u32(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) } } #[doc = "Vector long multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_laneq_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -29425,14 +28133,12 @@ pub unsafe fn vmull_lane_u32(a: uint32x2_t, b: uint32x2_t) -> u target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmull_laneq_u32(a: uint32x2_t, b: uint32x4_t) -> uint64x2_t { +pub fn vmull_laneq_u32(a: uint32x2_t, b: uint32x4_t) -> uint64x2_t { static_assert_uimm_bits!(LANE, 2); - vmull_u32(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) + unsafe { vmull_u32(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) } } #[doc = "Vector long multiply with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_n_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -29449,13 +28155,11 @@ pub unsafe fn vmull_laneq_u32(a: uint32x2_t, b: uint32x4_t) -> target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmull_n_s16(a: int16x4_t, b: i16) -> int32x4_t { +pub fn vmull_n_s16(a: int16x4_t, b: i16) -> int32x4_t { vmull_s16(a, vdup_n_s16(b)) } #[doc = "Vector long multiply with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_n_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -29472,13 +28176,11 @@ pub unsafe fn vmull_n_s16(a: int16x4_t, b: i16) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmull_n_s32(a: int32x2_t, b: i32) -> int64x2_t { +pub fn vmull_n_s32(a: int32x2_t, b: i32) -> int64x2_t { vmull_s32(a, vdup_n_s32(b)) } #[doc = "Vector long multiply with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_n_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -29495,13 +28197,11 @@ pub unsafe fn vmull_n_s32(a: int32x2_t, b: i32) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmull_n_u16(a: uint16x4_t, b: u16) -> uint32x4_t { +pub fn vmull_n_u16(a: uint16x4_t, b: u16) -> uint32x4_t { vmull_u16(a, vdup_n_u16(b)) } #[doc = "Vector long multiply with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_n_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -29518,13 +28218,11 @@ pub unsafe fn vmull_n_u16(a: uint16x4_t, b: u16) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmull_n_u32(a: uint32x2_t, b: u32) -> uint64x2_t { +pub fn vmull_n_u32(a: uint32x2_t, b: u32) -> uint64x2_t { vmull_u32(a, vdup_n_u32(b)) } #[doc = "Polynomial multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -29541,7 +28239,7 @@ pub unsafe fn vmull_n_u32(a: uint32x2_t, b: u32) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmull_p8(a: poly8x8_t, b: poly8x8_t) -> poly16x8_t { +pub fn vmull_p8(a: poly8x8_t, b: poly8x8_t) -> poly16x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -29550,12 +28248,10 @@ pub unsafe fn vmull_p8(a: poly8x8_t, b: poly8x8_t) -> poly16x8_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmullp.v8i16")] fn _vmull_p8(a: poly8x8_t, b: poly8x8_t) -> poly16x8_t; } - _vmull_p8(a, b) + unsafe { _vmull_p8(a, b) } } #[doc = "Signed multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -29572,7 +28268,7 @@ pub unsafe fn vmull_p8(a: poly8x8_t, b: poly8x8_t) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmull_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t { +pub fn vmull_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -29581,12 +28277,10 @@ pub unsafe fn vmull_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmulls.v4i16")] fn _vmull_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t; } - _vmull_s16(a, b) + unsafe { _vmull_s16(a, b) } } #[doc = "Signed multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -29603,7 +28297,7 @@ pub unsafe fn vmull_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmull_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t { +pub fn vmull_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -29612,12 +28306,10 @@ pub unsafe fn vmull_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmulls.v2i32")] fn _vmull_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t; } - _vmull_s32(a, b) + unsafe { _vmull_s32(a, b) } } #[doc = "Signed multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -29634,7 +28326,7 @@ pub unsafe fn vmull_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmull_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t { +pub fn vmull_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -29643,12 +28335,10 @@ pub unsafe fn vmull_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmulls.v8i8")] fn _vmull_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t; } - _vmull_s8(a, b) + unsafe { _vmull_s8(a, b) } } #[doc = "Unsigned multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -29665,7 +28355,7 @@ pub unsafe fn vmull_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmull_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t { +pub fn vmull_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -29674,12 +28364,10 @@ pub unsafe fn vmull_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmullu.v8i8")] fn _vmull_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t; } - _vmull_u8(a, b) + unsafe { _vmull_u8(a, b) } } #[doc = "Unsigned multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -29696,7 +28384,7 @@ pub unsafe fn vmull_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmull_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t { +pub fn vmull_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -29705,12 +28393,10 @@ pub unsafe fn vmull_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmullu.v4i16")] fn _vmull_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t; } - _vmull_u16(a, b) + unsafe { _vmull_u16(a, b) } } #[doc = "Unsigned multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -29727,7 +28413,7 @@ pub unsafe fn vmull_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmull_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t { +pub fn vmull_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -29736,12 +28422,10 @@ pub unsafe fn vmull_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmullu.v2i32")] fn _vmull_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t; } - _vmull_u32(a, b) + unsafe { _vmull_u32(a, b) } } #[doc = "Negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.f16"))] @@ -29751,13 +28435,11 @@ pub unsafe fn vmull_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vneg_f16(a: float16x4_t) -> float16x4_t { - simd_neg(a) +pub fn vneg_f16(a: float16x4_t) -> float16x4_t { + unsafe { simd_neg(a) } } #[doc = "Negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.f16"))] @@ -29767,13 +28449,11 @@ pub unsafe fn vneg_f16(a: float16x4_t) -> float16x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vnegq_f16(a: float16x8_t) -> float16x8_t { - simd_neg(a) +pub fn vnegq_f16(a: float16x8_t) -> float16x8_t { + unsafe { simd_neg(a) } } #[doc = "Negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -29790,13 +28470,11 @@ pub unsafe fn vnegq_f16(a: float16x8_t) -> float16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vneg_f32(a: float32x2_t) -> float32x2_t { - simd_neg(a) +pub fn vneg_f32(a: float32x2_t) -> float32x2_t { + unsafe { simd_neg(a) } } #[doc = "Negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -29813,13 +28491,11 @@ pub unsafe fn vneg_f32(a: float32x2_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vnegq_f32(a: float32x4_t) -> float32x4_t { - simd_neg(a) +pub fn vnegq_f32(a: float32x4_t) -> float32x4_t { + unsafe { simd_neg(a) } } #[doc = "Negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -29836,13 +28512,11 @@ pub unsafe fn vnegq_f32(a: float32x4_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vneg_s8(a: int8x8_t) -> int8x8_t { - simd_neg(a) +pub fn vneg_s8(a: int8x8_t) -> int8x8_t { + unsafe { simd_neg(a) } } #[doc = "Negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -29859,13 +28533,11 @@ pub unsafe fn vneg_s8(a: int8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vnegq_s8(a: int8x16_t) -> int8x16_t { - simd_neg(a) +pub fn vnegq_s8(a: int8x16_t) -> int8x16_t { + unsafe { simd_neg(a) } } #[doc = "Negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -29882,13 +28554,11 @@ pub unsafe fn vnegq_s8(a: int8x16_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vneg_s16(a: int16x4_t) -> int16x4_t { - simd_neg(a) +pub fn vneg_s16(a: int16x4_t) -> int16x4_t { + unsafe { simd_neg(a) } } #[doc = "Negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -29905,13 +28575,11 @@ pub unsafe fn vneg_s16(a: int16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vnegq_s16(a: int16x8_t) -> int16x8_t { - simd_neg(a) +pub fn vnegq_s16(a: int16x8_t) -> int16x8_t { + unsafe { simd_neg(a) } } #[doc = "Negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -29928,13 +28596,11 @@ pub unsafe fn vnegq_s16(a: int16x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vneg_s32(a: int32x2_t) -> int32x2_t { - simd_neg(a) +pub fn vneg_s32(a: int32x2_t) -> int32x2_t { + unsafe { simd_neg(a) } } #[doc = "Negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -29951,13 +28617,11 @@ pub unsafe fn vneg_s32(a: int32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vnegq_s32(a: int32x4_t) -> int32x4_t { - simd_neg(a) +pub fn vnegq_s32(a: int32x4_t) -> int32x4_t { + unsafe { simd_neg(a) } } #[doc = "Vector bitwise or (immediate, inclusive)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -29974,13 +28638,11 @@ pub unsafe fn vnegq_s32(a: int32x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vorr_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { - simd_or(a, b) +pub fn vorr_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { + unsafe { simd_or(a, b) } } #[doc = "Vector bitwise or (immediate, inclusive)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -29997,13 +28659,11 @@ pub unsafe fn vorr_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vorrq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { - simd_or(a, b) +pub fn vorrq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { + unsafe { simd_or(a, b) } } #[doc = "Vector bitwise or (immediate, inclusive)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -30020,13 +28680,11 @@ pub unsafe fn vorrq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vorr_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { - simd_or(a, b) +pub fn vorr_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + unsafe { simd_or(a, b) } } #[doc = "Vector bitwise or (immediate, inclusive)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -30043,13 +28701,11 @@ pub unsafe fn vorr_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vorrq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { - simd_or(a, b) +pub fn vorrq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + unsafe { simd_or(a, b) } } #[doc = "Vector bitwise or (immediate, inclusive)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -30066,13 +28722,11 @@ pub unsafe fn vorrq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vorr_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { - simd_or(a, b) +pub fn vorr_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + unsafe { simd_or(a, b) } } #[doc = "Vector bitwise or (immediate, inclusive)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -30089,13 +28743,11 @@ pub unsafe fn vorr_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vorrq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { - simd_or(a, b) +pub fn vorrq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + unsafe { simd_or(a, b) } } #[doc = "Vector bitwise or (immediate, inclusive)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -30112,13 +28764,11 @@ pub unsafe fn vorrq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vorr_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { - simd_or(a, b) +pub fn vorr_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { + unsafe { simd_or(a, b) } } #[doc = "Vector bitwise or (immediate, inclusive)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -30135,13 +28785,11 @@ pub unsafe fn vorr_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vorrq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { - simd_or(a, b) +pub fn vorrq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { + unsafe { simd_or(a, b) } } #[doc = "Vector bitwise or (immediate, inclusive)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -30158,13 +28806,11 @@ pub unsafe fn vorrq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vorr_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { - simd_or(a, b) +pub fn vorr_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + unsafe { simd_or(a, b) } } #[doc = "Vector bitwise or (immediate, inclusive)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -30181,13 +28827,11 @@ pub unsafe fn vorr_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vorrq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { - simd_or(a, b) +pub fn vorrq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + unsafe { simd_or(a, b) } } #[doc = "Vector bitwise or (immediate, inclusive)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -30204,13 +28848,11 @@ pub unsafe fn vorrq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vorr_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { - simd_or(a, b) +pub fn vorr_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + unsafe { simd_or(a, b) } } #[doc = "Vector bitwise or (immediate, inclusive)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -30227,13 +28869,11 @@ pub unsafe fn vorr_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vorrq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { - simd_or(a, b) +pub fn vorrq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + unsafe { simd_or(a, b) } } #[doc = "Vector bitwise or (immediate, inclusive)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -30250,13 +28890,11 @@ pub unsafe fn vorrq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vorr_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { - simd_or(a, b) +pub fn vorr_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + unsafe { simd_or(a, b) } } #[doc = "Vector bitwise or (immediate, inclusive)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -30273,13 +28911,11 @@ pub unsafe fn vorr_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vorrq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { - simd_or(a, b) +pub fn vorrq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + unsafe { simd_or(a, b) } } #[doc = "Vector bitwise or (immediate, inclusive)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -30296,13 +28932,11 @@ pub unsafe fn vorrq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vorr_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { - simd_or(a, b) +pub fn vorr_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { + unsafe { simd_or(a, b) } } #[doc = "Vector bitwise or (immediate, inclusive)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -30319,13 +28953,11 @@ pub unsafe fn vorr_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vorrq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { - simd_or(a, b) +pub fn vorrq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { + unsafe { simd_or(a, b) } } #[doc = "Signed Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadal_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -30342,22 +28974,20 @@ pub unsafe fn vorrq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vpadal_s8(a: int16x4_t, b: int8x8_t) -> int16x4_t { +pub fn vpadal_s8(a: int16x4_t, b: int8x8_t) -> int16x4_t { let x: int16x4_t; #[cfg(target_arch = "arm")] { x = priv_vpadal_s8(a, b); } #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))] - { + unsafe { x = simd_add(vpaddl_s8(b), a); }; x } #[doc = "Signed Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadalq_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -30374,22 +29004,20 @@ pub unsafe fn vpadal_s8(a: int16x4_t, b: int8x8_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vpadalq_s8(a: int16x8_t, b: int8x16_t) -> int16x8_t { +pub fn vpadalq_s8(a: int16x8_t, b: int8x16_t) -> int16x8_t { let x: int16x8_t; #[cfg(target_arch = "arm")] { x = priv_vpadalq_s8(a, b); } #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))] - { + unsafe { x = simd_add(vpaddlq_s8(b), a); }; x } #[doc = "Signed Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadal_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -30406,22 +29034,20 @@ pub unsafe fn vpadalq_s8(a: int16x8_t, b: int8x16_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vpadal_s16(a: int32x2_t, b: int16x4_t) -> int32x2_t { +pub fn vpadal_s16(a: int32x2_t, b: int16x4_t) -> int32x2_t { let x: int32x2_t; #[cfg(target_arch = "arm")] { x = priv_vpadal_s16(a, b); } #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))] - { + unsafe { x = simd_add(vpaddl_s16(b), a); }; x } #[doc = "Signed Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadalq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -30438,22 +29064,20 @@ pub unsafe fn vpadal_s16(a: int32x2_t, b: int16x4_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vpadalq_s16(a: int32x4_t, b: int16x8_t) -> int32x4_t { +pub fn vpadalq_s16(a: int32x4_t, b: int16x8_t) -> int32x4_t { let x: int32x4_t; #[cfg(target_arch = "arm")] { x = priv_vpadalq_s16(a, b); } #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))] - { + unsafe { x = simd_add(vpaddlq_s16(b), a); }; x } #[doc = "Signed Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadal_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -30470,22 +29094,20 @@ pub unsafe fn vpadalq_s16(a: int32x4_t, b: int16x8_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vpadal_s32(a: int64x1_t, b: int32x2_t) -> int64x1_t { +pub fn vpadal_s32(a: int64x1_t, b: int32x2_t) -> int64x1_t { let x: int64x1_t; #[cfg(target_arch = "arm")] { x = priv_vpadal_s32(a, b); } #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))] - { + unsafe { x = simd_add(vpaddl_s32(b), a); }; x } #[doc = "Signed Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadalq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -30502,22 +29124,20 @@ pub unsafe fn vpadal_s32(a: int64x1_t, b: int32x2_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vpadalq_s32(a: int64x2_t, b: int32x4_t) -> int64x2_t { +pub fn vpadalq_s32(a: int64x2_t, b: int32x4_t) -> int64x2_t { let x: int64x2_t; #[cfg(target_arch = "arm")] { x = priv_vpadalq_s32(a, b); } #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))] - { + unsafe { x = simd_add(vpaddlq_s32(b), a); }; x } #[doc = "Unsigned Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadal_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -30534,22 +29154,20 @@ pub unsafe fn vpadalq_s32(a: int64x2_t, b: int32x4_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vpadal_u8(a: uint16x4_t, b: uint8x8_t) -> uint16x4_t { +pub fn vpadal_u8(a: uint16x4_t, b: uint8x8_t) -> uint16x4_t { let x: uint16x4_t; #[cfg(target_arch = "arm")] { x = priv_vpadal_u8(a, b); } #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))] - { + unsafe { x = simd_add(vpaddl_u8(b), a); }; x } #[doc = "Unsigned Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadalq_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -30566,22 +29184,20 @@ pub unsafe fn vpadal_u8(a: uint16x4_t, b: uint8x8_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vpadalq_u8(a: uint16x8_t, b: uint8x16_t) -> uint16x8_t { +pub fn vpadalq_u8(a: uint16x8_t, b: uint8x16_t) -> uint16x8_t { let x: uint16x8_t; #[cfg(target_arch = "arm")] { x = priv_vpadalq_u8(a, b); } #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))] - { + unsafe { x = simd_add(vpaddlq_u8(b), a); }; x } #[doc = "Unsigned Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadal_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -30598,22 +29214,20 @@ pub unsafe fn vpadalq_u8(a: uint16x8_t, b: uint8x16_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vpadal_u16(a: uint32x2_t, b: uint16x4_t) -> uint32x2_t { +pub fn vpadal_u16(a: uint32x2_t, b: uint16x4_t) -> uint32x2_t { let x: uint32x2_t; #[cfg(target_arch = "arm")] { x = priv_vpadal_u16(a, b); } #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))] - { + unsafe { x = simd_add(vpaddl_u16(b), a); }; x } #[doc = "Unsigned Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadalq_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -30630,22 +29244,20 @@ pub unsafe fn vpadal_u16(a: uint32x2_t, b: uint16x4_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vpadalq_u16(a: uint32x4_t, b: uint16x8_t) -> uint32x4_t { +pub fn vpadalq_u16(a: uint32x4_t, b: uint16x8_t) -> uint32x4_t { let x: uint32x4_t; #[cfg(target_arch = "arm")] { x = priv_vpadalq_u16(a, b); } #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))] - { + unsafe { x = simd_add(vpaddlq_u16(b), a); }; x } #[doc = "Unsigned Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadal_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -30662,22 +29274,20 @@ pub unsafe fn vpadalq_u16(a: uint32x4_t, b: uint16x8_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vpadal_u32(a: uint64x1_t, b: uint32x2_t) -> uint64x1_t { +pub fn vpadal_u32(a: uint64x1_t, b: uint32x2_t) -> uint64x1_t { let x: uint64x1_t; #[cfg(target_arch = "arm")] { x = priv_vpadal_u32(a, b); } #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))] - { + unsafe { x = simd_add(vpaddl_u32(b), a); }; x } #[doc = "Unsigned Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadalq_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -30694,22 +29304,20 @@ pub unsafe fn vpadal_u32(a: uint64x1_t, b: uint32x2_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vpadalq_u32(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t { +pub fn vpadalq_u32(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t { let x: uint64x2_t; #[cfg(target_arch = "arm")] { x = priv_vpadalq_u32(a, b); } #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))] - { + unsafe { x = simd_add(vpaddlq_u32(b), a); }; x } #[doc = "Floating-point add pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))] @@ -30719,7 +29327,7 @@ pub unsafe fn vpadalq_u32(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vpadd_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { +pub fn vpadd_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadd.v4f16")] #[cfg_attr( @@ -30728,12 +29336,10 @@ pub unsafe fn vpadd_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { )] fn _vpadd_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t; } - _vpadd_f16(a, b) + unsafe { _vpadd_f16(a, b) } } #[doc = "Floating-point add pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -30750,7 +29356,7 @@ pub unsafe fn vpadd_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vpadd_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { +pub fn vpadd_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadd.v2f32")] #[cfg_attr( @@ -30759,12 +29365,10 @@ pub unsafe fn vpadd_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { )] fn _vpadd_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t; } - _vpadd_f32(a, b) + unsafe { _vpadd_f32(a, b) } } #[doc = "Add pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -30781,7 +29385,7 @@ pub unsafe fn vpadd_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vpadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { +pub fn vpadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -30790,12 +29394,10 @@ pub unsafe fn vpadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadd.v8i8")] fn _vpadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t; } - _vpadd_s8(a, b) + unsafe { _vpadd_s8(a, b) } } #[doc = "Add pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -30812,7 +29414,7 @@ pub unsafe fn vpadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vpadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { +pub fn vpadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -30821,12 +29423,10 @@ pub unsafe fn vpadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadd.v4i16")] fn _vpadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t; } - _vpadd_s16(a, b) + unsafe { _vpadd_s16(a, b) } } #[doc = "Add pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -30843,7 +29443,7 @@ pub unsafe fn vpadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vpadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { +pub fn vpadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -30852,12 +29452,10 @@ pub unsafe fn vpadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadd.v2i32")] fn _vpadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t; } - _vpadd_s32(a, b) + unsafe { _vpadd_s32(a, b) } } #[doc = "Add pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -30875,13 +29473,11 @@ pub unsafe fn vpadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vpadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { - transmute(vpadd_s8(transmute(a), transmute(b))) +pub fn vpadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + unsafe { transmute(vpadd_s8(transmute(a), transmute(b))) } } #[doc = "Add pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -30899,16 +29495,16 @@ pub unsafe fn vpadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vpadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { +pub fn vpadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: uint8x8_t = transmute(vpadd_s8(transmute(a), transmute(b))); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: uint8x8_t = transmute(vpadd_s8(transmute(a), transmute(b))); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Add pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -30926,13 +29522,11 @@ pub unsafe fn vpadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vpadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { - transmute(vpadd_s16(transmute(a), transmute(b))) +pub fn vpadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + unsafe { transmute(vpadd_s16(transmute(a), transmute(b))) } } #[doc = "Add pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -30950,16 +29544,16 @@ pub unsafe fn vpadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vpadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { +pub fn vpadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); let b: uint16x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); - let ret_val: uint16x4_t = transmute(vpadd_s16(transmute(a), transmute(b))); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + unsafe { + let ret_val: uint16x4_t = transmute(vpadd_s16(transmute(a), transmute(b))); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Add pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -30977,13 +29571,11 @@ pub unsafe fn vpadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vpadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { - transmute(vpadd_s32(transmute(a), transmute(b))) +pub fn vpadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + unsafe { transmute(vpadd_s32(transmute(a), transmute(b))) } } #[doc = "Add pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -31001,16 +29593,16 @@ pub unsafe fn vpadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vpadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { +pub fn vpadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]); let b: uint32x2_t = simd_shuffle!(b, b, [1, 0]); - let ret_val: uint32x2_t = transmute(vpadd_s32(transmute(a), transmute(b))); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: uint32x2_t = transmute(vpadd_s32(transmute(a), transmute(b))); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Signed Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddl_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -31027,7 +29619,7 @@ pub unsafe fn vpadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vpaddl_s8(a: int8x8_t) -> int16x4_t { +pub fn vpaddl_s8(a: int8x8_t) -> int16x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -31036,12 +29628,10 @@ pub unsafe fn vpaddl_s8(a: int8x8_t) -> int16x4_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddls.v4i16.v8i8")] fn _vpaddl_s8(a: int8x8_t) -> int16x4_t; } - _vpaddl_s8(a) + unsafe { _vpaddl_s8(a) } } #[doc = "Signed Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddlq_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -31058,7 +29648,7 @@ pub unsafe fn vpaddl_s8(a: int8x8_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vpaddlq_s8(a: int8x16_t) -> int16x8_t { +pub fn vpaddlq_s8(a: int8x16_t) -> int16x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -31067,12 +29657,10 @@ pub unsafe fn vpaddlq_s8(a: int8x16_t) -> int16x8_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddls.v8i16.v16i8")] fn _vpaddlq_s8(a: int8x16_t) -> int16x8_t; } - _vpaddlq_s8(a) + unsafe { _vpaddlq_s8(a) } } #[doc = "Signed Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddl_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -31089,7 +29677,7 @@ pub unsafe fn vpaddlq_s8(a: int8x16_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vpaddl_s16(a: int16x4_t) -> int32x2_t { +pub fn vpaddl_s16(a: int16x4_t) -> int32x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -31098,12 +29686,10 @@ pub unsafe fn vpaddl_s16(a: int16x4_t) -> int32x2_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddls.v2i32.v4i16")] fn _vpaddl_s16(a: int16x4_t) -> int32x2_t; } - _vpaddl_s16(a) + unsafe { _vpaddl_s16(a) } } #[doc = "Signed Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddlq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -31120,7 +29706,7 @@ pub unsafe fn vpaddl_s16(a: int16x4_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vpaddlq_s16(a: int16x8_t) -> int32x4_t { +pub fn vpaddlq_s16(a: int16x8_t) -> int32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -31129,12 +29715,10 @@ pub unsafe fn vpaddlq_s16(a: int16x8_t) -> int32x4_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddls.v4i32.v8i16")] fn _vpaddlq_s16(a: int16x8_t) -> int32x4_t; } - _vpaddlq_s16(a) + unsafe { _vpaddlq_s16(a) } } #[doc = "Signed Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddl_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -31151,7 +29735,7 @@ pub unsafe fn vpaddlq_s16(a: int16x8_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vpaddl_s32(a: int32x2_t) -> int64x1_t { +pub fn vpaddl_s32(a: int32x2_t) -> int64x1_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -31160,12 +29744,10 @@ pub unsafe fn vpaddl_s32(a: int32x2_t) -> int64x1_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddls.v1i64.v2i32")] fn _vpaddl_s32(a: int32x2_t) -> int64x1_t; } - _vpaddl_s32(a) + unsafe { _vpaddl_s32(a) } } #[doc = "Signed Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddlq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -31182,7 +29764,7 @@ pub unsafe fn vpaddl_s32(a: int32x2_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vpaddlq_s32(a: int32x4_t) -> int64x2_t { +pub fn vpaddlq_s32(a: int32x4_t) -> int64x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -31191,12 +29773,10 @@ pub unsafe fn vpaddlq_s32(a: int32x4_t) -> int64x2_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddls.v2i64.v4i32")] fn _vpaddlq_s32(a: int32x4_t) -> int64x2_t; } - _vpaddlq_s32(a) + unsafe { _vpaddlq_s32(a) } } #[doc = "Unsigned Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddl_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -31213,7 +29793,7 @@ pub unsafe fn vpaddlq_s32(a: int32x4_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vpaddl_u8(a: uint8x8_t) -> uint16x4_t { +pub fn vpaddl_u8(a: uint8x8_t) -> uint16x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -31222,12 +29802,10 @@ pub unsafe fn vpaddl_u8(a: uint8x8_t) -> uint16x4_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddlu.v4i16.v8i8")] fn _vpaddl_u8(a: uint8x8_t) -> uint16x4_t; } - _vpaddl_u8(a) + unsafe { _vpaddl_u8(a) } } #[doc = "Unsigned Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddlq_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -31244,7 +29822,7 @@ pub unsafe fn vpaddl_u8(a: uint8x8_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vpaddlq_u8(a: uint8x16_t) -> uint16x8_t { +pub fn vpaddlq_u8(a: uint8x16_t) -> uint16x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -31253,12 +29831,10 @@ pub unsafe fn vpaddlq_u8(a: uint8x16_t) -> uint16x8_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddlu.v8i16.v16i8")] fn _vpaddlq_u8(a: uint8x16_t) -> uint16x8_t; } - _vpaddlq_u8(a) + unsafe { _vpaddlq_u8(a) } } #[doc = "Unsigned Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddl_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -31275,7 +29851,7 @@ pub unsafe fn vpaddlq_u8(a: uint8x16_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vpaddl_u16(a: uint16x4_t) -> uint32x2_t { +pub fn vpaddl_u16(a: uint16x4_t) -> uint32x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -31284,12 +29860,10 @@ pub unsafe fn vpaddl_u16(a: uint16x4_t) -> uint32x2_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddlu.v2i32.v4i16")] fn _vpaddl_u16(a: uint16x4_t) -> uint32x2_t; } - _vpaddl_u16(a) + unsafe { _vpaddl_u16(a) } } #[doc = "Unsigned Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddlq_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -31306,7 +29880,7 @@ pub unsafe fn vpaddl_u16(a: uint16x4_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vpaddlq_u16(a: uint16x8_t) -> uint32x4_t { +pub fn vpaddlq_u16(a: uint16x8_t) -> uint32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -31315,12 +29889,10 @@ pub unsafe fn vpaddlq_u16(a: uint16x8_t) -> uint32x4_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddlu.v4i32.v8i16")] fn _vpaddlq_u16(a: uint16x8_t) -> uint32x4_t; } - _vpaddlq_u16(a) + unsafe { _vpaddlq_u16(a) } } #[doc = "Unsigned Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddl_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -31337,7 +29909,7 @@ pub unsafe fn vpaddlq_u16(a: uint16x8_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vpaddl_u32(a: uint32x2_t) -> uint64x1_t { +pub fn vpaddl_u32(a: uint32x2_t) -> uint64x1_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -31346,12 +29918,10 @@ pub unsafe fn vpaddl_u32(a: uint32x2_t) -> uint64x1_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddlu.v1i64.v2i32")] fn _vpaddl_u32(a: uint32x2_t) -> uint64x1_t; } - _vpaddl_u32(a) + unsafe { _vpaddl_u32(a) } } #[doc = "Unsigned Add and Accumulate Long Pairwise."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddlq_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -31368,7 +29938,7 @@ pub unsafe fn vpaddl_u32(a: uint32x2_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vpaddlq_u32(a: uint32x4_t) -> uint64x2_t { +pub fn vpaddlq_u32(a: uint32x4_t) -> uint64x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -31377,12 +29947,10 @@ pub unsafe fn vpaddlq_u32(a: uint32x4_t) -> uint64x2_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddlu.v2i64.v4i32")] fn _vpaddlq_u32(a: uint32x4_t) -> uint64x2_t; } - _vpaddlq_u32(a) + unsafe { _vpaddlq_u32(a) } } #[doc = "Folding maximum of adjacent pairs"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -31399,7 +29967,7 @@ pub unsafe fn vpaddlq_u32(a: uint32x4_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vpmax_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { +pub fn vpmax_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -31408,12 +29976,10 @@ pub unsafe fn vpmax_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxs.v2f32")] fn _vpmax_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t; } - _vpmax_f32(a, b) + unsafe { _vpmax_f32(a, b) } } #[doc = "Folding maximum of adjacent pairs"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -31430,7 +29996,7 @@ pub unsafe fn vpmax_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vpmax_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { +pub fn vpmax_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -31439,12 +30005,10 @@ pub unsafe fn vpmax_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxs.v8i8")] fn _vpmax_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t; } - _vpmax_s8(a, b) + unsafe { _vpmax_s8(a, b) } } #[doc = "Folding maximum of adjacent pairs"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -31461,7 +30025,7 @@ pub unsafe fn vpmax_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vpmax_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { +pub fn vpmax_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -31470,12 +30034,10 @@ pub unsafe fn vpmax_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxs.v4i16")] fn _vpmax_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t; } - _vpmax_s16(a, b) + unsafe { _vpmax_s16(a, b) } } #[doc = "Folding maximum of adjacent pairs"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -31492,7 +30054,7 @@ pub unsafe fn vpmax_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vpmax_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { +pub fn vpmax_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -31501,12 +30063,10 @@ pub unsafe fn vpmax_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxs.v2i32")] fn _vpmax_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t; } - _vpmax_s32(a, b) + unsafe { _vpmax_s32(a, b) } } #[doc = "Folding maximum of adjacent pairs"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -31523,7 +30083,7 @@ pub unsafe fn vpmax_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vpmax_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { +pub fn vpmax_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -31532,12 +30092,10 @@ pub unsafe fn vpmax_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxu.v8i8")] fn _vpmax_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t; } - _vpmax_u8(a, b) + unsafe { _vpmax_u8(a, b) } } #[doc = "Folding maximum of adjacent pairs"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -31554,7 +30112,7 @@ pub unsafe fn vpmax_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vpmax_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { +pub fn vpmax_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -31563,12 +30121,10 @@ pub unsafe fn vpmax_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxu.v4i16")] fn _vpmax_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t; } - _vpmax_u16(a, b) + unsafe { _vpmax_u16(a, b) } } #[doc = "Folding maximum of adjacent pairs"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -31585,7 +30141,7 @@ pub unsafe fn vpmax_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vpmax_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { +pub fn vpmax_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -31594,12 +30150,10 @@ pub unsafe fn vpmax_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxu.v2i32")] fn _vpmax_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t; } - _vpmax_u32(a, b) + unsafe { _vpmax_u32(a, b) } } #[doc = "Folding minimum of adjacent pairs"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -31616,7 +30170,7 @@ pub unsafe fn vpmax_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vpmin_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { +pub fn vpmin_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -31625,12 +30179,10 @@ pub unsafe fn vpmin_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmins.v2f32")] fn _vpmin_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t; } - _vpmin_f32(a, b) + unsafe { _vpmin_f32(a, b) } } #[doc = "Folding minimum of adjacent pairs"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -31647,7 +30199,7 @@ pub unsafe fn vpmin_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vpmin_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { +pub fn vpmin_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -31656,12 +30208,10 @@ pub unsafe fn vpmin_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmins.v8i8")] fn _vpmin_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t; } - _vpmin_s8(a, b) + unsafe { _vpmin_s8(a, b) } } #[doc = "Folding minimum of adjacent pairs"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -31678,7 +30228,7 @@ pub unsafe fn vpmin_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vpmin_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { +pub fn vpmin_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -31687,12 +30237,10 @@ pub unsafe fn vpmin_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmins.v4i16")] fn _vpmin_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t; } - _vpmin_s16(a, b) + unsafe { _vpmin_s16(a, b) } } #[doc = "Folding minimum of adjacent pairs"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -31709,7 +30257,7 @@ pub unsafe fn vpmin_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vpmin_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { +pub fn vpmin_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -31718,12 +30266,10 @@ pub unsafe fn vpmin_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmins.v2i32")] fn _vpmin_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t; } - _vpmin_s32(a, b) + unsafe { _vpmin_s32(a, b) } } #[doc = "Folding minimum of adjacent pairs"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -31740,7 +30286,7 @@ pub unsafe fn vpmin_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vpmin_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { +pub fn vpmin_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -31749,12 +30295,10 @@ pub unsafe fn vpmin_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpminu.v8i8")] fn _vpmin_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t; } - _vpmin_u8(a, b) + unsafe { _vpmin_u8(a, b) } } #[doc = "Folding minimum of adjacent pairs"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -31771,7 +30315,7 @@ pub unsafe fn vpmin_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vpmin_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { +pub fn vpmin_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -31780,12 +30324,10 @@ pub unsafe fn vpmin_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpminu.v4i16")] fn _vpmin_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t; } - _vpmin_u16(a, b) + unsafe { _vpmin_u16(a, b) } } #[doc = "Folding minimum of adjacent pairs"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -31802,7 +30344,7 @@ pub unsafe fn vpmin_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vpmin_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { +pub fn vpmin_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -31811,12 +30353,10 @@ pub unsafe fn vpmin_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpminu.v2i32")] fn _vpmin_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t; } - _vpmin_u32(a, b) + unsafe { _vpmin_u32(a, b) } } #[doc = "Signed saturating Absolute value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabs_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -31833,7 +30373,7 @@ pub unsafe fn vpmin_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqabs_s8(a: int8x8_t) -> int8x8_t { +pub fn vqabs_s8(a: int8x8_t) -> int8x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -31842,12 +30382,10 @@ pub unsafe fn vqabs_s8(a: int8x8_t) -> int8x8_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqabs.v8i8")] fn _vqabs_s8(a: int8x8_t) -> int8x8_t; } - _vqabs_s8(a) + unsafe { _vqabs_s8(a) } } #[doc = "Signed saturating Absolute value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsq_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -31864,7 +30402,7 @@ pub unsafe fn vqabs_s8(a: int8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqabsq_s8(a: int8x16_t) -> int8x16_t { +pub fn vqabsq_s8(a: int8x16_t) -> int8x16_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -31873,12 +30411,10 @@ pub unsafe fn vqabsq_s8(a: int8x16_t) -> int8x16_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqabs.v16i8")] fn _vqabsq_s8(a: int8x16_t) -> int8x16_t; } - _vqabsq_s8(a) + unsafe { _vqabsq_s8(a) } } #[doc = "Signed saturating Absolute value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabs_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -31895,7 +30431,7 @@ pub unsafe fn vqabsq_s8(a: int8x16_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqabs_s16(a: int16x4_t) -> int16x4_t { +pub fn vqabs_s16(a: int16x4_t) -> int16x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -31904,12 +30440,10 @@ pub unsafe fn vqabs_s16(a: int16x4_t) -> int16x4_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqabs.v4i16")] fn _vqabs_s16(a: int16x4_t) -> int16x4_t; } - _vqabs_s16(a) + unsafe { _vqabs_s16(a) } } #[doc = "Signed saturating Absolute value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -31926,7 +30460,7 @@ pub unsafe fn vqabs_s16(a: int16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqabsq_s16(a: int16x8_t) -> int16x8_t { +pub fn vqabsq_s16(a: int16x8_t) -> int16x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -31935,12 +30469,10 @@ pub unsafe fn vqabsq_s16(a: int16x8_t) -> int16x8_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqabs.v8i16")] fn _vqabsq_s16(a: int16x8_t) -> int16x8_t; } - _vqabsq_s16(a) + unsafe { _vqabsq_s16(a) } } #[doc = "Signed saturating Absolute value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabs_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -31957,7 +30489,7 @@ pub unsafe fn vqabsq_s16(a: int16x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqabs_s32(a: int32x2_t) -> int32x2_t { +pub fn vqabs_s32(a: int32x2_t) -> int32x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -31966,12 +30498,10 @@ pub unsafe fn vqabs_s32(a: int32x2_t) -> int32x2_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqabs.v2i32")] fn _vqabs_s32(a: int32x2_t) -> int32x2_t; } - _vqabs_s32(a) + unsafe { _vqabs_s32(a) } } #[doc = "Signed saturating Absolute value"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -31988,7 +30518,7 @@ pub unsafe fn vqabs_s32(a: int32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqabsq_s32(a: int32x4_t) -> int32x4_t { +pub fn vqabsq_s32(a: int32x4_t) -> int32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -31997,12 +30527,10 @@ pub unsafe fn vqabsq_s32(a: int32x4_t) -> int32x4_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqabs.v4i32")] fn _vqabsq_s32(a: int32x4_t) -> int32x4_t; } - _vqabsq_s32(a) + unsafe { _vqabsq_s32(a) } } #[doc = "Saturating add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -32019,7 +30547,7 @@ pub unsafe fn vqabsq_s32(a: int32x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { +pub fn vqadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -32028,12 +30556,10 @@ pub unsafe fn vqadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.sadd.sat.v8i8")] fn _vqadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t; } - _vqadd_s8(a, b) + unsafe { _vqadd_s8(a, b) } } #[doc = "Saturating add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -32050,7 +30576,7 @@ pub unsafe fn vqadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { +pub fn vqaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -32059,12 +30585,10 @@ pub unsafe fn vqaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.sadd.sat.v16i8")] fn _vqaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t; } - _vqaddq_s8(a, b) + unsafe { _vqaddq_s8(a, b) } } #[doc = "Saturating add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -32081,7 +30605,7 @@ pub unsafe fn vqaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { +pub fn vqadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -32090,12 +30614,10 @@ pub unsafe fn vqadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.sadd.sat.v4i16")] fn _vqadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t; } - _vqadd_s16(a, b) + unsafe { _vqadd_s16(a, b) } } #[doc = "Saturating add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -32112,7 +30634,7 @@ pub unsafe fn vqadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { +pub fn vqaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -32121,12 +30643,10 @@ pub unsafe fn vqaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.sadd.sat.v8i16")] fn _vqaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t; } - _vqaddq_s16(a, b) + unsafe { _vqaddq_s16(a, b) } } #[doc = "Saturating add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -32143,7 +30663,7 @@ pub unsafe fn vqaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { +pub fn vqadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -32152,12 +30672,10 @@ pub unsafe fn vqadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.sadd.sat.v2i32")] fn _vqadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t; } - _vqadd_s32(a, b) + unsafe { _vqadd_s32(a, b) } } #[doc = "Saturating add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -32174,7 +30692,7 @@ pub unsafe fn vqadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { +pub fn vqaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -32183,12 +30701,10 @@ pub unsafe fn vqaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.sadd.sat.v4i32")] fn _vqaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t; } - _vqaddq_s32(a, b) + unsafe { _vqaddq_s32(a, b) } } #[doc = "Saturating add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -32205,7 +30721,7 @@ pub unsafe fn vqaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqadd_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { +pub fn vqadd_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -32214,12 +30730,10 @@ pub unsafe fn vqadd_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.sadd.sat.v1i64")] fn _vqadd_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t; } - _vqadd_s64(a, b) + unsafe { _vqadd_s64(a, b) } } #[doc = "Saturating add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -32236,7 +30750,7 @@ pub unsafe fn vqadd_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqaddq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { +pub fn vqaddq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -32245,12 +30759,10 @@ pub unsafe fn vqaddq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.sadd.sat.v2i64")] fn _vqaddq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t; } - _vqaddq_s64(a, b) + unsafe { _vqaddq_s64(a, b) } } #[doc = "Saturating add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -32267,7 +30779,7 @@ pub unsafe fn vqaddq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { +pub fn vqadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -32276,12 +30788,10 @@ pub unsafe fn vqadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.uadd.sat.v8i8")] fn _vqadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t; } - _vqadd_u8(a, b) + unsafe { _vqadd_u8(a, b) } } #[doc = "Saturating add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -32298,7 +30808,7 @@ pub unsafe fn vqadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { +pub fn vqaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -32307,12 +30817,10 @@ pub unsafe fn vqaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.uadd.sat.v16i8")] fn _vqaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t; } - _vqaddq_u8(a, b) + unsafe { _vqaddq_u8(a, b) } } #[doc = "Saturating add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -32329,7 +30837,7 @@ pub unsafe fn vqaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { +pub fn vqadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -32338,12 +30846,10 @@ pub unsafe fn vqadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.uadd.sat.v4i16")] fn _vqadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t; } - _vqadd_u16(a, b) + unsafe { _vqadd_u16(a, b) } } #[doc = "Saturating add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -32360,7 +30866,7 @@ pub unsafe fn vqadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { +pub fn vqaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -32369,12 +30875,10 @@ pub unsafe fn vqaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.uadd.sat.v8i16")] fn _vqaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t; } - _vqaddq_u16(a, b) + unsafe { _vqaddq_u16(a, b) } } #[doc = "Saturating add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -32391,7 +30895,7 @@ pub unsafe fn vqaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { +pub fn vqadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -32400,12 +30904,10 @@ pub unsafe fn vqadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.uadd.sat.v2i32")] fn _vqadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t; } - _vqadd_u32(a, b) + unsafe { _vqadd_u32(a, b) } } #[doc = "Saturating add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -32422,7 +30924,7 @@ pub unsafe fn vqadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { +pub fn vqaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -32431,12 +30933,10 @@ pub unsafe fn vqaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.uadd.sat.v4i32")] fn _vqaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t; } - _vqaddq_u32(a, b) + unsafe { _vqaddq_u32(a, b) } } #[doc = "Saturating add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -32453,7 +30953,7 @@ pub unsafe fn vqaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqadd_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { +pub fn vqadd_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -32462,12 +30962,10 @@ pub unsafe fn vqadd_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.uadd.sat.v1i64")] fn _vqadd_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t; } - _vqadd_u64(a, b) + unsafe { _vqadd_u64(a, b) } } #[doc = "Saturating add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -32484,7 +30982,7 @@ pub unsafe fn vqadd_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqaddq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { +pub fn vqaddq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -32493,12 +30991,10 @@ pub unsafe fn vqaddq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.uadd.sat.v2i64")] fn _vqaddq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t; } - _vqaddq_u64(a, b) + unsafe { _vqaddq_u64(a, b) } } #[doc = "Vector widening saturating doubling multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_lane_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -32516,18 +31012,12 @@ pub unsafe fn vqaddq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqdmlal_lane_s16( - a: int32x4_t, - b: int16x4_t, - c: int16x4_t, -) -> int32x4_t { +pub fn vqdmlal_lane_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t { static_assert_uimm_bits!(N, 2); vqaddq_s32(a, vqdmull_lane_s16::(b, c)) } #[doc = "Vector widening saturating doubling multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_lane_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -32545,18 +31035,12 @@ pub unsafe fn vqdmlal_lane_s16( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqdmlal_lane_s32( - a: int64x2_t, - b: int32x2_t, - c: int32x2_t, -) -> int64x2_t { +pub fn vqdmlal_lane_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t { static_assert_uimm_bits!(N, 1); vqaddq_s64(a, vqdmull_lane_s32::(b, c)) } #[doc = "Vector widening saturating doubling multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_n_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -32573,13 +31057,11 @@ pub unsafe fn vqdmlal_lane_s32( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqdmlal_n_s16(a: int32x4_t, b: int16x4_t, c: i16) -> int32x4_t { +pub fn vqdmlal_n_s16(a: int32x4_t, b: int16x4_t, c: i16) -> int32x4_t { vqaddq_s32(a, vqdmull_n_s16(b, c)) } #[doc = "Vector widening saturating doubling multiply accumulate with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_n_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -32596,13 +31078,11 @@ pub unsafe fn vqdmlal_n_s16(a: int32x4_t, b: int16x4_t, c: i16) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqdmlal_n_s32(a: int64x2_t, b: int32x2_t, c: i32) -> int64x2_t { +pub fn vqdmlal_n_s32(a: int64x2_t, b: int32x2_t, c: i32) -> int64x2_t { vqaddq_s64(a, vqdmull_n_s32(b, c)) } #[doc = "Signed saturating doubling multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -32619,13 +31099,11 @@ pub unsafe fn vqdmlal_n_s32(a: int64x2_t, b: int32x2_t, c: i32) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqdmlal_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t { +pub fn vqdmlal_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t { vqaddq_s32(a, vqdmull_s16(b, c)) } #[doc = "Signed saturating doubling multiply-add long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -32642,13 +31120,11 @@ pub unsafe fn vqdmlal_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqdmlal_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t { +pub fn vqdmlal_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t { vqaddq_s64(a, vqdmull_s32(b, c)) } #[doc = "Vector widening saturating doubling multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_lane_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -32666,18 +31142,12 @@ pub unsafe fn vqdmlal_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqdmlsl_lane_s16( - a: int32x4_t, - b: int16x4_t, - c: int16x4_t, -) -> int32x4_t { +pub fn vqdmlsl_lane_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t { static_assert_uimm_bits!(N, 2); vqsubq_s32(a, vqdmull_lane_s16::(b, c)) } #[doc = "Vector widening saturating doubling multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_lane_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -32695,18 +31165,12 @@ pub unsafe fn vqdmlsl_lane_s16( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqdmlsl_lane_s32( - a: int64x2_t, - b: int32x2_t, - c: int32x2_t, -) -> int64x2_t { +pub fn vqdmlsl_lane_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t { static_assert_uimm_bits!(N, 1); vqsubq_s64(a, vqdmull_lane_s32::(b, c)) } #[doc = "Vector widening saturating doubling multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_n_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -32723,13 +31187,11 @@ pub unsafe fn vqdmlsl_lane_s32( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqdmlsl_n_s16(a: int32x4_t, b: int16x4_t, c: i16) -> int32x4_t { +pub fn vqdmlsl_n_s16(a: int32x4_t, b: int16x4_t, c: i16) -> int32x4_t { vqsubq_s32(a, vqdmull_n_s16(b, c)) } #[doc = "Vector widening saturating doubling multiply subtract with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_n_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -32746,13 +31208,11 @@ pub unsafe fn vqdmlsl_n_s16(a: int32x4_t, b: int16x4_t, c: i16) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqdmlsl_n_s32(a: int64x2_t, b: int32x2_t, c: i32) -> int64x2_t { +pub fn vqdmlsl_n_s32(a: int64x2_t, b: int32x2_t, c: i32) -> int64x2_t { vqsubq_s64(a, vqdmull_n_s32(b, c)) } #[doc = "Signed saturating doubling multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -32769,13 +31229,11 @@ pub unsafe fn vqdmlsl_n_s32(a: int64x2_t, b: int32x2_t, c: i32) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqdmlsl_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t { +pub fn vqdmlsl_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t { vqsubq_s32(a, vqdmull_s16(b, c)) } #[doc = "Signed saturating doubling multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -32792,13 +31250,11 @@ pub unsafe fn vqdmlsl_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqdmlsl_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t { +pub fn vqdmlsl_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t { vqsubq_s64(a, vqdmull_s32(b, c)) } #[doc = "Vector saturating doubling multiply high by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_laneq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -32816,14 +31272,12 @@ pub unsafe fn vqdmlsl_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqdmulh_laneq_s16(a: int16x4_t, b: int16x8_t) -> int16x4_t { +pub fn vqdmulh_laneq_s16(a: int16x4_t, b: int16x8_t) -> int16x4_t { static_assert_uimm_bits!(LANE, 3); - vqdmulh_s16(a, vdup_n_s16(simd_extract!(b, LANE as u32))) + unsafe { vqdmulh_s16(a, vdup_n_s16(simd_extract!(b, LANE as u32))) } } #[doc = "Vector saturating doubling multiply high by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_laneq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -32841,14 +31295,12 @@ pub unsafe fn vqdmulh_laneq_s16(a: int16x4_t, b: int16x8_t) -> target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqdmulhq_laneq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { +pub fn vqdmulhq_laneq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { static_assert_uimm_bits!(LANE, 3); - vqdmulhq_s16(a, vdupq_n_s16(simd_extract!(b, LANE as u32))) + unsafe { vqdmulhq_s16(a, vdupq_n_s16(simd_extract!(b, LANE as u32))) } } #[doc = "Vector saturating doubling multiply high by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_laneq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -32866,14 +31318,12 @@ pub unsafe fn vqdmulhq_laneq_s16(a: int16x8_t, b: int16x8_t) -> target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqdmulh_laneq_s32(a: int32x2_t, b: int32x4_t) -> int32x2_t { +pub fn vqdmulh_laneq_s32(a: int32x2_t, b: int32x4_t) -> int32x2_t { static_assert_uimm_bits!(LANE, 2); - vqdmulh_s32(a, vdup_n_s32(simd_extract!(b, LANE as u32))) + unsafe { vqdmulh_s32(a, vdup_n_s32(simd_extract!(b, LANE as u32))) } } #[doc = "Vector saturating doubling multiply high by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_laneq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -32891,14 +31341,12 @@ pub unsafe fn vqdmulh_laneq_s32(a: int32x2_t, b: int32x4_t) -> target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqdmulhq_laneq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { +pub fn vqdmulhq_laneq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { static_assert_uimm_bits!(LANE, 2); - vqdmulhq_s32(a, vdupq_n_s32(simd_extract!(b, LANE as u32))) + unsafe { vqdmulhq_s32(a, vdupq_n_s32(simd_extract!(b, LANE as u32))) } } #[doc = "Vector saturating doubling multiply high with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_n_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -32915,14 +31363,12 @@ pub unsafe fn vqdmulhq_laneq_s32(a: int32x4_t, b: int32x4_t) -> target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqdmulh_n_s16(a: int16x4_t, b: i16) -> int16x4_t { +pub fn vqdmulh_n_s16(a: int16x4_t, b: i16) -> int16x4_t { let b: int16x4_t = vdup_n_s16(b); vqdmulh_s16(a, b) } #[doc = "Vector saturating doubling multiply high with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_n_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -32939,14 +31385,12 @@ pub unsafe fn vqdmulh_n_s16(a: int16x4_t, b: i16) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqdmulhq_n_s16(a: int16x8_t, b: i16) -> int16x8_t { +pub fn vqdmulhq_n_s16(a: int16x8_t, b: i16) -> int16x8_t { let b: int16x8_t = vdupq_n_s16(b); vqdmulhq_s16(a, b) } #[doc = "Vector saturating doubling multiply high with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_n_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -32963,14 +31407,12 @@ pub unsafe fn vqdmulhq_n_s16(a: int16x8_t, b: i16) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqdmulh_n_s32(a: int32x2_t, b: i32) -> int32x2_t { +pub fn vqdmulh_n_s32(a: int32x2_t, b: i32) -> int32x2_t { let b: int32x2_t = vdup_n_s32(b); vqdmulh_s32(a, b) } #[doc = "Vector saturating doubling multiply high with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_n_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -32987,14 +31429,12 @@ pub unsafe fn vqdmulh_n_s32(a: int32x2_t, b: i32) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqdmulhq_n_s32(a: int32x4_t, b: i32) -> int32x4_t { +pub fn vqdmulhq_n_s32(a: int32x4_t, b: i32) -> int32x4_t { let b: int32x4_t = vdupq_n_s32(b); vqdmulhq_s32(a, b) } #[doc = "Signed saturating doubling multiply returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -33011,7 +31451,7 @@ pub unsafe fn vqdmulhq_n_s32(a: int32x4_t, b: i32) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqdmulh_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { +pub fn vqdmulh_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqdmulh.v4i16")] #[cfg_attr( @@ -33020,12 +31460,10 @@ pub unsafe fn vqdmulh_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { )] fn _vqdmulh_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t; } - _vqdmulh_s16(a, b) + unsafe { _vqdmulh_s16(a, b) } } #[doc = "Signed saturating doubling multiply returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -33042,7 +31480,7 @@ pub unsafe fn vqdmulh_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqdmulhq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { +pub fn vqdmulhq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqdmulh.v8i16")] #[cfg_attr( @@ -33051,12 +31489,10 @@ pub unsafe fn vqdmulhq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { )] fn _vqdmulhq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t; } - _vqdmulhq_s16(a, b) + unsafe { _vqdmulhq_s16(a, b) } } #[doc = "Signed saturating doubling multiply returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -33073,7 +31509,7 @@ pub unsafe fn vqdmulhq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqdmulh_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { +pub fn vqdmulh_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqdmulh.v2i32")] #[cfg_attr( @@ -33082,12 +31518,10 @@ pub unsafe fn vqdmulh_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { )] fn _vqdmulh_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t; } - _vqdmulh_s32(a, b) + unsafe { _vqdmulh_s32(a, b) } } #[doc = "Signed saturating doubling multiply returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -33104,7 +31538,7 @@ pub unsafe fn vqdmulh_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqdmulhq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { +pub fn vqdmulhq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqdmulh.v4i32")] #[cfg_attr( @@ -33113,12 +31547,10 @@ pub unsafe fn vqdmulhq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { )] fn _vqdmulhq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t; } - _vqdmulhq_s32(a, b) + unsafe { _vqdmulhq_s32(a, b) } } #[doc = "Vector saturating doubling long multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_lane_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -33136,15 +31568,15 @@ pub unsafe fn vqdmulhq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqdmull_lane_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t { +pub fn vqdmull_lane_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t { static_assert_uimm_bits!(N, 2); - let b: int16x4_t = simd_shuffle!(b, b, [N as u32, N as u32, N as u32, N as u32]); - vqdmull_s16(a, b) + unsafe { + let b: int16x4_t = simd_shuffle!(b, b, [N as u32, N as u32, N as u32, N as u32]); + vqdmull_s16(a, b) + } } #[doc = "Vector saturating doubling long multiply by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_lane_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -33162,15 +31594,15 @@ pub unsafe fn vqdmull_lane_s16(a: int16x4_t, b: int16x4_t) -> int3 target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqdmull_lane_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t { +pub fn vqdmull_lane_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t { static_assert_uimm_bits!(N, 1); - let b: int32x2_t = simd_shuffle!(b, b, [N as u32, N as u32]); - vqdmull_s32(a, b) + unsafe { + let b: int32x2_t = simd_shuffle!(b, b, [N as u32, N as u32]); + vqdmull_s32(a, b) + } } #[doc = "Vector saturating doubling long multiply with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_n_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -33187,13 +31619,11 @@ pub unsafe fn vqdmull_lane_s32(a: int32x2_t, b: int32x2_t) -> int6 target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqdmull_n_s16(a: int16x4_t, b: i16) -> int32x4_t { +pub fn vqdmull_n_s16(a: int16x4_t, b: i16) -> int32x4_t { vqdmull_s16(a, vdup_n_s16(b)) } #[doc = "Vector saturating doubling long multiply with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_n_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -33210,13 +31640,11 @@ pub unsafe fn vqdmull_n_s16(a: int16x4_t, b: i16) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqdmull_n_s32(a: int32x2_t, b: i32) -> int64x2_t { +pub fn vqdmull_n_s32(a: int32x2_t, b: i32) -> int64x2_t { vqdmull_s32(a, vdup_n_s32(b)) } #[doc = "Signed saturating doubling multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -33233,7 +31661,7 @@ pub unsafe fn vqdmull_n_s32(a: int32x2_t, b: i32) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqdmull_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t { +pub fn vqdmull_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqdmull.v4i32")] #[cfg_attr( @@ -33242,12 +31670,10 @@ pub unsafe fn vqdmull_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t { )] fn _vqdmull_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t; } - _vqdmull_s16(a, b) + unsafe { _vqdmull_s16(a, b) } } #[doc = "Signed saturating doubling multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -33264,7 +31690,7 @@ pub unsafe fn vqdmull_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqdmull_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t { +pub fn vqdmull_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqdmull.v2i64")] #[cfg_attr( @@ -33273,12 +31699,10 @@ pub unsafe fn vqdmull_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t { )] fn _vqdmull_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t; } - _vqdmull_s32(a, b) + unsafe { _vqdmull_s32(a, b) } } #[doc = "Signed saturating extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -33295,7 +31719,7 @@ pub unsafe fn vqdmull_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqmovn_s16(a: int16x8_t) -> int8x8_t { +pub fn vqmovn_s16(a: int16x8_t) -> int8x8_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovns.v8i8")] #[cfg_attr( @@ -33304,12 +31728,10 @@ pub unsafe fn vqmovn_s16(a: int16x8_t) -> int8x8_t { )] fn _vqmovn_s16(a: int16x8_t) -> int8x8_t; } - _vqmovn_s16(a) + unsafe { _vqmovn_s16(a) } } #[doc = "Signed saturating extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -33326,7 +31748,7 @@ pub unsafe fn vqmovn_s16(a: int16x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqmovn_s32(a: int32x4_t) -> int16x4_t { +pub fn vqmovn_s32(a: int32x4_t) -> int16x4_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovns.v4i16")] #[cfg_attr( @@ -33335,12 +31757,10 @@ pub unsafe fn vqmovn_s32(a: int32x4_t) -> int16x4_t { )] fn _vqmovn_s32(a: int32x4_t) -> int16x4_t; } - _vqmovn_s32(a) + unsafe { _vqmovn_s32(a) } } #[doc = "Signed saturating extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -33357,7 +31777,7 @@ pub unsafe fn vqmovn_s32(a: int32x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqmovn_s64(a: int64x2_t) -> int32x2_t { +pub fn vqmovn_s64(a: int64x2_t) -> int32x2_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovns.v2i32")] #[cfg_attr( @@ -33366,12 +31786,10 @@ pub unsafe fn vqmovn_s64(a: int64x2_t) -> int32x2_t { )] fn _vqmovn_s64(a: int64x2_t) -> int32x2_t; } - _vqmovn_s64(a) + unsafe { _vqmovn_s64(a) } } #[doc = "Unsigned saturating extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -33388,7 +31806,7 @@ pub unsafe fn vqmovn_s64(a: int64x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqmovn_u16(a: uint16x8_t) -> uint8x8_t { +pub fn vqmovn_u16(a: uint16x8_t) -> uint8x8_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovnu.v8i8")] #[cfg_attr( @@ -33397,12 +31815,10 @@ pub unsafe fn vqmovn_u16(a: uint16x8_t) -> uint8x8_t { )] fn _vqmovn_u16(a: uint16x8_t) -> uint8x8_t; } - _vqmovn_u16(a) + unsafe { _vqmovn_u16(a) } } #[doc = "Unsigned saturating extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -33419,7 +31835,7 @@ pub unsafe fn vqmovn_u16(a: uint16x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqmovn_u32(a: uint32x4_t) -> uint16x4_t { +pub fn vqmovn_u32(a: uint32x4_t) -> uint16x4_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovnu.v4i16")] #[cfg_attr( @@ -33428,12 +31844,10 @@ pub unsafe fn vqmovn_u32(a: uint32x4_t) -> uint16x4_t { )] fn _vqmovn_u32(a: uint32x4_t) -> uint16x4_t; } - _vqmovn_u32(a) + unsafe { _vqmovn_u32(a) } } #[doc = "Unsigned saturating extract narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -33450,7 +31864,7 @@ pub unsafe fn vqmovn_u32(a: uint32x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqmovn_u64(a: uint64x2_t) -> uint32x2_t { +pub fn vqmovn_u64(a: uint64x2_t) -> uint32x2_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovnu.v2i32")] #[cfg_attr( @@ -33459,12 +31873,10 @@ pub unsafe fn vqmovn_u64(a: uint64x2_t) -> uint32x2_t { )] fn _vqmovn_u64(a: uint64x2_t) -> uint32x2_t; } - _vqmovn_u64(a) + unsafe { _vqmovn_u64(a) } } #[doc = "Signed saturating extract unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -33481,7 +31893,7 @@ pub unsafe fn vqmovn_u64(a: uint64x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqmovun_s16(a: int16x8_t) -> uint8x8_t { +pub fn vqmovun_s16(a: int16x8_t) -> uint8x8_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovnsu.v8i8")] #[cfg_attr( @@ -33490,12 +31902,10 @@ pub unsafe fn vqmovun_s16(a: int16x8_t) -> uint8x8_t { )] fn _vqmovun_s16(a: int16x8_t) -> uint8x8_t; } - _vqmovun_s16(a) + unsafe { _vqmovun_s16(a) } } #[doc = "Signed saturating extract unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -33512,7 +31922,7 @@ pub unsafe fn vqmovun_s16(a: int16x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqmovun_s32(a: int32x4_t) -> uint16x4_t { +pub fn vqmovun_s32(a: int32x4_t) -> uint16x4_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovnsu.v4i16")] #[cfg_attr( @@ -33521,12 +31931,10 @@ pub unsafe fn vqmovun_s32(a: int32x4_t) -> uint16x4_t { )] fn _vqmovun_s32(a: int32x4_t) -> uint16x4_t; } - _vqmovun_s32(a) + unsafe { _vqmovun_s32(a) } } #[doc = "Signed saturating extract unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -33543,7 +31951,7 @@ pub unsafe fn vqmovun_s32(a: int32x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqmovun_s64(a: int64x2_t) -> uint32x2_t { +pub fn vqmovun_s64(a: int64x2_t) -> uint32x2_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovnsu.v2i32")] #[cfg_attr( @@ -33552,12 +31960,10 @@ pub unsafe fn vqmovun_s64(a: int64x2_t) -> uint32x2_t { )] fn _vqmovun_s64(a: int64x2_t) -> uint32x2_t; } - _vqmovun_s64(a) + unsafe { _vqmovun_s64(a) } } #[doc = "Signed saturating negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqneg_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -33574,7 +31980,7 @@ pub unsafe fn vqmovun_s64(a: int64x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqneg_s8(a: int8x8_t) -> int8x8_t { +pub fn vqneg_s8(a: int8x8_t) -> int8x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -33583,12 +31989,10 @@ pub unsafe fn vqneg_s8(a: int8x8_t) -> int8x8_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqneg.v8i8")] fn _vqneg_s8(a: int8x8_t) -> int8x8_t; } - _vqneg_s8(a) + unsafe { _vqneg_s8(a) } } #[doc = "Signed saturating negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegq_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -33605,7 +32009,7 @@ pub unsafe fn vqneg_s8(a: int8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqnegq_s8(a: int8x16_t) -> int8x16_t { +pub fn vqnegq_s8(a: int8x16_t) -> int8x16_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -33614,12 +32018,10 @@ pub unsafe fn vqnegq_s8(a: int8x16_t) -> int8x16_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqneg.v16i8")] fn _vqnegq_s8(a: int8x16_t) -> int8x16_t; } - _vqnegq_s8(a) + unsafe { _vqnegq_s8(a) } } #[doc = "Signed saturating negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqneg_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -33636,7 +32038,7 @@ pub unsafe fn vqnegq_s8(a: int8x16_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqneg_s16(a: int16x4_t) -> int16x4_t { +pub fn vqneg_s16(a: int16x4_t) -> int16x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -33645,12 +32047,10 @@ pub unsafe fn vqneg_s16(a: int16x4_t) -> int16x4_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqneg.v4i16")] fn _vqneg_s16(a: int16x4_t) -> int16x4_t; } - _vqneg_s16(a) + unsafe { _vqneg_s16(a) } } #[doc = "Signed saturating negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -33667,7 +32067,7 @@ pub unsafe fn vqneg_s16(a: int16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqnegq_s16(a: int16x8_t) -> int16x8_t { +pub fn vqnegq_s16(a: int16x8_t) -> int16x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -33676,12 +32076,10 @@ pub unsafe fn vqnegq_s16(a: int16x8_t) -> int16x8_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqneg.v8i16")] fn _vqnegq_s16(a: int16x8_t) -> int16x8_t; } - _vqnegq_s16(a) + unsafe { _vqnegq_s16(a) } } #[doc = "Signed saturating negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqneg_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -33698,7 +32096,7 @@ pub unsafe fn vqnegq_s16(a: int16x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqneg_s32(a: int32x2_t) -> int32x2_t { +pub fn vqneg_s32(a: int32x2_t) -> int32x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -33707,12 +32105,10 @@ pub unsafe fn vqneg_s32(a: int32x2_t) -> int32x2_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqneg.v2i32")] fn _vqneg_s32(a: int32x2_t) -> int32x2_t; } - _vqneg_s32(a) + unsafe { _vqneg_s32(a) } } #[doc = "Signed saturating negate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -33729,7 +32125,7 @@ pub unsafe fn vqneg_s32(a: int32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqnegq_s32(a: int32x4_t) -> int32x4_t { +pub fn vqnegq_s32(a: int32x4_t) -> int32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -33738,12 +32134,10 @@ pub unsafe fn vqnegq_s32(a: int32x4_t) -> int32x4_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqneg.v4i32")] fn _vqnegq_s32(a: int32x4_t) -> int32x4_t; } - _vqnegq_s32(a) + unsafe { _vqnegq_s32(a) } } #[doc = "Vector rounding saturating doubling multiply high by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_lane_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -33761,15 +32155,16 @@ pub unsafe fn vqnegq_s32(a: int32x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqrdmulh_lane_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { +pub fn vqrdmulh_lane_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { static_assert_uimm_bits!(LANE, 2); - let b: int16x4_t = simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vqrdmulh_s16(a, b) + unsafe { + let b: int16x4_t = + simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); + vqrdmulh_s16(a, b) + } } #[doc = "Vector rounding saturating doubling multiply high by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_lane_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -33787,15 +32182,15 @@ pub unsafe fn vqrdmulh_lane_s16(a: int16x4_t, b: int16x4_t) -> target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqrdmulh_lane_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { +pub fn vqrdmulh_lane_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { static_assert_uimm_bits!(LANE, 1); - let b: int32x2_t = simd_shuffle!(b, b, [LANE as u32, LANE as u32]); - vqrdmulh_s32(a, b) + unsafe { + let b: int32x2_t = simd_shuffle!(b, b, [LANE as u32, LANE as u32]); + vqrdmulh_s32(a, b) + } } #[doc = "Vector rounding saturating doubling multiply high by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_laneq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -33813,15 +32208,16 @@ pub unsafe fn vqrdmulh_lane_s32(a: int32x2_t, b: int32x2_t) -> target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqrdmulh_laneq_s16(a: int16x4_t, b: int16x8_t) -> int16x4_t { +pub fn vqrdmulh_laneq_s16(a: int16x4_t, b: int16x8_t) -> int16x4_t { static_assert_uimm_bits!(LANE, 3); - let b: int16x4_t = simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vqrdmulh_s16(a, b) + unsafe { + let b: int16x4_t = + simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); + vqrdmulh_s16(a, b) + } } #[doc = "Vector rounding saturating doubling multiply high by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_laneq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -33839,15 +32235,15 @@ pub unsafe fn vqrdmulh_laneq_s16(a: int16x4_t, b: int16x8_t) -> target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqrdmulh_laneq_s32(a: int32x2_t, b: int32x4_t) -> int32x2_t { +pub fn vqrdmulh_laneq_s32(a: int32x2_t, b: int32x4_t) -> int32x2_t { static_assert_uimm_bits!(LANE, 2); - let b: int32x2_t = simd_shuffle!(b, b, [LANE as u32, LANE as u32]); - vqrdmulh_s32(a, b) + unsafe { + let b: int32x2_t = simd_shuffle!(b, b, [LANE as u32, LANE as u32]); + vqrdmulh_s32(a, b) + } } #[doc = "Vector rounding saturating doubling multiply high by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_lane_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -33865,28 +32261,28 @@ pub unsafe fn vqrdmulh_laneq_s32(a: int32x2_t, b: int32x4_t) -> target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqrdmulhq_lane_s16(a: int16x8_t, b: int16x4_t) -> int16x8_t { +pub fn vqrdmulhq_lane_s16(a: int16x8_t, b: int16x4_t) -> int16x8_t { static_assert_uimm_bits!(LANE, 2); - let b: int16x8_t = simd_shuffle!( - b, - b, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ); - vqrdmulhq_s16(a, b) + unsafe { + let b: int16x8_t = simd_shuffle!( + b, + b, + [ + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32 + ] + ); + vqrdmulhq_s16(a, b) + } } #[doc = "Vector rounding saturating doubling multiply high by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_lane_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -33904,15 +32300,16 @@ pub unsafe fn vqrdmulhq_lane_s16(a: int16x8_t, b: int16x4_t) -> target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqrdmulhq_lane_s32(a: int32x4_t, b: int32x2_t) -> int32x4_t { +pub fn vqrdmulhq_lane_s32(a: int32x4_t, b: int32x2_t) -> int32x4_t { static_assert_uimm_bits!(LANE, 1); - let b: int32x4_t = simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vqrdmulhq_s32(a, b) + unsafe { + let b: int32x4_t = + simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); + vqrdmulhq_s32(a, b) + } } #[doc = "Vector rounding saturating doubling multiply high by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_laneq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -33930,28 +32327,28 @@ pub unsafe fn vqrdmulhq_lane_s32(a: int32x4_t, b: int32x2_t) -> target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqrdmulhq_laneq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { +pub fn vqrdmulhq_laneq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { static_assert_uimm_bits!(LANE, 3); - let b: int16x8_t = simd_shuffle!( - b, - b, - [ - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32, - LANE as u32 - ] - ); - vqrdmulhq_s16(a, b) + unsafe { + let b: int16x8_t = simd_shuffle!( + b, + b, + [ + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32 + ] + ); + vqrdmulhq_s16(a, b) + } } #[doc = "Vector rounding saturating doubling multiply high by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_laneq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -33969,15 +32366,16 @@ pub unsafe fn vqrdmulhq_laneq_s16(a: int16x8_t, b: int16x8_t) - target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqrdmulhq_laneq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { +pub fn vqrdmulhq_laneq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { static_assert_uimm_bits!(LANE, 2); - let b: int32x4_t = simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vqrdmulhq_s32(a, b) + unsafe { + let b: int32x4_t = + simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); + vqrdmulhq_s32(a, b) + } } #[doc = "Vector saturating rounding doubling multiply high with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_n_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -33994,13 +32392,11 @@ pub unsafe fn vqrdmulhq_laneq_s32(a: int32x4_t, b: int32x4_t) - target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqrdmulh_n_s16(a: int16x4_t, b: i16) -> int16x4_t { +pub fn vqrdmulh_n_s16(a: int16x4_t, b: i16) -> int16x4_t { vqrdmulh_s16(a, vdup_n_s16(b)) } #[doc = "Vector saturating rounding doubling multiply high with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_n_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -34017,13 +32413,11 @@ pub unsafe fn vqrdmulh_n_s16(a: int16x4_t, b: i16) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqrdmulhq_n_s16(a: int16x8_t, b: i16) -> int16x8_t { +pub fn vqrdmulhq_n_s16(a: int16x8_t, b: i16) -> int16x8_t { vqrdmulhq_s16(a, vdupq_n_s16(b)) } #[doc = "Vector saturating rounding doubling multiply high with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_n_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -34040,13 +32434,11 @@ pub unsafe fn vqrdmulhq_n_s16(a: int16x8_t, b: i16) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqrdmulh_n_s32(a: int32x2_t, b: i32) -> int32x2_t { +pub fn vqrdmulh_n_s32(a: int32x2_t, b: i32) -> int32x2_t { vqrdmulh_s32(a, vdup_n_s32(b)) } #[doc = "Vector saturating rounding doubling multiply high with scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_n_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -34063,13 +32455,11 @@ pub unsafe fn vqrdmulh_n_s32(a: int32x2_t, b: i32) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqrdmulhq_n_s32(a: int32x4_t, b: i32) -> int32x4_t { +pub fn vqrdmulhq_n_s32(a: int32x4_t, b: i32) -> int32x4_t { vqrdmulhq_s32(a, vdupq_n_s32(b)) } #[doc = "Signed saturating rounding doubling multiply returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -34086,7 +32476,7 @@ pub unsafe fn vqrdmulhq_n_s32(a: int32x4_t, b: i32) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqrdmulh_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { +pub fn vqrdmulh_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrdmulh.v4i16")] #[cfg_attr( @@ -34095,12 +32485,10 @@ pub unsafe fn vqrdmulh_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { )] fn _vqrdmulh_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t; } - _vqrdmulh_s16(a, b) + unsafe { _vqrdmulh_s16(a, b) } } #[doc = "Signed saturating rounding doubling multiply returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -34117,7 +32505,7 @@ pub unsafe fn vqrdmulh_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqrdmulhq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { +pub fn vqrdmulhq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrdmulh.v8i16")] #[cfg_attr( @@ -34126,12 +32514,10 @@ pub unsafe fn vqrdmulhq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { )] fn _vqrdmulhq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t; } - _vqrdmulhq_s16(a, b) + unsafe { _vqrdmulhq_s16(a, b) } } #[doc = "Signed saturating rounding doubling multiply returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -34148,7 +32534,7 @@ pub unsafe fn vqrdmulhq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqrdmulh_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { +pub fn vqrdmulh_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrdmulh.v2i32")] #[cfg_attr( @@ -34157,12 +32543,10 @@ pub unsafe fn vqrdmulh_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { )] fn _vqrdmulh_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t; } - _vqrdmulh_s32(a, b) + unsafe { _vqrdmulh_s32(a, b) } } #[doc = "Signed saturating rounding doubling multiply returning high half"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -34179,7 +32563,7 @@ pub unsafe fn vqrdmulh_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqrdmulhq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { +pub fn vqrdmulhq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrdmulh.v4i32")] #[cfg_attr( @@ -34188,12 +32572,10 @@ pub unsafe fn vqrdmulhq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { )] fn _vqrdmulhq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t; } - _vqrdmulhq_s32(a, b) + unsafe { _vqrdmulhq_s32(a, b) } } #[doc = "Signed saturating rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -34210,7 +32592,7 @@ pub unsafe fn vqrdmulhq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqrshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { +pub fn vqrshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshifts.v8i8")] #[cfg_attr( @@ -34219,12 +32601,10 @@ pub unsafe fn vqrshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { )] fn _vqrshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t; } - _vqrshl_s8(a, b) + unsafe { _vqrshl_s8(a, b) } } #[doc = "Signed saturating rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -34241,7 +32621,7 @@ pub unsafe fn vqrshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqrshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { +pub fn vqrshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshifts.v16i8")] #[cfg_attr( @@ -34250,12 +32630,10 @@ pub unsafe fn vqrshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { )] fn _vqrshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t; } - _vqrshlq_s8(a, b) + unsafe { _vqrshlq_s8(a, b) } } #[doc = "Signed saturating rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -34272,7 +32650,7 @@ pub unsafe fn vqrshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqrshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { +pub fn vqrshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshifts.v4i16")] #[cfg_attr( @@ -34281,12 +32659,10 @@ pub unsafe fn vqrshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { )] fn _vqrshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t; } - _vqrshl_s16(a, b) + unsafe { _vqrshl_s16(a, b) } } #[doc = "Signed saturating rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -34303,7 +32679,7 @@ pub unsafe fn vqrshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqrshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { +pub fn vqrshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshifts.v8i16")] #[cfg_attr( @@ -34312,12 +32688,10 @@ pub unsafe fn vqrshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { )] fn _vqrshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t; } - _vqrshlq_s16(a, b) + unsafe { _vqrshlq_s16(a, b) } } #[doc = "Signed saturating rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -34334,7 +32708,7 @@ pub unsafe fn vqrshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqrshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { +pub fn vqrshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshifts.v2i32")] #[cfg_attr( @@ -34343,12 +32717,10 @@ pub unsafe fn vqrshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { )] fn _vqrshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t; } - _vqrshl_s32(a, b) + unsafe { _vqrshl_s32(a, b) } } #[doc = "Signed saturating rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -34365,7 +32737,7 @@ pub unsafe fn vqrshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqrshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { +pub fn vqrshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshifts.v4i32")] #[cfg_attr( @@ -34374,12 +32746,10 @@ pub unsafe fn vqrshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { )] fn _vqrshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t; } - _vqrshlq_s32(a, b) + unsafe { _vqrshlq_s32(a, b) } } #[doc = "Signed saturating rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -34396,7 +32766,7 @@ pub unsafe fn vqrshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqrshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { +pub fn vqrshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshifts.v1i64")] #[cfg_attr( @@ -34405,12 +32775,10 @@ pub unsafe fn vqrshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { )] fn _vqrshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t; } - _vqrshl_s64(a, b) + unsafe { _vqrshl_s64(a, b) } } #[doc = "Signed saturating rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -34427,7 +32795,7 @@ pub unsafe fn vqrshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqrshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { +pub fn vqrshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshifts.v2i64")] #[cfg_attr( @@ -34436,12 +32804,10 @@ pub unsafe fn vqrshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { )] fn _vqrshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t; } - _vqrshlq_s64(a, b) + unsafe { _vqrshlq_s64(a, b) } } #[doc = "Unsigned signed saturating rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -34458,7 +32824,7 @@ pub unsafe fn vqrshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqrshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t { +pub fn vqrshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftu.v8i8")] #[cfg_attr( @@ -34467,12 +32833,10 @@ pub unsafe fn vqrshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t { )] fn _vqrshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t; } - _vqrshl_u8(a, b) + unsafe { _vqrshl_u8(a, b) } } #[doc = "Unsigned signed saturating rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -34489,7 +32853,7 @@ pub unsafe fn vqrshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqrshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t { +pub fn vqrshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftu.v16i8")] #[cfg_attr( @@ -34498,12 +32862,10 @@ pub unsafe fn vqrshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t { )] fn _vqrshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t; } - _vqrshlq_u8(a, b) + unsafe { _vqrshlq_u8(a, b) } } #[doc = "Unsigned signed saturating rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -34520,7 +32882,7 @@ pub unsafe fn vqrshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqrshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t { +pub fn vqrshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftu.v4i16")] #[cfg_attr( @@ -34529,12 +32891,10 @@ pub unsafe fn vqrshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t { )] fn _vqrshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t; } - _vqrshl_u16(a, b) + unsafe { _vqrshl_u16(a, b) } } #[doc = "Unsigned signed saturating rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -34551,7 +32911,7 @@ pub unsafe fn vqrshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqrshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t { +pub fn vqrshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftu.v8i16")] #[cfg_attr( @@ -34560,12 +32920,10 @@ pub unsafe fn vqrshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t { )] fn _vqrshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t; } - _vqrshlq_u16(a, b) + unsafe { _vqrshlq_u16(a, b) } } #[doc = "Unsigned signed saturating rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -34582,7 +32940,7 @@ pub unsafe fn vqrshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqrshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t { +pub fn vqrshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftu.v2i32")] #[cfg_attr( @@ -34591,12 +32949,10 @@ pub unsafe fn vqrshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t { )] fn _vqrshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t; } - _vqrshl_u32(a, b) + unsafe { _vqrshl_u32(a, b) } } #[doc = "Unsigned signed saturating rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -34613,7 +32969,7 @@ pub unsafe fn vqrshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqrshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t { +pub fn vqrshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftu.v4i32")] #[cfg_attr( @@ -34622,12 +32978,10 @@ pub unsafe fn vqrshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t { )] fn _vqrshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t; } - _vqrshlq_u32(a, b) + unsafe { _vqrshlq_u32(a, b) } } #[doc = "Unsigned signed saturating rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -34644,7 +32998,7 @@ pub unsafe fn vqrshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqrshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t { +pub fn vqrshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftu.v1i64")] #[cfg_attr( @@ -34653,12 +33007,10 @@ pub unsafe fn vqrshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t { )] fn _vqrshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t; } - _vqrshl_u64(a, b) + unsafe { _vqrshl_u64(a, b) } } #[doc = "Unsigned signed saturating rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -34675,7 +33027,7 @@ pub unsafe fn vqrshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqrshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t { +pub fn vqrshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftu.v2i64")] #[cfg_attr( @@ -34684,84 +33036,80 @@ pub unsafe fn vqrshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t { )] fn _vqrshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t; } - _vqrshlq_u64(a, b) + unsafe { _vqrshlq_u64(a, b) } } #[doc = "Signed saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vqrshrn, N = 2))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vqrshrn_n_s16(a: int16x8_t) -> int8x8_t { +pub fn vqrshrn_n_s16(a: int16x8_t) -> int8x8_t { static_assert!(N >= 1 && N <= 8); unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftns.v8i8")] fn _vqrshrn_n_s16(a: int16x8_t, n: int16x8_t) -> int8x8_t; } - _vqrshrn_n_s16( - a, - const { - int16x8_t([ - -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, - -N as i16, - ]) - }, - ) + unsafe { + _vqrshrn_n_s16( + a, + const { + int16x8_t([ + -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, + -N as i16, + ]) + }, + ) + } } #[doc = "Signed saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vqrshrn, N = 2))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vqrshrn_n_s32(a: int32x4_t) -> int16x4_t { +pub fn vqrshrn_n_s32(a: int32x4_t) -> int16x4_t { static_assert!(N >= 1 && N <= 16); unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftns.v4i16")] fn _vqrshrn_n_s32(a: int32x4_t, n: int32x4_t) -> int16x4_t; } - _vqrshrn_n_s32( - a, - const { int32x4_t([-N as i32, -N as i32, -N as i32, -N as i32]) }, - ) + unsafe { + _vqrshrn_n_s32( + a, + const { int32x4_t([-N as i32, -N as i32, -N as i32, -N as i32]) }, + ) + } } #[doc = "Signed saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vqrshrn, N = 2))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vqrshrn_n_s64(a: int64x2_t) -> int32x2_t { +pub fn vqrshrn_n_s64(a: int64x2_t) -> int32x2_t { static_assert!(N >= 1 && N <= 32); unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftns.v2i32")] fn _vqrshrn_n_s64(a: int64x2_t, n: int64x2_t) -> int32x2_t; } - _vqrshrn_n_s64(a, const { int64x2_t([-N as i64, -N as i64]) }) + unsafe { _vqrshrn_n_s64(a, const { int64x2_t([-N as i64, -N as i64]) }) } } #[doc = "Signed saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(sqrshrn, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqrshrn_n_s16(a: int16x8_t) -> int8x8_t { +pub fn vqrshrn_n_s16(a: int16x8_t) -> int8x8_t { static_assert!(N >= 1 && N <= 8); unsafe extern "unadjusted" { #[cfg_attr( @@ -34770,19 +33118,17 @@ pub unsafe fn vqrshrn_n_s16(a: int16x8_t) -> int8x8_t { )] fn _vqrshrn_n_s16(a: int16x8_t, n: i32) -> int8x8_t; } - _vqrshrn_n_s16(a, N) + unsafe { _vqrshrn_n_s16(a, N) } } #[doc = "Signed saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(sqrshrn, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqrshrn_n_s32(a: int32x4_t) -> int16x4_t { +pub fn vqrshrn_n_s32(a: int32x4_t) -> int16x4_t { static_assert!(N >= 1 && N <= 16); unsafe extern "unadjusted" { #[cfg_attr( @@ -34791,19 +33137,17 @@ pub unsafe fn vqrshrn_n_s32(a: int32x4_t) -> int16x4_t { )] fn _vqrshrn_n_s32(a: int32x4_t, n: i32) -> int16x4_t; } - _vqrshrn_n_s32(a, N) + unsafe { _vqrshrn_n_s32(a, N) } } #[doc = "Signed saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(sqrshrn, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqrshrn_n_s64(a: int64x2_t) -> int32x2_t { +pub fn vqrshrn_n_s64(a: int64x2_t) -> int32x2_t { static_assert!(N >= 1 && N <= 32); unsafe extern "unadjusted" { #[cfg_attr( @@ -34812,84 +33156,80 @@ pub unsafe fn vqrshrn_n_s64(a: int64x2_t) -> int32x2_t { )] fn _vqrshrn_n_s64(a: int64x2_t, n: i32) -> int32x2_t; } - _vqrshrn_n_s64(a, N) + unsafe { _vqrshrn_n_s64(a, N) } } #[doc = "Unsigned signed saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vqrshrn, N = 2))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vqrshrn_n_u16(a: uint16x8_t) -> uint8x8_t { +pub fn vqrshrn_n_u16(a: uint16x8_t) -> uint8x8_t { static_assert!(N >= 1 && N <= 8); unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnu.v8i8")] fn _vqrshrn_n_u16(a: uint16x8_t, n: uint16x8_t) -> uint8x8_t; } - _vqrshrn_n_u16( - a, - const { - uint16x8_t([ - -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, - -N as u16, - ]) - }, - ) + unsafe { + _vqrshrn_n_u16( + a, + const { + uint16x8_t([ + -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, + -N as u16, + ]) + }, + ) + } } #[doc = "Unsigned signed saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vqrshrn, N = 2))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vqrshrn_n_u32(a: uint32x4_t) -> uint16x4_t { +pub fn vqrshrn_n_u32(a: uint32x4_t) -> uint16x4_t { static_assert!(N >= 1 && N <= 16); unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnu.v4i16")] fn _vqrshrn_n_u32(a: uint32x4_t, n: uint32x4_t) -> uint16x4_t; } - _vqrshrn_n_u32( - a, - const { uint32x4_t([-N as u32, -N as u32, -N as u32, -N as u32]) }, - ) + unsafe { + _vqrshrn_n_u32( + a, + const { uint32x4_t([-N as u32, -N as u32, -N as u32, -N as u32]) }, + ) + } } #[doc = "Unsigned signed saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vqrshrn, N = 2))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vqrshrn_n_u64(a: uint64x2_t) -> uint32x2_t { +pub fn vqrshrn_n_u64(a: uint64x2_t) -> uint32x2_t { static_assert!(N >= 1 && N <= 32); unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnu.v2i32")] fn _vqrshrn_n_u64(a: uint64x2_t, n: uint64x2_t) -> uint32x2_t; } - _vqrshrn_n_u64(a, const { uint64x2_t([-N as u64, -N as u64]) }) + unsafe { _vqrshrn_n_u64(a, const { uint64x2_t([-N as u64, -N as u64]) }) } } #[doc = "Unsigned signed saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(uqrshrn, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqrshrn_n_u16(a: uint16x8_t) -> uint8x8_t { +pub fn vqrshrn_n_u16(a: uint16x8_t) -> uint8x8_t { static_assert!(N >= 1 && N <= 8); unsafe extern "unadjusted" { #[cfg_attr( @@ -34898,19 +33238,17 @@ pub unsafe fn vqrshrn_n_u16(a: uint16x8_t) -> uint8x8_t { )] fn _vqrshrn_n_u16(a: uint16x8_t, n: i32) -> uint8x8_t; } - _vqrshrn_n_u16(a, N) + unsafe { _vqrshrn_n_u16(a, N) } } #[doc = "Unsigned signed saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(uqrshrn, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqrshrn_n_u32(a: uint32x4_t) -> uint16x4_t { +pub fn vqrshrn_n_u32(a: uint32x4_t) -> uint16x4_t { static_assert!(N >= 1 && N <= 16); unsafe extern "unadjusted" { #[cfg_attr( @@ -34919,19 +33257,17 @@ pub unsafe fn vqrshrn_n_u32(a: uint32x4_t) -> uint16x4_t { )] fn _vqrshrn_n_u32(a: uint32x4_t, n: i32) -> uint16x4_t; } - _vqrshrn_n_u32(a, N) + unsafe { _vqrshrn_n_u32(a, N) } } #[doc = "Unsigned signed saturating rounded shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(uqrshrn, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqrshrn_n_u64(a: uint64x2_t) -> uint32x2_t { +pub fn vqrshrn_n_u64(a: uint64x2_t) -> uint32x2_t { static_assert!(N >= 1 && N <= 32); unsafe extern "unadjusted" { #[cfg_attr( @@ -34940,84 +33276,80 @@ pub unsafe fn vqrshrn_n_u64(a: uint64x2_t) -> uint32x2_t { )] fn _vqrshrn_n_u64(a: uint64x2_t, n: i32) -> uint32x2_t; } - _vqrshrn_n_u64(a, N) + unsafe { _vqrshrn_n_u64(a, N) } } #[doc = "Signed saturating rounded shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vqrshrun, N = 2))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vqrshrun_n_s16(a: int16x8_t) -> uint8x8_t { +pub fn vqrshrun_n_s16(a: int16x8_t) -> uint8x8_t { static_assert!(N >= 1 && N <= 8); unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnsu.v8i8")] fn _vqrshrun_n_s16(a: int16x8_t, n: int16x8_t) -> uint8x8_t; } - _vqrshrun_n_s16( - a, - const { - int16x8_t([ - -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, - -N as i16, - ]) - }, - ) + unsafe { + _vqrshrun_n_s16( + a, + const { + int16x8_t([ + -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, + -N as i16, + ]) + }, + ) + } } #[doc = "Signed saturating rounded shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vqrshrun, N = 2))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vqrshrun_n_s32(a: int32x4_t) -> uint16x4_t { +pub fn vqrshrun_n_s32(a: int32x4_t) -> uint16x4_t { static_assert!(N >= 1 && N <= 16); unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnsu.v4i16")] fn _vqrshrun_n_s32(a: int32x4_t, n: int32x4_t) -> uint16x4_t; } - _vqrshrun_n_s32( - a, - const { int32x4_t([-N as i32, -N as i32, -N as i32, -N as i32]) }, - ) + unsafe { + _vqrshrun_n_s32( + a, + const { int32x4_t([-N as i32, -N as i32, -N as i32, -N as i32]) }, + ) + } } #[doc = "Signed saturating rounded shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vqrshrun, N = 2))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vqrshrun_n_s64(a: int64x2_t) -> uint32x2_t { +pub fn vqrshrun_n_s64(a: int64x2_t) -> uint32x2_t { static_assert!(N >= 1 && N <= 32); unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnsu.v2i32")] fn _vqrshrun_n_s64(a: int64x2_t, n: int64x2_t) -> uint32x2_t; } - _vqrshrun_n_s64(a, const { int64x2_t([-N as i64, -N as i64]) }) + unsafe { _vqrshrun_n_s64(a, const { int64x2_t([-N as i64, -N as i64]) }) } } #[doc = "Signed saturating rounded shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(sqrshrun, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqrshrun_n_s16(a: int16x8_t) -> uint8x8_t { +pub fn vqrshrun_n_s16(a: int16x8_t) -> uint8x8_t { static_assert!(N >= 1 && N <= 8); unsafe extern "unadjusted" { #[cfg_attr( @@ -35026,19 +33358,17 @@ pub unsafe fn vqrshrun_n_s16(a: int16x8_t) -> uint8x8_t { )] fn _vqrshrun_n_s16(a: int16x8_t, n: i32) -> uint8x8_t; } - _vqrshrun_n_s16(a, N) + unsafe { _vqrshrun_n_s16(a, N) } } #[doc = "Signed saturating rounded shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(sqrshrun, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqrshrun_n_s32(a: int32x4_t) -> uint16x4_t { +pub fn vqrshrun_n_s32(a: int32x4_t) -> uint16x4_t { static_assert!(N >= 1 && N <= 16); unsafe extern "unadjusted" { #[cfg_attr( @@ -35047,19 +33377,17 @@ pub unsafe fn vqrshrun_n_s32(a: int32x4_t) -> uint16x4_t { )] fn _vqrshrun_n_s32(a: int32x4_t, n: i32) -> uint16x4_t; } - _vqrshrun_n_s32(a, N) + unsafe { _vqrshrun_n_s32(a, N) } } #[doc = "Signed saturating rounded shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(sqrshrun, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqrshrun_n_s64(a: int64x2_t) -> uint32x2_t { +pub fn vqrshrun_n_s64(a: int64x2_t) -> uint32x2_t { static_assert!(N >= 1 && N <= 32); unsafe extern "unadjusted" { #[cfg_attr( @@ -35068,12 +33396,10 @@ pub unsafe fn vqrshrun_n_s64(a: int64x2_t) -> uint32x2_t { )] fn _vqrshrun_n_s64(a: int64x2_t, n: i32) -> uint32x2_t; } - _vqrshrun_n_s64(a, N) + unsafe { _vqrshrun_n_s64(a, N) } } #[doc = "Signed saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -35091,14 +33417,12 @@ pub unsafe fn vqrshrun_n_s64(a: int64x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqshl_n_s8(a: int8x8_t) -> int8x8_t { +pub fn vqshl_n_s8(a: int8x8_t) -> int8x8_t { static_assert_uimm_bits!(N, 3); vqshl_s8(a, vdup_n_s8(N as _)) } #[doc = "Signed saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -35116,14 +33440,12 @@ pub unsafe fn vqshl_n_s8(a: int8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqshlq_n_s8(a: int8x16_t) -> int8x16_t { +pub fn vqshlq_n_s8(a: int8x16_t) -> int8x16_t { static_assert_uimm_bits!(N, 3); vqshlq_s8(a, vdupq_n_s8(N as _)) } #[doc = "Signed saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -35141,14 +33463,12 @@ pub unsafe fn vqshlq_n_s8(a: int8x16_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqshl_n_s16(a: int16x4_t) -> int16x4_t { +pub fn vqshl_n_s16(a: int16x4_t) -> int16x4_t { static_assert_uimm_bits!(N, 4); vqshl_s16(a, vdup_n_s16(N as _)) } #[doc = "Signed saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -35166,14 +33486,12 @@ pub unsafe fn vqshl_n_s16(a: int16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqshlq_n_s16(a: int16x8_t) -> int16x8_t { +pub fn vqshlq_n_s16(a: int16x8_t) -> int16x8_t { static_assert_uimm_bits!(N, 4); vqshlq_s16(a, vdupq_n_s16(N as _)) } #[doc = "Signed saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -35191,14 +33509,12 @@ pub unsafe fn vqshlq_n_s16(a: int16x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqshl_n_s32(a: int32x2_t) -> int32x2_t { +pub fn vqshl_n_s32(a: int32x2_t) -> int32x2_t { static_assert_uimm_bits!(N, 5); vqshl_s32(a, vdup_n_s32(N as _)) } #[doc = "Signed saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -35216,14 +33532,12 @@ pub unsafe fn vqshl_n_s32(a: int32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqshlq_n_s32(a: int32x4_t) -> int32x4_t { +pub fn vqshlq_n_s32(a: int32x4_t) -> int32x4_t { static_assert_uimm_bits!(N, 5); vqshlq_s32(a, vdupq_n_s32(N as _)) } #[doc = "Signed saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -35241,14 +33555,12 @@ pub unsafe fn vqshlq_n_s32(a: int32x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqshl_n_s64(a: int64x1_t) -> int64x1_t { +pub fn vqshl_n_s64(a: int64x1_t) -> int64x1_t { static_assert_uimm_bits!(N, 6); vqshl_s64(a, vdup_n_s64(N as _)) } #[doc = "Signed saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -35266,14 +33578,12 @@ pub unsafe fn vqshl_n_s64(a: int64x1_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqshlq_n_s64(a: int64x2_t) -> int64x2_t { +pub fn vqshlq_n_s64(a: int64x2_t) -> int64x2_t { static_assert_uimm_bits!(N, 6); vqshlq_s64(a, vdupq_n_s64(N as _)) } #[doc = "Unsigned saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -35291,14 +33601,12 @@ pub unsafe fn vqshlq_n_s64(a: int64x2_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqshl_n_u8(a: uint8x8_t) -> uint8x8_t { +pub fn vqshl_n_u8(a: uint8x8_t) -> uint8x8_t { static_assert_uimm_bits!(N, 3); vqshl_u8(a, vdup_n_s8(N as _)) } #[doc = "Unsigned saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -35316,14 +33624,12 @@ pub unsafe fn vqshl_n_u8(a: uint8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqshlq_n_u8(a: uint8x16_t) -> uint8x16_t { +pub fn vqshlq_n_u8(a: uint8x16_t) -> uint8x16_t { static_assert_uimm_bits!(N, 3); vqshlq_u8(a, vdupq_n_s8(N as _)) } #[doc = "Unsigned saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -35341,14 +33647,12 @@ pub unsafe fn vqshlq_n_u8(a: uint8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqshl_n_u16(a: uint16x4_t) -> uint16x4_t { +pub fn vqshl_n_u16(a: uint16x4_t) -> uint16x4_t { static_assert_uimm_bits!(N, 4); vqshl_u16(a, vdup_n_s16(N as _)) } #[doc = "Unsigned saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -35366,14 +33670,12 @@ pub unsafe fn vqshl_n_u16(a: uint16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqshlq_n_u16(a: uint16x8_t) -> uint16x8_t { +pub fn vqshlq_n_u16(a: uint16x8_t) -> uint16x8_t { static_assert_uimm_bits!(N, 4); vqshlq_u16(a, vdupq_n_s16(N as _)) } #[doc = "Unsigned saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -35391,14 +33693,12 @@ pub unsafe fn vqshlq_n_u16(a: uint16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqshl_n_u32(a: uint32x2_t) -> uint32x2_t { +pub fn vqshl_n_u32(a: uint32x2_t) -> uint32x2_t { static_assert_uimm_bits!(N, 5); vqshl_u32(a, vdup_n_s32(N as _)) } #[doc = "Unsigned saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -35416,14 +33716,12 @@ pub unsafe fn vqshl_n_u32(a: uint32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqshlq_n_u32(a: uint32x4_t) -> uint32x4_t { +pub fn vqshlq_n_u32(a: uint32x4_t) -> uint32x4_t { static_assert_uimm_bits!(N, 5); vqshlq_u32(a, vdupq_n_s32(N as _)) } #[doc = "Unsigned saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -35441,14 +33739,12 @@ pub unsafe fn vqshlq_n_u32(a: uint32x4_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqshl_n_u64(a: uint64x1_t) -> uint64x1_t { +pub fn vqshl_n_u64(a: uint64x1_t) -> uint64x1_t { static_assert_uimm_bits!(N, 6); vqshl_u64(a, vdup_n_s64(N as _)) } #[doc = "Unsigned saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -35466,14 +33762,12 @@ pub unsafe fn vqshl_n_u64(a: uint64x1_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqshlq_n_u64(a: uint64x2_t) -> uint64x2_t { +pub fn vqshlq_n_u64(a: uint64x2_t) -> uint64x2_t { static_assert_uimm_bits!(N, 6); vqshlq_u64(a, vdupq_n_s64(N as _)) } #[doc = "Signed saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -35490,7 +33784,7 @@ pub unsafe fn vqshlq_n_u64(a: uint64x2_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { +pub fn vqshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshifts.v8i8")] #[cfg_attr( @@ -35499,12 +33793,10 @@ pub unsafe fn vqshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { )] fn _vqshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t; } - _vqshl_s8(a, b) + unsafe { _vqshl_s8(a, b) } } #[doc = "Signed saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -35521,7 +33813,7 @@ pub unsafe fn vqshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { +pub fn vqshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshifts.v16i8")] #[cfg_attr( @@ -35530,12 +33822,10 @@ pub unsafe fn vqshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { )] fn _vqshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t; } - _vqshlq_s8(a, b) + unsafe { _vqshlq_s8(a, b) } } #[doc = "Signed saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -35552,7 +33842,7 @@ pub unsafe fn vqshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { +pub fn vqshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshifts.v4i16")] #[cfg_attr( @@ -35561,12 +33851,10 @@ pub unsafe fn vqshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { )] fn _vqshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t; } - _vqshl_s16(a, b) + unsafe { _vqshl_s16(a, b) } } #[doc = "Signed saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -35583,7 +33871,7 @@ pub unsafe fn vqshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { +pub fn vqshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshifts.v8i16")] #[cfg_attr( @@ -35592,12 +33880,10 @@ pub unsafe fn vqshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { )] fn _vqshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t; } - _vqshlq_s16(a, b) + unsafe { _vqshlq_s16(a, b) } } #[doc = "Signed saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -35614,7 +33900,7 @@ pub unsafe fn vqshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { +pub fn vqshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshifts.v2i32")] #[cfg_attr( @@ -35623,12 +33909,10 @@ pub unsafe fn vqshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { )] fn _vqshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t; } - _vqshl_s32(a, b) + unsafe { _vqshl_s32(a, b) } } #[doc = "Signed saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -35645,7 +33929,7 @@ pub unsafe fn vqshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { +pub fn vqshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshifts.v4i32")] #[cfg_attr( @@ -35654,12 +33938,10 @@ pub unsafe fn vqshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { )] fn _vqshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t; } - _vqshlq_s32(a, b) + unsafe { _vqshlq_s32(a, b) } } #[doc = "Signed saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -35676,7 +33958,7 @@ pub unsafe fn vqshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { +pub fn vqshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshifts.v1i64")] #[cfg_attr( @@ -35685,12 +33967,10 @@ pub unsafe fn vqshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { )] fn _vqshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t; } - _vqshl_s64(a, b) + unsafe { _vqshl_s64(a, b) } } #[doc = "Signed saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -35707,7 +33987,7 @@ pub unsafe fn vqshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { +pub fn vqshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshifts.v2i64")] #[cfg_attr( @@ -35716,12 +33996,10 @@ pub unsafe fn vqshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { )] fn _vqshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t; } - _vqshlq_s64(a, b) + unsafe { _vqshlq_s64(a, b) } } #[doc = "Unsigned saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -35738,7 +34016,7 @@ pub unsafe fn vqshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t { +pub fn vqshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftu.v8i8")] #[cfg_attr( @@ -35747,12 +34025,10 @@ pub unsafe fn vqshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t { )] fn _vqshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t; } - _vqshl_u8(a, b) + unsafe { _vqshl_u8(a, b) } } #[doc = "Unsigned saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -35769,7 +34045,7 @@ pub unsafe fn vqshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t { +pub fn vqshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftu.v16i8")] #[cfg_attr( @@ -35778,12 +34054,10 @@ pub unsafe fn vqshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t { )] fn _vqshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t; } - _vqshlq_u8(a, b) + unsafe { _vqshlq_u8(a, b) } } #[doc = "Unsigned saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -35800,7 +34074,7 @@ pub unsafe fn vqshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t { +pub fn vqshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftu.v4i16")] #[cfg_attr( @@ -35809,12 +34083,10 @@ pub unsafe fn vqshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t { )] fn _vqshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t; } - _vqshl_u16(a, b) + unsafe { _vqshl_u16(a, b) } } #[doc = "Unsigned saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -35831,7 +34103,7 @@ pub unsafe fn vqshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t { +pub fn vqshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftu.v8i16")] #[cfg_attr( @@ -35840,12 +34112,10 @@ pub unsafe fn vqshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t { )] fn _vqshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t; } - _vqshlq_u16(a, b) + unsafe { _vqshlq_u16(a, b) } } #[doc = "Unsigned saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -35862,7 +34132,7 @@ pub unsafe fn vqshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t { +pub fn vqshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftu.v2i32")] #[cfg_attr( @@ -35871,12 +34141,10 @@ pub unsafe fn vqshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t { )] fn _vqshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t; } - _vqshl_u32(a, b) + unsafe { _vqshl_u32(a, b) } } #[doc = "Unsigned saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -35893,7 +34161,7 @@ pub unsafe fn vqshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t { +pub fn vqshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftu.v4i32")] #[cfg_attr( @@ -35902,12 +34170,10 @@ pub unsafe fn vqshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t { )] fn _vqshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t; } - _vqshlq_u32(a, b) + unsafe { _vqshlq_u32(a, b) } } #[doc = "Unsigned saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -35924,7 +34190,7 @@ pub unsafe fn vqshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t { +pub fn vqshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftu.v1i64")] #[cfg_attr( @@ -35933,12 +34199,10 @@ pub unsafe fn vqshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t { )] fn _vqshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t; } - _vqshl_u64(a, b) + unsafe { _vqshl_u64(a, b) } } #[doc = "Unsigned saturating shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -35955,7 +34219,7 @@ pub unsafe fn vqshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t { +pub fn vqshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftu.v2i64")] #[cfg_attr( @@ -35964,191 +34228,183 @@ pub unsafe fn vqshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t { )] fn _vqshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t; } - _vqshlq_u64(a, b) + unsafe { _vqshlq_u64(a, b) } } #[doc = "Signed saturating shift left unsigned"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vqshlu, N = 2))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vqshlu_n_s8(a: int8x8_t) -> uint8x8_t { +pub fn vqshlu_n_s8(a: int8x8_t) -> uint8x8_t { static_assert_uimm_bits!(N, 3); unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v8i8")] fn _vqshlu_n_s8(a: int8x8_t, n: int8x8_t) -> uint8x8_t; } - _vqshlu_n_s8( - a, - const { - int8x8_t([ - N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, - ]) - }, - ) + unsafe { + _vqshlu_n_s8( + a, + const { + int8x8_t([ + N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, + ]) + }, + ) + } } #[doc = "Signed saturating shift left unsigned"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vqshlu, N = 2))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vqshluq_n_s8(a: int8x16_t) -> uint8x16_t { +pub fn vqshluq_n_s8(a: int8x16_t) -> uint8x16_t { static_assert_uimm_bits!(N, 3); unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v16i8")] fn _vqshluq_n_s8(a: int8x16_t, n: int8x16_t) -> uint8x16_t; } - _vqshluq_n_s8( - a, - const { - int8x16_t([ - N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, - N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, - ]) - }, - ) + unsafe { + _vqshluq_n_s8( + a, + const { + int8x16_t([ + N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, + N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, + ]) + }, + ) + } } #[doc = "Signed saturating shift left unsigned"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vqshlu, N = 2))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vqshlu_n_s16(a: int16x4_t) -> uint16x4_t { +pub fn vqshlu_n_s16(a: int16x4_t) -> uint16x4_t { static_assert_uimm_bits!(N, 4); unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v4i16")] fn _vqshlu_n_s16(a: int16x4_t, n: int16x4_t) -> uint16x4_t; } - _vqshlu_n_s16( - a, - const { int16x4_t([N as i16, N as i16, N as i16, N as i16]) }, - ) + unsafe { + _vqshlu_n_s16( + a, + const { int16x4_t([N as i16, N as i16, N as i16, N as i16]) }, + ) + } } #[doc = "Signed saturating shift left unsigned"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vqshlu, N = 2))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vqshluq_n_s16(a: int16x8_t) -> uint16x8_t { +pub fn vqshluq_n_s16(a: int16x8_t) -> uint16x8_t { static_assert_uimm_bits!(N, 4); unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v8i16")] fn _vqshluq_n_s16(a: int16x8_t, n: int16x8_t) -> uint16x8_t; } - _vqshluq_n_s16( - a, - const { - int16x8_t([ - N as i16, N as i16, N as i16, N as i16, N as i16, N as i16, N as i16, N as i16, - ]) - }, - ) + unsafe { + _vqshluq_n_s16( + a, + const { + int16x8_t([ + N as i16, N as i16, N as i16, N as i16, N as i16, N as i16, N as i16, N as i16, + ]) + }, + ) + } } #[doc = "Signed saturating shift left unsigned"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vqshlu, N = 2))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vqshlu_n_s32(a: int32x2_t) -> uint32x2_t { +pub fn vqshlu_n_s32(a: int32x2_t) -> uint32x2_t { static_assert_uimm_bits!(N, 5); unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v2i32")] fn _vqshlu_n_s32(a: int32x2_t, n: int32x2_t) -> uint32x2_t; } - _vqshlu_n_s32(a, const { int32x2_t([N as i32, N as i32]) }) + unsafe { _vqshlu_n_s32(a, const { int32x2_t([N as i32, N as i32]) }) } } #[doc = "Signed saturating shift left unsigned"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vqshlu, N = 2))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vqshluq_n_s32(a: int32x4_t) -> uint32x4_t { +pub fn vqshluq_n_s32(a: int32x4_t) -> uint32x4_t { static_assert_uimm_bits!(N, 5); unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v4i32")] fn _vqshluq_n_s32(a: int32x4_t, n: int32x4_t) -> uint32x4_t; } - _vqshluq_n_s32( - a, - const { int32x4_t([N as i32, N as i32, N as i32, N as i32]) }, - ) + unsafe { + _vqshluq_n_s32( + a, + const { int32x4_t([N as i32, N as i32, N as i32, N as i32]) }, + ) + } } #[doc = "Signed saturating shift left unsigned"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vqshlu, N = 2))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vqshlu_n_s64(a: int64x1_t) -> uint64x1_t { +pub fn vqshlu_n_s64(a: int64x1_t) -> uint64x1_t { static_assert_uimm_bits!(N, 6); unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v1i64")] fn _vqshlu_n_s64(a: int64x1_t, n: int64x1_t) -> uint64x1_t; } - _vqshlu_n_s64(a, const { int64x1_t([N as i64]) }) + unsafe { _vqshlu_n_s64(a, const { int64x1_t([N as i64]) }) } } #[doc = "Signed saturating shift left unsigned"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vqshlu, N = 2))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vqshluq_n_s64(a: int64x2_t) -> uint64x2_t { +pub fn vqshluq_n_s64(a: int64x2_t) -> uint64x2_t { static_assert_uimm_bits!(N, 6); unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v2i64")] fn _vqshluq_n_s64(a: int64x2_t, n: int64x2_t) -> uint64x2_t; } - _vqshluq_n_s64(a, const { int64x2_t([N as i64, N as i64]) }) + unsafe { _vqshluq_n_s64(a, const { int64x2_t([N as i64, N as i64]) }) } } #[doc = "Signed saturating shift left unsigned"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(sqshlu, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshlu_n_s8(a: int8x8_t) -> uint8x8_t { +pub fn vqshlu_n_s8(a: int8x8_t) -> uint8x8_t { static_assert_uimm_bits!(N, 3); unsafe extern "unadjusted" { #[cfg_attr( @@ -36157,26 +34413,26 @@ pub unsafe fn vqshlu_n_s8(a: int8x8_t) -> uint8x8_t { )] fn _vqshlu_n_s8(a: int8x8_t, n: int8x8_t) -> uint8x8_t; } - _vqshlu_n_s8( - a, - const { - int8x8_t([ - N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, - ]) - }, - ) + unsafe { + _vqshlu_n_s8( + a, + const { + int8x8_t([ + N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, + ]) + }, + ) + } } #[doc = "Signed saturating shift left unsigned"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(sqshlu, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshluq_n_s8(a: int8x16_t) -> uint8x16_t { +pub fn vqshluq_n_s8(a: int8x16_t) -> uint8x16_t { static_assert_uimm_bits!(N, 3); unsafe extern "unadjusted" { #[cfg_attr( @@ -36185,27 +34441,27 @@ pub unsafe fn vqshluq_n_s8(a: int8x16_t) -> uint8x16_t { )] fn _vqshluq_n_s8(a: int8x16_t, n: int8x16_t) -> uint8x16_t; } - _vqshluq_n_s8( - a, - const { - int8x16_t([ - N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, - N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, - ]) - }, - ) + unsafe { + _vqshluq_n_s8( + a, + const { + int8x16_t([ + N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, + N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, + ]) + }, + ) + } } #[doc = "Signed saturating shift left unsigned"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(sqshlu, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshlu_n_s16(a: int16x4_t) -> uint16x4_t { +pub fn vqshlu_n_s16(a: int16x4_t) -> uint16x4_t { static_assert_uimm_bits!(N, 4); unsafe extern "unadjusted" { #[cfg_attr( @@ -36214,22 +34470,22 @@ pub unsafe fn vqshlu_n_s16(a: int16x4_t) -> uint16x4_t { )] fn _vqshlu_n_s16(a: int16x4_t, n: int16x4_t) -> uint16x4_t; } - _vqshlu_n_s16( - a, - const { int16x4_t([N as i16, N as i16, N as i16, N as i16]) }, - ) + unsafe { + _vqshlu_n_s16( + a, + const { int16x4_t([N as i16, N as i16, N as i16, N as i16]) }, + ) + } } #[doc = "Signed saturating shift left unsigned"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(sqshlu, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshluq_n_s16(a: int16x8_t) -> uint16x8_t { +pub fn vqshluq_n_s16(a: int16x8_t) -> uint16x8_t { static_assert_uimm_bits!(N, 4); unsafe extern "unadjusted" { #[cfg_attr( @@ -36238,26 +34494,26 @@ pub unsafe fn vqshluq_n_s16(a: int16x8_t) -> uint16x8_t { )] fn _vqshluq_n_s16(a: int16x8_t, n: int16x8_t) -> uint16x8_t; } - _vqshluq_n_s16( - a, - const { - int16x8_t([ - N as i16, N as i16, N as i16, N as i16, N as i16, N as i16, N as i16, N as i16, - ]) - }, - ) + unsafe { + _vqshluq_n_s16( + a, + const { + int16x8_t([ + N as i16, N as i16, N as i16, N as i16, N as i16, N as i16, N as i16, N as i16, + ]) + }, + ) + } } #[doc = "Signed saturating shift left unsigned"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(sqshlu, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshlu_n_s32(a: int32x2_t) -> uint32x2_t { +pub fn vqshlu_n_s32(a: int32x2_t) -> uint32x2_t { static_assert_uimm_bits!(N, 5); unsafe extern "unadjusted" { #[cfg_attr( @@ -36266,19 +34522,17 @@ pub unsafe fn vqshlu_n_s32(a: int32x2_t) -> uint32x2_t { )] fn _vqshlu_n_s32(a: int32x2_t, n: int32x2_t) -> uint32x2_t; } - _vqshlu_n_s32(a, const { int32x2_t([N as i32, N as i32]) }) + unsafe { _vqshlu_n_s32(a, const { int32x2_t([N as i32, N as i32]) }) } } #[doc = "Signed saturating shift left unsigned"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(sqshlu, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshluq_n_s32(a: int32x4_t) -> uint32x4_t { +pub fn vqshluq_n_s32(a: int32x4_t) -> uint32x4_t { static_assert_uimm_bits!(N, 5); unsafe extern "unadjusted" { #[cfg_attr( @@ -36287,22 +34541,22 @@ pub unsafe fn vqshluq_n_s32(a: int32x4_t) -> uint32x4_t { )] fn _vqshluq_n_s32(a: int32x4_t, n: int32x4_t) -> uint32x4_t; } - _vqshluq_n_s32( - a, - const { int32x4_t([N as i32, N as i32, N as i32, N as i32]) }, - ) + unsafe { + _vqshluq_n_s32( + a, + const { int32x4_t([N as i32, N as i32, N as i32, N as i32]) }, + ) + } } #[doc = "Signed saturating shift left unsigned"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(sqshlu, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshlu_n_s64(a: int64x1_t) -> uint64x1_t { +pub fn vqshlu_n_s64(a: int64x1_t) -> uint64x1_t { static_assert_uimm_bits!(N, 6); unsafe extern "unadjusted" { #[cfg_attr( @@ -36311,19 +34565,17 @@ pub unsafe fn vqshlu_n_s64(a: int64x1_t) -> uint64x1_t { )] fn _vqshlu_n_s64(a: int64x1_t, n: int64x1_t) -> uint64x1_t; } - _vqshlu_n_s64(a, const { int64x1_t([N as i64]) }) + unsafe { _vqshlu_n_s64(a, const { int64x1_t([N as i64]) }) } } #[doc = "Signed saturating shift left unsigned"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(sqshlu, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshluq_n_s64(a: int64x2_t) -> uint64x2_t { +pub fn vqshluq_n_s64(a: int64x2_t) -> uint64x2_t { static_assert_uimm_bits!(N, 6); unsafe extern "unadjusted" { #[cfg_attr( @@ -36332,84 +34584,80 @@ pub unsafe fn vqshluq_n_s64(a: int64x2_t) -> uint64x2_t { )] fn _vqshluq_n_s64(a: int64x2_t, n: int64x2_t) -> uint64x2_t; } - _vqshluq_n_s64(a, const { int64x2_t([N as i64, N as i64]) }) + unsafe { _vqshluq_n_s64(a, const { int64x2_t([N as i64, N as i64]) }) } } #[doc = "Signed saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vqshrn, N = 2))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vqshrn_n_s16(a: int16x8_t) -> int8x8_t { +pub fn vqshrn_n_s16(a: int16x8_t) -> int8x8_t { static_assert!(N >= 1 && N <= 8); unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftns.v8i8")] fn _vqshrn_n_s16(a: int16x8_t, n: int16x8_t) -> int8x8_t; } - _vqshrn_n_s16( - a, - const { - int16x8_t([ - -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, - -N as i16, - ]) - }, - ) + unsafe { + _vqshrn_n_s16( + a, + const { + int16x8_t([ + -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, + -N as i16, + ]) + }, + ) + } } #[doc = "Signed saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vqshrn, N = 2))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vqshrn_n_s32(a: int32x4_t) -> int16x4_t { +pub fn vqshrn_n_s32(a: int32x4_t) -> int16x4_t { static_assert!(N >= 1 && N <= 16); unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftns.v4i16")] fn _vqshrn_n_s32(a: int32x4_t, n: int32x4_t) -> int16x4_t; } - _vqshrn_n_s32( - a, - const { int32x4_t([-N as i32, -N as i32, -N as i32, -N as i32]) }, - ) + unsafe { + _vqshrn_n_s32( + a, + const { int32x4_t([-N as i32, -N as i32, -N as i32, -N as i32]) }, + ) + } } #[doc = "Signed saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vqshrn, N = 2))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vqshrn_n_s64(a: int64x2_t) -> int32x2_t { +pub fn vqshrn_n_s64(a: int64x2_t) -> int32x2_t { static_assert!(N >= 1 && N <= 32); unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftns.v2i32")] fn _vqshrn_n_s64(a: int64x2_t, n: int64x2_t) -> int32x2_t; } - _vqshrn_n_s64(a, const { int64x2_t([-N as i64, -N as i64]) }) + unsafe { _vqshrn_n_s64(a, const { int64x2_t([-N as i64, -N as i64]) }) } } #[doc = "Signed saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(sqshrn, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshrn_n_s16(a: int16x8_t) -> int8x8_t { +pub fn vqshrn_n_s16(a: int16x8_t) -> int8x8_t { static_assert!(N >= 1 && N <= 8); unsafe extern "unadjusted" { #[cfg_attr( @@ -36418,19 +34666,17 @@ pub unsafe fn vqshrn_n_s16(a: int16x8_t) -> int8x8_t { )] fn _vqshrn_n_s16(a: int16x8_t, n: i32) -> int8x8_t; } - _vqshrn_n_s16(a, N) + unsafe { _vqshrn_n_s16(a, N) } } #[doc = "Signed saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(sqshrn, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshrn_n_s32(a: int32x4_t) -> int16x4_t { +pub fn vqshrn_n_s32(a: int32x4_t) -> int16x4_t { static_assert!(N >= 1 && N <= 16); unsafe extern "unadjusted" { #[cfg_attr( @@ -36439,19 +34685,17 @@ pub unsafe fn vqshrn_n_s32(a: int32x4_t) -> int16x4_t { )] fn _vqshrn_n_s32(a: int32x4_t, n: i32) -> int16x4_t; } - _vqshrn_n_s32(a, N) + unsafe { _vqshrn_n_s32(a, N) } } #[doc = "Signed saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(sqshrn, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshrn_n_s64(a: int64x2_t) -> int32x2_t { +pub fn vqshrn_n_s64(a: int64x2_t) -> int32x2_t { static_assert!(N >= 1 && N <= 32); unsafe extern "unadjusted" { #[cfg_attr( @@ -36460,84 +34704,80 @@ pub unsafe fn vqshrn_n_s64(a: int64x2_t) -> int32x2_t { )] fn _vqshrn_n_s64(a: int64x2_t, n: i32) -> int32x2_t; } - _vqshrn_n_s64(a, N) + unsafe { _vqshrn_n_s64(a, N) } } #[doc = "Unsigned saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vqshrn, N = 2))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vqshrn_n_u16(a: uint16x8_t) -> uint8x8_t { +pub fn vqshrn_n_u16(a: uint16x8_t) -> uint8x8_t { static_assert!(N >= 1 && N <= 8); unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftnu.v8i8")] fn _vqshrn_n_u16(a: uint16x8_t, n: uint16x8_t) -> uint8x8_t; } - _vqshrn_n_u16( - a, - const { - uint16x8_t([ - -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, - -N as u16, - ]) - }, - ) + unsafe { + _vqshrn_n_u16( + a, + const { + uint16x8_t([ + -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, + -N as u16, + ]) + }, + ) + } } #[doc = "Unsigned saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vqshrn, N = 2))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vqshrn_n_u32(a: uint32x4_t) -> uint16x4_t { +pub fn vqshrn_n_u32(a: uint32x4_t) -> uint16x4_t { static_assert!(N >= 1 && N <= 16); unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftnu.v4i16")] fn _vqshrn_n_u32(a: uint32x4_t, n: uint32x4_t) -> uint16x4_t; } - _vqshrn_n_u32( - a, - const { uint32x4_t([-N as u32, -N as u32, -N as u32, -N as u32]) }, - ) + unsafe { + _vqshrn_n_u32( + a, + const { uint32x4_t([-N as u32, -N as u32, -N as u32, -N as u32]) }, + ) + } } #[doc = "Unsigned saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vqshrn, N = 2))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vqshrn_n_u64(a: uint64x2_t) -> uint32x2_t { +pub fn vqshrn_n_u64(a: uint64x2_t) -> uint32x2_t { static_assert!(N >= 1 && N <= 32); unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftnu.v2i32")] fn _vqshrn_n_u64(a: uint64x2_t, n: uint64x2_t) -> uint32x2_t; } - _vqshrn_n_u64(a, const { uint64x2_t([-N as u64, -N as u64]) }) + unsafe { _vqshrn_n_u64(a, const { uint64x2_t([-N as u64, -N as u64]) }) } } #[doc = "Unsigned saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(uqshrn, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshrn_n_u16(a: uint16x8_t) -> uint8x8_t { +pub fn vqshrn_n_u16(a: uint16x8_t) -> uint8x8_t { static_assert!(N >= 1 && N <= 8); unsafe extern "unadjusted" { #[cfg_attr( @@ -36546,19 +34786,17 @@ pub unsafe fn vqshrn_n_u16(a: uint16x8_t) -> uint8x8_t { )] fn _vqshrn_n_u16(a: uint16x8_t, n: i32) -> uint8x8_t; } - _vqshrn_n_u16(a, N) + unsafe { _vqshrn_n_u16(a, N) } } #[doc = "Unsigned saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(uqshrn, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshrn_n_u32(a: uint32x4_t) -> uint16x4_t { +pub fn vqshrn_n_u32(a: uint32x4_t) -> uint16x4_t { static_assert!(N >= 1 && N <= 16); unsafe extern "unadjusted" { #[cfg_attr( @@ -36567,19 +34805,17 @@ pub unsafe fn vqshrn_n_u32(a: uint32x4_t) -> uint16x4_t { )] fn _vqshrn_n_u32(a: uint32x4_t, n: i32) -> uint16x4_t; } - _vqshrn_n_u32(a, N) + unsafe { _vqshrn_n_u32(a, N) } } #[doc = "Unsigned saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(uqshrn, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshrn_n_u64(a: uint64x2_t) -> uint32x2_t { +pub fn vqshrn_n_u64(a: uint64x2_t) -> uint32x2_t { static_assert!(N >= 1 && N <= 32); unsafe extern "unadjusted" { #[cfg_attr( @@ -36588,84 +34824,80 @@ pub unsafe fn vqshrn_n_u64(a: uint64x2_t) -> uint32x2_t { )] fn _vqshrn_n_u64(a: uint64x2_t, n: i32) -> uint32x2_t; } - _vqshrn_n_u64(a, N) + unsafe { _vqshrn_n_u64(a, N) } } #[doc = "Signed saturating shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vqshrun, N = 2))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vqshrun_n_s16(a: int16x8_t) -> uint8x8_t { +pub fn vqshrun_n_s16(a: int16x8_t) -> uint8x8_t { static_assert!(N >= 1 && N <= 8); unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftnsu.v8i8")] fn _vqshrun_n_s16(a: int16x8_t, n: int16x8_t) -> uint8x8_t; } - _vqshrun_n_s16( - a, - const { - int16x8_t([ - -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, - -N as i16, - ]) - }, - ) + unsafe { + _vqshrun_n_s16( + a, + const { + int16x8_t([ + -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, + -N as i16, + ]) + }, + ) + } } #[doc = "Signed saturating shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vqshrun, N = 2))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vqshrun_n_s32(a: int32x4_t) -> uint16x4_t { +pub fn vqshrun_n_s32(a: int32x4_t) -> uint16x4_t { static_assert!(N >= 1 && N <= 16); unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftnsu.v4i16")] fn _vqshrun_n_s32(a: int32x4_t, n: int32x4_t) -> uint16x4_t; } - _vqshrun_n_s32( - a, - const { int32x4_t([-N as i32, -N as i32, -N as i32, -N as i32]) }, - ) + unsafe { + _vqshrun_n_s32( + a, + const { int32x4_t([-N as i32, -N as i32, -N as i32, -N as i32]) }, + ) + } } #[doc = "Signed saturating shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vqshrun, N = 2))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vqshrun_n_s64(a: int64x2_t) -> uint32x2_t { +pub fn vqshrun_n_s64(a: int64x2_t) -> uint32x2_t { static_assert!(N >= 1 && N <= 32); unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftnsu.v2i32")] fn _vqshrun_n_s64(a: int64x2_t, n: int64x2_t) -> uint32x2_t; } - _vqshrun_n_s64(a, const { int64x2_t([-N as i64, -N as i64]) }) + unsafe { _vqshrun_n_s64(a, const { int64x2_t([-N as i64, -N as i64]) }) } } #[doc = "Signed saturating shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(sqshrun, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshrun_n_s16(a: int16x8_t) -> uint8x8_t { +pub fn vqshrun_n_s16(a: int16x8_t) -> uint8x8_t { static_assert!(N >= 1 && N <= 8); unsafe extern "unadjusted" { #[cfg_attr( @@ -36674,19 +34906,17 @@ pub unsafe fn vqshrun_n_s16(a: int16x8_t) -> uint8x8_t { )] fn _vqshrun_n_s16(a: int16x8_t, n: i32) -> uint8x8_t; } - _vqshrun_n_s16(a, N) + unsafe { _vqshrun_n_s16(a, N) } } #[doc = "Signed saturating shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(sqshrun, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshrun_n_s32(a: int32x4_t) -> uint16x4_t { +pub fn vqshrun_n_s32(a: int32x4_t) -> uint16x4_t { static_assert!(N >= 1 && N <= 16); unsafe extern "unadjusted" { #[cfg_attr( @@ -36695,19 +34925,17 @@ pub unsafe fn vqshrun_n_s32(a: int32x4_t) -> uint16x4_t { )] fn _vqshrun_n_s32(a: int32x4_t, n: i32) -> uint16x4_t; } - _vqshrun_n_s32(a, N) + unsafe { _vqshrun_n_s32(a, N) } } #[doc = "Signed saturating shift right unsigned narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(sqshrun, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshrun_n_s64(a: int64x2_t) -> uint32x2_t { +pub fn vqshrun_n_s64(a: int64x2_t) -> uint32x2_t { static_assert!(N >= 1 && N <= 32); unsafe extern "unadjusted" { #[cfg_attr( @@ -36716,12 +34944,10 @@ pub unsafe fn vqshrun_n_s64(a: int64x2_t) -> uint32x2_t { )] fn _vqshrun_n_s64(a: int64x2_t, n: i32) -> uint32x2_t; } - _vqshrun_n_s64(a, N) + unsafe { _vqshrun_n_s64(a, N) } } #[doc = "Saturating subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -36738,7 +34964,7 @@ pub unsafe fn vqshrun_n_s64(a: int64x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqsub_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { +pub fn vqsub_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -36747,12 +34973,10 @@ pub unsafe fn vqsub_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.ssub.sat.v8i8")] fn _vqsub_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t; } - _vqsub_s8(a, b) + unsafe { _vqsub_s8(a, b) } } #[doc = "Saturating subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -36769,7 +34993,7 @@ pub unsafe fn vqsub_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqsubq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { +pub fn vqsubq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -36778,12 +35002,10 @@ pub unsafe fn vqsubq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.ssub.sat.v16i8")] fn _vqsubq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t; } - _vqsubq_s8(a, b) + unsafe { _vqsubq_s8(a, b) } } #[doc = "Saturating subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -36800,7 +35022,7 @@ pub unsafe fn vqsubq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqsub_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { +pub fn vqsub_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -36809,12 +35031,10 @@ pub unsafe fn vqsub_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.ssub.sat.v4i16")] fn _vqsub_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t; } - _vqsub_s16(a, b) + unsafe { _vqsub_s16(a, b) } } #[doc = "Saturating subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -36831,7 +35051,7 @@ pub unsafe fn vqsub_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqsubq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { +pub fn vqsubq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -36840,12 +35060,10 @@ pub unsafe fn vqsubq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.ssub.sat.v8i16")] fn _vqsubq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t; } - _vqsubq_s16(a, b) + unsafe { _vqsubq_s16(a, b) } } #[doc = "Saturating subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -36862,7 +35080,7 @@ pub unsafe fn vqsubq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqsub_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { +pub fn vqsub_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -36871,12 +35089,10 @@ pub unsafe fn vqsub_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.ssub.sat.v2i32")] fn _vqsub_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t; } - _vqsub_s32(a, b) + unsafe { _vqsub_s32(a, b) } } #[doc = "Saturating subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -36893,7 +35109,7 @@ pub unsafe fn vqsub_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqsubq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { +pub fn vqsubq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -36902,12 +35118,10 @@ pub unsafe fn vqsubq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.ssub.sat.v4i32")] fn _vqsubq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t; } - _vqsubq_s32(a, b) + unsafe { _vqsubq_s32(a, b) } } #[doc = "Saturating subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -36924,7 +35138,7 @@ pub unsafe fn vqsubq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqsub_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { +pub fn vqsub_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -36933,12 +35147,10 @@ pub unsafe fn vqsub_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.ssub.sat.v1i64")] fn _vqsub_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t; } - _vqsub_s64(a, b) + unsafe { _vqsub_s64(a, b) } } #[doc = "Saturating subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -36955,7 +35167,7 @@ pub unsafe fn vqsub_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqsubq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { +pub fn vqsubq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -36964,12 +35176,10 @@ pub unsafe fn vqsubq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.ssub.sat.v2i64")] fn _vqsubq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t; } - _vqsubq_s64(a, b) + unsafe { _vqsubq_s64(a, b) } } #[doc = "Saturating subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -36986,7 +35196,7 @@ pub unsafe fn vqsubq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqsub_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { +pub fn vqsub_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -36995,12 +35205,10 @@ pub unsafe fn vqsub_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.usub.sat.v8i8")] fn _vqsub_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t; } - _vqsub_u8(a, b) + unsafe { _vqsub_u8(a, b) } } #[doc = "Saturating subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -37017,7 +35225,7 @@ pub unsafe fn vqsub_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqsubq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { +pub fn vqsubq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -37026,12 +35234,10 @@ pub unsafe fn vqsubq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.usub.sat.v16i8")] fn _vqsubq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t; } - _vqsubq_u8(a, b) + unsafe { _vqsubq_u8(a, b) } } #[doc = "Saturating subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -37048,7 +35254,7 @@ pub unsafe fn vqsubq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqsub_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { +pub fn vqsub_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -37057,12 +35263,10 @@ pub unsafe fn vqsub_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.usub.sat.v4i16")] fn _vqsub_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t; } - _vqsub_u16(a, b) + unsafe { _vqsub_u16(a, b) } } #[doc = "Saturating subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -37079,7 +35283,7 @@ pub unsafe fn vqsub_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqsubq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { +pub fn vqsubq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -37088,12 +35292,10 @@ pub unsafe fn vqsubq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.usub.sat.v8i16")] fn _vqsubq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t; } - _vqsubq_u16(a, b) + unsafe { _vqsubq_u16(a, b) } } #[doc = "Saturating subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -37110,7 +35312,7 @@ pub unsafe fn vqsubq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqsub_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { +pub fn vqsub_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -37119,12 +35321,10 @@ pub unsafe fn vqsub_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.usub.sat.v2i32")] fn _vqsub_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t; } - _vqsub_u32(a, b) + unsafe { _vqsub_u32(a, b) } } #[doc = "Saturating subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -37141,7 +35341,7 @@ pub unsafe fn vqsub_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqsubq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { +pub fn vqsubq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -37150,12 +35350,10 @@ pub unsafe fn vqsubq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.usub.sat.v4i32")] fn _vqsubq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t; } - _vqsubq_u32(a, b) + unsafe { _vqsubq_u32(a, b) } } #[doc = "Saturating subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -37172,7 +35370,7 @@ pub unsafe fn vqsubq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqsub_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { +pub fn vqsub_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -37181,12 +35379,10 @@ pub unsafe fn vqsub_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.usub.sat.v1i64")] fn _vqsub_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t; } - _vqsub_u64(a, b) + unsafe { _vqsub_u64(a, b) } } #[doc = "Saturating subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -37203,7 +35399,7 @@ pub unsafe fn vqsub_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vqsubq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { +pub fn vqsubq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -37212,12 +35408,10 @@ pub unsafe fn vqsubq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.usub.sat.v2i64")] fn _vqsubq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t; } - _vqsubq_u64(a, b) + unsafe { _vqsubq_u64(a, b) } } #[doc = "Rounding Add returning High Narrow (high half)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_high_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -37234,14 +35428,12 @@ pub unsafe fn vqsubq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vraddhn_high_s16(a: int8x8_t, b: int16x8_t, c: int16x8_t) -> int8x16_t { +pub fn vraddhn_high_s16(a: int8x8_t, b: int16x8_t, c: int16x8_t) -> int8x16_t { let x = vraddhn_s16(b, c); - simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) + unsafe { simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) } } #[doc = "Rounding Add returning High Narrow (high half)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_high_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -37258,14 +35450,12 @@ pub unsafe fn vraddhn_high_s16(a: int8x8_t, b: int16x8_t, c: int16x8_t) -> int8x target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vraddhn_high_s32(a: int16x4_t, b: int32x4_t, c: int32x4_t) -> int16x8_t { +pub fn vraddhn_high_s32(a: int16x4_t, b: int32x4_t, c: int32x4_t) -> int16x8_t { let x = vraddhn_s32(b, c); - simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7]) + unsafe { simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7]) } } #[doc = "Rounding Add returning High Narrow (high half)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_high_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -37282,14 +35472,12 @@ pub unsafe fn vraddhn_high_s32(a: int16x4_t, b: int32x4_t, c: int32x4_t) -> int1 target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vraddhn_high_s64(a: int32x2_t, b: int64x2_t, c: int64x2_t) -> int32x4_t { +pub fn vraddhn_high_s64(a: int32x2_t, b: int64x2_t, c: int64x2_t) -> int32x4_t { let x = vraddhn_s64(b, c); - simd_shuffle!(a, x, [0, 1, 2, 3]) + unsafe { simd_shuffle!(a, x, [0, 1, 2, 3]) } } #[doc = "Rounding Add returning High Narrow (high half)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_high_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -37306,14 +35494,14 @@ pub unsafe fn vraddhn_high_s64(a: int32x2_t, b: int64x2_t, c: int64x2_t) -> int3 target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vraddhn_high_u16(a: uint8x8_t, b: uint16x8_t, c: uint16x8_t) -> uint8x16_t { - let x: uint8x8_t = transmute(vraddhn_s16(transmute(b), transmute(c))); - simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) +pub fn vraddhn_high_u16(a: uint8x8_t, b: uint16x8_t, c: uint16x8_t) -> uint8x16_t { + unsafe { + let x: uint8x8_t = transmute(vraddhn_s16(transmute(b), transmute(c))); + simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) + } } #[doc = "Rounding Add returning High Narrow (high half)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_high_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -37330,14 +35518,14 @@ pub unsafe fn vraddhn_high_u16(a: uint8x8_t, b: uint16x8_t, c: uint16x8_t) -> ui target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vraddhn_high_u32(a: uint16x4_t, b: uint32x4_t, c: uint32x4_t) -> uint16x8_t { - let x: uint16x4_t = transmute(vraddhn_s32(transmute(b), transmute(c))); - simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7]) +pub fn vraddhn_high_u32(a: uint16x4_t, b: uint32x4_t, c: uint32x4_t) -> uint16x8_t { + unsafe { + let x: uint16x4_t = transmute(vraddhn_s32(transmute(b), transmute(c))); + simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7]) + } } #[doc = "Rounding Add returning High Narrow (high half)."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_high_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -37354,14 +35542,14 @@ pub unsafe fn vraddhn_high_u32(a: uint16x4_t, b: uint32x4_t, c: uint32x4_t) -> u target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vraddhn_high_u64(a: uint32x2_t, b: uint64x2_t, c: uint64x2_t) -> uint32x4_t { - let x: uint32x2_t = transmute(vraddhn_s64(transmute(b), transmute(c))); - simd_shuffle!(a, x, [0, 1, 2, 3]) +pub fn vraddhn_high_u64(a: uint32x2_t, b: uint64x2_t, c: uint64x2_t) -> uint32x4_t { + unsafe { + let x: uint32x2_t = transmute(vraddhn_s64(transmute(b), transmute(c))); + simd_shuffle!(a, x, [0, 1, 2, 3]) + } } #[doc = "Rounding Add returning High Narrow."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -37378,7 +35566,7 @@ pub unsafe fn vraddhn_high_u64(a: uint32x2_t, b: uint64x2_t, c: uint64x2_t) -> u target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vraddhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t { +pub fn vraddhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -37387,12 +35575,10 @@ pub unsafe fn vraddhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vraddhn.v8i8")] fn _vraddhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t; } - _vraddhn_s16(a, b) + unsafe { _vraddhn_s16(a, b) } } #[doc = "Rounding Add returning High Narrow."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -37409,7 +35595,7 @@ pub unsafe fn vraddhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vraddhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t { +pub fn vraddhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -37418,12 +35604,10 @@ pub unsafe fn vraddhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vraddhn.v4i16")] fn _vraddhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t; } - _vraddhn_s32(a, b) + unsafe { _vraddhn_s32(a, b) } } #[doc = "Rounding Add returning High Narrow."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -37440,7 +35624,7 @@ pub unsafe fn vraddhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vraddhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t { +pub fn vraddhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -37449,12 +35633,10 @@ pub unsafe fn vraddhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vraddhn.v2i32")] fn _vraddhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t; } - _vraddhn_s64(a, b) + unsafe { _vraddhn_s64(a, b) } } #[doc = "Rounding Add returning High Narrow."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -37472,13 +35654,11 @@ pub unsafe fn vraddhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vraddhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t { - transmute(vraddhn_s16(transmute(a), transmute(b))) +pub fn vraddhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t { + unsafe { transmute(vraddhn_s16(transmute(a), transmute(b))) } } #[doc = "Rounding Add returning High Narrow."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -37496,16 +35676,16 @@ pub unsafe fn vraddhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vraddhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t { +pub fn vraddhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t { let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); let b: uint16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: uint8x8_t = transmute(vraddhn_s16(transmute(a), transmute(b))); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: uint8x8_t = transmute(vraddhn_s16(transmute(a), transmute(b))); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Rounding Add returning High Narrow."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -37523,13 +35703,11 @@ pub unsafe fn vraddhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vraddhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t { - transmute(vraddhn_s32(transmute(a), transmute(b))) +pub fn vraddhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t { + unsafe { transmute(vraddhn_s32(transmute(a), transmute(b))) } } #[doc = "Rounding Add returning High Narrow."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -37547,16 +35725,16 @@ pub unsafe fn vraddhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vraddhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t { +pub fn vraddhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t { let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); let b: uint32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); - let ret_val: uint16x4_t = transmute(vraddhn_s32(transmute(a), transmute(b))); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + unsafe { + let ret_val: uint16x4_t = transmute(vraddhn_s32(transmute(a), transmute(b))); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Rounding Add returning High Narrow."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -37574,13 +35752,11 @@ pub unsafe fn vraddhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vraddhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t { - transmute(vraddhn_s64(transmute(a), transmute(b))) +pub fn vraddhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t { + unsafe { transmute(vraddhn_s64(transmute(a), transmute(b))) } } #[doc = "Rounding Add returning High Narrow."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -37598,16 +35774,16 @@ pub unsafe fn vraddhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vraddhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t { +pub fn vraddhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t { let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]); let b: uint64x2_t = simd_shuffle!(b, b, [1, 0]); - let ret_val: uint32x2_t = transmute(vraddhn_s64(transmute(a), transmute(b))); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: uint32x2_t = transmute(vraddhn_s64(transmute(a), transmute(b))); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Reciprocal estimate."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpe_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecpe))] @@ -37617,7 +35793,7 @@ pub unsafe fn vraddhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vrecpe_f16(a: float16x4_t) -> float16x4_t { +pub fn vrecpe_f16(a: float16x4_t) -> float16x4_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecpe.v4f16")] #[cfg_attr( @@ -37626,12 +35802,10 @@ pub unsafe fn vrecpe_f16(a: float16x4_t) -> float16x4_t { )] fn _vrecpe_f16(a: float16x4_t) -> float16x4_t; } - _vrecpe_f16(a) + unsafe { _vrecpe_f16(a) } } #[doc = "Reciprocal estimate."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpeq_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecpe))] @@ -37641,7 +35815,7 @@ pub unsafe fn vrecpe_f16(a: float16x4_t) -> float16x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vrecpeq_f16(a: float16x8_t) -> float16x8_t { +pub fn vrecpeq_f16(a: float16x8_t) -> float16x8_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecpe.v8f16")] #[cfg_attr( @@ -37650,12 +35824,10 @@ pub unsafe fn vrecpeq_f16(a: float16x8_t) -> float16x8_t { )] fn _vrecpeq_f16(a: float16x8_t) -> float16x8_t; } - _vrecpeq_f16(a) + unsafe { _vrecpeq_f16(a) } } #[doc = "Reciprocal estimate."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpe_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -37672,7 +35844,7 @@ pub unsafe fn vrecpeq_f16(a: float16x8_t) -> float16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrecpe_f32(a: float32x2_t) -> float32x2_t { +pub fn vrecpe_f32(a: float32x2_t) -> float32x2_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecpe.v2f32")] #[cfg_attr( @@ -37681,12 +35853,10 @@ pub unsafe fn vrecpe_f32(a: float32x2_t) -> float32x2_t { )] fn _vrecpe_f32(a: float32x2_t) -> float32x2_t; } - _vrecpe_f32(a) + unsafe { _vrecpe_f32(a) } } #[doc = "Reciprocal estimate."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpeq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -37703,7 +35873,7 @@ pub unsafe fn vrecpe_f32(a: float32x2_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrecpeq_f32(a: float32x4_t) -> float32x4_t { +pub fn vrecpeq_f32(a: float32x4_t) -> float32x4_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecpe.v4f32")] #[cfg_attr( @@ -37712,12 +35882,10 @@ pub unsafe fn vrecpeq_f32(a: float32x4_t) -> float32x4_t { )] fn _vrecpeq_f32(a: float32x4_t) -> float32x4_t; } - _vrecpeq_f32(a) + unsafe { _vrecpeq_f32(a) } } #[doc = "Unsigned reciprocal estimate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpe_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -37734,7 +35902,7 @@ pub unsafe fn vrecpeq_f32(a: float32x4_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrecpe_u32(a: uint32x2_t) -> uint32x2_t { +pub fn vrecpe_u32(a: uint32x2_t) -> uint32x2_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecpe.v2i32")] #[cfg_attr( @@ -37743,12 +35911,10 @@ pub unsafe fn vrecpe_u32(a: uint32x2_t) -> uint32x2_t { )] fn _vrecpe_u32(a: uint32x2_t) -> uint32x2_t; } - _vrecpe_u32(a) + unsafe { _vrecpe_u32(a) } } #[doc = "Unsigned reciprocal estimate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpeq_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -37765,7 +35931,7 @@ pub unsafe fn vrecpe_u32(a: uint32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrecpeq_u32(a: uint32x4_t) -> uint32x4_t { +pub fn vrecpeq_u32(a: uint32x4_t) -> uint32x4_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecpe.v4i32")] #[cfg_attr( @@ -37774,12 +35940,10 @@ pub unsafe fn vrecpeq_u32(a: uint32x4_t) -> uint32x4_t { )] fn _vrecpeq_u32(a: uint32x4_t) -> uint32x4_t; } - _vrecpeq_u32(a) + unsafe { _vrecpeq_u32(a) } } #[doc = "Floating-point reciprocal step"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecps_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecps))] @@ -37789,7 +35953,7 @@ pub unsafe fn vrecpeq_u32(a: uint32x4_t) -> uint32x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vrecps_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { +pub fn vrecps_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecps.v4f16")] #[cfg_attr( @@ -37798,12 +35962,10 @@ pub unsafe fn vrecps_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { )] fn _vrecps_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t; } - _vrecps_f16(a, b) + unsafe { _vrecps_f16(a, b) } } #[doc = "Floating-point reciprocal step"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpsq_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecps))] @@ -37813,7 +35975,7 @@ pub unsafe fn vrecps_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vrecpsq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { +pub fn vrecpsq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecps.v8f16")] #[cfg_attr( @@ -37822,12 +35984,10 @@ pub unsafe fn vrecpsq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { )] fn _vrecpsq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t; } - _vrecpsq_f16(a, b) + unsafe { _vrecpsq_f16(a, b) } } #[doc = "Floating-point reciprocal step"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecps_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -37844,7 +36004,7 @@ pub unsafe fn vrecpsq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrecps_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { +pub fn vrecps_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecps.v2f32")] #[cfg_attr( @@ -37853,12 +36013,10 @@ pub unsafe fn vrecps_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { )] fn _vrecps_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t; } - _vrecps_f32(a, b) + unsafe { _vrecps_f32(a, b) } } #[doc = "Floating-point reciprocal step"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpsq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -37875,7 +36033,7 @@ pub unsafe fn vrecps_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrecpsq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { +pub fn vrecpsq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecps.v4f32")] #[cfg_attr( @@ -37884,12 +36042,10 @@ pub unsafe fn vrecpsq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { )] fn _vrecpsq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t; } - _vrecpsq_f32(a, b) + unsafe { _vrecpsq_f32(a, b) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -37900,13 +36056,11 @@ pub unsafe fn vrecpsq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpret_f32_f16(a: float16x4_t) -> float32x2_t { - transmute(a) +pub fn vreinterpret_f32_f16(a: float16x4_t) -> float32x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -37917,15 +36071,15 @@ pub unsafe fn vreinterpret_f32_f16(a: float16x4_t) -> float32x2_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpret_f32_f16(a: float16x4_t) -> float32x2_t { +pub fn vreinterpret_f32_f16(a: float16x4_t) -> float32x2_t { let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - let ret_val: float32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: float32x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -37936,13 +36090,11 @@ pub unsafe fn vreinterpret_f32_f16(a: float16x4_t) -> float32x2_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpret_s8_f16(a: float16x4_t) -> int8x8_t { - transmute(a) +pub fn vreinterpret_s8_f16(a: float16x4_t) -> int8x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -37953,15 +36105,15 @@ pub unsafe fn vreinterpret_s8_f16(a: float16x4_t) -> int8x8_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpret_s8_f16(a: float16x4_t) -> int8x8_t { +pub fn vreinterpret_s8_f16(a: float16x4_t) -> int8x8_t { let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - let ret_val: int8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: int8x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -37972,13 +36124,11 @@ pub unsafe fn vreinterpret_s8_f16(a: float16x4_t) -> int8x8_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpret_s16_f16(a: float16x4_t) -> int16x4_t { - transmute(a) +pub fn vreinterpret_s16_f16(a: float16x4_t) -> int16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -37989,15 +36139,15 @@ pub unsafe fn vreinterpret_s16_f16(a: float16x4_t) -> int16x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpret_s16_f16(a: float16x4_t) -> int16x4_t { +pub fn vreinterpret_s16_f16(a: float16x4_t) -> int16x4_t { let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - let ret_val: int16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + unsafe { + let ret_val: int16x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -38008,13 +36158,11 @@ pub unsafe fn vreinterpret_s16_f16(a: float16x4_t) -> int16x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpret_s32_f16(a: float16x4_t) -> int32x2_t { - transmute(a) +pub fn vreinterpret_s32_f16(a: float16x4_t) -> int32x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -38025,15 +36173,15 @@ pub unsafe fn vreinterpret_s32_f16(a: float16x4_t) -> int32x2_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpret_s32_f16(a: float16x4_t) -> int32x2_t { +pub fn vreinterpret_s32_f16(a: float16x4_t) -> int32x2_t { let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - let ret_val: int32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: int32x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -38044,13 +36192,11 @@ pub unsafe fn vreinterpret_s32_f16(a: float16x4_t) -> int32x2_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpret_s64_f16(a: float16x4_t) -> int64x1_t { - transmute(a) +pub fn vreinterpret_s64_f16(a: float16x4_t) -> int64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -38061,14 +36207,12 @@ pub unsafe fn vreinterpret_s64_f16(a: float16x4_t) -> int64x1_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpret_s64_f16(a: float16x4_t) -> int64x1_t { +pub fn vreinterpret_s64_f16(a: float16x4_t) -> int64x1_t { let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - transmute(a) + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -38079,13 +36223,11 @@ pub unsafe fn vreinterpret_s64_f16(a: float16x4_t) -> int64x1_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpret_u8_f16(a: float16x4_t) -> uint8x8_t { - transmute(a) +pub fn vreinterpret_u8_f16(a: float16x4_t) -> uint8x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -38096,15 +36238,15 @@ pub unsafe fn vreinterpret_u8_f16(a: float16x4_t) -> uint8x8_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpret_u8_f16(a: float16x4_t) -> uint8x8_t { +pub fn vreinterpret_u8_f16(a: float16x4_t) -> uint8x8_t { let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - let ret_val: uint8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: uint8x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -38115,13 +36257,11 @@ pub unsafe fn vreinterpret_u8_f16(a: float16x4_t) -> uint8x8_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpret_u16_f16(a: float16x4_t) -> uint16x4_t { - transmute(a) +pub fn vreinterpret_u16_f16(a: float16x4_t) -> uint16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -38132,15 +36272,15 @@ pub unsafe fn vreinterpret_u16_f16(a: float16x4_t) -> uint16x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpret_u16_f16(a: float16x4_t) -> uint16x4_t { +pub fn vreinterpret_u16_f16(a: float16x4_t) -> uint16x4_t { let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - let ret_val: uint16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + unsafe { + let ret_val: uint16x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -38151,13 +36291,11 @@ pub unsafe fn vreinterpret_u16_f16(a: float16x4_t) -> uint16x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpret_u32_f16(a: float16x4_t) -> uint32x2_t { - transmute(a) +pub fn vreinterpret_u32_f16(a: float16x4_t) -> uint32x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -38168,15 +36306,15 @@ pub unsafe fn vreinterpret_u32_f16(a: float16x4_t) -> uint32x2_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpret_u32_f16(a: float16x4_t) -> uint32x2_t { +pub fn vreinterpret_u32_f16(a: float16x4_t) -> uint32x2_t { let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - let ret_val: uint32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: uint32x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -38187,13 +36325,11 @@ pub unsafe fn vreinterpret_u32_f16(a: float16x4_t) -> uint32x2_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpret_u64_f16(a: float16x4_t) -> uint64x1_t { - transmute(a) +pub fn vreinterpret_u64_f16(a: float16x4_t) -> uint64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -38204,14 +36340,12 @@ pub unsafe fn vreinterpret_u64_f16(a: float16x4_t) -> uint64x1_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpret_u64_f16(a: float16x4_t) -> uint64x1_t { +pub fn vreinterpret_u64_f16(a: float16x4_t) -> uint64x1_t { let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - transmute(a) + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -38222,13 +36356,11 @@ pub unsafe fn vreinterpret_u64_f16(a: float16x4_t) -> uint64x1_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpret_p8_f16(a: float16x4_t) -> poly8x8_t { - transmute(a) +pub fn vreinterpret_p8_f16(a: float16x4_t) -> poly8x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -38239,15 +36371,15 @@ pub unsafe fn vreinterpret_p8_f16(a: float16x4_t) -> poly8x8_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpret_p8_f16(a: float16x4_t) -> poly8x8_t { +pub fn vreinterpret_p8_f16(a: float16x4_t) -> poly8x8_t { let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - let ret_val: poly8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: poly8x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -38258,13 +36390,11 @@ pub unsafe fn vreinterpret_p8_f16(a: float16x4_t) -> poly8x8_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpret_p16_f16(a: float16x4_t) -> poly16x4_t { - transmute(a) +pub fn vreinterpret_p16_f16(a: float16x4_t) -> poly16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -38275,15 +36405,15 @@ pub unsafe fn vreinterpret_p16_f16(a: float16x4_t) -> poly16x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpret_p16_f16(a: float16x4_t) -> poly16x4_t { +pub fn vreinterpret_p16_f16(a: float16x4_t) -> poly16x4_t { let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - let ret_val: poly16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + unsafe { + let ret_val: poly16x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -38294,13 +36424,11 @@ pub unsafe fn vreinterpret_p16_f16(a: float16x4_t) -> poly16x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpretq_f32_f16(a: float16x8_t) -> float32x4_t { - transmute(a) +pub fn vreinterpretq_f32_f16(a: float16x8_t) -> float32x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -38311,15 +36439,15 @@ pub unsafe fn vreinterpretq_f32_f16(a: float16x8_t) -> float32x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpretq_f32_f16(a: float16x8_t) -> float32x4_t { +pub fn vreinterpretq_f32_f16(a: float16x8_t) -> float32x4_t { let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: float32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + unsafe { + let ret_val: float32x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -38330,13 +36458,11 @@ pub unsafe fn vreinterpretq_f32_f16(a: float16x8_t) -> float32x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpretq_s8_f16(a: float16x8_t) -> int8x16_t { - transmute(a) +pub fn vreinterpretq_s8_f16(a: float16x8_t) -> int8x16_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -38347,19 +36473,19 @@ pub unsafe fn vreinterpretq_s8_f16(a: float16x8_t) -> int8x16_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpretq_s8_f16(a: float16x8_t) -> int8x16_t { +pub fn vreinterpretq_s8_f16(a: float16x8_t) -> int8x16_t { let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: int8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) + unsafe { + let ret_val: int8x16_t = transmute(a); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -38370,13 +36496,11 @@ pub unsafe fn vreinterpretq_s8_f16(a: float16x8_t) -> int8x16_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpretq_s16_f16(a: float16x8_t) -> int16x8_t { - transmute(a) +pub fn vreinterpretq_s16_f16(a: float16x8_t) -> int16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -38387,15 +36511,15 @@ pub unsafe fn vreinterpretq_s16_f16(a: float16x8_t) -> int16x8_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpretq_s16_f16(a: float16x8_t) -> int16x8_t { +pub fn vreinterpretq_s16_f16(a: float16x8_t) -> int16x8_t { let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: int16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: int16x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -38406,13 +36530,11 @@ pub unsafe fn vreinterpretq_s16_f16(a: float16x8_t) -> int16x8_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpretq_s32_f16(a: float16x8_t) -> int32x4_t { - transmute(a) +pub fn vreinterpretq_s32_f16(a: float16x8_t) -> int32x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -38423,15 +36545,15 @@ pub unsafe fn vreinterpretq_s32_f16(a: float16x8_t) -> int32x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpretq_s32_f16(a: float16x8_t) -> int32x4_t { +pub fn vreinterpretq_s32_f16(a: float16x8_t) -> int32x4_t { let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: int32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + unsafe { + let ret_val: int32x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -38442,13 +36564,11 @@ pub unsafe fn vreinterpretq_s32_f16(a: float16x8_t) -> int32x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpretq_s64_f16(a: float16x8_t) -> int64x2_t { - transmute(a) +pub fn vreinterpretq_s64_f16(a: float16x8_t) -> int64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -38459,15 +36579,15 @@ pub unsafe fn vreinterpretq_s64_f16(a: float16x8_t) -> int64x2_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpretq_s64_f16(a: float16x8_t) -> int64x2_t { +pub fn vreinterpretq_s64_f16(a: float16x8_t) -> int64x2_t { let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: int64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: int64x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -38478,13 +36598,11 @@ pub unsafe fn vreinterpretq_s64_f16(a: float16x8_t) -> int64x2_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpretq_u8_f16(a: float16x8_t) -> uint8x16_t { - transmute(a) +pub fn vreinterpretq_u8_f16(a: float16x8_t) -> uint8x16_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -38495,19 +36613,19 @@ pub unsafe fn vreinterpretq_u8_f16(a: float16x8_t) -> uint8x16_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpretq_u8_f16(a: float16x8_t) -> uint8x16_t { +pub fn vreinterpretq_u8_f16(a: float16x8_t) -> uint8x16_t { let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: uint8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) + unsafe { + let ret_val: uint8x16_t = transmute(a); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -38518,13 +36636,11 @@ pub unsafe fn vreinterpretq_u8_f16(a: float16x8_t) -> uint8x16_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpretq_u16_f16(a: float16x8_t) -> uint16x8_t { - transmute(a) +pub fn vreinterpretq_u16_f16(a: float16x8_t) -> uint16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -38535,15 +36651,15 @@ pub unsafe fn vreinterpretq_u16_f16(a: float16x8_t) -> uint16x8_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpretq_u16_f16(a: float16x8_t) -> uint16x8_t { +pub fn vreinterpretq_u16_f16(a: float16x8_t) -> uint16x8_t { let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: uint16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: uint16x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -38554,13 +36670,11 @@ pub unsafe fn vreinterpretq_u16_f16(a: float16x8_t) -> uint16x8_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpretq_u32_f16(a: float16x8_t) -> uint32x4_t { - transmute(a) +pub fn vreinterpretq_u32_f16(a: float16x8_t) -> uint32x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -38571,15 +36685,15 @@ pub unsafe fn vreinterpretq_u32_f16(a: float16x8_t) -> uint32x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpretq_u32_f16(a: float16x8_t) -> uint32x4_t { +pub fn vreinterpretq_u32_f16(a: float16x8_t) -> uint32x4_t { let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: uint32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + unsafe { + let ret_val: uint32x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -38590,13 +36704,11 @@ pub unsafe fn vreinterpretq_u32_f16(a: float16x8_t) -> uint32x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpretq_u64_f16(a: float16x8_t) -> uint64x2_t { - transmute(a) +pub fn vreinterpretq_u64_f16(a: float16x8_t) -> uint64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -38607,15 +36719,15 @@ pub unsafe fn vreinterpretq_u64_f16(a: float16x8_t) -> uint64x2_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpretq_u64_f16(a: float16x8_t) -> uint64x2_t { +pub fn vreinterpretq_u64_f16(a: float16x8_t) -> uint64x2_t { let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: uint64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: uint64x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -38626,13 +36738,11 @@ pub unsafe fn vreinterpretq_u64_f16(a: float16x8_t) -> uint64x2_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpretq_p8_f16(a: float16x8_t) -> poly8x16_t { - transmute(a) +pub fn vreinterpretq_p8_f16(a: float16x8_t) -> poly8x16_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -38643,19 +36753,19 @@ pub unsafe fn vreinterpretq_p8_f16(a: float16x8_t) -> poly8x16_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpretq_p8_f16(a: float16x8_t) -> poly8x16_t { +pub fn vreinterpretq_p8_f16(a: float16x8_t) -> poly8x16_t { let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: poly8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) + unsafe { + let ret_val: poly8x16_t = transmute(a); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -38666,13 +36776,11 @@ pub unsafe fn vreinterpretq_p8_f16(a: float16x8_t) -> poly8x16_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpretq_p16_f16(a: float16x8_t) -> poly16x8_t { - transmute(a) +pub fn vreinterpretq_p16_f16(a: float16x8_t) -> poly16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -38683,15 +36791,15 @@ pub unsafe fn vreinterpretq_p16_f16(a: float16x8_t) -> poly16x8_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpretq_p16_f16(a: float16x8_t) -> poly16x8_t { +pub fn vreinterpretq_p16_f16(a: float16x8_t) -> poly16x8_t { let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: poly16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: poly16x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -38702,13 +36810,11 @@ pub unsafe fn vreinterpretq_p16_f16(a: float16x8_t) -> poly16x8_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpret_f16_f32(a: float32x2_t) -> float16x4_t { - transmute(a) +pub fn vreinterpret_f16_f32(a: float32x2_t) -> float16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -38719,15 +36825,15 @@ pub unsafe fn vreinterpret_f16_f32(a: float32x2_t) -> float16x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpret_f16_f32(a: float32x2_t) -> float16x4_t { +pub fn vreinterpret_f16_f32(a: float32x2_t) -> float16x4_t { let a: float32x2_t = simd_shuffle!(a, a, [1, 0]); - let ret_val: float16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + unsafe { + let ret_val: float16x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -38738,13 +36844,11 @@ pub unsafe fn vreinterpret_f16_f32(a: float32x2_t) -> float16x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpretq_f16_f32(a: float32x4_t) -> float16x8_t { - transmute(a) +pub fn vreinterpretq_f16_f32(a: float32x4_t) -> float16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -38755,15 +36859,15 @@ pub unsafe fn vreinterpretq_f16_f32(a: float32x4_t) -> float16x8_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpretq_f16_f32(a: float32x4_t) -> float16x8_t { +pub fn vreinterpretq_f16_f32(a: float32x4_t) -> float16x8_t { let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - let ret_val: float16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: float16x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -38774,13 +36878,11 @@ pub unsafe fn vreinterpretq_f16_f32(a: float32x4_t) -> float16x8_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpret_f16_s8(a: int8x8_t) -> float16x4_t { - transmute(a) +pub fn vreinterpret_f16_s8(a: int8x8_t) -> float16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -38791,15 +36893,15 @@ pub unsafe fn vreinterpret_f16_s8(a: int8x8_t) -> float16x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpret_f16_s8(a: int8x8_t) -> float16x4_t { +pub fn vreinterpret_f16_s8(a: int8x8_t) -> float16x4_t { let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: float16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + unsafe { + let ret_val: float16x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -38810,13 +36912,11 @@ pub unsafe fn vreinterpret_f16_s8(a: int8x8_t) -> float16x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpretq_f16_s8(a: int8x16_t) -> float16x8_t { - transmute(a) +pub fn vreinterpretq_f16_s8(a: int8x16_t) -> float16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -38827,15 +36927,15 @@ pub unsafe fn vreinterpretq_f16_s8(a: int8x16_t) -> float16x8_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpretq_f16_s8(a: int8x16_t) -> float16x8_t { +pub fn vreinterpretq_f16_s8(a: int8x16_t) -> float16x8_t { let a: int8x16_t = simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: float16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: float16x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -38846,13 +36946,11 @@ pub unsafe fn vreinterpretq_f16_s8(a: int8x16_t) -> float16x8_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpret_f16_s16(a: int16x4_t) -> float16x4_t { - transmute(a) +pub fn vreinterpret_f16_s16(a: int16x4_t) -> float16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -38863,15 +36961,15 @@ pub unsafe fn vreinterpret_f16_s16(a: int16x4_t) -> float16x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpret_f16_s16(a: int16x4_t) -> float16x4_t { +pub fn vreinterpret_f16_s16(a: int16x4_t) -> float16x4_t { let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - let ret_val: float16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + unsafe { + let ret_val: float16x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -38882,13 +36980,11 @@ pub unsafe fn vreinterpret_f16_s16(a: int16x4_t) -> float16x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpretq_f16_s16(a: int16x8_t) -> float16x8_t { - transmute(a) +pub fn vreinterpretq_f16_s16(a: int16x8_t) -> float16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -38899,15 +36995,15 @@ pub unsafe fn vreinterpretq_f16_s16(a: int16x8_t) -> float16x8_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpretq_f16_s16(a: int16x8_t) -> float16x8_t { +pub fn vreinterpretq_f16_s16(a: int16x8_t) -> float16x8_t { let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: float16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: float16x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -38918,13 +37014,11 @@ pub unsafe fn vreinterpretq_f16_s16(a: int16x8_t) -> float16x8_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpret_f16_s32(a: int32x2_t) -> float16x4_t { - transmute(a) +pub fn vreinterpret_f16_s32(a: int32x2_t) -> float16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -38935,15 +37029,15 @@ pub unsafe fn vreinterpret_f16_s32(a: int32x2_t) -> float16x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpret_f16_s32(a: int32x2_t) -> float16x4_t { +pub fn vreinterpret_f16_s32(a: int32x2_t) -> float16x4_t { let a: int32x2_t = simd_shuffle!(a, a, [1, 0]); - let ret_val: float16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + unsafe { + let ret_val: float16x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -38954,13 +37048,11 @@ pub unsafe fn vreinterpret_f16_s32(a: int32x2_t) -> float16x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpretq_f16_s32(a: int32x4_t) -> float16x8_t { - transmute(a) +pub fn vreinterpretq_f16_s32(a: int32x4_t) -> float16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -38971,15 +37063,15 @@ pub unsafe fn vreinterpretq_f16_s32(a: int32x4_t) -> float16x8_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpretq_f16_s32(a: int32x4_t) -> float16x8_t { +pub fn vreinterpretq_f16_s32(a: int32x4_t) -> float16x8_t { let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - let ret_val: float16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: float16x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -38990,13 +37082,11 @@ pub unsafe fn vreinterpretq_f16_s32(a: int32x4_t) -> float16x8_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpret_f16_s64(a: int64x1_t) -> float16x4_t { - transmute(a) +pub fn vreinterpret_f16_s64(a: int64x1_t) -> float16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -39007,14 +37097,14 @@ pub unsafe fn vreinterpret_f16_s64(a: int64x1_t) -> float16x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpret_f16_s64(a: int64x1_t) -> float16x4_t { - let ret_val: float16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) +pub fn vreinterpret_f16_s64(a: int64x1_t) -> float16x4_t { + unsafe { + let ret_val: float16x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -39025,13 +37115,11 @@ pub unsafe fn vreinterpret_f16_s64(a: int64x1_t) -> float16x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpretq_f16_s64(a: int64x2_t) -> float16x8_t { - transmute(a) +pub fn vreinterpretq_f16_s64(a: int64x2_t) -> float16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -39042,15 +37130,15 @@ pub unsafe fn vreinterpretq_f16_s64(a: int64x2_t) -> float16x8_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpretq_f16_s64(a: int64x2_t) -> float16x8_t { +pub fn vreinterpretq_f16_s64(a: int64x2_t) -> float16x8_t { let a: int64x2_t = simd_shuffle!(a, a, [1, 0]); - let ret_val: float16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: float16x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -39061,13 +37149,11 @@ pub unsafe fn vreinterpretq_f16_s64(a: int64x2_t) -> float16x8_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpret_f16_u8(a: uint8x8_t) -> float16x4_t { - transmute(a) +pub fn vreinterpret_f16_u8(a: uint8x8_t) -> float16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -39078,15 +37164,15 @@ pub unsafe fn vreinterpret_f16_u8(a: uint8x8_t) -> float16x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpret_f16_u8(a: uint8x8_t) -> float16x4_t { +pub fn vreinterpret_f16_u8(a: uint8x8_t) -> float16x4_t { let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: float16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + unsafe { + let ret_val: float16x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -39097,13 +37183,11 @@ pub unsafe fn vreinterpret_f16_u8(a: uint8x8_t) -> float16x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpretq_f16_u8(a: uint8x16_t) -> float16x8_t { - transmute(a) +pub fn vreinterpretq_f16_u8(a: uint8x16_t) -> float16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -39114,15 +37198,15 @@ pub unsafe fn vreinterpretq_f16_u8(a: uint8x16_t) -> float16x8_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpretq_f16_u8(a: uint8x16_t) -> float16x8_t { +pub fn vreinterpretq_f16_u8(a: uint8x16_t) -> float16x8_t { let a: uint8x16_t = simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: float16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: float16x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -39133,13 +37217,11 @@ pub unsafe fn vreinterpretq_f16_u8(a: uint8x16_t) -> float16x8_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpret_f16_u16(a: uint16x4_t) -> float16x4_t { - transmute(a) +pub fn vreinterpret_f16_u16(a: uint16x4_t) -> float16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -39150,15 +37232,15 @@ pub unsafe fn vreinterpret_f16_u16(a: uint16x4_t) -> float16x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpret_f16_u16(a: uint16x4_t) -> float16x4_t { +pub fn vreinterpret_f16_u16(a: uint16x4_t) -> float16x4_t { let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - let ret_val: float16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + unsafe { + let ret_val: float16x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -39169,13 +37251,11 @@ pub unsafe fn vreinterpret_f16_u16(a: uint16x4_t) -> float16x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpretq_f16_u16(a: uint16x8_t) -> float16x8_t { - transmute(a) +pub fn vreinterpretq_f16_u16(a: uint16x8_t) -> float16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -39186,15 +37266,15 @@ pub unsafe fn vreinterpretq_f16_u16(a: uint16x8_t) -> float16x8_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpretq_f16_u16(a: uint16x8_t) -> float16x8_t { +pub fn vreinterpretq_f16_u16(a: uint16x8_t) -> float16x8_t { let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: float16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: float16x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -39205,13 +37285,11 @@ pub unsafe fn vreinterpretq_f16_u16(a: uint16x8_t) -> float16x8_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpret_f16_u32(a: uint32x2_t) -> float16x4_t { - transmute(a) +pub fn vreinterpret_f16_u32(a: uint32x2_t) -> float16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -39222,15 +37300,15 @@ pub unsafe fn vreinterpret_f16_u32(a: uint32x2_t) -> float16x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpret_f16_u32(a: uint32x2_t) -> float16x4_t { +pub fn vreinterpret_f16_u32(a: uint32x2_t) -> float16x4_t { let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]); - let ret_val: float16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + unsafe { + let ret_val: float16x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -39241,13 +37319,11 @@ pub unsafe fn vreinterpret_f16_u32(a: uint32x2_t) -> float16x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpretq_f16_u32(a: uint32x4_t) -> float16x8_t { - transmute(a) +pub fn vreinterpretq_f16_u32(a: uint32x4_t) -> float16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -39258,15 +37334,15 @@ pub unsafe fn vreinterpretq_f16_u32(a: uint32x4_t) -> float16x8_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpretq_f16_u32(a: uint32x4_t) -> float16x8_t { +pub fn vreinterpretq_f16_u32(a: uint32x4_t) -> float16x8_t { let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - let ret_val: float16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: float16x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -39277,13 +37353,11 @@ pub unsafe fn vreinterpretq_f16_u32(a: uint32x4_t) -> float16x8_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpret_f16_u64(a: uint64x1_t) -> float16x4_t { - transmute(a) +pub fn vreinterpret_f16_u64(a: uint64x1_t) -> float16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -39294,14 +37368,14 @@ pub unsafe fn vreinterpret_f16_u64(a: uint64x1_t) -> float16x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpret_f16_u64(a: uint64x1_t) -> float16x4_t { - let ret_val: float16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) +pub fn vreinterpret_f16_u64(a: uint64x1_t) -> float16x4_t { + unsafe { + let ret_val: float16x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -39312,13 +37386,11 @@ pub unsafe fn vreinterpret_f16_u64(a: uint64x1_t) -> float16x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpretq_f16_u64(a: uint64x2_t) -> float16x8_t { - transmute(a) +pub fn vreinterpretq_f16_u64(a: uint64x2_t) -> float16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -39329,15 +37401,15 @@ pub unsafe fn vreinterpretq_f16_u64(a: uint64x2_t) -> float16x8_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpretq_f16_u64(a: uint64x2_t) -> float16x8_t { +pub fn vreinterpretq_f16_u64(a: uint64x2_t) -> float16x8_t { let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]); - let ret_val: float16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: float16x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -39348,13 +37420,11 @@ pub unsafe fn vreinterpretq_f16_u64(a: uint64x2_t) -> float16x8_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpret_f16_p8(a: poly8x8_t) -> float16x4_t { - transmute(a) +pub fn vreinterpret_f16_p8(a: poly8x8_t) -> float16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -39365,15 +37435,15 @@ pub unsafe fn vreinterpret_f16_p8(a: poly8x8_t) -> float16x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpret_f16_p8(a: poly8x8_t) -> float16x4_t { +pub fn vreinterpret_f16_p8(a: poly8x8_t) -> float16x4_t { let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: float16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + unsafe { + let ret_val: float16x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -39384,13 +37454,11 @@ pub unsafe fn vreinterpret_f16_p8(a: poly8x8_t) -> float16x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpretq_f16_p8(a: poly8x16_t) -> float16x8_t { - transmute(a) +pub fn vreinterpretq_f16_p8(a: poly8x16_t) -> float16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -39401,15 +37469,15 @@ pub unsafe fn vreinterpretq_f16_p8(a: poly8x16_t) -> float16x8_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpretq_f16_p8(a: poly8x16_t) -> float16x8_t { +pub fn vreinterpretq_f16_p8(a: poly8x16_t) -> float16x8_t { let a: poly8x16_t = simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: float16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: float16x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -39420,13 +37488,11 @@ pub unsafe fn vreinterpretq_f16_p8(a: poly8x16_t) -> float16x8_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpret_f16_p16(a: poly16x4_t) -> float16x4_t { - transmute(a) +pub fn vreinterpret_f16_p16(a: poly16x4_t) -> float16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -39437,15 +37503,15 @@ pub unsafe fn vreinterpret_f16_p16(a: poly16x4_t) -> float16x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpret_f16_p16(a: poly16x4_t) -> float16x4_t { +pub fn vreinterpret_f16_p16(a: poly16x4_t) -> float16x4_t { let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - let ret_val: float16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + unsafe { + let ret_val: float16x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -39456,13 +37522,11 @@ pub unsafe fn vreinterpret_f16_p16(a: poly16x4_t) -> float16x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpretq_f16_p16(a: poly16x8_t) -> float16x8_t { - transmute(a) +pub fn vreinterpretq_f16_p16(a: poly16x8_t) -> float16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -39473,15 +37537,15 @@ pub unsafe fn vreinterpretq_f16_p16(a: poly16x8_t) -> float16x8_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpretq_f16_p16(a: poly16x8_t) -> float16x8_t { +pub fn vreinterpretq_f16_p16(a: poly16x8_t) -> float16x8_t { let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: float16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: float16x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p128)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] @@ -39492,13 +37556,11 @@ pub unsafe fn vreinterpretq_f16_p16(a: poly16x8_t) -> float16x8_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpretq_f16_p128(a: p128) -> float16x8_t { - transmute(a) +pub fn vreinterpretq_f16_p128(a: p128) -> float16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p128)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] @@ -39509,14 +37571,14 @@ pub unsafe fn vreinterpretq_f16_p128(a: p128) -> float16x8_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpretq_f16_p128(a: p128) -> float16x8_t { - let ret_val: float16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) +pub fn vreinterpretq_f16_p128(a: p128) -> float16x8_t { + unsafe { + let ret_val: float16x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] @@ -39527,13 +37589,11 @@ pub unsafe fn vreinterpretq_f16_p128(a: p128) -> float16x8_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpret_p64_f16(a: float16x4_t) -> poly64x1_t { - transmute(a) +pub fn vreinterpret_p64_f16(a: float16x4_t) -> poly64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] @@ -39544,14 +37604,12 @@ pub unsafe fn vreinterpret_p64_f16(a: float16x4_t) -> poly64x1_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpret_p64_f16(a: float16x4_t) -> poly64x1_t { +pub fn vreinterpret_p64_f16(a: float16x4_t) -> poly64x1_t { let a: float16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - transmute(a) + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] @@ -39562,13 +37620,11 @@ pub unsafe fn vreinterpret_p64_f16(a: float16x4_t) -> poly64x1_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpretq_p128_f16(a: float16x8_t) -> p128 { - transmute(a) +pub fn vreinterpretq_p128_f16(a: float16x8_t) -> p128 { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] @@ -39579,14 +37635,12 @@ pub unsafe fn vreinterpretq_p128_f16(a: float16x8_t) -> p128 { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpretq_p128_f16(a: float16x8_t) -> p128 { +pub fn vreinterpretq_p128_f16(a: float16x8_t) -> p128 { let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - transmute(a) + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] @@ -39597,13 +37651,11 @@ pub unsafe fn vreinterpretq_p128_f16(a: float16x8_t) -> p128 { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpretq_p64_f16(a: float16x8_t) -> poly64x2_t { - transmute(a) +pub fn vreinterpretq_p64_f16(a: float16x8_t) -> poly64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] @@ -39614,15 +37666,15 @@ pub unsafe fn vreinterpretq_p64_f16(a: float16x8_t) -> poly64x2_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpretq_p64_f16(a: float16x8_t) -> poly64x2_t { +pub fn vreinterpretq_p64_f16(a: float16x8_t) -> poly64x2_t { let a: float16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: poly64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: poly64x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] @@ -39633,13 +37685,11 @@ pub unsafe fn vreinterpretq_p64_f16(a: float16x8_t) -> poly64x2_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpret_f16_p64(a: poly64x1_t) -> float16x4_t { - transmute(a) +pub fn vreinterpret_f16_p64(a: poly64x1_t) -> float16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] @@ -39650,14 +37700,14 @@ pub unsafe fn vreinterpret_f16_p64(a: poly64x1_t) -> float16x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpret_f16_p64(a: poly64x1_t) -> float16x4_t { - let ret_val: float16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) +pub fn vreinterpret_f16_p64(a: poly64x1_t) -> float16x4_t { + unsafe { + let ret_val: float16x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] @@ -39668,13 +37718,11 @@ pub unsafe fn vreinterpret_f16_p64(a: poly64x1_t) -> float16x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpretq_f16_p64(a: poly64x2_t) -> float16x8_t { - transmute(a) +pub fn vreinterpretq_f16_p64(a: poly64x2_t) -> float16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] @@ -39685,15 +37733,15 @@ pub unsafe fn vreinterpretq_f16_p64(a: poly64x2_t) -> float16x8_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vreinterpretq_f16_p64(a: poly64x2_t) -> float16x8_t { +pub fn vreinterpretq_f16_p64(a: poly64x2_t) -> float16x8_t { let a: poly64x2_t = simd_shuffle!(a, a, [1, 0]); - let ret_val: float16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: float16x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p128)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -39711,13 +37759,11 @@ pub unsafe fn vreinterpretq_f16_p64(a: poly64x2_t) -> float16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_f32_p128(a: p128) -> float32x4_t { - transmute(a) +pub fn vreinterpretq_f32_p128(a: p128) -> float32x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p128)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -39735,14 +37781,14 @@ pub unsafe fn vreinterpretq_f32_p128(a: p128) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_f32_p128(a: p128) -> float32x4_t { - let ret_val: float32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) +pub fn vreinterpretq_f32_p128(a: p128) -> float32x4_t { + unsafe { + let ret_val: float32x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -39760,13 +37806,11 @@ pub unsafe fn vreinterpretq_f32_p128(a: p128) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s8_f32(a: float32x2_t) -> int8x8_t { - transmute(a) +pub fn vreinterpret_s8_f32(a: float32x2_t) -> int8x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -39784,15 +37828,15 @@ pub unsafe fn vreinterpret_s8_f32(a: float32x2_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s8_f32(a: float32x2_t) -> int8x8_t { +pub fn vreinterpret_s8_f32(a: float32x2_t) -> int8x8_t { let a: float32x2_t = simd_shuffle!(a, a, [1, 0]); - let ret_val: int8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: int8x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -39810,13 +37854,11 @@ pub unsafe fn vreinterpret_s8_f32(a: float32x2_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s16_f32(a: float32x2_t) -> int16x4_t { - transmute(a) +pub fn vreinterpret_s16_f32(a: float32x2_t) -> int16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -39834,15 +37876,15 @@ pub unsafe fn vreinterpret_s16_f32(a: float32x2_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s16_f32(a: float32x2_t) -> int16x4_t { +pub fn vreinterpret_s16_f32(a: float32x2_t) -> int16x4_t { let a: float32x2_t = simd_shuffle!(a, a, [1, 0]); - let ret_val: int16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + unsafe { + let ret_val: int16x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -39860,13 +37902,11 @@ pub unsafe fn vreinterpret_s16_f32(a: float32x2_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s32_f32(a: float32x2_t) -> int32x2_t { - transmute(a) +pub fn vreinterpret_s32_f32(a: float32x2_t) -> int32x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -39884,15 +37924,15 @@ pub unsafe fn vreinterpret_s32_f32(a: float32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s32_f32(a: float32x2_t) -> int32x2_t { +pub fn vreinterpret_s32_f32(a: float32x2_t) -> int32x2_t { let a: float32x2_t = simd_shuffle!(a, a, [1, 0]); - let ret_val: int32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: int32x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -39910,13 +37950,11 @@ pub unsafe fn vreinterpret_s32_f32(a: float32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s64_f32(a: float32x2_t) -> int64x1_t { - transmute(a) +pub fn vreinterpret_s64_f32(a: float32x2_t) -> int64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -39934,14 +37972,12 @@ pub unsafe fn vreinterpret_s64_f32(a: float32x2_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s64_f32(a: float32x2_t) -> int64x1_t { +pub fn vreinterpret_s64_f32(a: float32x2_t) -> int64x1_t { let a: float32x2_t = simd_shuffle!(a, a, [1, 0]); - transmute(a) + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -39959,13 +37995,11 @@ pub unsafe fn vreinterpret_s64_f32(a: float32x2_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u8_f32(a: float32x2_t) -> uint8x8_t { - transmute(a) +pub fn vreinterpret_u8_f32(a: float32x2_t) -> uint8x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -39983,15 +38017,15 @@ pub unsafe fn vreinterpret_u8_f32(a: float32x2_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u8_f32(a: float32x2_t) -> uint8x8_t { +pub fn vreinterpret_u8_f32(a: float32x2_t) -> uint8x8_t { let a: float32x2_t = simd_shuffle!(a, a, [1, 0]); - let ret_val: uint8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: uint8x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -40009,13 +38043,11 @@ pub unsafe fn vreinterpret_u8_f32(a: float32x2_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u16_f32(a: float32x2_t) -> uint16x4_t { - transmute(a) +pub fn vreinterpret_u16_f32(a: float32x2_t) -> uint16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -40033,15 +38065,15 @@ pub unsafe fn vreinterpret_u16_f32(a: float32x2_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u16_f32(a: float32x2_t) -> uint16x4_t { +pub fn vreinterpret_u16_f32(a: float32x2_t) -> uint16x4_t { let a: float32x2_t = simd_shuffle!(a, a, [1, 0]); - let ret_val: uint16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + unsafe { + let ret_val: uint16x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -40059,13 +38091,11 @@ pub unsafe fn vreinterpret_u16_f32(a: float32x2_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u32_f32(a: float32x2_t) -> uint32x2_t { - transmute(a) +pub fn vreinterpret_u32_f32(a: float32x2_t) -> uint32x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -40083,15 +38113,15 @@ pub unsafe fn vreinterpret_u32_f32(a: float32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u32_f32(a: float32x2_t) -> uint32x2_t { +pub fn vreinterpret_u32_f32(a: float32x2_t) -> uint32x2_t { let a: float32x2_t = simd_shuffle!(a, a, [1, 0]); - let ret_val: uint32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: uint32x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -40109,13 +38139,11 @@ pub unsafe fn vreinterpret_u32_f32(a: float32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u64_f32(a: float32x2_t) -> uint64x1_t { - transmute(a) +pub fn vreinterpret_u64_f32(a: float32x2_t) -> uint64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -40133,14 +38161,12 @@ pub unsafe fn vreinterpret_u64_f32(a: float32x2_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u64_f32(a: float32x2_t) -> uint64x1_t { +pub fn vreinterpret_u64_f32(a: float32x2_t) -> uint64x1_t { let a: float32x2_t = simd_shuffle!(a, a, [1, 0]); - transmute(a) + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -40158,13 +38184,11 @@ pub unsafe fn vreinterpret_u64_f32(a: float32x2_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_p8_f32(a: float32x2_t) -> poly8x8_t { - transmute(a) +pub fn vreinterpret_p8_f32(a: float32x2_t) -> poly8x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -40182,15 +38206,15 @@ pub unsafe fn vreinterpret_p8_f32(a: float32x2_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_p8_f32(a: float32x2_t) -> poly8x8_t { +pub fn vreinterpret_p8_f32(a: float32x2_t) -> poly8x8_t { let a: float32x2_t = simd_shuffle!(a, a, [1, 0]); - let ret_val: poly8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: poly8x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -40208,13 +38232,11 @@ pub unsafe fn vreinterpret_p8_f32(a: float32x2_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_p16_f32(a: float32x2_t) -> poly16x4_t { - transmute(a) +pub fn vreinterpret_p16_f32(a: float32x2_t) -> poly16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -40232,15 +38254,15 @@ pub unsafe fn vreinterpret_p16_f32(a: float32x2_t) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_p16_f32(a: float32x2_t) -> poly16x4_t { +pub fn vreinterpret_p16_f32(a: float32x2_t) -> poly16x4_t { let a: float32x2_t = simd_shuffle!(a, a, [1, 0]); - let ret_val: poly16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + unsafe { + let ret_val: poly16x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -40258,13 +38280,11 @@ pub unsafe fn vreinterpret_p16_f32(a: float32x2_t) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p128_f32(a: float32x4_t) -> p128 { - transmute(a) +pub fn vreinterpretq_p128_f32(a: float32x4_t) -> p128 { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -40282,14 +38302,12 @@ pub unsafe fn vreinterpretq_p128_f32(a: float32x4_t) -> p128 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p128_f32(a: float32x4_t) -> p128 { +pub fn vreinterpretq_p128_f32(a: float32x4_t) -> p128 { let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - transmute(a) + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -40307,13 +38325,11 @@ pub unsafe fn vreinterpretq_p128_f32(a: float32x4_t) -> p128 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s8_f32(a: float32x4_t) -> int8x16_t { - transmute(a) +pub fn vreinterpretq_s8_f32(a: float32x4_t) -> int8x16_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -40331,19 +38347,19 @@ pub unsafe fn vreinterpretq_s8_f32(a: float32x4_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s8_f32(a: float32x4_t) -> int8x16_t { +pub fn vreinterpretq_s8_f32(a: float32x4_t) -> int8x16_t { let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - let ret_val: int8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) + unsafe { + let ret_val: int8x16_t = transmute(a); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -40361,13 +38377,11 @@ pub unsafe fn vreinterpretq_s8_f32(a: float32x4_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s16_f32(a: float32x4_t) -> int16x8_t { - transmute(a) +pub fn vreinterpretq_s16_f32(a: float32x4_t) -> int16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -40385,15 +38399,15 @@ pub unsafe fn vreinterpretq_s16_f32(a: float32x4_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s16_f32(a: float32x4_t) -> int16x8_t { +pub fn vreinterpretq_s16_f32(a: float32x4_t) -> int16x8_t { let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - let ret_val: int16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: int16x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -40411,13 +38425,11 @@ pub unsafe fn vreinterpretq_s16_f32(a: float32x4_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s32_f32(a: float32x4_t) -> int32x4_t { - transmute(a) +pub fn vreinterpretq_s32_f32(a: float32x4_t) -> int32x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -40435,15 +38447,15 @@ pub unsafe fn vreinterpretq_s32_f32(a: float32x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s32_f32(a: float32x4_t) -> int32x4_t { +pub fn vreinterpretq_s32_f32(a: float32x4_t) -> int32x4_t { let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - let ret_val: int32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + unsafe { + let ret_val: int32x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -40461,13 +38473,11 @@ pub unsafe fn vreinterpretq_s32_f32(a: float32x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s64_f32(a: float32x4_t) -> int64x2_t { - transmute(a) +pub fn vreinterpretq_s64_f32(a: float32x4_t) -> int64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -40485,15 +38495,15 @@ pub unsafe fn vreinterpretq_s64_f32(a: float32x4_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s64_f32(a: float32x4_t) -> int64x2_t { +pub fn vreinterpretq_s64_f32(a: float32x4_t) -> int64x2_t { let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - let ret_val: int64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: int64x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -40511,13 +38521,11 @@ pub unsafe fn vreinterpretq_s64_f32(a: float32x4_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u8_f32(a: float32x4_t) -> uint8x16_t { - transmute(a) +pub fn vreinterpretq_u8_f32(a: float32x4_t) -> uint8x16_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -40535,19 +38543,19 @@ pub unsafe fn vreinterpretq_u8_f32(a: float32x4_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u8_f32(a: float32x4_t) -> uint8x16_t { +pub fn vreinterpretq_u8_f32(a: float32x4_t) -> uint8x16_t { let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - let ret_val: uint8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) + unsafe { + let ret_val: uint8x16_t = transmute(a); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -40565,13 +38573,11 @@ pub unsafe fn vreinterpretq_u8_f32(a: float32x4_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u16_f32(a: float32x4_t) -> uint16x8_t { - transmute(a) +pub fn vreinterpretq_u16_f32(a: float32x4_t) -> uint16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -40589,15 +38595,15 @@ pub unsafe fn vreinterpretq_u16_f32(a: float32x4_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u16_f32(a: float32x4_t) -> uint16x8_t { +pub fn vreinterpretq_u16_f32(a: float32x4_t) -> uint16x8_t { let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - let ret_val: uint16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: uint16x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -40615,13 +38621,11 @@ pub unsafe fn vreinterpretq_u16_f32(a: float32x4_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u32_f32(a: float32x4_t) -> uint32x4_t { - transmute(a) +pub fn vreinterpretq_u32_f32(a: float32x4_t) -> uint32x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -40639,15 +38643,15 @@ pub unsafe fn vreinterpretq_u32_f32(a: float32x4_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u32_f32(a: float32x4_t) -> uint32x4_t { +pub fn vreinterpretq_u32_f32(a: float32x4_t) -> uint32x4_t { let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - let ret_val: uint32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + unsafe { + let ret_val: uint32x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -40665,13 +38669,11 @@ pub unsafe fn vreinterpretq_u32_f32(a: float32x4_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u64_f32(a: float32x4_t) -> uint64x2_t { - transmute(a) +pub fn vreinterpretq_u64_f32(a: float32x4_t) -> uint64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -40689,15 +38691,15 @@ pub unsafe fn vreinterpretq_u64_f32(a: float32x4_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u64_f32(a: float32x4_t) -> uint64x2_t { +pub fn vreinterpretq_u64_f32(a: float32x4_t) -> uint64x2_t { let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - let ret_val: uint64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: uint64x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -40715,13 +38717,11 @@ pub unsafe fn vreinterpretq_u64_f32(a: float32x4_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p8_f32(a: float32x4_t) -> poly8x16_t { - transmute(a) +pub fn vreinterpretq_p8_f32(a: float32x4_t) -> poly8x16_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -40739,19 +38739,19 @@ pub unsafe fn vreinterpretq_p8_f32(a: float32x4_t) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p8_f32(a: float32x4_t) -> poly8x16_t { +pub fn vreinterpretq_p8_f32(a: float32x4_t) -> poly8x16_t { let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - let ret_val: poly8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) + unsafe { + let ret_val: poly8x16_t = transmute(a); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -40769,13 +38769,11 @@ pub unsafe fn vreinterpretq_p8_f32(a: float32x4_t) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p16_f32(a: float32x4_t) -> poly16x8_t { - transmute(a) +pub fn vreinterpretq_p16_f32(a: float32x4_t) -> poly16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -40793,15 +38791,15 @@ pub unsafe fn vreinterpretq_p16_f32(a: float32x4_t) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p16_f32(a: float32x4_t) -> poly16x8_t { +pub fn vreinterpretq_p16_f32(a: float32x4_t) -> poly16x8_t { let a: float32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - let ret_val: poly16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: poly16x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -40819,13 +38817,11 @@ pub unsafe fn vreinterpretq_p16_f32(a: float32x4_t) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_f32_s8(a: int8x8_t) -> float32x2_t { - transmute(a) +pub fn vreinterpret_f32_s8(a: int8x8_t) -> float32x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -40843,15 +38839,15 @@ pub unsafe fn vreinterpret_f32_s8(a: int8x8_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_f32_s8(a: int8x8_t) -> float32x2_t { +pub fn vreinterpret_f32_s8(a: int8x8_t) -> float32x2_t { let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: float32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: float32x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -40869,13 +38865,11 @@ pub unsafe fn vreinterpret_f32_s8(a: int8x8_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s16_s8(a: int8x8_t) -> int16x4_t { - transmute(a) +pub fn vreinterpret_s16_s8(a: int8x8_t) -> int16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -40893,15 +38887,15 @@ pub unsafe fn vreinterpret_s16_s8(a: int8x8_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s16_s8(a: int8x8_t) -> int16x4_t { +pub fn vreinterpret_s16_s8(a: int8x8_t) -> int16x4_t { let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: int16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + unsafe { + let ret_val: int16x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -40919,13 +38913,11 @@ pub unsafe fn vreinterpret_s16_s8(a: int8x8_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s32_s8(a: int8x8_t) -> int32x2_t { - transmute(a) +pub fn vreinterpret_s32_s8(a: int8x8_t) -> int32x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -40943,15 +38935,15 @@ pub unsafe fn vreinterpret_s32_s8(a: int8x8_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s32_s8(a: int8x8_t) -> int32x2_t { +pub fn vreinterpret_s32_s8(a: int8x8_t) -> int32x2_t { let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: int32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: int32x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -40969,13 +38961,11 @@ pub unsafe fn vreinterpret_s32_s8(a: int8x8_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s64_s8(a: int8x8_t) -> int64x1_t { - transmute(a) +pub fn vreinterpret_s64_s8(a: int8x8_t) -> int64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -40993,14 +38983,12 @@ pub unsafe fn vreinterpret_s64_s8(a: int8x8_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s64_s8(a: int8x8_t) -> int64x1_t { +pub fn vreinterpret_s64_s8(a: int8x8_t) -> int64x1_t { let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - transmute(a) + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -41018,13 +39006,11 @@ pub unsafe fn vreinterpret_s64_s8(a: int8x8_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u8_s8(a: int8x8_t) -> uint8x8_t { - transmute(a) +pub fn vreinterpret_u8_s8(a: int8x8_t) -> uint8x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -41042,15 +39028,15 @@ pub unsafe fn vreinterpret_u8_s8(a: int8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u8_s8(a: int8x8_t) -> uint8x8_t { +pub fn vreinterpret_u8_s8(a: int8x8_t) -> uint8x8_t { let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: uint8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: uint8x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -41068,13 +39054,11 @@ pub unsafe fn vreinterpret_u8_s8(a: int8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u16_s8(a: int8x8_t) -> uint16x4_t { - transmute(a) +pub fn vreinterpret_u16_s8(a: int8x8_t) -> uint16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -41092,15 +39076,15 @@ pub unsafe fn vreinterpret_u16_s8(a: int8x8_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u16_s8(a: int8x8_t) -> uint16x4_t { +pub fn vreinterpret_u16_s8(a: int8x8_t) -> uint16x4_t { let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: uint16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + unsafe { + let ret_val: uint16x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -41118,13 +39102,11 @@ pub unsafe fn vreinterpret_u16_s8(a: int8x8_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u32_s8(a: int8x8_t) -> uint32x2_t { - transmute(a) +pub fn vreinterpret_u32_s8(a: int8x8_t) -> uint32x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -41142,15 +39124,15 @@ pub unsafe fn vreinterpret_u32_s8(a: int8x8_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u32_s8(a: int8x8_t) -> uint32x2_t { +pub fn vreinterpret_u32_s8(a: int8x8_t) -> uint32x2_t { let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: uint32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: uint32x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -41168,13 +39150,11 @@ pub unsafe fn vreinterpret_u32_s8(a: int8x8_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u64_s8(a: int8x8_t) -> uint64x1_t { - transmute(a) +pub fn vreinterpret_u64_s8(a: int8x8_t) -> uint64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -41192,14 +39172,12 @@ pub unsafe fn vreinterpret_u64_s8(a: int8x8_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u64_s8(a: int8x8_t) -> uint64x1_t { +pub fn vreinterpret_u64_s8(a: int8x8_t) -> uint64x1_t { let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - transmute(a) + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -41217,13 +39195,11 @@ pub unsafe fn vreinterpret_u64_s8(a: int8x8_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_p8_s8(a: int8x8_t) -> poly8x8_t { - transmute(a) +pub fn vreinterpret_p8_s8(a: int8x8_t) -> poly8x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -41241,15 +39217,15 @@ pub unsafe fn vreinterpret_p8_s8(a: int8x8_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_p8_s8(a: int8x8_t) -> poly8x8_t { +pub fn vreinterpret_p8_s8(a: int8x8_t) -> poly8x8_t { let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: poly8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: poly8x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -41267,13 +39243,11 @@ pub unsafe fn vreinterpret_p8_s8(a: int8x8_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_p16_s8(a: int8x8_t) -> poly16x4_t { - transmute(a) +pub fn vreinterpret_p16_s8(a: int8x8_t) -> poly16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -41291,15 +39265,15 @@ pub unsafe fn vreinterpret_p16_s8(a: int8x8_t) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_p16_s8(a: int8x8_t) -> poly16x4_t { +pub fn vreinterpret_p16_s8(a: int8x8_t) -> poly16x4_t { let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: poly16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + unsafe { + let ret_val: poly16x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -41317,13 +39291,11 @@ pub unsafe fn vreinterpret_p16_s8(a: int8x8_t) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_f32_s8(a: int8x16_t) -> float32x4_t { - transmute(a) +pub fn vreinterpretq_f32_s8(a: int8x16_t) -> float32x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -41341,15 +39313,15 @@ pub unsafe fn vreinterpretq_f32_s8(a: int8x16_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_f32_s8(a: int8x16_t) -> float32x4_t { +pub fn vreinterpretq_f32_s8(a: int8x16_t) -> float32x4_t { let a: int8x16_t = simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: float32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + unsafe { + let ret_val: float32x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -41367,13 +39339,11 @@ pub unsafe fn vreinterpretq_f32_s8(a: int8x16_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s16_s8(a: int8x16_t) -> int16x8_t { - transmute(a) +pub fn vreinterpretq_s16_s8(a: int8x16_t) -> int16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -41391,15 +39361,15 @@ pub unsafe fn vreinterpretq_s16_s8(a: int8x16_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s16_s8(a: int8x16_t) -> int16x8_t { +pub fn vreinterpretq_s16_s8(a: int8x16_t) -> int16x8_t { let a: int8x16_t = simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: int16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: int16x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -41417,13 +39387,11 @@ pub unsafe fn vreinterpretq_s16_s8(a: int8x16_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s32_s8(a: int8x16_t) -> int32x4_t { - transmute(a) +pub fn vreinterpretq_s32_s8(a: int8x16_t) -> int32x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -41441,15 +39409,15 @@ pub unsafe fn vreinterpretq_s32_s8(a: int8x16_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s32_s8(a: int8x16_t) -> int32x4_t { +pub fn vreinterpretq_s32_s8(a: int8x16_t) -> int32x4_t { let a: int8x16_t = simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: int32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + unsafe { + let ret_val: int32x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -41467,13 +39435,11 @@ pub unsafe fn vreinterpretq_s32_s8(a: int8x16_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s64_s8(a: int8x16_t) -> int64x2_t { - transmute(a) +pub fn vreinterpretq_s64_s8(a: int8x16_t) -> int64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -41491,15 +39457,15 @@ pub unsafe fn vreinterpretq_s64_s8(a: int8x16_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s64_s8(a: int8x16_t) -> int64x2_t { +pub fn vreinterpretq_s64_s8(a: int8x16_t) -> int64x2_t { let a: int8x16_t = simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: int64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: int64x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -41517,13 +39483,11 @@ pub unsafe fn vreinterpretq_s64_s8(a: int8x16_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u8_s8(a: int8x16_t) -> uint8x16_t { - transmute(a) +pub fn vreinterpretq_u8_s8(a: int8x16_t) -> uint8x16_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -41541,19 +39505,19 @@ pub unsafe fn vreinterpretq_u8_s8(a: int8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u8_s8(a: int8x16_t) -> uint8x16_t { +pub fn vreinterpretq_u8_s8(a: int8x16_t) -> uint8x16_t { let a: int8x16_t = simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: uint8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) + unsafe { + let ret_val: uint8x16_t = transmute(a); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -41571,13 +39535,11 @@ pub unsafe fn vreinterpretq_u8_s8(a: int8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u16_s8(a: int8x16_t) -> uint16x8_t { - transmute(a) +pub fn vreinterpretq_u16_s8(a: int8x16_t) -> uint16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -41595,15 +39557,15 @@ pub unsafe fn vreinterpretq_u16_s8(a: int8x16_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u16_s8(a: int8x16_t) -> uint16x8_t { +pub fn vreinterpretq_u16_s8(a: int8x16_t) -> uint16x8_t { let a: int8x16_t = simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: uint16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: uint16x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -41621,13 +39583,11 @@ pub unsafe fn vreinterpretq_u16_s8(a: int8x16_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u32_s8(a: int8x16_t) -> uint32x4_t { - transmute(a) +pub fn vreinterpretq_u32_s8(a: int8x16_t) -> uint32x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -41645,15 +39605,15 @@ pub unsafe fn vreinterpretq_u32_s8(a: int8x16_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u32_s8(a: int8x16_t) -> uint32x4_t { +pub fn vreinterpretq_u32_s8(a: int8x16_t) -> uint32x4_t { let a: int8x16_t = simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: uint32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + unsafe { + let ret_val: uint32x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -41671,13 +39631,11 @@ pub unsafe fn vreinterpretq_u32_s8(a: int8x16_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u64_s8(a: int8x16_t) -> uint64x2_t { - transmute(a) +pub fn vreinterpretq_u64_s8(a: int8x16_t) -> uint64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -41695,15 +39653,15 @@ pub unsafe fn vreinterpretq_u64_s8(a: int8x16_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u64_s8(a: int8x16_t) -> uint64x2_t { +pub fn vreinterpretq_u64_s8(a: int8x16_t) -> uint64x2_t { let a: int8x16_t = simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: uint64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: uint64x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -41721,13 +39679,11 @@ pub unsafe fn vreinterpretq_u64_s8(a: int8x16_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p8_s8(a: int8x16_t) -> poly8x16_t { - transmute(a) +pub fn vreinterpretq_p8_s8(a: int8x16_t) -> poly8x16_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -41745,19 +39701,19 @@ pub unsafe fn vreinterpretq_p8_s8(a: int8x16_t) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p8_s8(a: int8x16_t) -> poly8x16_t { +pub fn vreinterpretq_p8_s8(a: int8x16_t) -> poly8x16_t { let a: int8x16_t = simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: poly8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) + unsafe { + let ret_val: poly8x16_t = transmute(a); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -41775,13 +39731,11 @@ pub unsafe fn vreinterpretq_p8_s8(a: int8x16_t) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p16_s8(a: int8x16_t) -> poly16x8_t { - transmute(a) +pub fn vreinterpretq_p16_s8(a: int8x16_t) -> poly16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -41799,15 +39753,15 @@ pub unsafe fn vreinterpretq_p16_s8(a: int8x16_t) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p16_s8(a: int8x16_t) -> poly16x8_t { +pub fn vreinterpretq_p16_s8(a: int8x16_t) -> poly16x8_t { let a: int8x16_t = simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: poly16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: poly16x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -41825,13 +39779,11 @@ pub unsafe fn vreinterpretq_p16_s8(a: int8x16_t) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_f32_s16(a: int16x4_t) -> float32x2_t { - transmute(a) +pub fn vreinterpret_f32_s16(a: int16x4_t) -> float32x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -41849,15 +39801,15 @@ pub unsafe fn vreinterpret_f32_s16(a: int16x4_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_f32_s16(a: int16x4_t) -> float32x2_t { +pub fn vreinterpret_f32_s16(a: int16x4_t) -> float32x2_t { let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - let ret_val: float32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: float32x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -41875,13 +39827,11 @@ pub unsafe fn vreinterpret_f32_s16(a: int16x4_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s8_s16(a: int16x4_t) -> int8x8_t { - transmute(a) +pub fn vreinterpret_s8_s16(a: int16x4_t) -> int8x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -41899,15 +39849,15 @@ pub unsafe fn vreinterpret_s8_s16(a: int16x4_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s8_s16(a: int16x4_t) -> int8x8_t { +pub fn vreinterpret_s8_s16(a: int16x4_t) -> int8x8_t { let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - let ret_val: int8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: int8x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -41925,13 +39875,11 @@ pub unsafe fn vreinterpret_s8_s16(a: int16x4_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s32_s16(a: int16x4_t) -> int32x2_t { - transmute(a) +pub fn vreinterpret_s32_s16(a: int16x4_t) -> int32x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -41949,15 +39897,15 @@ pub unsafe fn vreinterpret_s32_s16(a: int16x4_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s32_s16(a: int16x4_t) -> int32x2_t { +pub fn vreinterpret_s32_s16(a: int16x4_t) -> int32x2_t { let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - let ret_val: int32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: int32x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -41975,13 +39923,11 @@ pub unsafe fn vreinterpret_s32_s16(a: int16x4_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s64_s16(a: int16x4_t) -> int64x1_t { - transmute(a) +pub fn vreinterpret_s64_s16(a: int16x4_t) -> int64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -41999,14 +39945,12 @@ pub unsafe fn vreinterpret_s64_s16(a: int16x4_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s64_s16(a: int16x4_t) -> int64x1_t { +pub fn vreinterpret_s64_s16(a: int16x4_t) -> int64x1_t { let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - transmute(a) + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -42024,13 +39968,11 @@ pub unsafe fn vreinterpret_s64_s16(a: int16x4_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u8_s16(a: int16x4_t) -> uint8x8_t { - transmute(a) +pub fn vreinterpret_u8_s16(a: int16x4_t) -> uint8x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -42048,15 +39990,15 @@ pub unsafe fn vreinterpret_u8_s16(a: int16x4_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u8_s16(a: int16x4_t) -> uint8x8_t { +pub fn vreinterpret_u8_s16(a: int16x4_t) -> uint8x8_t { let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - let ret_val: uint8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: uint8x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -42074,13 +40016,11 @@ pub unsafe fn vreinterpret_u8_s16(a: int16x4_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u16_s16(a: int16x4_t) -> uint16x4_t { - transmute(a) +pub fn vreinterpret_u16_s16(a: int16x4_t) -> uint16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -42098,15 +40038,15 @@ pub unsafe fn vreinterpret_u16_s16(a: int16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u16_s16(a: int16x4_t) -> uint16x4_t { +pub fn vreinterpret_u16_s16(a: int16x4_t) -> uint16x4_t { let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - let ret_val: uint16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + unsafe { + let ret_val: uint16x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -42124,13 +40064,11 @@ pub unsafe fn vreinterpret_u16_s16(a: int16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u32_s16(a: int16x4_t) -> uint32x2_t { - transmute(a) +pub fn vreinterpret_u32_s16(a: int16x4_t) -> uint32x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -42148,15 +40086,15 @@ pub unsafe fn vreinterpret_u32_s16(a: int16x4_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u32_s16(a: int16x4_t) -> uint32x2_t { +pub fn vreinterpret_u32_s16(a: int16x4_t) -> uint32x2_t { let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - let ret_val: uint32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: uint32x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -42174,13 +40112,11 @@ pub unsafe fn vreinterpret_u32_s16(a: int16x4_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u64_s16(a: int16x4_t) -> uint64x1_t { - transmute(a) +pub fn vreinterpret_u64_s16(a: int16x4_t) -> uint64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -42198,14 +40134,12 @@ pub unsafe fn vreinterpret_u64_s16(a: int16x4_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u64_s16(a: int16x4_t) -> uint64x1_t { +pub fn vreinterpret_u64_s16(a: int16x4_t) -> uint64x1_t { let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - transmute(a) + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -42223,13 +40157,11 @@ pub unsafe fn vreinterpret_u64_s16(a: int16x4_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_p8_s16(a: int16x4_t) -> poly8x8_t { - transmute(a) +pub fn vreinterpret_p8_s16(a: int16x4_t) -> poly8x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -42247,15 +40179,15 @@ pub unsafe fn vreinterpret_p8_s16(a: int16x4_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_p8_s16(a: int16x4_t) -> poly8x8_t { +pub fn vreinterpret_p8_s16(a: int16x4_t) -> poly8x8_t { let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - let ret_val: poly8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: poly8x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -42273,13 +40205,11 @@ pub unsafe fn vreinterpret_p8_s16(a: int16x4_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_p16_s16(a: int16x4_t) -> poly16x4_t { - transmute(a) +pub fn vreinterpret_p16_s16(a: int16x4_t) -> poly16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -42297,15 +40227,15 @@ pub unsafe fn vreinterpret_p16_s16(a: int16x4_t) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_p16_s16(a: int16x4_t) -> poly16x4_t { +pub fn vreinterpret_p16_s16(a: int16x4_t) -> poly16x4_t { let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - let ret_val: poly16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + unsafe { + let ret_val: poly16x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -42323,13 +40253,11 @@ pub unsafe fn vreinterpret_p16_s16(a: int16x4_t) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_f32_s16(a: int16x8_t) -> float32x4_t { - transmute(a) +pub fn vreinterpretq_f32_s16(a: int16x8_t) -> float32x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -42347,15 +40275,15 @@ pub unsafe fn vreinterpretq_f32_s16(a: int16x8_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_f32_s16(a: int16x8_t) -> float32x4_t { +pub fn vreinterpretq_f32_s16(a: int16x8_t) -> float32x4_t { let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: float32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + unsafe { + let ret_val: float32x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -42373,13 +40301,11 @@ pub unsafe fn vreinterpretq_f32_s16(a: int16x8_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s8_s16(a: int16x8_t) -> int8x16_t { - transmute(a) +pub fn vreinterpretq_s8_s16(a: int16x8_t) -> int8x16_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -42397,19 +40323,19 @@ pub unsafe fn vreinterpretq_s8_s16(a: int16x8_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s8_s16(a: int16x8_t) -> int8x16_t { +pub fn vreinterpretq_s8_s16(a: int16x8_t) -> int8x16_t { let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: int8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) + unsafe { + let ret_val: int8x16_t = transmute(a); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -42427,13 +40353,11 @@ pub unsafe fn vreinterpretq_s8_s16(a: int16x8_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s32_s16(a: int16x8_t) -> int32x4_t { - transmute(a) +pub fn vreinterpretq_s32_s16(a: int16x8_t) -> int32x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -42451,15 +40375,15 @@ pub unsafe fn vreinterpretq_s32_s16(a: int16x8_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s32_s16(a: int16x8_t) -> int32x4_t { +pub fn vreinterpretq_s32_s16(a: int16x8_t) -> int32x4_t { let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: int32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + unsafe { + let ret_val: int32x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -42477,13 +40401,11 @@ pub unsafe fn vreinterpretq_s32_s16(a: int16x8_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s64_s16(a: int16x8_t) -> int64x2_t { - transmute(a) +pub fn vreinterpretq_s64_s16(a: int16x8_t) -> int64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -42501,15 +40423,15 @@ pub unsafe fn vreinterpretq_s64_s16(a: int16x8_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s64_s16(a: int16x8_t) -> int64x2_t { +pub fn vreinterpretq_s64_s16(a: int16x8_t) -> int64x2_t { let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: int64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: int64x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -42527,13 +40449,11 @@ pub unsafe fn vreinterpretq_s64_s16(a: int16x8_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u8_s16(a: int16x8_t) -> uint8x16_t { - transmute(a) +pub fn vreinterpretq_u8_s16(a: int16x8_t) -> uint8x16_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -42551,19 +40471,19 @@ pub unsafe fn vreinterpretq_u8_s16(a: int16x8_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u8_s16(a: int16x8_t) -> uint8x16_t { +pub fn vreinterpretq_u8_s16(a: int16x8_t) -> uint8x16_t { let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: uint8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) + unsafe { + let ret_val: uint8x16_t = transmute(a); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -42581,13 +40501,11 @@ pub unsafe fn vreinterpretq_u8_s16(a: int16x8_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u16_s16(a: int16x8_t) -> uint16x8_t { - transmute(a) +pub fn vreinterpretq_u16_s16(a: int16x8_t) -> uint16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -42605,15 +40523,15 @@ pub unsafe fn vreinterpretq_u16_s16(a: int16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u16_s16(a: int16x8_t) -> uint16x8_t { +pub fn vreinterpretq_u16_s16(a: int16x8_t) -> uint16x8_t { let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: uint16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: uint16x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -42631,13 +40549,11 @@ pub unsafe fn vreinterpretq_u16_s16(a: int16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u32_s16(a: int16x8_t) -> uint32x4_t { - transmute(a) +pub fn vreinterpretq_u32_s16(a: int16x8_t) -> uint32x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -42655,15 +40571,15 @@ pub unsafe fn vreinterpretq_u32_s16(a: int16x8_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u32_s16(a: int16x8_t) -> uint32x4_t { +pub fn vreinterpretq_u32_s16(a: int16x8_t) -> uint32x4_t { let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: uint32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + unsafe { + let ret_val: uint32x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -42681,13 +40597,11 @@ pub unsafe fn vreinterpretq_u32_s16(a: int16x8_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u64_s16(a: int16x8_t) -> uint64x2_t { - transmute(a) +pub fn vreinterpretq_u64_s16(a: int16x8_t) -> uint64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -42705,15 +40619,15 @@ pub unsafe fn vreinterpretq_u64_s16(a: int16x8_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u64_s16(a: int16x8_t) -> uint64x2_t { +pub fn vreinterpretq_u64_s16(a: int16x8_t) -> uint64x2_t { let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: uint64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: uint64x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -42731,13 +40645,11 @@ pub unsafe fn vreinterpretq_u64_s16(a: int16x8_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p8_s16(a: int16x8_t) -> poly8x16_t { - transmute(a) +pub fn vreinterpretq_p8_s16(a: int16x8_t) -> poly8x16_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -42755,19 +40667,19 @@ pub unsafe fn vreinterpretq_p8_s16(a: int16x8_t) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p8_s16(a: int16x8_t) -> poly8x16_t { +pub fn vreinterpretq_p8_s16(a: int16x8_t) -> poly8x16_t { let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: poly8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) + unsafe { + let ret_val: poly8x16_t = transmute(a); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -42785,13 +40697,11 @@ pub unsafe fn vreinterpretq_p8_s16(a: int16x8_t) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p16_s16(a: int16x8_t) -> poly16x8_t { - transmute(a) +pub fn vreinterpretq_p16_s16(a: int16x8_t) -> poly16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -42809,15 +40719,15 @@ pub unsafe fn vreinterpretq_p16_s16(a: int16x8_t) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p16_s16(a: int16x8_t) -> poly16x8_t { +pub fn vreinterpretq_p16_s16(a: int16x8_t) -> poly16x8_t { let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: poly16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: poly16x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -42835,13 +40745,11 @@ pub unsafe fn vreinterpretq_p16_s16(a: int16x8_t) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_f32_s32(a: int32x2_t) -> float32x2_t { - transmute(a) +pub fn vreinterpret_f32_s32(a: int32x2_t) -> float32x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -42859,15 +40767,15 @@ pub unsafe fn vreinterpret_f32_s32(a: int32x2_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_f32_s32(a: int32x2_t) -> float32x2_t { +pub fn vreinterpret_f32_s32(a: int32x2_t) -> float32x2_t { let a: int32x2_t = simd_shuffle!(a, a, [1, 0]); - let ret_val: float32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: float32x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -42885,13 +40793,11 @@ pub unsafe fn vreinterpret_f32_s32(a: int32x2_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s8_s32(a: int32x2_t) -> int8x8_t { - transmute(a) +pub fn vreinterpret_s8_s32(a: int32x2_t) -> int8x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -42909,15 +40815,15 @@ pub unsafe fn vreinterpret_s8_s32(a: int32x2_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s8_s32(a: int32x2_t) -> int8x8_t { +pub fn vreinterpret_s8_s32(a: int32x2_t) -> int8x8_t { let a: int32x2_t = simd_shuffle!(a, a, [1, 0]); - let ret_val: int8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: int8x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -42935,13 +40841,11 @@ pub unsafe fn vreinterpret_s8_s32(a: int32x2_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s16_s32(a: int32x2_t) -> int16x4_t { - transmute(a) +pub fn vreinterpret_s16_s32(a: int32x2_t) -> int16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -42959,15 +40863,15 @@ pub unsafe fn vreinterpret_s16_s32(a: int32x2_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s16_s32(a: int32x2_t) -> int16x4_t { +pub fn vreinterpret_s16_s32(a: int32x2_t) -> int16x4_t { let a: int32x2_t = simd_shuffle!(a, a, [1, 0]); - let ret_val: int16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + unsafe { + let ret_val: int16x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -42985,13 +40889,11 @@ pub unsafe fn vreinterpret_s16_s32(a: int32x2_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s64_s32(a: int32x2_t) -> int64x1_t { - transmute(a) +pub fn vreinterpret_s64_s32(a: int32x2_t) -> int64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -43009,14 +40911,12 @@ pub unsafe fn vreinterpret_s64_s32(a: int32x2_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s64_s32(a: int32x2_t) -> int64x1_t { +pub fn vreinterpret_s64_s32(a: int32x2_t) -> int64x1_t { let a: int32x2_t = simd_shuffle!(a, a, [1, 0]); - transmute(a) + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -43034,13 +40934,11 @@ pub unsafe fn vreinterpret_s64_s32(a: int32x2_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u8_s32(a: int32x2_t) -> uint8x8_t { - transmute(a) +pub fn vreinterpret_u8_s32(a: int32x2_t) -> uint8x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -43058,15 +40956,15 @@ pub unsafe fn vreinterpret_u8_s32(a: int32x2_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u8_s32(a: int32x2_t) -> uint8x8_t { +pub fn vreinterpret_u8_s32(a: int32x2_t) -> uint8x8_t { let a: int32x2_t = simd_shuffle!(a, a, [1, 0]); - let ret_val: uint8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: uint8x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -43084,13 +40982,11 @@ pub unsafe fn vreinterpret_u8_s32(a: int32x2_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u16_s32(a: int32x2_t) -> uint16x4_t { - transmute(a) +pub fn vreinterpret_u16_s32(a: int32x2_t) -> uint16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -43108,15 +41004,15 @@ pub unsafe fn vreinterpret_u16_s32(a: int32x2_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u16_s32(a: int32x2_t) -> uint16x4_t { +pub fn vreinterpret_u16_s32(a: int32x2_t) -> uint16x4_t { let a: int32x2_t = simd_shuffle!(a, a, [1, 0]); - let ret_val: uint16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + unsafe { + let ret_val: uint16x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -43134,13 +41030,11 @@ pub unsafe fn vreinterpret_u16_s32(a: int32x2_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u32_s32(a: int32x2_t) -> uint32x2_t { - transmute(a) +pub fn vreinterpret_u32_s32(a: int32x2_t) -> uint32x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -43158,15 +41052,15 @@ pub unsafe fn vreinterpret_u32_s32(a: int32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u32_s32(a: int32x2_t) -> uint32x2_t { +pub fn vreinterpret_u32_s32(a: int32x2_t) -> uint32x2_t { let a: int32x2_t = simd_shuffle!(a, a, [1, 0]); - let ret_val: uint32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: uint32x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -43184,13 +41078,11 @@ pub unsafe fn vreinterpret_u32_s32(a: int32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u64_s32(a: int32x2_t) -> uint64x1_t { - transmute(a) +pub fn vreinterpret_u64_s32(a: int32x2_t) -> uint64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -43208,14 +41100,12 @@ pub unsafe fn vreinterpret_u64_s32(a: int32x2_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u64_s32(a: int32x2_t) -> uint64x1_t { +pub fn vreinterpret_u64_s32(a: int32x2_t) -> uint64x1_t { let a: int32x2_t = simd_shuffle!(a, a, [1, 0]); - transmute(a) + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -43233,13 +41123,11 @@ pub unsafe fn vreinterpret_u64_s32(a: int32x2_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_p8_s32(a: int32x2_t) -> poly8x8_t { - transmute(a) +pub fn vreinterpret_p8_s32(a: int32x2_t) -> poly8x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -43257,15 +41145,15 @@ pub unsafe fn vreinterpret_p8_s32(a: int32x2_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_p8_s32(a: int32x2_t) -> poly8x8_t { +pub fn vreinterpret_p8_s32(a: int32x2_t) -> poly8x8_t { let a: int32x2_t = simd_shuffle!(a, a, [1, 0]); - let ret_val: poly8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: poly8x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -43283,13 +41171,11 @@ pub unsafe fn vreinterpret_p8_s32(a: int32x2_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_p16_s32(a: int32x2_t) -> poly16x4_t { - transmute(a) +pub fn vreinterpret_p16_s32(a: int32x2_t) -> poly16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -43307,15 +41193,15 @@ pub unsafe fn vreinterpret_p16_s32(a: int32x2_t) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_p16_s32(a: int32x2_t) -> poly16x4_t { +pub fn vreinterpret_p16_s32(a: int32x2_t) -> poly16x4_t { let a: int32x2_t = simd_shuffle!(a, a, [1, 0]); - let ret_val: poly16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + unsafe { + let ret_val: poly16x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -43333,13 +41219,11 @@ pub unsafe fn vreinterpret_p16_s32(a: int32x2_t) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_f32_s32(a: int32x4_t) -> float32x4_t { - transmute(a) +pub fn vreinterpretq_f32_s32(a: int32x4_t) -> float32x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -43357,15 +41241,15 @@ pub unsafe fn vreinterpretq_f32_s32(a: int32x4_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_f32_s32(a: int32x4_t) -> float32x4_t { +pub fn vreinterpretq_f32_s32(a: int32x4_t) -> float32x4_t { let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - let ret_val: float32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + unsafe { + let ret_val: float32x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -43383,13 +41267,11 @@ pub unsafe fn vreinterpretq_f32_s32(a: int32x4_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s8_s32(a: int32x4_t) -> int8x16_t { - transmute(a) +pub fn vreinterpretq_s8_s32(a: int32x4_t) -> int8x16_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -43407,19 +41289,19 @@ pub unsafe fn vreinterpretq_s8_s32(a: int32x4_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s8_s32(a: int32x4_t) -> int8x16_t { +pub fn vreinterpretq_s8_s32(a: int32x4_t) -> int8x16_t { let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - let ret_val: int8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) + unsafe { + let ret_val: int8x16_t = transmute(a); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -43437,13 +41319,11 @@ pub unsafe fn vreinterpretq_s8_s32(a: int32x4_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s16_s32(a: int32x4_t) -> int16x8_t { - transmute(a) +pub fn vreinterpretq_s16_s32(a: int32x4_t) -> int16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -43461,15 +41341,15 @@ pub unsafe fn vreinterpretq_s16_s32(a: int32x4_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s16_s32(a: int32x4_t) -> int16x8_t { +pub fn vreinterpretq_s16_s32(a: int32x4_t) -> int16x8_t { let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - let ret_val: int16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: int16x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -43487,13 +41367,11 @@ pub unsafe fn vreinterpretq_s16_s32(a: int32x4_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s64_s32(a: int32x4_t) -> int64x2_t { - transmute(a) +pub fn vreinterpretq_s64_s32(a: int32x4_t) -> int64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -43511,15 +41389,15 @@ pub unsafe fn vreinterpretq_s64_s32(a: int32x4_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s64_s32(a: int32x4_t) -> int64x2_t { +pub fn vreinterpretq_s64_s32(a: int32x4_t) -> int64x2_t { let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - let ret_val: int64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: int64x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -43537,13 +41415,11 @@ pub unsafe fn vreinterpretq_s64_s32(a: int32x4_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u8_s32(a: int32x4_t) -> uint8x16_t { - transmute(a) +pub fn vreinterpretq_u8_s32(a: int32x4_t) -> uint8x16_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -43561,19 +41437,19 @@ pub unsafe fn vreinterpretq_u8_s32(a: int32x4_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u8_s32(a: int32x4_t) -> uint8x16_t { +pub fn vreinterpretq_u8_s32(a: int32x4_t) -> uint8x16_t { let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - let ret_val: uint8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) + unsafe { + let ret_val: uint8x16_t = transmute(a); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -43591,13 +41467,11 @@ pub unsafe fn vreinterpretq_u8_s32(a: int32x4_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u16_s32(a: int32x4_t) -> uint16x8_t { - transmute(a) +pub fn vreinterpretq_u16_s32(a: int32x4_t) -> uint16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -43615,15 +41489,15 @@ pub unsafe fn vreinterpretq_u16_s32(a: int32x4_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u16_s32(a: int32x4_t) -> uint16x8_t { +pub fn vreinterpretq_u16_s32(a: int32x4_t) -> uint16x8_t { let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - let ret_val: uint16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: uint16x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -43641,13 +41515,11 @@ pub unsafe fn vreinterpretq_u16_s32(a: int32x4_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u32_s32(a: int32x4_t) -> uint32x4_t { - transmute(a) +pub fn vreinterpretq_u32_s32(a: int32x4_t) -> uint32x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -43665,15 +41537,15 @@ pub unsafe fn vreinterpretq_u32_s32(a: int32x4_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u32_s32(a: int32x4_t) -> uint32x4_t { +pub fn vreinterpretq_u32_s32(a: int32x4_t) -> uint32x4_t { let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - let ret_val: uint32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + unsafe { + let ret_val: uint32x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -43691,13 +41563,11 @@ pub unsafe fn vreinterpretq_u32_s32(a: int32x4_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u64_s32(a: int32x4_t) -> uint64x2_t { - transmute(a) +pub fn vreinterpretq_u64_s32(a: int32x4_t) -> uint64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -43715,15 +41585,15 @@ pub unsafe fn vreinterpretq_u64_s32(a: int32x4_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u64_s32(a: int32x4_t) -> uint64x2_t { +pub fn vreinterpretq_u64_s32(a: int32x4_t) -> uint64x2_t { let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - let ret_val: uint64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: uint64x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -43741,13 +41611,11 @@ pub unsafe fn vreinterpretq_u64_s32(a: int32x4_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p8_s32(a: int32x4_t) -> poly8x16_t { - transmute(a) +pub fn vreinterpretq_p8_s32(a: int32x4_t) -> poly8x16_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -43765,19 +41633,19 @@ pub unsafe fn vreinterpretq_p8_s32(a: int32x4_t) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p8_s32(a: int32x4_t) -> poly8x16_t { +pub fn vreinterpretq_p8_s32(a: int32x4_t) -> poly8x16_t { let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - let ret_val: poly8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) + unsafe { + let ret_val: poly8x16_t = transmute(a); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -43795,13 +41663,11 @@ pub unsafe fn vreinterpretq_p8_s32(a: int32x4_t) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p16_s32(a: int32x4_t) -> poly16x8_t { - transmute(a) +pub fn vreinterpretq_p16_s32(a: int32x4_t) -> poly16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -43819,15 +41685,15 @@ pub unsafe fn vreinterpretq_p16_s32(a: int32x4_t) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p16_s32(a: int32x4_t) -> poly16x8_t { +pub fn vreinterpretq_p16_s32(a: int32x4_t) -> poly16x8_t { let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - let ret_val: poly16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: poly16x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -43845,13 +41711,11 @@ pub unsafe fn vreinterpretq_p16_s32(a: int32x4_t) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_f32_s64(a: int64x1_t) -> float32x2_t { - transmute(a) +pub fn vreinterpret_f32_s64(a: int64x1_t) -> float32x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -43869,14 +41733,14 @@ pub unsafe fn vreinterpret_f32_s64(a: int64x1_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_f32_s64(a: int64x1_t) -> float32x2_t { - let ret_val: float32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) +pub fn vreinterpret_f32_s64(a: int64x1_t) -> float32x2_t { + unsafe { + let ret_val: float32x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -43894,13 +41758,11 @@ pub unsafe fn vreinterpret_f32_s64(a: int64x1_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s8_s64(a: int64x1_t) -> int8x8_t { - transmute(a) +pub fn vreinterpret_s8_s64(a: int64x1_t) -> int8x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -43918,14 +41780,14 @@ pub unsafe fn vreinterpret_s8_s64(a: int64x1_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s8_s64(a: int64x1_t) -> int8x8_t { - let ret_val: int8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) +pub fn vreinterpret_s8_s64(a: int64x1_t) -> int8x8_t { + unsafe { + let ret_val: int8x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -43943,13 +41805,11 @@ pub unsafe fn vreinterpret_s8_s64(a: int64x1_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s16_s64(a: int64x1_t) -> int16x4_t { - transmute(a) +pub fn vreinterpret_s16_s64(a: int64x1_t) -> int16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -43967,14 +41827,14 @@ pub unsafe fn vreinterpret_s16_s64(a: int64x1_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s16_s64(a: int64x1_t) -> int16x4_t { - let ret_val: int16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) +pub fn vreinterpret_s16_s64(a: int64x1_t) -> int16x4_t { + unsafe { + let ret_val: int16x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -43992,13 +41852,11 @@ pub unsafe fn vreinterpret_s16_s64(a: int64x1_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s32_s64(a: int64x1_t) -> int32x2_t { - transmute(a) +pub fn vreinterpret_s32_s64(a: int64x1_t) -> int32x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -44016,14 +41874,14 @@ pub unsafe fn vreinterpret_s32_s64(a: int64x1_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s32_s64(a: int64x1_t) -> int32x2_t { - let ret_val: int32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) +pub fn vreinterpret_s32_s64(a: int64x1_t) -> int32x2_t { + unsafe { + let ret_val: int32x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -44041,13 +41899,11 @@ pub unsafe fn vreinterpret_s32_s64(a: int64x1_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u8_s64(a: int64x1_t) -> uint8x8_t { - transmute(a) +pub fn vreinterpret_u8_s64(a: int64x1_t) -> uint8x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -44065,14 +41921,14 @@ pub unsafe fn vreinterpret_u8_s64(a: int64x1_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u8_s64(a: int64x1_t) -> uint8x8_t { - let ret_val: uint8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) +pub fn vreinterpret_u8_s64(a: int64x1_t) -> uint8x8_t { + unsafe { + let ret_val: uint8x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -44090,13 +41946,11 @@ pub unsafe fn vreinterpret_u8_s64(a: int64x1_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u16_s64(a: int64x1_t) -> uint16x4_t { - transmute(a) +pub fn vreinterpret_u16_s64(a: int64x1_t) -> uint16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -44114,14 +41968,14 @@ pub unsafe fn vreinterpret_u16_s64(a: int64x1_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u16_s64(a: int64x1_t) -> uint16x4_t { - let ret_val: uint16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) +pub fn vreinterpret_u16_s64(a: int64x1_t) -> uint16x4_t { + unsafe { + let ret_val: uint16x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -44139,13 +41993,11 @@ pub unsafe fn vreinterpret_u16_s64(a: int64x1_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u32_s64(a: int64x1_t) -> uint32x2_t { - transmute(a) +pub fn vreinterpret_u32_s64(a: int64x1_t) -> uint32x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -44163,14 +42015,14 @@ pub unsafe fn vreinterpret_u32_s64(a: int64x1_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u32_s64(a: int64x1_t) -> uint32x2_t { - let ret_val: uint32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) +pub fn vreinterpret_u32_s64(a: int64x1_t) -> uint32x2_t { + unsafe { + let ret_val: uint32x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -44187,13 +42039,11 @@ pub unsafe fn vreinterpret_u32_s64(a: int64x1_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u64_s64(a: int64x1_t) -> uint64x1_t { - transmute(a) +pub fn vreinterpret_u64_s64(a: int64x1_t) -> uint64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -44211,13 +42061,11 @@ pub unsafe fn vreinterpret_u64_s64(a: int64x1_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_p8_s64(a: int64x1_t) -> poly8x8_t { - transmute(a) +pub fn vreinterpret_p8_s64(a: int64x1_t) -> poly8x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -44235,14 +42083,14 @@ pub unsafe fn vreinterpret_p8_s64(a: int64x1_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_p8_s64(a: int64x1_t) -> poly8x8_t { - let ret_val: poly8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) +pub fn vreinterpret_p8_s64(a: int64x1_t) -> poly8x8_t { + unsafe { + let ret_val: poly8x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -44260,13 +42108,11 @@ pub unsafe fn vreinterpret_p8_s64(a: int64x1_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_p16_s64(a: int64x1_t) -> poly16x4_t { - transmute(a) +pub fn vreinterpret_p16_s64(a: int64x1_t) -> poly16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -44284,14 +42130,14 @@ pub unsafe fn vreinterpret_p16_s64(a: int64x1_t) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_p16_s64(a: int64x1_t) -> poly16x4_t { - let ret_val: poly16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) +pub fn vreinterpret_p16_s64(a: int64x1_t) -> poly16x4_t { + unsafe { + let ret_val: poly16x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -44309,13 +42155,11 @@ pub unsafe fn vreinterpret_p16_s64(a: int64x1_t) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_f32_s64(a: int64x2_t) -> float32x4_t { - transmute(a) +pub fn vreinterpretq_f32_s64(a: int64x2_t) -> float32x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -44333,15 +42177,15 @@ pub unsafe fn vreinterpretq_f32_s64(a: int64x2_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_f32_s64(a: int64x2_t) -> float32x4_t { +pub fn vreinterpretq_f32_s64(a: int64x2_t) -> float32x4_t { let a: int64x2_t = simd_shuffle!(a, a, [1, 0]); - let ret_val: float32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + unsafe { + let ret_val: float32x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -44359,13 +42203,11 @@ pub unsafe fn vreinterpretq_f32_s64(a: int64x2_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s8_s64(a: int64x2_t) -> int8x16_t { - transmute(a) +pub fn vreinterpretq_s8_s64(a: int64x2_t) -> int8x16_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -44383,19 +42225,19 @@ pub unsafe fn vreinterpretq_s8_s64(a: int64x2_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s8_s64(a: int64x2_t) -> int8x16_t { +pub fn vreinterpretq_s8_s64(a: int64x2_t) -> int8x16_t { let a: int64x2_t = simd_shuffle!(a, a, [1, 0]); - let ret_val: int8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) + unsafe { + let ret_val: int8x16_t = transmute(a); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -44413,13 +42255,11 @@ pub unsafe fn vreinterpretq_s8_s64(a: int64x2_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s16_s64(a: int64x2_t) -> int16x8_t { - transmute(a) +pub fn vreinterpretq_s16_s64(a: int64x2_t) -> int16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -44437,15 +42277,15 @@ pub unsafe fn vreinterpretq_s16_s64(a: int64x2_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s16_s64(a: int64x2_t) -> int16x8_t { +pub fn vreinterpretq_s16_s64(a: int64x2_t) -> int16x8_t { let a: int64x2_t = simd_shuffle!(a, a, [1, 0]); - let ret_val: int16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: int16x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -44463,13 +42303,11 @@ pub unsafe fn vreinterpretq_s16_s64(a: int64x2_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s32_s64(a: int64x2_t) -> int32x4_t { - transmute(a) +pub fn vreinterpretq_s32_s64(a: int64x2_t) -> int32x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -44487,15 +42325,15 @@ pub unsafe fn vreinterpretq_s32_s64(a: int64x2_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s32_s64(a: int64x2_t) -> int32x4_t { +pub fn vreinterpretq_s32_s64(a: int64x2_t) -> int32x4_t { let a: int64x2_t = simd_shuffle!(a, a, [1, 0]); - let ret_val: int32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + unsafe { + let ret_val: int32x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -44513,13 +42351,11 @@ pub unsafe fn vreinterpretq_s32_s64(a: int64x2_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u8_s64(a: int64x2_t) -> uint8x16_t { - transmute(a) +pub fn vreinterpretq_u8_s64(a: int64x2_t) -> uint8x16_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -44537,19 +42373,19 @@ pub unsafe fn vreinterpretq_u8_s64(a: int64x2_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u8_s64(a: int64x2_t) -> uint8x16_t { +pub fn vreinterpretq_u8_s64(a: int64x2_t) -> uint8x16_t { let a: int64x2_t = simd_shuffle!(a, a, [1, 0]); - let ret_val: uint8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) + unsafe { + let ret_val: uint8x16_t = transmute(a); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -44567,13 +42403,11 @@ pub unsafe fn vreinterpretq_u8_s64(a: int64x2_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u16_s64(a: int64x2_t) -> uint16x8_t { - transmute(a) +pub fn vreinterpretq_u16_s64(a: int64x2_t) -> uint16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -44591,15 +42425,15 @@ pub unsafe fn vreinterpretq_u16_s64(a: int64x2_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u16_s64(a: int64x2_t) -> uint16x8_t { +pub fn vreinterpretq_u16_s64(a: int64x2_t) -> uint16x8_t { let a: int64x2_t = simd_shuffle!(a, a, [1, 0]); - let ret_val: uint16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: uint16x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -44617,13 +42451,11 @@ pub unsafe fn vreinterpretq_u16_s64(a: int64x2_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u32_s64(a: int64x2_t) -> uint32x4_t { - transmute(a) +pub fn vreinterpretq_u32_s64(a: int64x2_t) -> uint32x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -44641,15 +42473,15 @@ pub unsafe fn vreinterpretq_u32_s64(a: int64x2_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u32_s64(a: int64x2_t) -> uint32x4_t { +pub fn vreinterpretq_u32_s64(a: int64x2_t) -> uint32x4_t { let a: int64x2_t = simd_shuffle!(a, a, [1, 0]); - let ret_val: uint32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + unsafe { + let ret_val: uint32x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -44667,13 +42499,11 @@ pub unsafe fn vreinterpretq_u32_s64(a: int64x2_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u64_s64(a: int64x2_t) -> uint64x2_t { - transmute(a) +pub fn vreinterpretq_u64_s64(a: int64x2_t) -> uint64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -44691,15 +42521,15 @@ pub unsafe fn vreinterpretq_u64_s64(a: int64x2_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u64_s64(a: int64x2_t) -> uint64x2_t { +pub fn vreinterpretq_u64_s64(a: int64x2_t) -> uint64x2_t { let a: int64x2_t = simd_shuffle!(a, a, [1, 0]); - let ret_val: uint64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: uint64x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -44717,13 +42547,11 @@ pub unsafe fn vreinterpretq_u64_s64(a: int64x2_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p8_s64(a: int64x2_t) -> poly8x16_t { - transmute(a) +pub fn vreinterpretq_p8_s64(a: int64x2_t) -> poly8x16_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -44741,19 +42569,19 @@ pub unsafe fn vreinterpretq_p8_s64(a: int64x2_t) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p8_s64(a: int64x2_t) -> poly8x16_t { +pub fn vreinterpretq_p8_s64(a: int64x2_t) -> poly8x16_t { let a: int64x2_t = simd_shuffle!(a, a, [1, 0]); - let ret_val: poly8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) + unsafe { + let ret_val: poly8x16_t = transmute(a); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -44771,13 +42599,11 @@ pub unsafe fn vreinterpretq_p8_s64(a: int64x2_t) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p16_s64(a: int64x2_t) -> poly16x8_t { - transmute(a) +pub fn vreinterpretq_p16_s64(a: int64x2_t) -> poly16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -44795,15 +42621,15 @@ pub unsafe fn vreinterpretq_p16_s64(a: int64x2_t) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p16_s64(a: int64x2_t) -> poly16x8_t { +pub fn vreinterpretq_p16_s64(a: int64x2_t) -> poly16x8_t { let a: int64x2_t = simd_shuffle!(a, a, [1, 0]); - let ret_val: poly16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: poly16x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -44821,13 +42647,11 @@ pub unsafe fn vreinterpretq_p16_s64(a: int64x2_t) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_f32_u8(a: uint8x8_t) -> float32x2_t { - transmute(a) +pub fn vreinterpret_f32_u8(a: uint8x8_t) -> float32x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -44845,15 +42669,15 @@ pub unsafe fn vreinterpret_f32_u8(a: uint8x8_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_f32_u8(a: uint8x8_t) -> float32x2_t { +pub fn vreinterpret_f32_u8(a: uint8x8_t) -> float32x2_t { let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: float32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: float32x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -44871,13 +42695,11 @@ pub unsafe fn vreinterpret_f32_u8(a: uint8x8_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s8_u8(a: uint8x8_t) -> int8x8_t { - transmute(a) +pub fn vreinterpret_s8_u8(a: uint8x8_t) -> int8x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -44895,15 +42717,15 @@ pub unsafe fn vreinterpret_s8_u8(a: uint8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s8_u8(a: uint8x8_t) -> int8x8_t { +pub fn vreinterpret_s8_u8(a: uint8x8_t) -> int8x8_t { let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: int8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: int8x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -44921,13 +42743,11 @@ pub unsafe fn vreinterpret_s8_u8(a: uint8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s16_u8(a: uint8x8_t) -> int16x4_t { - transmute(a) +pub fn vreinterpret_s16_u8(a: uint8x8_t) -> int16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -44945,15 +42765,15 @@ pub unsafe fn vreinterpret_s16_u8(a: uint8x8_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s16_u8(a: uint8x8_t) -> int16x4_t { +pub fn vreinterpret_s16_u8(a: uint8x8_t) -> int16x4_t { let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: int16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + unsafe { + let ret_val: int16x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -44971,13 +42791,11 @@ pub unsafe fn vreinterpret_s16_u8(a: uint8x8_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s32_u8(a: uint8x8_t) -> int32x2_t { - transmute(a) +pub fn vreinterpret_s32_u8(a: uint8x8_t) -> int32x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -44995,15 +42813,15 @@ pub unsafe fn vreinterpret_s32_u8(a: uint8x8_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s32_u8(a: uint8x8_t) -> int32x2_t { +pub fn vreinterpret_s32_u8(a: uint8x8_t) -> int32x2_t { let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: int32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: int32x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -45021,13 +42839,11 @@ pub unsafe fn vreinterpret_s32_u8(a: uint8x8_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s64_u8(a: uint8x8_t) -> int64x1_t { - transmute(a) +pub fn vreinterpret_s64_u8(a: uint8x8_t) -> int64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -45045,14 +42861,12 @@ pub unsafe fn vreinterpret_s64_u8(a: uint8x8_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s64_u8(a: uint8x8_t) -> int64x1_t { +pub fn vreinterpret_s64_u8(a: uint8x8_t) -> int64x1_t { let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - transmute(a) + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -45070,13 +42884,11 @@ pub unsafe fn vreinterpret_s64_u8(a: uint8x8_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u16_u8(a: uint8x8_t) -> uint16x4_t { - transmute(a) +pub fn vreinterpret_u16_u8(a: uint8x8_t) -> uint16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -45094,15 +42906,15 @@ pub unsafe fn vreinterpret_u16_u8(a: uint8x8_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u16_u8(a: uint8x8_t) -> uint16x4_t { +pub fn vreinterpret_u16_u8(a: uint8x8_t) -> uint16x4_t { let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: uint16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + unsafe { + let ret_val: uint16x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -45120,13 +42932,11 @@ pub unsafe fn vreinterpret_u16_u8(a: uint8x8_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u32_u8(a: uint8x8_t) -> uint32x2_t { - transmute(a) +pub fn vreinterpret_u32_u8(a: uint8x8_t) -> uint32x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -45144,15 +42954,15 @@ pub unsafe fn vreinterpret_u32_u8(a: uint8x8_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u32_u8(a: uint8x8_t) -> uint32x2_t { +pub fn vreinterpret_u32_u8(a: uint8x8_t) -> uint32x2_t { let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: uint32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: uint32x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -45170,13 +42980,11 @@ pub unsafe fn vreinterpret_u32_u8(a: uint8x8_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u64_u8(a: uint8x8_t) -> uint64x1_t { - transmute(a) +pub fn vreinterpret_u64_u8(a: uint8x8_t) -> uint64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -45194,14 +43002,12 @@ pub unsafe fn vreinterpret_u64_u8(a: uint8x8_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u64_u8(a: uint8x8_t) -> uint64x1_t { +pub fn vreinterpret_u64_u8(a: uint8x8_t) -> uint64x1_t { let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - transmute(a) + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -45219,13 +43025,11 @@ pub unsafe fn vreinterpret_u64_u8(a: uint8x8_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_p8_u8(a: uint8x8_t) -> poly8x8_t { - transmute(a) +pub fn vreinterpret_p8_u8(a: uint8x8_t) -> poly8x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -45243,15 +43047,15 @@ pub unsafe fn vreinterpret_p8_u8(a: uint8x8_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_p8_u8(a: uint8x8_t) -> poly8x8_t { +pub fn vreinterpret_p8_u8(a: uint8x8_t) -> poly8x8_t { let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: poly8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: poly8x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -45269,13 +43073,11 @@ pub unsafe fn vreinterpret_p8_u8(a: uint8x8_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_p16_u8(a: uint8x8_t) -> poly16x4_t { - transmute(a) +pub fn vreinterpret_p16_u8(a: uint8x8_t) -> poly16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -45293,15 +43095,15 @@ pub unsafe fn vreinterpret_p16_u8(a: uint8x8_t) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_p16_u8(a: uint8x8_t) -> poly16x4_t { +pub fn vreinterpret_p16_u8(a: uint8x8_t) -> poly16x4_t { let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: poly16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + unsafe { + let ret_val: poly16x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -45319,13 +43121,11 @@ pub unsafe fn vreinterpret_p16_u8(a: uint8x8_t) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_f32_u8(a: uint8x16_t) -> float32x4_t { - transmute(a) +pub fn vreinterpretq_f32_u8(a: uint8x16_t) -> float32x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -45343,15 +43143,15 @@ pub unsafe fn vreinterpretq_f32_u8(a: uint8x16_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_f32_u8(a: uint8x16_t) -> float32x4_t { +pub fn vreinterpretq_f32_u8(a: uint8x16_t) -> float32x4_t { let a: uint8x16_t = simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: float32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + unsafe { + let ret_val: float32x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -45369,13 +43169,11 @@ pub unsafe fn vreinterpretq_f32_u8(a: uint8x16_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s8_u8(a: uint8x16_t) -> int8x16_t { - transmute(a) +pub fn vreinterpretq_s8_u8(a: uint8x16_t) -> int8x16_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -45393,19 +43191,19 @@ pub unsafe fn vreinterpretq_s8_u8(a: uint8x16_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s8_u8(a: uint8x16_t) -> int8x16_t { +pub fn vreinterpretq_s8_u8(a: uint8x16_t) -> int8x16_t { let a: uint8x16_t = simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: int8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) + unsafe { + let ret_val: int8x16_t = transmute(a); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -45423,13 +43221,11 @@ pub unsafe fn vreinterpretq_s8_u8(a: uint8x16_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s16_u8(a: uint8x16_t) -> int16x8_t { - transmute(a) +pub fn vreinterpretq_s16_u8(a: uint8x16_t) -> int16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -45447,15 +43243,15 @@ pub unsafe fn vreinterpretq_s16_u8(a: uint8x16_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s16_u8(a: uint8x16_t) -> int16x8_t { +pub fn vreinterpretq_s16_u8(a: uint8x16_t) -> int16x8_t { let a: uint8x16_t = simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: int16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: int16x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -45473,13 +43269,11 @@ pub unsafe fn vreinterpretq_s16_u8(a: uint8x16_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s32_u8(a: uint8x16_t) -> int32x4_t { - transmute(a) +pub fn vreinterpretq_s32_u8(a: uint8x16_t) -> int32x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -45497,15 +43291,15 @@ pub unsafe fn vreinterpretq_s32_u8(a: uint8x16_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s32_u8(a: uint8x16_t) -> int32x4_t { +pub fn vreinterpretq_s32_u8(a: uint8x16_t) -> int32x4_t { let a: uint8x16_t = simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: int32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + unsafe { + let ret_val: int32x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -45523,13 +43317,11 @@ pub unsafe fn vreinterpretq_s32_u8(a: uint8x16_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s64_u8(a: uint8x16_t) -> int64x2_t { - transmute(a) +pub fn vreinterpretq_s64_u8(a: uint8x16_t) -> int64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -45547,15 +43339,15 @@ pub unsafe fn vreinterpretq_s64_u8(a: uint8x16_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s64_u8(a: uint8x16_t) -> int64x2_t { +pub fn vreinterpretq_s64_u8(a: uint8x16_t) -> int64x2_t { let a: uint8x16_t = simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: int64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: int64x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -45573,13 +43365,11 @@ pub unsafe fn vreinterpretq_s64_u8(a: uint8x16_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u16_u8(a: uint8x16_t) -> uint16x8_t { - transmute(a) +pub fn vreinterpretq_u16_u8(a: uint8x16_t) -> uint16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -45597,15 +43387,15 @@ pub unsafe fn vreinterpretq_u16_u8(a: uint8x16_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u16_u8(a: uint8x16_t) -> uint16x8_t { +pub fn vreinterpretq_u16_u8(a: uint8x16_t) -> uint16x8_t { let a: uint8x16_t = simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: uint16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: uint16x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -45623,13 +43413,11 @@ pub unsafe fn vreinterpretq_u16_u8(a: uint8x16_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u32_u8(a: uint8x16_t) -> uint32x4_t { - transmute(a) +pub fn vreinterpretq_u32_u8(a: uint8x16_t) -> uint32x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -45647,15 +43435,15 @@ pub unsafe fn vreinterpretq_u32_u8(a: uint8x16_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u32_u8(a: uint8x16_t) -> uint32x4_t { +pub fn vreinterpretq_u32_u8(a: uint8x16_t) -> uint32x4_t { let a: uint8x16_t = simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: uint32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + unsafe { + let ret_val: uint32x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -45673,13 +43461,11 @@ pub unsafe fn vreinterpretq_u32_u8(a: uint8x16_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u64_u8(a: uint8x16_t) -> uint64x2_t { - transmute(a) +pub fn vreinterpretq_u64_u8(a: uint8x16_t) -> uint64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -45697,15 +43483,15 @@ pub unsafe fn vreinterpretq_u64_u8(a: uint8x16_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u64_u8(a: uint8x16_t) -> uint64x2_t { +pub fn vreinterpretq_u64_u8(a: uint8x16_t) -> uint64x2_t { let a: uint8x16_t = simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: uint64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: uint64x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -45723,13 +43509,11 @@ pub unsafe fn vreinterpretq_u64_u8(a: uint8x16_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p8_u8(a: uint8x16_t) -> poly8x16_t { - transmute(a) +pub fn vreinterpretq_p8_u8(a: uint8x16_t) -> poly8x16_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -45747,19 +43531,19 @@ pub unsafe fn vreinterpretq_p8_u8(a: uint8x16_t) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p8_u8(a: uint8x16_t) -> poly8x16_t { +pub fn vreinterpretq_p8_u8(a: uint8x16_t) -> poly8x16_t { let a: uint8x16_t = simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: poly8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) + unsafe { + let ret_val: poly8x16_t = transmute(a); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -45777,13 +43561,11 @@ pub unsafe fn vreinterpretq_p8_u8(a: uint8x16_t) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p16_u8(a: uint8x16_t) -> poly16x8_t { - transmute(a) +pub fn vreinterpretq_p16_u8(a: uint8x16_t) -> poly16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -45801,15 +43583,15 @@ pub unsafe fn vreinterpretq_p16_u8(a: uint8x16_t) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p16_u8(a: uint8x16_t) -> poly16x8_t { +pub fn vreinterpretq_p16_u8(a: uint8x16_t) -> poly16x8_t { let a: uint8x16_t = simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: poly16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: poly16x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -45827,13 +43609,11 @@ pub unsafe fn vreinterpretq_p16_u8(a: uint8x16_t) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_f32_u16(a: uint16x4_t) -> float32x2_t { - transmute(a) +pub fn vreinterpret_f32_u16(a: uint16x4_t) -> float32x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -45851,15 +43631,15 @@ pub unsafe fn vreinterpret_f32_u16(a: uint16x4_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_f32_u16(a: uint16x4_t) -> float32x2_t { +pub fn vreinterpret_f32_u16(a: uint16x4_t) -> float32x2_t { let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - let ret_val: float32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: float32x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -45877,13 +43657,11 @@ pub unsafe fn vreinterpret_f32_u16(a: uint16x4_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s8_u16(a: uint16x4_t) -> int8x8_t { - transmute(a) +pub fn vreinterpret_s8_u16(a: uint16x4_t) -> int8x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -45901,15 +43679,15 @@ pub unsafe fn vreinterpret_s8_u16(a: uint16x4_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s8_u16(a: uint16x4_t) -> int8x8_t { +pub fn vreinterpret_s8_u16(a: uint16x4_t) -> int8x8_t { let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - let ret_val: int8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: int8x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -45927,13 +43705,11 @@ pub unsafe fn vreinterpret_s8_u16(a: uint16x4_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s16_u16(a: uint16x4_t) -> int16x4_t { - transmute(a) +pub fn vreinterpret_s16_u16(a: uint16x4_t) -> int16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -45951,15 +43727,15 @@ pub unsafe fn vreinterpret_s16_u16(a: uint16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s16_u16(a: uint16x4_t) -> int16x4_t { +pub fn vreinterpret_s16_u16(a: uint16x4_t) -> int16x4_t { let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - let ret_val: int16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + unsafe { + let ret_val: int16x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -45977,13 +43753,11 @@ pub unsafe fn vreinterpret_s16_u16(a: uint16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s32_u16(a: uint16x4_t) -> int32x2_t { - transmute(a) +pub fn vreinterpret_s32_u16(a: uint16x4_t) -> int32x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -46001,15 +43775,15 @@ pub unsafe fn vreinterpret_s32_u16(a: uint16x4_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s32_u16(a: uint16x4_t) -> int32x2_t { +pub fn vreinterpret_s32_u16(a: uint16x4_t) -> int32x2_t { let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - let ret_val: int32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: int32x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -46027,13 +43801,11 @@ pub unsafe fn vreinterpret_s32_u16(a: uint16x4_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s64_u16(a: uint16x4_t) -> int64x1_t { - transmute(a) +pub fn vreinterpret_s64_u16(a: uint16x4_t) -> int64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -46051,14 +43823,12 @@ pub unsafe fn vreinterpret_s64_u16(a: uint16x4_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s64_u16(a: uint16x4_t) -> int64x1_t { +pub fn vreinterpret_s64_u16(a: uint16x4_t) -> int64x1_t { let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - transmute(a) + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -46076,13 +43846,11 @@ pub unsafe fn vreinterpret_s64_u16(a: uint16x4_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u8_u16(a: uint16x4_t) -> uint8x8_t { - transmute(a) +pub fn vreinterpret_u8_u16(a: uint16x4_t) -> uint8x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -46100,15 +43868,15 @@ pub unsafe fn vreinterpret_u8_u16(a: uint16x4_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u8_u16(a: uint16x4_t) -> uint8x8_t { +pub fn vreinterpret_u8_u16(a: uint16x4_t) -> uint8x8_t { let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - let ret_val: uint8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: uint8x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -46126,13 +43894,11 @@ pub unsafe fn vreinterpret_u8_u16(a: uint16x4_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u32_u16(a: uint16x4_t) -> uint32x2_t { - transmute(a) +pub fn vreinterpret_u32_u16(a: uint16x4_t) -> uint32x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -46150,15 +43916,15 @@ pub unsafe fn vreinterpret_u32_u16(a: uint16x4_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u32_u16(a: uint16x4_t) -> uint32x2_t { +pub fn vreinterpret_u32_u16(a: uint16x4_t) -> uint32x2_t { let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - let ret_val: uint32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: uint32x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -46176,13 +43942,11 @@ pub unsafe fn vreinterpret_u32_u16(a: uint16x4_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u64_u16(a: uint16x4_t) -> uint64x1_t { - transmute(a) +pub fn vreinterpret_u64_u16(a: uint16x4_t) -> uint64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -46200,14 +43964,12 @@ pub unsafe fn vreinterpret_u64_u16(a: uint16x4_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u64_u16(a: uint16x4_t) -> uint64x1_t { +pub fn vreinterpret_u64_u16(a: uint16x4_t) -> uint64x1_t { let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - transmute(a) + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -46225,13 +43987,11 @@ pub unsafe fn vreinterpret_u64_u16(a: uint16x4_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_p8_u16(a: uint16x4_t) -> poly8x8_t { - transmute(a) +pub fn vreinterpret_p8_u16(a: uint16x4_t) -> poly8x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -46249,15 +44009,15 @@ pub unsafe fn vreinterpret_p8_u16(a: uint16x4_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_p8_u16(a: uint16x4_t) -> poly8x8_t { +pub fn vreinterpret_p8_u16(a: uint16x4_t) -> poly8x8_t { let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - let ret_val: poly8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: poly8x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -46275,13 +44035,11 @@ pub unsafe fn vreinterpret_p8_u16(a: uint16x4_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_p16_u16(a: uint16x4_t) -> poly16x4_t { - transmute(a) +pub fn vreinterpret_p16_u16(a: uint16x4_t) -> poly16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -46299,15 +44057,15 @@ pub unsafe fn vreinterpret_p16_u16(a: uint16x4_t) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_p16_u16(a: uint16x4_t) -> poly16x4_t { +pub fn vreinterpret_p16_u16(a: uint16x4_t) -> poly16x4_t { let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - let ret_val: poly16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + unsafe { + let ret_val: poly16x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -46325,13 +44083,11 @@ pub unsafe fn vreinterpret_p16_u16(a: uint16x4_t) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_f32_u16(a: uint16x8_t) -> float32x4_t { - transmute(a) +pub fn vreinterpretq_f32_u16(a: uint16x8_t) -> float32x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -46349,15 +44105,15 @@ pub unsafe fn vreinterpretq_f32_u16(a: uint16x8_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_f32_u16(a: uint16x8_t) -> float32x4_t { +pub fn vreinterpretq_f32_u16(a: uint16x8_t) -> float32x4_t { let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: float32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + unsafe { + let ret_val: float32x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -46375,13 +44131,11 @@ pub unsafe fn vreinterpretq_f32_u16(a: uint16x8_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s8_u16(a: uint16x8_t) -> int8x16_t { - transmute(a) +pub fn vreinterpretq_s8_u16(a: uint16x8_t) -> int8x16_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -46399,19 +44153,19 @@ pub unsafe fn vreinterpretq_s8_u16(a: uint16x8_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s8_u16(a: uint16x8_t) -> int8x16_t { +pub fn vreinterpretq_s8_u16(a: uint16x8_t) -> int8x16_t { let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: int8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) + unsafe { + let ret_val: int8x16_t = transmute(a); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -46429,13 +44183,11 @@ pub unsafe fn vreinterpretq_s8_u16(a: uint16x8_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s16_u16(a: uint16x8_t) -> int16x8_t { - transmute(a) +pub fn vreinterpretq_s16_u16(a: uint16x8_t) -> int16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -46453,15 +44205,15 @@ pub unsafe fn vreinterpretq_s16_u16(a: uint16x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s16_u16(a: uint16x8_t) -> int16x8_t { +pub fn vreinterpretq_s16_u16(a: uint16x8_t) -> int16x8_t { let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: int16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: int16x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -46479,13 +44231,11 @@ pub unsafe fn vreinterpretq_s16_u16(a: uint16x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s32_u16(a: uint16x8_t) -> int32x4_t { - transmute(a) +pub fn vreinterpretq_s32_u16(a: uint16x8_t) -> int32x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -46503,15 +44253,15 @@ pub unsafe fn vreinterpretq_s32_u16(a: uint16x8_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s32_u16(a: uint16x8_t) -> int32x4_t { +pub fn vreinterpretq_s32_u16(a: uint16x8_t) -> int32x4_t { let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: int32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + unsafe { + let ret_val: int32x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -46529,13 +44279,11 @@ pub unsafe fn vreinterpretq_s32_u16(a: uint16x8_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s64_u16(a: uint16x8_t) -> int64x2_t { - transmute(a) +pub fn vreinterpretq_s64_u16(a: uint16x8_t) -> int64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -46553,15 +44301,15 @@ pub unsafe fn vreinterpretq_s64_u16(a: uint16x8_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s64_u16(a: uint16x8_t) -> int64x2_t { +pub fn vreinterpretq_s64_u16(a: uint16x8_t) -> int64x2_t { let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: int64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: int64x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -46579,13 +44327,11 @@ pub unsafe fn vreinterpretq_s64_u16(a: uint16x8_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u8_u16(a: uint16x8_t) -> uint8x16_t { - transmute(a) +pub fn vreinterpretq_u8_u16(a: uint16x8_t) -> uint8x16_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -46603,19 +44349,19 @@ pub unsafe fn vreinterpretq_u8_u16(a: uint16x8_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u8_u16(a: uint16x8_t) -> uint8x16_t { +pub fn vreinterpretq_u8_u16(a: uint16x8_t) -> uint8x16_t { let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: uint8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) + unsafe { + let ret_val: uint8x16_t = transmute(a); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -46633,13 +44379,11 @@ pub unsafe fn vreinterpretq_u8_u16(a: uint16x8_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u32_u16(a: uint16x8_t) -> uint32x4_t { - transmute(a) +pub fn vreinterpretq_u32_u16(a: uint16x8_t) -> uint32x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -46657,15 +44401,15 @@ pub unsafe fn vreinterpretq_u32_u16(a: uint16x8_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u32_u16(a: uint16x8_t) -> uint32x4_t { +pub fn vreinterpretq_u32_u16(a: uint16x8_t) -> uint32x4_t { let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: uint32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + unsafe { + let ret_val: uint32x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -46683,13 +44427,11 @@ pub unsafe fn vreinterpretq_u32_u16(a: uint16x8_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u64_u16(a: uint16x8_t) -> uint64x2_t { - transmute(a) +pub fn vreinterpretq_u64_u16(a: uint16x8_t) -> uint64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -46707,15 +44449,15 @@ pub unsafe fn vreinterpretq_u64_u16(a: uint16x8_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u64_u16(a: uint16x8_t) -> uint64x2_t { +pub fn vreinterpretq_u64_u16(a: uint16x8_t) -> uint64x2_t { let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: uint64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: uint64x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -46733,13 +44475,11 @@ pub unsafe fn vreinterpretq_u64_u16(a: uint16x8_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p8_u16(a: uint16x8_t) -> poly8x16_t { - transmute(a) +pub fn vreinterpretq_p8_u16(a: uint16x8_t) -> poly8x16_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -46757,19 +44497,19 @@ pub unsafe fn vreinterpretq_p8_u16(a: uint16x8_t) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p8_u16(a: uint16x8_t) -> poly8x16_t { +pub fn vreinterpretq_p8_u16(a: uint16x8_t) -> poly8x16_t { let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: poly8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) + unsafe { + let ret_val: poly8x16_t = transmute(a); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -46787,13 +44527,11 @@ pub unsafe fn vreinterpretq_p8_u16(a: uint16x8_t) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p16_u16(a: uint16x8_t) -> poly16x8_t { - transmute(a) +pub fn vreinterpretq_p16_u16(a: uint16x8_t) -> poly16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -46811,15 +44549,15 @@ pub unsafe fn vreinterpretq_p16_u16(a: uint16x8_t) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p16_u16(a: uint16x8_t) -> poly16x8_t { +pub fn vreinterpretq_p16_u16(a: uint16x8_t) -> poly16x8_t { let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: poly16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: poly16x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -46837,13 +44575,11 @@ pub unsafe fn vreinterpretq_p16_u16(a: uint16x8_t) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_f32_u32(a: uint32x2_t) -> float32x2_t { - transmute(a) +pub fn vreinterpret_f32_u32(a: uint32x2_t) -> float32x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -46861,15 +44597,15 @@ pub unsafe fn vreinterpret_f32_u32(a: uint32x2_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_f32_u32(a: uint32x2_t) -> float32x2_t { +pub fn vreinterpret_f32_u32(a: uint32x2_t) -> float32x2_t { let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]); - let ret_val: float32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: float32x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -46887,13 +44623,11 @@ pub unsafe fn vreinterpret_f32_u32(a: uint32x2_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s8_u32(a: uint32x2_t) -> int8x8_t { - transmute(a) +pub fn vreinterpret_s8_u32(a: uint32x2_t) -> int8x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -46911,15 +44645,15 @@ pub unsafe fn vreinterpret_s8_u32(a: uint32x2_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s8_u32(a: uint32x2_t) -> int8x8_t { +pub fn vreinterpret_s8_u32(a: uint32x2_t) -> int8x8_t { let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]); - let ret_val: int8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: int8x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -46937,13 +44671,11 @@ pub unsafe fn vreinterpret_s8_u32(a: uint32x2_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s16_u32(a: uint32x2_t) -> int16x4_t { - transmute(a) +pub fn vreinterpret_s16_u32(a: uint32x2_t) -> int16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -46961,15 +44693,15 @@ pub unsafe fn vreinterpret_s16_u32(a: uint32x2_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s16_u32(a: uint32x2_t) -> int16x4_t { +pub fn vreinterpret_s16_u32(a: uint32x2_t) -> int16x4_t { let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]); - let ret_val: int16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + unsafe { + let ret_val: int16x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -46987,13 +44719,11 @@ pub unsafe fn vreinterpret_s16_u32(a: uint32x2_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s32_u32(a: uint32x2_t) -> int32x2_t { - transmute(a) +pub fn vreinterpret_s32_u32(a: uint32x2_t) -> int32x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -47011,15 +44741,15 @@ pub unsafe fn vreinterpret_s32_u32(a: uint32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s32_u32(a: uint32x2_t) -> int32x2_t { +pub fn vreinterpret_s32_u32(a: uint32x2_t) -> int32x2_t { let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]); - let ret_val: int32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: int32x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -47037,13 +44767,11 @@ pub unsafe fn vreinterpret_s32_u32(a: uint32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s64_u32(a: uint32x2_t) -> int64x1_t { - transmute(a) +pub fn vreinterpret_s64_u32(a: uint32x2_t) -> int64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -47061,14 +44789,12 @@ pub unsafe fn vreinterpret_s64_u32(a: uint32x2_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s64_u32(a: uint32x2_t) -> int64x1_t { +pub fn vreinterpret_s64_u32(a: uint32x2_t) -> int64x1_t { let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]); - transmute(a) + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -47086,13 +44812,11 @@ pub unsafe fn vreinterpret_s64_u32(a: uint32x2_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u8_u32(a: uint32x2_t) -> uint8x8_t { - transmute(a) +pub fn vreinterpret_u8_u32(a: uint32x2_t) -> uint8x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -47110,15 +44834,15 @@ pub unsafe fn vreinterpret_u8_u32(a: uint32x2_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u8_u32(a: uint32x2_t) -> uint8x8_t { +pub fn vreinterpret_u8_u32(a: uint32x2_t) -> uint8x8_t { let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]); - let ret_val: uint8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: uint8x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -47136,13 +44860,11 @@ pub unsafe fn vreinterpret_u8_u32(a: uint32x2_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u16_u32(a: uint32x2_t) -> uint16x4_t { - transmute(a) +pub fn vreinterpret_u16_u32(a: uint32x2_t) -> uint16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -47160,15 +44882,15 @@ pub unsafe fn vreinterpret_u16_u32(a: uint32x2_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u16_u32(a: uint32x2_t) -> uint16x4_t { +pub fn vreinterpret_u16_u32(a: uint32x2_t) -> uint16x4_t { let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]); - let ret_val: uint16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + unsafe { + let ret_val: uint16x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -47186,13 +44908,11 @@ pub unsafe fn vreinterpret_u16_u32(a: uint32x2_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u64_u32(a: uint32x2_t) -> uint64x1_t { - transmute(a) +pub fn vreinterpret_u64_u32(a: uint32x2_t) -> uint64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -47210,14 +44930,12 @@ pub unsafe fn vreinterpret_u64_u32(a: uint32x2_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u64_u32(a: uint32x2_t) -> uint64x1_t { +pub fn vreinterpret_u64_u32(a: uint32x2_t) -> uint64x1_t { let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]); - transmute(a) + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -47235,13 +44953,11 @@ pub unsafe fn vreinterpret_u64_u32(a: uint32x2_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_p8_u32(a: uint32x2_t) -> poly8x8_t { - transmute(a) +pub fn vreinterpret_p8_u32(a: uint32x2_t) -> poly8x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -47259,15 +44975,15 @@ pub unsafe fn vreinterpret_p8_u32(a: uint32x2_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_p8_u32(a: uint32x2_t) -> poly8x8_t { +pub fn vreinterpret_p8_u32(a: uint32x2_t) -> poly8x8_t { let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]); - let ret_val: poly8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: poly8x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -47285,13 +45001,11 @@ pub unsafe fn vreinterpret_p8_u32(a: uint32x2_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_p16_u32(a: uint32x2_t) -> poly16x4_t { - transmute(a) +pub fn vreinterpret_p16_u32(a: uint32x2_t) -> poly16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -47309,15 +45023,15 @@ pub unsafe fn vreinterpret_p16_u32(a: uint32x2_t) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_p16_u32(a: uint32x2_t) -> poly16x4_t { +pub fn vreinterpret_p16_u32(a: uint32x2_t) -> poly16x4_t { let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]); - let ret_val: poly16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + unsafe { + let ret_val: poly16x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -47335,13 +45049,11 @@ pub unsafe fn vreinterpret_p16_u32(a: uint32x2_t) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_f32_u32(a: uint32x4_t) -> float32x4_t { - transmute(a) +pub fn vreinterpretq_f32_u32(a: uint32x4_t) -> float32x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -47359,15 +45071,15 @@ pub unsafe fn vreinterpretq_f32_u32(a: uint32x4_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_f32_u32(a: uint32x4_t) -> float32x4_t { +pub fn vreinterpretq_f32_u32(a: uint32x4_t) -> float32x4_t { let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - let ret_val: float32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + unsafe { + let ret_val: float32x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -47385,13 +45097,11 @@ pub unsafe fn vreinterpretq_f32_u32(a: uint32x4_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s8_u32(a: uint32x4_t) -> int8x16_t { - transmute(a) +pub fn vreinterpretq_s8_u32(a: uint32x4_t) -> int8x16_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -47409,19 +45119,19 @@ pub unsafe fn vreinterpretq_s8_u32(a: uint32x4_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s8_u32(a: uint32x4_t) -> int8x16_t { +pub fn vreinterpretq_s8_u32(a: uint32x4_t) -> int8x16_t { let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - let ret_val: int8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) + unsafe { + let ret_val: int8x16_t = transmute(a); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -47439,13 +45149,11 @@ pub unsafe fn vreinterpretq_s8_u32(a: uint32x4_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s16_u32(a: uint32x4_t) -> int16x8_t { - transmute(a) +pub fn vreinterpretq_s16_u32(a: uint32x4_t) -> int16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -47463,15 +45171,15 @@ pub unsafe fn vreinterpretq_s16_u32(a: uint32x4_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s16_u32(a: uint32x4_t) -> int16x8_t { +pub fn vreinterpretq_s16_u32(a: uint32x4_t) -> int16x8_t { let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - let ret_val: int16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: int16x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -47489,13 +45197,11 @@ pub unsafe fn vreinterpretq_s16_u32(a: uint32x4_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s32_u32(a: uint32x4_t) -> int32x4_t { - transmute(a) +pub fn vreinterpretq_s32_u32(a: uint32x4_t) -> int32x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -47513,15 +45219,15 @@ pub unsafe fn vreinterpretq_s32_u32(a: uint32x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s32_u32(a: uint32x4_t) -> int32x4_t { +pub fn vreinterpretq_s32_u32(a: uint32x4_t) -> int32x4_t { let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - let ret_val: int32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + unsafe { + let ret_val: int32x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -47539,13 +45245,11 @@ pub unsafe fn vreinterpretq_s32_u32(a: uint32x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s64_u32(a: uint32x4_t) -> int64x2_t { - transmute(a) +pub fn vreinterpretq_s64_u32(a: uint32x4_t) -> int64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -47563,15 +45267,15 @@ pub unsafe fn vreinterpretq_s64_u32(a: uint32x4_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s64_u32(a: uint32x4_t) -> int64x2_t { +pub fn vreinterpretq_s64_u32(a: uint32x4_t) -> int64x2_t { let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - let ret_val: int64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: int64x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -47589,13 +45293,11 @@ pub unsafe fn vreinterpretq_s64_u32(a: uint32x4_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u8_u32(a: uint32x4_t) -> uint8x16_t { - transmute(a) +pub fn vreinterpretq_u8_u32(a: uint32x4_t) -> uint8x16_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -47613,19 +45315,19 @@ pub unsafe fn vreinterpretq_u8_u32(a: uint32x4_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u8_u32(a: uint32x4_t) -> uint8x16_t { +pub fn vreinterpretq_u8_u32(a: uint32x4_t) -> uint8x16_t { let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - let ret_val: uint8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) + unsafe { + let ret_val: uint8x16_t = transmute(a); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -47643,13 +45345,11 @@ pub unsafe fn vreinterpretq_u8_u32(a: uint32x4_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u16_u32(a: uint32x4_t) -> uint16x8_t { - transmute(a) +pub fn vreinterpretq_u16_u32(a: uint32x4_t) -> uint16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -47667,15 +45367,15 @@ pub unsafe fn vreinterpretq_u16_u32(a: uint32x4_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u16_u32(a: uint32x4_t) -> uint16x8_t { +pub fn vreinterpretq_u16_u32(a: uint32x4_t) -> uint16x8_t { let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - let ret_val: uint16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: uint16x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -47693,13 +45393,11 @@ pub unsafe fn vreinterpretq_u16_u32(a: uint32x4_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u64_u32(a: uint32x4_t) -> uint64x2_t { - transmute(a) +pub fn vreinterpretq_u64_u32(a: uint32x4_t) -> uint64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -47717,15 +45415,15 @@ pub unsafe fn vreinterpretq_u64_u32(a: uint32x4_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u64_u32(a: uint32x4_t) -> uint64x2_t { +pub fn vreinterpretq_u64_u32(a: uint32x4_t) -> uint64x2_t { let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - let ret_val: uint64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: uint64x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -47743,13 +45441,11 @@ pub unsafe fn vreinterpretq_u64_u32(a: uint32x4_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p8_u32(a: uint32x4_t) -> poly8x16_t { - transmute(a) +pub fn vreinterpretq_p8_u32(a: uint32x4_t) -> poly8x16_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -47767,19 +45463,19 @@ pub unsafe fn vreinterpretq_p8_u32(a: uint32x4_t) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p8_u32(a: uint32x4_t) -> poly8x16_t { +pub fn vreinterpretq_p8_u32(a: uint32x4_t) -> poly8x16_t { let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - let ret_val: poly8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) + unsafe { + let ret_val: poly8x16_t = transmute(a); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -47797,13 +45493,11 @@ pub unsafe fn vreinterpretq_p8_u32(a: uint32x4_t) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p16_u32(a: uint32x4_t) -> poly16x8_t { - transmute(a) +pub fn vreinterpretq_p16_u32(a: uint32x4_t) -> poly16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -47821,15 +45515,15 @@ pub unsafe fn vreinterpretq_p16_u32(a: uint32x4_t) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p16_u32(a: uint32x4_t) -> poly16x8_t { +pub fn vreinterpretq_p16_u32(a: uint32x4_t) -> poly16x8_t { let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - let ret_val: poly16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: poly16x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -47847,13 +45541,11 @@ pub unsafe fn vreinterpretq_p16_u32(a: uint32x4_t) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_f32_u64(a: uint64x1_t) -> float32x2_t { - transmute(a) +pub fn vreinterpret_f32_u64(a: uint64x1_t) -> float32x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -47871,14 +45563,14 @@ pub unsafe fn vreinterpret_f32_u64(a: uint64x1_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_f32_u64(a: uint64x1_t) -> float32x2_t { - let ret_val: float32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) +pub fn vreinterpret_f32_u64(a: uint64x1_t) -> float32x2_t { + unsafe { + let ret_val: float32x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -47896,13 +45588,11 @@ pub unsafe fn vreinterpret_f32_u64(a: uint64x1_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s8_u64(a: uint64x1_t) -> int8x8_t { - transmute(a) +pub fn vreinterpret_s8_u64(a: uint64x1_t) -> int8x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -47920,14 +45610,14 @@ pub unsafe fn vreinterpret_s8_u64(a: uint64x1_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s8_u64(a: uint64x1_t) -> int8x8_t { - let ret_val: int8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) +pub fn vreinterpret_s8_u64(a: uint64x1_t) -> int8x8_t { + unsafe { + let ret_val: int8x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -47945,13 +45635,11 @@ pub unsafe fn vreinterpret_s8_u64(a: uint64x1_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s16_u64(a: uint64x1_t) -> int16x4_t { - transmute(a) +pub fn vreinterpret_s16_u64(a: uint64x1_t) -> int16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -47969,14 +45657,14 @@ pub unsafe fn vreinterpret_s16_u64(a: uint64x1_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s16_u64(a: uint64x1_t) -> int16x4_t { - let ret_val: int16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) +pub fn vreinterpret_s16_u64(a: uint64x1_t) -> int16x4_t { + unsafe { + let ret_val: int16x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -47994,13 +45682,11 @@ pub unsafe fn vreinterpret_s16_u64(a: uint64x1_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s32_u64(a: uint64x1_t) -> int32x2_t { - transmute(a) +pub fn vreinterpret_s32_u64(a: uint64x1_t) -> int32x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -48018,14 +45704,14 @@ pub unsafe fn vreinterpret_s32_u64(a: uint64x1_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s32_u64(a: uint64x1_t) -> int32x2_t { - let ret_val: int32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) +pub fn vreinterpret_s32_u64(a: uint64x1_t) -> int32x2_t { + unsafe { + let ret_val: int32x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -48042,13 +45728,11 @@ pub unsafe fn vreinterpret_s32_u64(a: uint64x1_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s64_u64(a: uint64x1_t) -> int64x1_t { - transmute(a) +pub fn vreinterpret_s64_u64(a: uint64x1_t) -> int64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -48066,13 +45750,11 @@ pub unsafe fn vreinterpret_s64_u64(a: uint64x1_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u8_u64(a: uint64x1_t) -> uint8x8_t { - transmute(a) +pub fn vreinterpret_u8_u64(a: uint64x1_t) -> uint8x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -48090,14 +45772,14 @@ pub unsafe fn vreinterpret_u8_u64(a: uint64x1_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u8_u64(a: uint64x1_t) -> uint8x8_t { - let ret_val: uint8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) +pub fn vreinterpret_u8_u64(a: uint64x1_t) -> uint8x8_t { + unsafe { + let ret_val: uint8x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -48115,13 +45797,11 @@ pub unsafe fn vreinterpret_u8_u64(a: uint64x1_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u16_u64(a: uint64x1_t) -> uint16x4_t { - transmute(a) +pub fn vreinterpret_u16_u64(a: uint64x1_t) -> uint16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -48139,14 +45819,14 @@ pub unsafe fn vreinterpret_u16_u64(a: uint64x1_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u16_u64(a: uint64x1_t) -> uint16x4_t { - let ret_val: uint16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) +pub fn vreinterpret_u16_u64(a: uint64x1_t) -> uint16x4_t { + unsafe { + let ret_val: uint16x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -48164,13 +45844,11 @@ pub unsafe fn vreinterpret_u16_u64(a: uint64x1_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u32_u64(a: uint64x1_t) -> uint32x2_t { - transmute(a) +pub fn vreinterpret_u32_u64(a: uint64x1_t) -> uint32x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -48188,14 +45866,14 @@ pub unsafe fn vreinterpret_u32_u64(a: uint64x1_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u32_u64(a: uint64x1_t) -> uint32x2_t { - let ret_val: uint32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) +pub fn vreinterpret_u32_u64(a: uint64x1_t) -> uint32x2_t { + unsafe { + let ret_val: uint32x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -48213,13 +45891,11 @@ pub unsafe fn vreinterpret_u32_u64(a: uint64x1_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_p8_u64(a: uint64x1_t) -> poly8x8_t { - transmute(a) +pub fn vreinterpret_p8_u64(a: uint64x1_t) -> poly8x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -48237,14 +45913,14 @@ pub unsafe fn vreinterpret_p8_u64(a: uint64x1_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_p8_u64(a: uint64x1_t) -> poly8x8_t { - let ret_val: poly8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) +pub fn vreinterpret_p8_u64(a: uint64x1_t) -> poly8x8_t { + unsafe { + let ret_val: poly8x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -48262,13 +45938,11 @@ pub unsafe fn vreinterpret_p8_u64(a: uint64x1_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_p16_u64(a: uint64x1_t) -> poly16x4_t { - transmute(a) +pub fn vreinterpret_p16_u64(a: uint64x1_t) -> poly16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -48286,14 +45960,14 @@ pub unsafe fn vreinterpret_p16_u64(a: uint64x1_t) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_p16_u64(a: uint64x1_t) -> poly16x4_t { - let ret_val: poly16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) +pub fn vreinterpret_p16_u64(a: uint64x1_t) -> poly16x4_t { + unsafe { + let ret_val: poly16x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -48311,13 +45985,11 @@ pub unsafe fn vreinterpret_p16_u64(a: uint64x1_t) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_f32_u64(a: uint64x2_t) -> float32x4_t { - transmute(a) +pub fn vreinterpretq_f32_u64(a: uint64x2_t) -> float32x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -48335,15 +46007,15 @@ pub unsafe fn vreinterpretq_f32_u64(a: uint64x2_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_f32_u64(a: uint64x2_t) -> float32x4_t { +pub fn vreinterpretq_f32_u64(a: uint64x2_t) -> float32x4_t { let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]); - let ret_val: float32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + unsafe { + let ret_val: float32x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -48361,13 +46033,11 @@ pub unsafe fn vreinterpretq_f32_u64(a: uint64x2_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s8_u64(a: uint64x2_t) -> int8x16_t { - transmute(a) +pub fn vreinterpretq_s8_u64(a: uint64x2_t) -> int8x16_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -48385,19 +46055,19 @@ pub unsafe fn vreinterpretq_s8_u64(a: uint64x2_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s8_u64(a: uint64x2_t) -> int8x16_t { +pub fn vreinterpretq_s8_u64(a: uint64x2_t) -> int8x16_t { let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]); - let ret_val: int8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) + unsafe { + let ret_val: int8x16_t = transmute(a); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -48415,13 +46085,11 @@ pub unsafe fn vreinterpretq_s8_u64(a: uint64x2_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s16_u64(a: uint64x2_t) -> int16x8_t { - transmute(a) +pub fn vreinterpretq_s16_u64(a: uint64x2_t) -> int16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -48439,15 +46107,15 @@ pub unsafe fn vreinterpretq_s16_u64(a: uint64x2_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s16_u64(a: uint64x2_t) -> int16x8_t { +pub fn vreinterpretq_s16_u64(a: uint64x2_t) -> int16x8_t { let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]); - let ret_val: int16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: int16x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -48465,13 +46133,11 @@ pub unsafe fn vreinterpretq_s16_u64(a: uint64x2_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s32_u64(a: uint64x2_t) -> int32x4_t { - transmute(a) +pub fn vreinterpretq_s32_u64(a: uint64x2_t) -> int32x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -48489,15 +46155,15 @@ pub unsafe fn vreinterpretq_s32_u64(a: uint64x2_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s32_u64(a: uint64x2_t) -> int32x4_t { +pub fn vreinterpretq_s32_u64(a: uint64x2_t) -> int32x4_t { let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]); - let ret_val: int32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + unsafe { + let ret_val: int32x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -48515,13 +46181,11 @@ pub unsafe fn vreinterpretq_s32_u64(a: uint64x2_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s64_u64(a: uint64x2_t) -> int64x2_t { - transmute(a) +pub fn vreinterpretq_s64_u64(a: uint64x2_t) -> int64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -48539,15 +46203,15 @@ pub unsafe fn vreinterpretq_s64_u64(a: uint64x2_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s64_u64(a: uint64x2_t) -> int64x2_t { +pub fn vreinterpretq_s64_u64(a: uint64x2_t) -> int64x2_t { let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]); - let ret_val: int64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: int64x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -48565,13 +46229,11 @@ pub unsafe fn vreinterpretq_s64_u64(a: uint64x2_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u8_u64(a: uint64x2_t) -> uint8x16_t { - transmute(a) +pub fn vreinterpretq_u8_u64(a: uint64x2_t) -> uint8x16_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -48589,19 +46251,19 @@ pub unsafe fn vreinterpretq_u8_u64(a: uint64x2_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u8_u64(a: uint64x2_t) -> uint8x16_t { +pub fn vreinterpretq_u8_u64(a: uint64x2_t) -> uint8x16_t { let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]); - let ret_val: uint8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) + unsafe { + let ret_val: uint8x16_t = transmute(a); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -48619,13 +46281,11 @@ pub unsafe fn vreinterpretq_u8_u64(a: uint64x2_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u16_u64(a: uint64x2_t) -> uint16x8_t { - transmute(a) +pub fn vreinterpretq_u16_u64(a: uint64x2_t) -> uint16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -48643,15 +46303,15 @@ pub unsafe fn vreinterpretq_u16_u64(a: uint64x2_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u16_u64(a: uint64x2_t) -> uint16x8_t { +pub fn vreinterpretq_u16_u64(a: uint64x2_t) -> uint16x8_t { let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]); - let ret_val: uint16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: uint16x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -48669,13 +46329,11 @@ pub unsafe fn vreinterpretq_u16_u64(a: uint64x2_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u32_u64(a: uint64x2_t) -> uint32x4_t { - transmute(a) +pub fn vreinterpretq_u32_u64(a: uint64x2_t) -> uint32x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -48693,15 +46351,15 @@ pub unsafe fn vreinterpretq_u32_u64(a: uint64x2_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u32_u64(a: uint64x2_t) -> uint32x4_t { +pub fn vreinterpretq_u32_u64(a: uint64x2_t) -> uint32x4_t { let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]); - let ret_val: uint32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + unsafe { + let ret_val: uint32x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -48719,13 +46377,11 @@ pub unsafe fn vreinterpretq_u32_u64(a: uint64x2_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p8_u64(a: uint64x2_t) -> poly8x16_t { - transmute(a) +pub fn vreinterpretq_p8_u64(a: uint64x2_t) -> poly8x16_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -48743,19 +46399,19 @@ pub unsafe fn vreinterpretq_p8_u64(a: uint64x2_t) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p8_u64(a: uint64x2_t) -> poly8x16_t { +pub fn vreinterpretq_p8_u64(a: uint64x2_t) -> poly8x16_t { let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]); - let ret_val: poly8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) + unsafe { + let ret_val: poly8x16_t = transmute(a); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -48773,13 +46429,11 @@ pub unsafe fn vreinterpretq_p8_u64(a: uint64x2_t) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p16_u64(a: uint64x2_t) -> poly16x8_t { - transmute(a) +pub fn vreinterpretq_p16_u64(a: uint64x2_t) -> poly16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -48797,15 +46451,15 @@ pub unsafe fn vreinterpretq_p16_u64(a: uint64x2_t) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p16_u64(a: uint64x2_t) -> poly16x8_t { +pub fn vreinterpretq_p16_u64(a: uint64x2_t) -> poly16x8_t { let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]); - let ret_val: poly16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: poly16x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -48823,13 +46477,11 @@ pub unsafe fn vreinterpretq_p16_u64(a: uint64x2_t) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_f32_p8(a: poly8x8_t) -> float32x2_t { - transmute(a) +pub fn vreinterpret_f32_p8(a: poly8x8_t) -> float32x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -48847,15 +46499,15 @@ pub unsafe fn vreinterpret_f32_p8(a: poly8x8_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_f32_p8(a: poly8x8_t) -> float32x2_t { +pub fn vreinterpret_f32_p8(a: poly8x8_t) -> float32x2_t { let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: float32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: float32x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -48873,13 +46525,11 @@ pub unsafe fn vreinterpret_f32_p8(a: poly8x8_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s8_p8(a: poly8x8_t) -> int8x8_t { - transmute(a) +pub fn vreinterpret_s8_p8(a: poly8x8_t) -> int8x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -48897,15 +46547,15 @@ pub unsafe fn vreinterpret_s8_p8(a: poly8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s8_p8(a: poly8x8_t) -> int8x8_t { +pub fn vreinterpret_s8_p8(a: poly8x8_t) -> int8x8_t { let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: int8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: int8x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -48923,13 +46573,11 @@ pub unsafe fn vreinterpret_s8_p8(a: poly8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s16_p8(a: poly8x8_t) -> int16x4_t { - transmute(a) +pub fn vreinterpret_s16_p8(a: poly8x8_t) -> int16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -48947,15 +46595,15 @@ pub unsafe fn vreinterpret_s16_p8(a: poly8x8_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s16_p8(a: poly8x8_t) -> int16x4_t { +pub fn vreinterpret_s16_p8(a: poly8x8_t) -> int16x4_t { let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: int16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + unsafe { + let ret_val: int16x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -48973,13 +46621,11 @@ pub unsafe fn vreinterpret_s16_p8(a: poly8x8_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s32_p8(a: poly8x8_t) -> int32x2_t { - transmute(a) +pub fn vreinterpret_s32_p8(a: poly8x8_t) -> int32x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -48997,15 +46643,15 @@ pub unsafe fn vreinterpret_s32_p8(a: poly8x8_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s32_p8(a: poly8x8_t) -> int32x2_t { +pub fn vreinterpret_s32_p8(a: poly8x8_t) -> int32x2_t { let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: int32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: int32x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -49023,13 +46669,11 @@ pub unsafe fn vreinterpret_s32_p8(a: poly8x8_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s64_p8(a: poly8x8_t) -> int64x1_t { - transmute(a) +pub fn vreinterpret_s64_p8(a: poly8x8_t) -> int64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -49047,14 +46691,12 @@ pub unsafe fn vreinterpret_s64_p8(a: poly8x8_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s64_p8(a: poly8x8_t) -> int64x1_t { +pub fn vreinterpret_s64_p8(a: poly8x8_t) -> int64x1_t { let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - transmute(a) + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -49072,13 +46714,11 @@ pub unsafe fn vreinterpret_s64_p8(a: poly8x8_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u8_p8(a: poly8x8_t) -> uint8x8_t { - transmute(a) +pub fn vreinterpret_u8_p8(a: poly8x8_t) -> uint8x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -49096,15 +46736,15 @@ pub unsafe fn vreinterpret_u8_p8(a: poly8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u8_p8(a: poly8x8_t) -> uint8x8_t { +pub fn vreinterpret_u8_p8(a: poly8x8_t) -> uint8x8_t { let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: uint8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: uint8x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -49122,13 +46762,11 @@ pub unsafe fn vreinterpret_u8_p8(a: poly8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u16_p8(a: poly8x8_t) -> uint16x4_t { - transmute(a) +pub fn vreinterpret_u16_p8(a: poly8x8_t) -> uint16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -49146,15 +46784,15 @@ pub unsafe fn vreinterpret_u16_p8(a: poly8x8_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u16_p8(a: poly8x8_t) -> uint16x4_t { +pub fn vreinterpret_u16_p8(a: poly8x8_t) -> uint16x4_t { let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: uint16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + unsafe { + let ret_val: uint16x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -49172,13 +46810,11 @@ pub unsafe fn vreinterpret_u16_p8(a: poly8x8_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u32_p8(a: poly8x8_t) -> uint32x2_t { - transmute(a) +pub fn vreinterpret_u32_p8(a: poly8x8_t) -> uint32x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -49196,15 +46832,15 @@ pub unsafe fn vreinterpret_u32_p8(a: poly8x8_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u32_p8(a: poly8x8_t) -> uint32x2_t { +pub fn vreinterpret_u32_p8(a: poly8x8_t) -> uint32x2_t { let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: uint32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: uint32x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -49222,13 +46858,11 @@ pub unsafe fn vreinterpret_u32_p8(a: poly8x8_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u64_p8(a: poly8x8_t) -> uint64x1_t { - transmute(a) +pub fn vreinterpret_u64_p8(a: poly8x8_t) -> uint64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -49246,14 +46880,12 @@ pub unsafe fn vreinterpret_u64_p8(a: poly8x8_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u64_p8(a: poly8x8_t) -> uint64x1_t { +pub fn vreinterpret_u64_p8(a: poly8x8_t) -> uint64x1_t { let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - transmute(a) + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -49271,13 +46903,11 @@ pub unsafe fn vreinterpret_u64_p8(a: poly8x8_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_p16_p8(a: poly8x8_t) -> poly16x4_t { - transmute(a) +pub fn vreinterpret_p16_p8(a: poly8x8_t) -> poly16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -49295,15 +46925,15 @@ pub unsafe fn vreinterpret_p16_p8(a: poly8x8_t) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_p16_p8(a: poly8x8_t) -> poly16x4_t { +pub fn vreinterpret_p16_p8(a: poly8x8_t) -> poly16x4_t { let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: poly16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + unsafe { + let ret_val: poly16x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -49321,13 +46951,11 @@ pub unsafe fn vreinterpret_p16_p8(a: poly8x8_t) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_f32_p8(a: poly8x16_t) -> float32x4_t { - transmute(a) +pub fn vreinterpretq_f32_p8(a: poly8x16_t) -> float32x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -49345,15 +46973,15 @@ pub unsafe fn vreinterpretq_f32_p8(a: poly8x16_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_f32_p8(a: poly8x16_t) -> float32x4_t { +pub fn vreinterpretq_f32_p8(a: poly8x16_t) -> float32x4_t { let a: poly8x16_t = simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: float32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + unsafe { + let ret_val: float32x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -49371,13 +46999,11 @@ pub unsafe fn vreinterpretq_f32_p8(a: poly8x16_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s8_p8(a: poly8x16_t) -> int8x16_t { - transmute(a) +pub fn vreinterpretq_s8_p8(a: poly8x16_t) -> int8x16_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -49395,19 +47021,19 @@ pub unsafe fn vreinterpretq_s8_p8(a: poly8x16_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s8_p8(a: poly8x16_t) -> int8x16_t { +pub fn vreinterpretq_s8_p8(a: poly8x16_t) -> int8x16_t { let a: poly8x16_t = simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: int8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) + unsafe { + let ret_val: int8x16_t = transmute(a); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -49425,13 +47051,11 @@ pub unsafe fn vreinterpretq_s8_p8(a: poly8x16_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s16_p8(a: poly8x16_t) -> int16x8_t { - transmute(a) +pub fn vreinterpretq_s16_p8(a: poly8x16_t) -> int16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -49449,15 +47073,15 @@ pub unsafe fn vreinterpretq_s16_p8(a: poly8x16_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s16_p8(a: poly8x16_t) -> int16x8_t { +pub fn vreinterpretq_s16_p8(a: poly8x16_t) -> int16x8_t { let a: poly8x16_t = simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: int16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: int16x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -49475,13 +47099,11 @@ pub unsafe fn vreinterpretq_s16_p8(a: poly8x16_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s32_p8(a: poly8x16_t) -> int32x4_t { - transmute(a) +pub fn vreinterpretq_s32_p8(a: poly8x16_t) -> int32x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -49499,15 +47121,15 @@ pub unsafe fn vreinterpretq_s32_p8(a: poly8x16_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s32_p8(a: poly8x16_t) -> int32x4_t { +pub fn vreinterpretq_s32_p8(a: poly8x16_t) -> int32x4_t { let a: poly8x16_t = simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: int32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + unsafe { + let ret_val: int32x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -49525,13 +47147,11 @@ pub unsafe fn vreinterpretq_s32_p8(a: poly8x16_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s64_p8(a: poly8x16_t) -> int64x2_t { - transmute(a) +pub fn vreinterpretq_s64_p8(a: poly8x16_t) -> int64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -49549,15 +47169,15 @@ pub unsafe fn vreinterpretq_s64_p8(a: poly8x16_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s64_p8(a: poly8x16_t) -> int64x2_t { +pub fn vreinterpretq_s64_p8(a: poly8x16_t) -> int64x2_t { let a: poly8x16_t = simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: int64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: int64x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -49575,13 +47195,11 @@ pub unsafe fn vreinterpretq_s64_p8(a: poly8x16_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u8_p8(a: poly8x16_t) -> uint8x16_t { - transmute(a) +pub fn vreinterpretq_u8_p8(a: poly8x16_t) -> uint8x16_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -49599,19 +47217,19 @@ pub unsafe fn vreinterpretq_u8_p8(a: poly8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u8_p8(a: poly8x16_t) -> uint8x16_t { +pub fn vreinterpretq_u8_p8(a: poly8x16_t) -> uint8x16_t { let a: poly8x16_t = simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: uint8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) + unsafe { + let ret_val: uint8x16_t = transmute(a); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -49629,13 +47247,11 @@ pub unsafe fn vreinterpretq_u8_p8(a: poly8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u16_p8(a: poly8x16_t) -> uint16x8_t { - transmute(a) +pub fn vreinterpretq_u16_p8(a: poly8x16_t) -> uint16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -49653,15 +47269,15 @@ pub unsafe fn vreinterpretq_u16_p8(a: poly8x16_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u16_p8(a: poly8x16_t) -> uint16x8_t { +pub fn vreinterpretq_u16_p8(a: poly8x16_t) -> uint16x8_t { let a: poly8x16_t = simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: uint16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: uint16x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -49679,13 +47295,11 @@ pub unsafe fn vreinterpretq_u16_p8(a: poly8x16_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u32_p8(a: poly8x16_t) -> uint32x4_t { - transmute(a) +pub fn vreinterpretq_u32_p8(a: poly8x16_t) -> uint32x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -49703,15 +47317,15 @@ pub unsafe fn vreinterpretq_u32_p8(a: poly8x16_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u32_p8(a: poly8x16_t) -> uint32x4_t { +pub fn vreinterpretq_u32_p8(a: poly8x16_t) -> uint32x4_t { let a: poly8x16_t = simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: uint32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + unsafe { + let ret_val: uint32x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -49729,13 +47343,11 @@ pub unsafe fn vreinterpretq_u32_p8(a: poly8x16_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u64_p8(a: poly8x16_t) -> uint64x2_t { - transmute(a) +pub fn vreinterpretq_u64_p8(a: poly8x16_t) -> uint64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -49753,15 +47365,15 @@ pub unsafe fn vreinterpretq_u64_p8(a: poly8x16_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u64_p8(a: poly8x16_t) -> uint64x2_t { +pub fn vreinterpretq_u64_p8(a: poly8x16_t) -> uint64x2_t { let a: poly8x16_t = simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: uint64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: uint64x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -49779,13 +47391,11 @@ pub unsafe fn vreinterpretq_u64_p8(a: poly8x16_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p16_p8(a: poly8x16_t) -> poly16x8_t { - transmute(a) +pub fn vreinterpretq_p16_p8(a: poly8x16_t) -> poly16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -49803,15 +47413,15 @@ pub unsafe fn vreinterpretq_p16_p8(a: poly8x16_t) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p16_p8(a: poly8x16_t) -> poly16x8_t { +pub fn vreinterpretq_p16_p8(a: poly8x16_t) -> poly16x8_t { let a: poly8x16_t = simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: poly16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: poly16x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -49829,13 +47439,11 @@ pub unsafe fn vreinterpretq_p16_p8(a: poly8x16_t) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_f32_p16(a: poly16x4_t) -> float32x2_t { - transmute(a) +pub fn vreinterpret_f32_p16(a: poly16x4_t) -> float32x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -49853,15 +47461,15 @@ pub unsafe fn vreinterpret_f32_p16(a: poly16x4_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_f32_p16(a: poly16x4_t) -> float32x2_t { +pub fn vreinterpret_f32_p16(a: poly16x4_t) -> float32x2_t { let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - let ret_val: float32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: float32x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -49879,13 +47487,11 @@ pub unsafe fn vreinterpret_f32_p16(a: poly16x4_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s8_p16(a: poly16x4_t) -> int8x8_t { - transmute(a) +pub fn vreinterpret_s8_p16(a: poly16x4_t) -> int8x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -49903,15 +47509,15 @@ pub unsafe fn vreinterpret_s8_p16(a: poly16x4_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s8_p16(a: poly16x4_t) -> int8x8_t { +pub fn vreinterpret_s8_p16(a: poly16x4_t) -> int8x8_t { let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - let ret_val: int8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: int8x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -49929,13 +47535,11 @@ pub unsafe fn vreinterpret_s8_p16(a: poly16x4_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s16_p16(a: poly16x4_t) -> int16x4_t { - transmute(a) +pub fn vreinterpret_s16_p16(a: poly16x4_t) -> int16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -49953,15 +47557,15 @@ pub unsafe fn vreinterpret_s16_p16(a: poly16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s16_p16(a: poly16x4_t) -> int16x4_t { +pub fn vreinterpret_s16_p16(a: poly16x4_t) -> int16x4_t { let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - let ret_val: int16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + unsafe { + let ret_val: int16x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -49979,13 +47583,11 @@ pub unsafe fn vreinterpret_s16_p16(a: poly16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s32_p16(a: poly16x4_t) -> int32x2_t { - transmute(a) +pub fn vreinterpret_s32_p16(a: poly16x4_t) -> int32x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -50003,15 +47605,15 @@ pub unsafe fn vreinterpret_s32_p16(a: poly16x4_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s32_p16(a: poly16x4_t) -> int32x2_t { +pub fn vreinterpret_s32_p16(a: poly16x4_t) -> int32x2_t { let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - let ret_val: int32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: int32x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -50029,13 +47631,11 @@ pub unsafe fn vreinterpret_s32_p16(a: poly16x4_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s64_p16(a: poly16x4_t) -> int64x1_t { - transmute(a) +pub fn vreinterpret_s64_p16(a: poly16x4_t) -> int64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -50053,14 +47653,12 @@ pub unsafe fn vreinterpret_s64_p16(a: poly16x4_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s64_p16(a: poly16x4_t) -> int64x1_t { +pub fn vreinterpret_s64_p16(a: poly16x4_t) -> int64x1_t { let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - transmute(a) + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -50078,13 +47676,11 @@ pub unsafe fn vreinterpret_s64_p16(a: poly16x4_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u8_p16(a: poly16x4_t) -> uint8x8_t { - transmute(a) +pub fn vreinterpret_u8_p16(a: poly16x4_t) -> uint8x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -50102,15 +47698,15 @@ pub unsafe fn vreinterpret_u8_p16(a: poly16x4_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u8_p16(a: poly16x4_t) -> uint8x8_t { +pub fn vreinterpret_u8_p16(a: poly16x4_t) -> uint8x8_t { let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - let ret_val: uint8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: uint8x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -50128,13 +47724,11 @@ pub unsafe fn vreinterpret_u8_p16(a: poly16x4_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u16_p16(a: poly16x4_t) -> uint16x4_t { - transmute(a) +pub fn vreinterpret_u16_p16(a: poly16x4_t) -> uint16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -50152,15 +47746,15 @@ pub unsafe fn vreinterpret_u16_p16(a: poly16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u16_p16(a: poly16x4_t) -> uint16x4_t { +pub fn vreinterpret_u16_p16(a: poly16x4_t) -> uint16x4_t { let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - let ret_val: uint16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + unsafe { + let ret_val: uint16x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -50178,13 +47772,11 @@ pub unsafe fn vreinterpret_u16_p16(a: poly16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u32_p16(a: poly16x4_t) -> uint32x2_t { - transmute(a) +pub fn vreinterpret_u32_p16(a: poly16x4_t) -> uint32x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -50202,15 +47794,15 @@ pub unsafe fn vreinterpret_u32_p16(a: poly16x4_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u32_p16(a: poly16x4_t) -> uint32x2_t { +pub fn vreinterpret_u32_p16(a: poly16x4_t) -> uint32x2_t { let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - let ret_val: uint32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: uint32x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -50228,13 +47820,11 @@ pub unsafe fn vreinterpret_u32_p16(a: poly16x4_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u64_p16(a: poly16x4_t) -> uint64x1_t { - transmute(a) +pub fn vreinterpret_u64_p16(a: poly16x4_t) -> uint64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -50252,14 +47842,12 @@ pub unsafe fn vreinterpret_u64_p16(a: poly16x4_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u64_p16(a: poly16x4_t) -> uint64x1_t { +pub fn vreinterpret_u64_p16(a: poly16x4_t) -> uint64x1_t { let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - transmute(a) + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -50277,13 +47865,11 @@ pub unsafe fn vreinterpret_u64_p16(a: poly16x4_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_p8_p16(a: poly16x4_t) -> poly8x8_t { - transmute(a) +pub fn vreinterpret_p8_p16(a: poly16x4_t) -> poly8x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -50301,15 +47887,15 @@ pub unsafe fn vreinterpret_p8_p16(a: poly16x4_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_p8_p16(a: poly16x4_t) -> poly8x8_t { +pub fn vreinterpret_p8_p16(a: poly16x4_t) -> poly8x8_t { let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - let ret_val: poly8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: poly8x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -50327,13 +47913,11 @@ pub unsafe fn vreinterpret_p8_p16(a: poly16x4_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_f32_p16(a: poly16x8_t) -> float32x4_t { - transmute(a) +pub fn vreinterpretq_f32_p16(a: poly16x8_t) -> float32x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -50351,15 +47935,15 @@ pub unsafe fn vreinterpretq_f32_p16(a: poly16x8_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_f32_p16(a: poly16x8_t) -> float32x4_t { +pub fn vreinterpretq_f32_p16(a: poly16x8_t) -> float32x4_t { let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: float32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + unsafe { + let ret_val: float32x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -50377,13 +47961,11 @@ pub unsafe fn vreinterpretq_f32_p16(a: poly16x8_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s8_p16(a: poly16x8_t) -> int8x16_t { - transmute(a) +pub fn vreinterpretq_s8_p16(a: poly16x8_t) -> int8x16_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -50401,19 +47983,19 @@ pub unsafe fn vreinterpretq_s8_p16(a: poly16x8_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s8_p16(a: poly16x8_t) -> int8x16_t { +pub fn vreinterpretq_s8_p16(a: poly16x8_t) -> int8x16_t { let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: int8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) + unsafe { + let ret_val: int8x16_t = transmute(a); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -50431,13 +48013,11 @@ pub unsafe fn vreinterpretq_s8_p16(a: poly16x8_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s16_p16(a: poly16x8_t) -> int16x8_t { - transmute(a) +pub fn vreinterpretq_s16_p16(a: poly16x8_t) -> int16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -50455,15 +48035,15 @@ pub unsafe fn vreinterpretq_s16_p16(a: poly16x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s16_p16(a: poly16x8_t) -> int16x8_t { +pub fn vreinterpretq_s16_p16(a: poly16x8_t) -> int16x8_t { let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: int16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: int16x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -50481,13 +48061,11 @@ pub unsafe fn vreinterpretq_s16_p16(a: poly16x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s32_p16(a: poly16x8_t) -> int32x4_t { - transmute(a) +pub fn vreinterpretq_s32_p16(a: poly16x8_t) -> int32x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -50505,15 +48083,15 @@ pub unsafe fn vreinterpretq_s32_p16(a: poly16x8_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s32_p16(a: poly16x8_t) -> int32x4_t { +pub fn vreinterpretq_s32_p16(a: poly16x8_t) -> int32x4_t { let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: int32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + unsafe { + let ret_val: int32x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -50531,13 +48109,11 @@ pub unsafe fn vreinterpretq_s32_p16(a: poly16x8_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s64_p16(a: poly16x8_t) -> int64x2_t { - transmute(a) +pub fn vreinterpretq_s64_p16(a: poly16x8_t) -> int64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -50555,15 +48131,15 @@ pub unsafe fn vreinterpretq_s64_p16(a: poly16x8_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s64_p16(a: poly16x8_t) -> int64x2_t { +pub fn vreinterpretq_s64_p16(a: poly16x8_t) -> int64x2_t { let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: int64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: int64x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -50581,13 +48157,11 @@ pub unsafe fn vreinterpretq_s64_p16(a: poly16x8_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u8_p16(a: poly16x8_t) -> uint8x16_t { - transmute(a) +pub fn vreinterpretq_u8_p16(a: poly16x8_t) -> uint8x16_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -50605,19 +48179,19 @@ pub unsafe fn vreinterpretq_u8_p16(a: poly16x8_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u8_p16(a: poly16x8_t) -> uint8x16_t { +pub fn vreinterpretq_u8_p16(a: poly16x8_t) -> uint8x16_t { let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: uint8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) + unsafe { + let ret_val: uint8x16_t = transmute(a); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -50635,13 +48209,11 @@ pub unsafe fn vreinterpretq_u8_p16(a: poly16x8_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u16_p16(a: poly16x8_t) -> uint16x8_t { - transmute(a) +pub fn vreinterpretq_u16_p16(a: poly16x8_t) -> uint16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -50659,15 +48231,15 @@ pub unsafe fn vreinterpretq_u16_p16(a: poly16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u16_p16(a: poly16x8_t) -> uint16x8_t { +pub fn vreinterpretq_u16_p16(a: poly16x8_t) -> uint16x8_t { let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: uint16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: uint16x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -50685,13 +48257,11 @@ pub unsafe fn vreinterpretq_u16_p16(a: poly16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u32_p16(a: poly16x8_t) -> uint32x4_t { - transmute(a) +pub fn vreinterpretq_u32_p16(a: poly16x8_t) -> uint32x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -50709,15 +48279,15 @@ pub unsafe fn vreinterpretq_u32_p16(a: poly16x8_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u32_p16(a: poly16x8_t) -> uint32x4_t { +pub fn vreinterpretq_u32_p16(a: poly16x8_t) -> uint32x4_t { let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: uint32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + unsafe { + let ret_val: uint32x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -50735,13 +48305,11 @@ pub unsafe fn vreinterpretq_u32_p16(a: poly16x8_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u64_p16(a: poly16x8_t) -> uint64x2_t { - transmute(a) +pub fn vreinterpretq_u64_p16(a: poly16x8_t) -> uint64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -50759,15 +48327,15 @@ pub unsafe fn vreinterpretq_u64_p16(a: poly16x8_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u64_p16(a: poly16x8_t) -> uint64x2_t { +pub fn vreinterpretq_u64_p16(a: poly16x8_t) -> uint64x2_t { let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: uint64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: uint64x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -50785,13 +48353,11 @@ pub unsafe fn vreinterpretq_u64_p16(a: poly16x8_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p8_p16(a: poly16x8_t) -> poly8x16_t { - transmute(a) +pub fn vreinterpretq_p8_p16(a: poly16x8_t) -> poly8x16_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -50809,19 +48375,19 @@ pub unsafe fn vreinterpretq_p8_p16(a: poly16x8_t) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p8_p16(a: poly16x8_t) -> poly8x16_t { +pub fn vreinterpretq_p8_p16(a: poly16x8_t) -> poly8x16_t { let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: poly8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) + unsafe { + let ret_val: poly8x16_t = transmute(a); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p128)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon,aes")] @@ -50839,13 +48405,11 @@ pub unsafe fn vreinterpretq_p8_p16(a: poly16x8_t) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s8_p128(a: p128) -> int8x16_t { - transmute(a) +pub fn vreinterpretq_s8_p128(a: p128) -> int8x16_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p128)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon,aes")] @@ -50863,18 +48427,18 @@ pub unsafe fn vreinterpretq_s8_p128(a: p128) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s8_p128(a: p128) -> int8x16_t { - let ret_val: int8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) +pub fn vreinterpretq_s8_p128(a: p128) -> int8x16_t { + unsafe { + let ret_val: int8x16_t = transmute(a); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p128)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon,aes")] @@ -50892,13 +48456,11 @@ pub unsafe fn vreinterpretq_s8_p128(a: p128) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s16_p128(a: p128) -> int16x8_t { - transmute(a) +pub fn vreinterpretq_s16_p128(a: p128) -> int16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p128)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon,aes")] @@ -50916,14 +48478,14 @@ pub unsafe fn vreinterpretq_s16_p128(a: p128) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s16_p128(a: p128) -> int16x8_t { - let ret_val: int16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) +pub fn vreinterpretq_s16_p128(a: p128) -> int16x8_t { + unsafe { + let ret_val: int16x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p128)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon,aes")] @@ -50941,13 +48503,11 @@ pub unsafe fn vreinterpretq_s16_p128(a: p128) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s32_p128(a: p128) -> int32x4_t { - transmute(a) +pub fn vreinterpretq_s32_p128(a: p128) -> int32x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p128)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon,aes")] @@ -50965,14 +48525,14 @@ pub unsafe fn vreinterpretq_s32_p128(a: p128) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s32_p128(a: p128) -> int32x4_t { - let ret_val: int32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) +pub fn vreinterpretq_s32_p128(a: p128) -> int32x4_t { + unsafe { + let ret_val: int32x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p128)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon,aes")] @@ -50990,13 +48550,11 @@ pub unsafe fn vreinterpretq_s32_p128(a: p128) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s64_p128(a: p128) -> int64x2_t { - transmute(a) +pub fn vreinterpretq_s64_p128(a: p128) -> int64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p128)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon,aes")] @@ -51014,14 +48572,14 @@ pub unsafe fn vreinterpretq_s64_p128(a: p128) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s64_p128(a: p128) -> int64x2_t { - let ret_val: int64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) +pub fn vreinterpretq_s64_p128(a: p128) -> int64x2_t { + unsafe { + let ret_val: int64x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p128)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon,aes")] @@ -51039,13 +48597,11 @@ pub unsafe fn vreinterpretq_s64_p128(a: p128) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u8_p128(a: p128) -> uint8x16_t { - transmute(a) +pub fn vreinterpretq_u8_p128(a: p128) -> uint8x16_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p128)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon,aes")] @@ -51063,18 +48619,18 @@ pub unsafe fn vreinterpretq_u8_p128(a: p128) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u8_p128(a: p128) -> uint8x16_t { - let ret_val: uint8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) +pub fn vreinterpretq_u8_p128(a: p128) -> uint8x16_t { + unsafe { + let ret_val: uint8x16_t = transmute(a); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p128)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon,aes")] @@ -51092,13 +48648,11 @@ pub unsafe fn vreinterpretq_u8_p128(a: p128) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u16_p128(a: p128) -> uint16x8_t { - transmute(a) +pub fn vreinterpretq_u16_p128(a: p128) -> uint16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p128)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon,aes")] @@ -51116,14 +48670,14 @@ pub unsafe fn vreinterpretq_u16_p128(a: p128) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u16_p128(a: p128) -> uint16x8_t { - let ret_val: uint16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) +pub fn vreinterpretq_u16_p128(a: p128) -> uint16x8_t { + unsafe { + let ret_val: uint16x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p128)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon,aes")] @@ -51141,13 +48695,11 @@ pub unsafe fn vreinterpretq_u16_p128(a: p128) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u32_p128(a: p128) -> uint32x4_t { - transmute(a) +pub fn vreinterpretq_u32_p128(a: p128) -> uint32x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p128)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon,aes")] @@ -51165,14 +48717,14 @@ pub unsafe fn vreinterpretq_u32_p128(a: p128) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u32_p128(a: p128) -> uint32x4_t { - let ret_val: uint32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) +pub fn vreinterpretq_u32_p128(a: p128) -> uint32x4_t { + unsafe { + let ret_val: uint32x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p128)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon,aes")] @@ -51190,13 +48742,11 @@ pub unsafe fn vreinterpretq_u32_p128(a: p128) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u64_p128(a: p128) -> uint64x2_t { - transmute(a) +pub fn vreinterpretq_u64_p128(a: p128) -> uint64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p128)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon,aes")] @@ -51214,14 +48764,14 @@ pub unsafe fn vreinterpretq_u64_p128(a: p128) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u64_p128(a: p128) -> uint64x2_t { - let ret_val: uint64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) +pub fn vreinterpretq_u64_p128(a: p128) -> uint64x2_t { + unsafe { + let ret_val: uint64x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p128)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon,aes")] @@ -51239,13 +48789,11 @@ pub unsafe fn vreinterpretq_u64_p128(a: p128) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p8_p128(a: p128) -> poly8x16_t { - transmute(a) +pub fn vreinterpretq_p8_p128(a: p128) -> poly8x16_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p128)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon,aes")] @@ -51263,18 +48811,18 @@ pub unsafe fn vreinterpretq_p8_p128(a: p128) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p8_p128(a: p128) -> poly8x16_t { - let ret_val: poly8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) +pub fn vreinterpretq_p8_p128(a: p128) -> poly8x16_t { + unsafe { + let ret_val: poly8x16_t = transmute(a); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p128)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon,aes")] @@ -51292,13 +48840,11 @@ pub unsafe fn vreinterpretq_p8_p128(a: p128) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p16_p128(a: p128) -> poly16x8_t { - transmute(a) +pub fn vreinterpretq_p16_p128(a: p128) -> poly16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p128)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon,aes")] @@ -51316,14 +48862,14 @@ pub unsafe fn vreinterpretq_p16_p128(a: p128) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p16_p128(a: p128) -> poly16x8_t { - let ret_val: poly16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) +pub fn vreinterpretq_p16_p128(a: p128) -> poly16x8_t { + unsafe { + let ret_val: poly16x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p128)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon,aes")] @@ -51341,13 +48887,11 @@ pub unsafe fn vreinterpretq_p16_p128(a: p128) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p64_p128(a: p128) -> poly64x2_t { - transmute(a) +pub fn vreinterpretq_p64_p128(a: p128) -> poly64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p128)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon,aes")] @@ -51365,14 +48909,14 @@ pub unsafe fn vreinterpretq_p64_p128(a: p128) -> poly64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p64_p128(a: p128) -> poly64x2_t { - let ret_val: poly64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) +pub fn vreinterpretq_p64_p128(a: p128) -> poly64x2_t { + unsafe { + let ret_val: poly64x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon,aes")] @@ -51390,13 +48934,11 @@ pub unsafe fn vreinterpretq_p64_p128(a: p128) -> poly64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_p64_s8(a: int8x8_t) -> poly64x1_t { - transmute(a) +pub fn vreinterpret_p64_s8(a: int8x8_t) -> poly64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon,aes")] @@ -51414,14 +48956,12 @@ pub unsafe fn vreinterpret_p64_s8(a: int8x8_t) -> poly64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_p64_s8(a: int8x8_t) -> poly64x1_t { +pub fn vreinterpret_p64_s8(a: int8x8_t) -> poly64x1_t { let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - transmute(a) + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon,aes")] @@ -51439,13 +48979,11 @@ pub unsafe fn vreinterpret_p64_s8(a: int8x8_t) -> poly64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p128_s8(a: int8x16_t) -> p128 { - transmute(a) +pub fn vreinterpretq_p128_s8(a: int8x16_t) -> p128 { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon,aes")] @@ -51463,14 +49001,12 @@ pub unsafe fn vreinterpretq_p128_s8(a: int8x16_t) -> p128 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p128_s8(a: int8x16_t) -> p128 { +pub fn vreinterpretq_p128_s8(a: int8x16_t) -> p128 { let a: int8x16_t = simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); - transmute(a) + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon,aes")] @@ -51488,13 +49024,11 @@ pub unsafe fn vreinterpretq_p128_s8(a: int8x16_t) -> p128 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p64_s8(a: int8x16_t) -> poly64x2_t { - transmute(a) +pub fn vreinterpretq_p64_s8(a: int8x16_t) -> poly64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon,aes")] @@ -51512,15 +49046,15 @@ pub unsafe fn vreinterpretq_p64_s8(a: int8x16_t) -> poly64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p64_s8(a: int8x16_t) -> poly64x2_t { +pub fn vreinterpretq_p64_s8(a: int8x16_t) -> poly64x2_t { let a: int8x16_t = simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: poly64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: poly64x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon,aes")] @@ -51538,13 +49072,11 @@ pub unsafe fn vreinterpretq_p64_s8(a: int8x16_t) -> poly64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_p64_s16(a: int16x4_t) -> poly64x1_t { - transmute(a) +pub fn vreinterpret_p64_s16(a: int16x4_t) -> poly64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon,aes")] @@ -51562,14 +49094,12 @@ pub unsafe fn vreinterpret_p64_s16(a: int16x4_t) -> poly64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_p64_s16(a: int16x4_t) -> poly64x1_t { +pub fn vreinterpret_p64_s16(a: int16x4_t) -> poly64x1_t { let a: int16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - transmute(a) + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon,aes")] @@ -51587,13 +49117,11 @@ pub unsafe fn vreinterpret_p64_s16(a: int16x4_t) -> poly64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p128_s16(a: int16x8_t) -> p128 { - transmute(a) +pub fn vreinterpretq_p128_s16(a: int16x8_t) -> p128 { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon,aes")] @@ -51611,14 +49139,12 @@ pub unsafe fn vreinterpretq_p128_s16(a: int16x8_t) -> p128 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p128_s16(a: int16x8_t) -> p128 { +pub fn vreinterpretq_p128_s16(a: int16x8_t) -> p128 { let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - transmute(a) + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon,aes")] @@ -51636,13 +49162,11 @@ pub unsafe fn vreinterpretq_p128_s16(a: int16x8_t) -> p128 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p64_s16(a: int16x8_t) -> poly64x2_t { - transmute(a) +pub fn vreinterpretq_p64_s16(a: int16x8_t) -> poly64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon,aes")] @@ -51660,15 +49184,15 @@ pub unsafe fn vreinterpretq_p64_s16(a: int16x8_t) -> poly64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p64_s16(a: int16x8_t) -> poly64x2_t { +pub fn vreinterpretq_p64_s16(a: int16x8_t) -> poly64x2_t { let a: int16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: poly64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: poly64x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon,aes")] @@ -51686,13 +49210,11 @@ pub unsafe fn vreinterpretq_p64_s16(a: int16x8_t) -> poly64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_p64_s32(a: int32x2_t) -> poly64x1_t { - transmute(a) +pub fn vreinterpret_p64_s32(a: int32x2_t) -> poly64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon,aes")] @@ -51710,14 +49232,12 @@ pub unsafe fn vreinterpret_p64_s32(a: int32x2_t) -> poly64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_p64_s32(a: int32x2_t) -> poly64x1_t { +pub fn vreinterpret_p64_s32(a: int32x2_t) -> poly64x1_t { let a: int32x2_t = simd_shuffle!(a, a, [1, 0]); - transmute(a) + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon,aes")] @@ -51735,13 +49255,11 @@ pub unsafe fn vreinterpret_p64_s32(a: int32x2_t) -> poly64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p128_s32(a: int32x4_t) -> p128 { - transmute(a) +pub fn vreinterpretq_p128_s32(a: int32x4_t) -> p128 { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon,aes")] @@ -51759,14 +49277,12 @@ pub unsafe fn vreinterpretq_p128_s32(a: int32x4_t) -> p128 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p128_s32(a: int32x4_t) -> p128 { +pub fn vreinterpretq_p128_s32(a: int32x4_t) -> p128 { let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - transmute(a) + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon,aes")] @@ -51784,13 +49300,11 @@ pub unsafe fn vreinterpretq_p128_s32(a: int32x4_t) -> p128 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p64_s32(a: int32x4_t) -> poly64x2_t { - transmute(a) +pub fn vreinterpretq_p64_s32(a: int32x4_t) -> poly64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon,aes")] @@ -51808,15 +49322,15 @@ pub unsafe fn vreinterpretq_p64_s32(a: int32x4_t) -> poly64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p64_s32(a: int32x4_t) -> poly64x2_t { +pub fn vreinterpretq_p64_s32(a: int32x4_t) -> poly64x2_t { let a: int32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - let ret_val: poly64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: poly64x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon,aes")] @@ -51834,13 +49348,11 @@ pub unsafe fn vreinterpretq_p64_s32(a: int32x4_t) -> poly64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p128_s64(a: int64x2_t) -> p128 { - transmute(a) +pub fn vreinterpretq_p128_s64(a: int64x2_t) -> p128 { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon,aes")] @@ -51858,14 +49370,12 @@ pub unsafe fn vreinterpretq_p128_s64(a: int64x2_t) -> p128 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p128_s64(a: int64x2_t) -> p128 { +pub fn vreinterpretq_p128_s64(a: int64x2_t) -> p128 { let a: int64x2_t = simd_shuffle!(a, a, [1, 0]); - transmute(a) + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon,aes")] @@ -51883,13 +49393,11 @@ pub unsafe fn vreinterpretq_p128_s64(a: int64x2_t) -> p128 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_p64_u8(a: uint8x8_t) -> poly64x1_t { - transmute(a) +pub fn vreinterpret_p64_u8(a: uint8x8_t) -> poly64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon,aes")] @@ -51907,14 +49415,12 @@ pub unsafe fn vreinterpret_p64_u8(a: uint8x8_t) -> poly64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_p64_u8(a: uint8x8_t) -> poly64x1_t { +pub fn vreinterpret_p64_u8(a: uint8x8_t) -> poly64x1_t { let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - transmute(a) + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon,aes")] @@ -51932,13 +49438,11 @@ pub unsafe fn vreinterpret_p64_u8(a: uint8x8_t) -> poly64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p128_u8(a: uint8x16_t) -> p128 { - transmute(a) +pub fn vreinterpretq_p128_u8(a: uint8x16_t) -> p128 { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon,aes")] @@ -51956,14 +49460,12 @@ pub unsafe fn vreinterpretq_p128_u8(a: uint8x16_t) -> p128 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p128_u8(a: uint8x16_t) -> p128 { +pub fn vreinterpretq_p128_u8(a: uint8x16_t) -> p128 { let a: uint8x16_t = simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); - transmute(a) + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon,aes")] @@ -51981,13 +49483,11 @@ pub unsafe fn vreinterpretq_p128_u8(a: uint8x16_t) -> p128 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p64_u8(a: uint8x16_t) -> poly64x2_t { - transmute(a) +pub fn vreinterpretq_p64_u8(a: uint8x16_t) -> poly64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon,aes")] @@ -52005,15 +49505,15 @@ pub unsafe fn vreinterpretq_p64_u8(a: uint8x16_t) -> poly64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p64_u8(a: uint8x16_t) -> poly64x2_t { +pub fn vreinterpretq_p64_u8(a: uint8x16_t) -> poly64x2_t { let a: uint8x16_t = simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: poly64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: poly64x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon,aes")] @@ -52031,13 +49531,11 @@ pub unsafe fn vreinterpretq_p64_u8(a: uint8x16_t) -> poly64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_p64_u16(a: uint16x4_t) -> poly64x1_t { - transmute(a) +pub fn vreinterpret_p64_u16(a: uint16x4_t) -> poly64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon,aes")] @@ -52055,14 +49553,12 @@ pub unsafe fn vreinterpret_p64_u16(a: uint16x4_t) -> poly64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_p64_u16(a: uint16x4_t) -> poly64x1_t { +pub fn vreinterpret_p64_u16(a: uint16x4_t) -> poly64x1_t { let a: uint16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - transmute(a) + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon,aes")] @@ -52080,13 +49576,11 @@ pub unsafe fn vreinterpret_p64_u16(a: uint16x4_t) -> poly64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p128_u16(a: uint16x8_t) -> p128 { - transmute(a) +pub fn vreinterpretq_p128_u16(a: uint16x8_t) -> p128 { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon,aes")] @@ -52104,14 +49598,12 @@ pub unsafe fn vreinterpretq_p128_u16(a: uint16x8_t) -> p128 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p128_u16(a: uint16x8_t) -> p128 { +pub fn vreinterpretq_p128_u16(a: uint16x8_t) -> p128 { let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - transmute(a) + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon,aes")] @@ -52129,13 +49621,11 @@ pub unsafe fn vreinterpretq_p128_u16(a: uint16x8_t) -> p128 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p64_u16(a: uint16x8_t) -> poly64x2_t { - transmute(a) +pub fn vreinterpretq_p64_u16(a: uint16x8_t) -> poly64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon,aes")] @@ -52153,15 +49643,15 @@ pub unsafe fn vreinterpretq_p64_u16(a: uint16x8_t) -> poly64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p64_u16(a: uint16x8_t) -> poly64x2_t { +pub fn vreinterpretq_p64_u16(a: uint16x8_t) -> poly64x2_t { let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: poly64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: poly64x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon,aes")] @@ -52179,13 +49669,11 @@ pub unsafe fn vreinterpretq_p64_u16(a: uint16x8_t) -> poly64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_p64_u32(a: uint32x2_t) -> poly64x1_t { - transmute(a) +pub fn vreinterpret_p64_u32(a: uint32x2_t) -> poly64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon,aes")] @@ -52203,14 +49691,12 @@ pub unsafe fn vreinterpret_p64_u32(a: uint32x2_t) -> poly64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_p64_u32(a: uint32x2_t) -> poly64x1_t { +pub fn vreinterpret_p64_u32(a: uint32x2_t) -> poly64x1_t { let a: uint32x2_t = simd_shuffle!(a, a, [1, 0]); - transmute(a) + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon,aes")] @@ -52228,13 +49714,11 @@ pub unsafe fn vreinterpret_p64_u32(a: uint32x2_t) -> poly64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p128_u32(a: uint32x4_t) -> p128 { - transmute(a) +pub fn vreinterpretq_p128_u32(a: uint32x4_t) -> p128 { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon,aes")] @@ -52252,14 +49736,12 @@ pub unsafe fn vreinterpretq_p128_u32(a: uint32x4_t) -> p128 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p128_u32(a: uint32x4_t) -> p128 { +pub fn vreinterpretq_p128_u32(a: uint32x4_t) -> p128 { let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - transmute(a) + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon,aes")] @@ -52277,13 +49759,11 @@ pub unsafe fn vreinterpretq_p128_u32(a: uint32x4_t) -> p128 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p64_u32(a: uint32x4_t) -> poly64x2_t { - transmute(a) +pub fn vreinterpretq_p64_u32(a: uint32x4_t) -> poly64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon,aes")] @@ -52301,15 +49781,15 @@ pub unsafe fn vreinterpretq_p64_u32(a: uint32x4_t) -> poly64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p64_u32(a: uint32x4_t) -> poly64x2_t { +pub fn vreinterpretq_p64_u32(a: uint32x4_t) -> poly64x2_t { let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - let ret_val: poly64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: poly64x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon,aes")] @@ -52327,13 +49807,11 @@ pub unsafe fn vreinterpretq_p64_u32(a: uint32x4_t) -> poly64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p128_u64(a: uint64x2_t) -> p128 { - transmute(a) +pub fn vreinterpretq_p128_u64(a: uint64x2_t) -> p128 { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon,aes")] @@ -52351,14 +49829,12 @@ pub unsafe fn vreinterpretq_p128_u64(a: uint64x2_t) -> p128 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p128_u64(a: uint64x2_t) -> p128 { +pub fn vreinterpretq_p128_u64(a: uint64x2_t) -> p128 { let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]); - transmute(a) + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon,aes")] @@ -52376,13 +49852,11 @@ pub unsafe fn vreinterpretq_p128_u64(a: uint64x2_t) -> p128 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_p64_p8(a: poly8x8_t) -> poly64x1_t { - transmute(a) +pub fn vreinterpret_p64_p8(a: poly8x8_t) -> poly64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon,aes")] @@ -52400,14 +49874,12 @@ pub unsafe fn vreinterpret_p64_p8(a: poly8x8_t) -> poly64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_p64_p8(a: poly8x8_t) -> poly64x1_t { +pub fn vreinterpret_p64_p8(a: poly8x8_t) -> poly64x1_t { let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - transmute(a) + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon,aes")] @@ -52425,13 +49897,11 @@ pub unsafe fn vreinterpret_p64_p8(a: poly8x8_t) -> poly64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p128_p8(a: poly8x16_t) -> p128 { - transmute(a) +pub fn vreinterpretq_p128_p8(a: poly8x16_t) -> p128 { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon,aes")] @@ -52449,14 +49919,12 @@ pub unsafe fn vreinterpretq_p128_p8(a: poly8x16_t) -> p128 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p128_p8(a: poly8x16_t) -> p128 { +pub fn vreinterpretq_p128_p8(a: poly8x16_t) -> p128 { let a: poly8x16_t = simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); - transmute(a) + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon,aes")] @@ -52474,13 +49942,11 @@ pub unsafe fn vreinterpretq_p128_p8(a: poly8x16_t) -> p128 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p64_p8(a: poly8x16_t) -> poly64x2_t { - transmute(a) +pub fn vreinterpretq_p64_p8(a: poly8x16_t) -> poly64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon,aes")] @@ -52498,15 +49964,15 @@ pub unsafe fn vreinterpretq_p64_p8(a: poly8x16_t) -> poly64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p64_p8(a: poly8x16_t) -> poly64x2_t { +pub fn vreinterpretq_p64_p8(a: poly8x16_t) -> poly64x2_t { let a: poly8x16_t = simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: poly64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: poly64x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon,aes")] @@ -52524,13 +49990,11 @@ pub unsafe fn vreinterpretq_p64_p8(a: poly8x16_t) -> poly64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_p64_p16(a: poly16x4_t) -> poly64x1_t { - transmute(a) +pub fn vreinterpret_p64_p16(a: poly16x4_t) -> poly64x1_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon,aes")] @@ -52548,14 +50012,12 @@ pub unsafe fn vreinterpret_p64_p16(a: poly16x4_t) -> poly64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_p64_p16(a: poly16x4_t) -> poly64x1_t { +pub fn vreinterpret_p64_p16(a: poly16x4_t) -> poly64x1_t { let a: poly16x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); - transmute(a) + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon,aes")] @@ -52573,13 +50035,11 @@ pub unsafe fn vreinterpret_p64_p16(a: poly16x4_t) -> poly64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p128_p16(a: poly16x8_t) -> p128 { - transmute(a) +pub fn vreinterpretq_p128_p16(a: poly16x8_t) -> p128 { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon,aes")] @@ -52597,14 +50057,12 @@ pub unsafe fn vreinterpretq_p128_p16(a: poly16x8_t) -> p128 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p128_p16(a: poly16x8_t) -> p128 { +pub fn vreinterpretq_p128_p16(a: poly16x8_t) -> p128 { let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - transmute(a) + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon,aes")] @@ -52622,13 +50080,11 @@ pub unsafe fn vreinterpretq_p128_p16(a: poly16x8_t) -> p128 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p64_p16(a: poly16x8_t) -> poly64x2_t { - transmute(a) +pub fn vreinterpretq_p64_p16(a: poly16x8_t) -> poly64x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon,aes")] @@ -52646,15 +50102,15 @@ pub unsafe fn vreinterpretq_p64_p16(a: poly16x8_t) -> poly64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p64_p16(a: poly16x8_t) -> poly64x2_t { +pub fn vreinterpretq_p64_p16(a: poly16x8_t) -> poly64x2_t { let a: poly16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: poly64x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: poly64x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon,aes")] @@ -52672,13 +50128,11 @@ pub unsafe fn vreinterpretq_p64_p16(a: poly16x8_t) -> poly64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s8_p64(a: poly64x1_t) -> int8x8_t { - transmute(a) +pub fn vreinterpret_s8_p64(a: poly64x1_t) -> int8x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon,aes")] @@ -52696,14 +50150,14 @@ pub unsafe fn vreinterpret_s8_p64(a: poly64x1_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s8_p64(a: poly64x1_t) -> int8x8_t { - let ret_val: int8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) +pub fn vreinterpret_s8_p64(a: poly64x1_t) -> int8x8_t { + unsafe { + let ret_val: int8x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon,aes")] @@ -52721,13 +50175,11 @@ pub unsafe fn vreinterpret_s8_p64(a: poly64x1_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s16_p64(a: poly64x1_t) -> int16x4_t { - transmute(a) +pub fn vreinterpret_s16_p64(a: poly64x1_t) -> int16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon,aes")] @@ -52745,14 +50197,14 @@ pub unsafe fn vreinterpret_s16_p64(a: poly64x1_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s16_p64(a: poly64x1_t) -> int16x4_t { - let ret_val: int16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) +pub fn vreinterpret_s16_p64(a: poly64x1_t) -> int16x4_t { + unsafe { + let ret_val: int16x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon,aes")] @@ -52770,13 +50222,11 @@ pub unsafe fn vreinterpret_s16_p64(a: poly64x1_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s32_p64(a: poly64x1_t) -> int32x2_t { - transmute(a) +pub fn vreinterpret_s32_p64(a: poly64x1_t) -> int32x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon,aes")] @@ -52794,14 +50244,14 @@ pub unsafe fn vreinterpret_s32_p64(a: poly64x1_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_s32_p64(a: poly64x1_t) -> int32x2_t { - let ret_val: int32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) +pub fn vreinterpret_s32_p64(a: poly64x1_t) -> int32x2_t { + unsafe { + let ret_val: int32x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon,aes")] @@ -52819,13 +50269,11 @@ pub unsafe fn vreinterpret_s32_p64(a: poly64x1_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u8_p64(a: poly64x1_t) -> uint8x8_t { - transmute(a) +pub fn vreinterpret_u8_p64(a: poly64x1_t) -> uint8x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon,aes")] @@ -52843,14 +50291,14 @@ pub unsafe fn vreinterpret_u8_p64(a: poly64x1_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u8_p64(a: poly64x1_t) -> uint8x8_t { - let ret_val: uint8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) +pub fn vreinterpret_u8_p64(a: poly64x1_t) -> uint8x8_t { + unsafe { + let ret_val: uint8x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon,aes")] @@ -52868,13 +50316,11 @@ pub unsafe fn vreinterpret_u8_p64(a: poly64x1_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u16_p64(a: poly64x1_t) -> uint16x4_t { - transmute(a) +pub fn vreinterpret_u16_p64(a: poly64x1_t) -> uint16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon,aes")] @@ -52892,14 +50338,14 @@ pub unsafe fn vreinterpret_u16_p64(a: poly64x1_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u16_p64(a: poly64x1_t) -> uint16x4_t { - let ret_val: uint16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) +pub fn vreinterpret_u16_p64(a: poly64x1_t) -> uint16x4_t { + unsafe { + let ret_val: uint16x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon,aes")] @@ -52917,13 +50363,11 @@ pub unsafe fn vreinterpret_u16_p64(a: poly64x1_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u32_p64(a: poly64x1_t) -> uint32x2_t { - transmute(a) +pub fn vreinterpret_u32_p64(a: poly64x1_t) -> uint32x2_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon,aes")] @@ -52941,14 +50385,14 @@ pub unsafe fn vreinterpret_u32_p64(a: poly64x1_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_u32_p64(a: poly64x1_t) -> uint32x2_t { - let ret_val: uint32x2_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [1, 0]) +pub fn vreinterpret_u32_p64(a: poly64x1_t) -> uint32x2_t { + unsafe { + let ret_val: uint32x2_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon,aes")] @@ -52966,13 +50410,11 @@ pub unsafe fn vreinterpret_u32_p64(a: poly64x1_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_p8_p64(a: poly64x1_t) -> poly8x8_t { - transmute(a) +pub fn vreinterpret_p8_p64(a: poly64x1_t) -> poly8x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon,aes")] @@ -52990,14 +50432,14 @@ pub unsafe fn vreinterpret_p8_p64(a: poly64x1_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_p8_p64(a: poly64x1_t) -> poly8x8_t { - let ret_val: poly8x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) +pub fn vreinterpret_p8_p64(a: poly64x1_t) -> poly8x8_t { + unsafe { + let ret_val: poly8x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon,aes")] @@ -53015,13 +50457,11 @@ pub unsafe fn vreinterpret_p8_p64(a: poly64x1_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_p16_p64(a: poly64x1_t) -> poly16x4_t { - transmute(a) +pub fn vreinterpret_p16_p64(a: poly64x1_t) -> poly16x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon,aes")] @@ -53039,14 +50479,14 @@ pub unsafe fn vreinterpret_p16_p64(a: poly64x1_t) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpret_p16_p64(a: poly64x1_t) -> poly16x4_t { - let ret_val: poly16x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) +pub fn vreinterpret_p16_p64(a: poly64x1_t) -> poly16x4_t { + unsafe { + let ret_val: poly16x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon,aes")] @@ -53064,13 +50504,11 @@ pub unsafe fn vreinterpret_p16_p64(a: poly64x1_t) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p128_p64(a: poly64x2_t) -> p128 { - transmute(a) +pub fn vreinterpretq_p128_p64(a: poly64x2_t) -> p128 { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon,aes")] @@ -53088,14 +50526,12 @@ pub unsafe fn vreinterpretq_p128_p64(a: poly64x2_t) -> p128 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p128_p64(a: poly64x2_t) -> p128 { +pub fn vreinterpretq_p128_p64(a: poly64x2_t) -> p128 { let a: poly64x2_t = simd_shuffle!(a, a, [1, 0]); - transmute(a) + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon,aes")] @@ -53113,13 +50549,11 @@ pub unsafe fn vreinterpretq_p128_p64(a: poly64x2_t) -> p128 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s8_p64(a: poly64x2_t) -> int8x16_t { - transmute(a) +pub fn vreinterpretq_s8_p64(a: poly64x2_t) -> int8x16_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon,aes")] @@ -53137,19 +50571,19 @@ pub unsafe fn vreinterpretq_s8_p64(a: poly64x2_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s8_p64(a: poly64x2_t) -> int8x16_t { +pub fn vreinterpretq_s8_p64(a: poly64x2_t) -> int8x16_t { let a: poly64x2_t = simd_shuffle!(a, a, [1, 0]); - let ret_val: int8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) + unsafe { + let ret_val: int8x16_t = transmute(a); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon,aes")] @@ -53167,13 +50601,11 @@ pub unsafe fn vreinterpretq_s8_p64(a: poly64x2_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s16_p64(a: poly64x2_t) -> int16x8_t { - transmute(a) +pub fn vreinterpretq_s16_p64(a: poly64x2_t) -> int16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon,aes")] @@ -53191,15 +50623,15 @@ pub unsafe fn vreinterpretq_s16_p64(a: poly64x2_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s16_p64(a: poly64x2_t) -> int16x8_t { +pub fn vreinterpretq_s16_p64(a: poly64x2_t) -> int16x8_t { let a: poly64x2_t = simd_shuffle!(a, a, [1, 0]); - let ret_val: int16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: int16x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon,aes")] @@ -53217,13 +50649,11 @@ pub unsafe fn vreinterpretq_s16_p64(a: poly64x2_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s32_p64(a: poly64x2_t) -> int32x4_t { - transmute(a) +pub fn vreinterpretq_s32_p64(a: poly64x2_t) -> int32x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon,aes")] @@ -53241,15 +50671,15 @@ pub unsafe fn vreinterpretq_s32_p64(a: poly64x2_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_s32_p64(a: poly64x2_t) -> int32x4_t { +pub fn vreinterpretq_s32_p64(a: poly64x2_t) -> int32x4_t { let a: poly64x2_t = simd_shuffle!(a, a, [1, 0]); - let ret_val: int32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + unsafe { + let ret_val: int32x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon,aes")] @@ -53267,13 +50697,11 @@ pub unsafe fn vreinterpretq_s32_p64(a: poly64x2_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u8_p64(a: poly64x2_t) -> uint8x16_t { - transmute(a) +pub fn vreinterpretq_u8_p64(a: poly64x2_t) -> uint8x16_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon,aes")] @@ -53291,19 +50719,19 @@ pub unsafe fn vreinterpretq_u8_p64(a: poly64x2_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u8_p64(a: poly64x2_t) -> uint8x16_t { +pub fn vreinterpretq_u8_p64(a: poly64x2_t) -> uint8x16_t { let a: poly64x2_t = simd_shuffle!(a, a, [1, 0]); - let ret_val: uint8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) + unsafe { + let ret_val: uint8x16_t = transmute(a); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon,aes")] @@ -53321,13 +50749,11 @@ pub unsafe fn vreinterpretq_u8_p64(a: poly64x2_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u16_p64(a: poly64x2_t) -> uint16x8_t { - transmute(a) +pub fn vreinterpretq_u16_p64(a: poly64x2_t) -> uint16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon,aes")] @@ -53345,15 +50771,15 @@ pub unsafe fn vreinterpretq_u16_p64(a: poly64x2_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u16_p64(a: poly64x2_t) -> uint16x8_t { +pub fn vreinterpretq_u16_p64(a: poly64x2_t) -> uint16x8_t { let a: poly64x2_t = simd_shuffle!(a, a, [1, 0]); - let ret_val: uint16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: uint16x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon,aes")] @@ -53371,13 +50797,11 @@ pub unsafe fn vreinterpretq_u16_p64(a: poly64x2_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u32_p64(a: poly64x2_t) -> uint32x4_t { - transmute(a) +pub fn vreinterpretq_u32_p64(a: poly64x2_t) -> uint32x4_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon,aes")] @@ -53395,15 +50819,15 @@ pub unsafe fn vreinterpretq_u32_p64(a: poly64x2_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_u32_p64(a: poly64x2_t) -> uint32x4_t { +pub fn vreinterpretq_u32_p64(a: poly64x2_t) -> uint32x4_t { let a: poly64x2_t = simd_shuffle!(a, a, [1, 0]); - let ret_val: uint32x4_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + unsafe { + let ret_val: uint32x4_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon,aes")] @@ -53421,13 +50845,11 @@ pub unsafe fn vreinterpretq_u32_p64(a: poly64x2_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p8_p64(a: poly64x2_t) -> poly8x16_t { - transmute(a) +pub fn vreinterpretq_p8_p64(a: poly64x2_t) -> poly8x16_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon,aes")] @@ -53445,19 +50867,19 @@ pub unsafe fn vreinterpretq_p8_p64(a: poly64x2_t) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p8_p64(a: poly64x2_t) -> poly8x16_t { +pub fn vreinterpretq_p8_p64(a: poly64x2_t) -> poly8x16_t { let a: poly64x2_t = simd_shuffle!(a, a, [1, 0]); - let ret_val: poly8x16_t = transmute(a); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) + unsafe { + let ret_val: poly8x16_t = transmute(a); + simd_shuffle!( + ret_val, + ret_val, + [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] + ) + } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon,aes")] @@ -53475,13 +50897,11 @@ pub unsafe fn vreinterpretq_p8_p64(a: poly64x2_t) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p16_p64(a: poly64x2_t) -> poly16x8_t { - transmute(a) +pub fn vreinterpretq_p16_p64(a: poly64x2_t) -> poly16x8_t { + unsafe { transmute(a) } } #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon,aes")] @@ -53499,15 +50919,15 @@ pub unsafe fn vreinterpretq_p16_p64(a: poly64x2_t) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vreinterpretq_p16_p64(a: poly64x2_t) -> poly16x8_t { +pub fn vreinterpretq_p16_p64(a: poly64x2_t) -> poly16x8_t { let a: poly64x2_t = simd_shuffle!(a, a, [1, 0]); - let ret_val: poly16x8_t = transmute(a); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: poly16x8_t = transmute(a); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Reverse elements in 64-bit doublewords"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrev64))] @@ -53517,13 +50937,11 @@ pub unsafe fn vreinterpretq_p16_p64(a: poly64x2_t) -> poly16x8_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vrev64_f16(a: float16x4_t) -> float16x4_t { - simd_shuffle!(a, a, [3, 2, 1, 0]) +pub fn vrev64_f16(a: float16x4_t) -> float16x4_t { + unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) } } #[doc = "Reverse elements in 64-bit doublewords"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrev64))] @@ -53533,13 +50951,11 @@ pub unsafe fn vrev64_f16(a: float16x4_t) -> float16x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vrev64q_f16(a: float16x8_t) -> float16x8_t { - simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]) +pub fn vrev64q_f16(a: float16x8_t) -> float16x8_t { + unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]) } } #[doc = "Rounding halving add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -53556,7 +50972,7 @@ pub unsafe fn vrev64q_f16(a: float16x8_t) -> float16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrhadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { +pub fn vrhadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -53565,12 +50981,10 @@ pub unsafe fn vrhadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhadds.v8i8")] fn _vrhadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t; } - _vrhadd_s8(a, b) + unsafe { _vrhadd_s8(a, b) } } #[doc = "Rounding halving add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -53587,7 +51001,7 @@ pub unsafe fn vrhadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrhaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { +pub fn vrhaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -53596,12 +51010,10 @@ pub unsafe fn vrhaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhadds.v16i8")] fn _vrhaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t; } - _vrhaddq_s8(a, b) + unsafe { _vrhaddq_s8(a, b) } } #[doc = "Rounding halving add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -53618,7 +51030,7 @@ pub unsafe fn vrhaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrhadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { +pub fn vrhadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -53627,12 +51039,10 @@ pub unsafe fn vrhadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhadds.v4i16")] fn _vrhadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t; } - _vrhadd_s16(a, b) + unsafe { _vrhadd_s16(a, b) } } #[doc = "Rounding halving add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -53649,7 +51059,7 @@ pub unsafe fn vrhadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrhaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { +pub fn vrhaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -53658,12 +51068,10 @@ pub unsafe fn vrhaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhadds.v8i16")] fn _vrhaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t; } - _vrhaddq_s16(a, b) + unsafe { _vrhaddq_s16(a, b) } } #[doc = "Rounding halving add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -53680,7 +51088,7 @@ pub unsafe fn vrhaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrhadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { +pub fn vrhadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -53689,12 +51097,10 @@ pub unsafe fn vrhadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhadds.v2i32")] fn _vrhadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t; } - _vrhadd_s32(a, b) + unsafe { _vrhadd_s32(a, b) } } #[doc = "Rounding halving add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -53711,7 +51117,7 @@ pub unsafe fn vrhadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrhaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { +pub fn vrhaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -53720,12 +51126,10 @@ pub unsafe fn vrhaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhadds.v4i32")] fn _vrhaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t; } - _vrhaddq_s32(a, b) + unsafe { _vrhaddq_s32(a, b) } } #[doc = "Rounding halving add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -53742,7 +51146,7 @@ pub unsafe fn vrhaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrhadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { +pub fn vrhadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -53751,12 +51155,10 @@ pub unsafe fn vrhadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhaddu.v8i8")] fn _vrhadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t; } - _vrhadd_u8(a, b) + unsafe { _vrhadd_u8(a, b) } } #[doc = "Rounding halving add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -53773,7 +51175,7 @@ pub unsafe fn vrhadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrhaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { +pub fn vrhaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -53782,12 +51184,10 @@ pub unsafe fn vrhaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhaddu.v16i8")] fn _vrhaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t; } - _vrhaddq_u8(a, b) + unsafe { _vrhaddq_u8(a, b) } } #[doc = "Rounding halving add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -53804,7 +51204,7 @@ pub unsafe fn vrhaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrhadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { +pub fn vrhadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -53813,12 +51213,10 @@ pub unsafe fn vrhadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhaddu.v4i16")] fn _vrhadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t; } - _vrhadd_u16(a, b) + unsafe { _vrhadd_u16(a, b) } } #[doc = "Rounding halving add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -53835,7 +51233,7 @@ pub unsafe fn vrhadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrhaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { +pub fn vrhaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -53844,12 +51242,10 @@ pub unsafe fn vrhaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhaddu.v8i16")] fn _vrhaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t; } - _vrhaddq_u16(a, b) + unsafe { _vrhaddq_u16(a, b) } } #[doc = "Rounding halving add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -53866,7 +51262,7 @@ pub unsafe fn vrhaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrhadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { +pub fn vrhadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -53875,12 +51271,10 @@ pub unsafe fn vrhadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhaddu.v2i32")] fn _vrhadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t; } - _vrhadd_u32(a, b) + unsafe { _vrhadd_u32(a, b) } } #[doc = "Rounding halving add"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -53897,7 +51291,7 @@ pub unsafe fn vrhadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrhaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { +pub fn vrhaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -53906,12 +51300,10 @@ pub unsafe fn vrhaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhaddu.v4i32")] fn _vrhaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t; } - _vrhaddq_u32(a, b) + unsafe { _vrhaddq_u32(a, b) } } #[doc = "Floating-point round to integral, to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndn_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrintn))] @@ -53921,7 +51313,7 @@ pub unsafe fn vrhaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vrndn_f16(a: float16x4_t) -> float16x4_t { +pub fn vrndn_f16(a: float16x4_t) -> float16x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -53930,12 +51322,10 @@ pub unsafe fn vrndn_f16(a: float16x4_t) -> float16x4_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrintn.v4f16")] fn _vrndn_f16(a: float16x4_t) -> float16x4_t; } - _vrndn_f16(a) + unsafe { _vrndn_f16(a) } } #[doc = "Floating-point round to integral, to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndnq_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrintn))] @@ -53945,7 +51335,7 @@ pub unsafe fn vrndn_f16(a: float16x4_t) -> float16x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vrndnq_f16(a: float16x8_t) -> float16x8_t { +pub fn vrndnq_f16(a: float16x8_t) -> float16x8_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -53954,12 +51344,10 @@ pub unsafe fn vrndnq_f16(a: float16x8_t) -> float16x8_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrintn.v8f16")] fn _vrndnq_f16(a: float16x8_t) -> float16x8_t; } - _vrndnq_f16(a) + unsafe { _vrndnq_f16(a) } } #[doc = "Floating-point round to integral, to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndn_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))] @@ -53976,7 +51364,7 @@ pub unsafe fn vrndnq_f16(a: float16x8_t) -> float16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrndn_f32(a: float32x2_t) -> float32x2_t { +pub fn vrndn_f32(a: float32x2_t) -> float32x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -53985,12 +51373,10 @@ pub unsafe fn vrndn_f32(a: float32x2_t) -> float32x2_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrintn.v2f32")] fn _vrndn_f32(a: float32x2_t) -> float32x2_t; } - _vrndn_f32(a) + unsafe { _vrndn_f32(a) } } #[doc = "Floating-point round to integral, to nearest with ties to even"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndnq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))] @@ -54007,7 +51393,7 @@ pub unsafe fn vrndn_f32(a: float32x2_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrndnq_f32(a: float32x4_t) -> float32x4_t { +pub fn vrndnq_f32(a: float32x4_t) -> float32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -54016,12 +51402,10 @@ pub unsafe fn vrndnq_f32(a: float32x4_t) -> float32x4_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrintn.v4f32")] fn _vrndnq_f32(a: float32x4_t) -> float32x4_t; } - _vrndnq_f32(a) + unsafe { _vrndnq_f32(a) } } #[doc = "Signed rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -54038,7 +51422,7 @@ pub unsafe fn vrndnq_f32(a: float32x4_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { +pub fn vrshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshifts.v8i8")] #[cfg_attr( @@ -54047,12 +51431,10 @@ pub unsafe fn vrshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { )] fn _vrshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t; } - _vrshl_s8(a, b) + unsafe { _vrshl_s8(a, b) } } #[doc = "Signed rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -54069,7 +51451,7 @@ pub unsafe fn vrshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { +pub fn vrshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshifts.v16i8")] #[cfg_attr( @@ -54078,12 +51460,10 @@ pub unsafe fn vrshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { )] fn _vrshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t; } - _vrshlq_s8(a, b) + unsafe { _vrshlq_s8(a, b) } } #[doc = "Signed rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -54100,7 +51480,7 @@ pub unsafe fn vrshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { +pub fn vrshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshifts.v4i16")] #[cfg_attr( @@ -54109,12 +51489,10 @@ pub unsafe fn vrshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { )] fn _vrshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t; } - _vrshl_s16(a, b) + unsafe { _vrshl_s16(a, b) } } #[doc = "Signed rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -54131,7 +51509,7 @@ pub unsafe fn vrshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { +pub fn vrshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshifts.v8i16")] #[cfg_attr( @@ -54140,12 +51518,10 @@ pub unsafe fn vrshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { )] fn _vrshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t; } - _vrshlq_s16(a, b) + unsafe { _vrshlq_s16(a, b) } } #[doc = "Signed rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -54162,7 +51538,7 @@ pub unsafe fn vrshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { +pub fn vrshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshifts.v2i32")] #[cfg_attr( @@ -54171,12 +51547,10 @@ pub unsafe fn vrshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { )] fn _vrshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t; } - _vrshl_s32(a, b) + unsafe { _vrshl_s32(a, b) } } #[doc = "Signed rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -54193,7 +51567,7 @@ pub unsafe fn vrshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { +pub fn vrshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshifts.v4i32")] #[cfg_attr( @@ -54202,12 +51576,10 @@ pub unsafe fn vrshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { )] fn _vrshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t; } - _vrshlq_s32(a, b) + unsafe { _vrshlq_s32(a, b) } } #[doc = "Signed rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -54224,7 +51596,7 @@ pub unsafe fn vrshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { +pub fn vrshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshifts.v1i64")] #[cfg_attr( @@ -54233,12 +51605,10 @@ pub unsafe fn vrshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { )] fn _vrshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t; } - _vrshl_s64(a, b) + unsafe { _vrshl_s64(a, b) } } #[doc = "Signed rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -54255,7 +51625,7 @@ pub unsafe fn vrshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { +pub fn vrshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshifts.v2i64")] #[cfg_attr( @@ -54264,12 +51634,10 @@ pub unsafe fn vrshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { )] fn _vrshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t; } - _vrshlq_s64(a, b) + unsafe { _vrshlq_s64(a, b) } } #[doc = "Unsigned rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -54286,7 +51654,7 @@ pub unsafe fn vrshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t { +pub fn vrshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftu.v8i8")] #[cfg_attr( @@ -54295,12 +51663,10 @@ pub unsafe fn vrshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t { )] fn _vrshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t; } - _vrshl_u8(a, b) + unsafe { _vrshl_u8(a, b) } } #[doc = "Unsigned rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -54317,7 +51683,7 @@ pub unsafe fn vrshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t { +pub fn vrshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftu.v16i8")] #[cfg_attr( @@ -54326,12 +51692,10 @@ pub unsafe fn vrshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t { )] fn _vrshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t; } - _vrshlq_u8(a, b) + unsafe { _vrshlq_u8(a, b) } } #[doc = "Unsigned rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -54348,7 +51712,7 @@ pub unsafe fn vrshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t { +pub fn vrshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftu.v4i16")] #[cfg_attr( @@ -54357,12 +51721,10 @@ pub unsafe fn vrshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t { )] fn _vrshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t; } - _vrshl_u16(a, b) + unsafe { _vrshl_u16(a, b) } } #[doc = "Unsigned rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -54379,7 +51741,7 @@ pub unsafe fn vrshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t { +pub fn vrshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftu.v8i16")] #[cfg_attr( @@ -54388,12 +51750,10 @@ pub unsafe fn vrshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t { )] fn _vrshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t; } - _vrshlq_u16(a, b) + unsafe { _vrshlq_u16(a, b) } } #[doc = "Unsigned rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -54410,7 +51770,7 @@ pub unsafe fn vrshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t { +pub fn vrshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftu.v2i32")] #[cfg_attr( @@ -54419,12 +51779,10 @@ pub unsafe fn vrshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t { )] fn _vrshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t; } - _vrshl_u32(a, b) + unsafe { _vrshl_u32(a, b) } } #[doc = "Unsigned rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -54441,7 +51799,7 @@ pub unsafe fn vrshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t { +pub fn vrshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftu.v4i32")] #[cfg_attr( @@ -54450,12 +51808,10 @@ pub unsafe fn vrshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t { )] fn _vrshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t; } - _vrshlq_u32(a, b) + unsafe { _vrshlq_u32(a, b) } } #[doc = "Unsigned rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -54472,7 +51828,7 @@ pub unsafe fn vrshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t { +pub fn vrshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftu.v1i64")] #[cfg_attr( @@ -54481,12 +51837,10 @@ pub unsafe fn vrshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t { )] fn _vrshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t; } - _vrshl_u64(a, b) + unsafe { _vrshl_u64(a, b) } } #[doc = "Unsigned rounding shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -54503,7 +51857,7 @@ pub unsafe fn vrshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t { +pub fn vrshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftu.v2i64")] #[cfg_attr( @@ -54512,12 +51866,10 @@ pub unsafe fn vrshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t { )] fn _vrshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t; } - _vrshlq_u64(a, b) + unsafe { _vrshlq_u64(a, b) } } #[doc = "Signed rounding shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -54535,14 +51887,12 @@ pub unsafe fn vrshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrshr_n_s8(a: int8x8_t) -> int8x8_t { +pub fn vrshr_n_s8(a: int8x8_t) -> int8x8_t { static_assert!(N >= 1 && N <= 8); vrshl_s8(a, vdup_n_s8(-N as _)) } #[doc = "Signed rounding shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -54560,14 +51910,12 @@ pub unsafe fn vrshr_n_s8(a: int8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrshrq_n_s8(a: int8x16_t) -> int8x16_t { +pub fn vrshrq_n_s8(a: int8x16_t) -> int8x16_t { static_assert!(N >= 1 && N <= 8); vrshlq_s8(a, vdupq_n_s8(-N as _)) } #[doc = "Signed rounding shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -54585,14 +51933,12 @@ pub unsafe fn vrshrq_n_s8(a: int8x16_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrshr_n_s16(a: int16x4_t) -> int16x4_t { +pub fn vrshr_n_s16(a: int16x4_t) -> int16x4_t { static_assert!(N >= 1 && N <= 16); vrshl_s16(a, vdup_n_s16(-N as _)) } #[doc = "Signed rounding shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -54610,14 +51956,12 @@ pub unsafe fn vrshr_n_s16(a: int16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrshrq_n_s16(a: int16x8_t) -> int16x8_t { +pub fn vrshrq_n_s16(a: int16x8_t) -> int16x8_t { static_assert!(N >= 1 && N <= 16); vrshlq_s16(a, vdupq_n_s16(-N as _)) } #[doc = "Signed rounding shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -54635,14 +51979,12 @@ pub unsafe fn vrshrq_n_s16(a: int16x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrshr_n_s32(a: int32x2_t) -> int32x2_t { +pub fn vrshr_n_s32(a: int32x2_t) -> int32x2_t { static_assert!(N >= 1 && N <= 32); vrshl_s32(a, vdup_n_s32(-N as _)) } #[doc = "Signed rounding shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -54660,14 +52002,12 @@ pub unsafe fn vrshr_n_s32(a: int32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrshrq_n_s32(a: int32x4_t) -> int32x4_t { +pub fn vrshrq_n_s32(a: int32x4_t) -> int32x4_t { static_assert!(N >= 1 && N <= 32); vrshlq_s32(a, vdupq_n_s32(-N as _)) } #[doc = "Signed rounding shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -54685,14 +52025,12 @@ pub unsafe fn vrshrq_n_s32(a: int32x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrshr_n_s64(a: int64x1_t) -> int64x1_t { +pub fn vrshr_n_s64(a: int64x1_t) -> int64x1_t { static_assert!(N >= 1 && N <= 64); vrshl_s64(a, vdup_n_s64(-N as _)) } #[doc = "Signed rounding shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -54710,14 +52048,12 @@ pub unsafe fn vrshr_n_s64(a: int64x1_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrshrq_n_s64(a: int64x2_t) -> int64x2_t { +pub fn vrshrq_n_s64(a: int64x2_t) -> int64x2_t { static_assert!(N >= 1 && N <= 64); vrshlq_s64(a, vdupq_n_s64(-N as _)) } #[doc = "Unsigned rounding shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -54735,14 +52071,12 @@ pub unsafe fn vrshrq_n_s64(a: int64x2_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrshr_n_u8(a: uint8x8_t) -> uint8x8_t { +pub fn vrshr_n_u8(a: uint8x8_t) -> uint8x8_t { static_assert!(N >= 1 && N <= 8); vrshl_u8(a, vdup_n_s8(-N as _)) } #[doc = "Unsigned rounding shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -54760,14 +52094,12 @@ pub unsafe fn vrshr_n_u8(a: uint8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrshrq_n_u8(a: uint8x16_t) -> uint8x16_t { +pub fn vrshrq_n_u8(a: uint8x16_t) -> uint8x16_t { static_assert!(N >= 1 && N <= 8); vrshlq_u8(a, vdupq_n_s8(-N as _)) } #[doc = "Unsigned rounding shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -54785,14 +52117,12 @@ pub unsafe fn vrshrq_n_u8(a: uint8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrshr_n_u16(a: uint16x4_t) -> uint16x4_t { +pub fn vrshr_n_u16(a: uint16x4_t) -> uint16x4_t { static_assert!(N >= 1 && N <= 16); vrshl_u16(a, vdup_n_s16(-N as _)) } #[doc = "Unsigned rounding shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -54810,14 +52140,12 @@ pub unsafe fn vrshr_n_u16(a: uint16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrshrq_n_u16(a: uint16x8_t) -> uint16x8_t { +pub fn vrshrq_n_u16(a: uint16x8_t) -> uint16x8_t { static_assert!(N >= 1 && N <= 16); vrshlq_u16(a, vdupq_n_s16(-N as _)) } #[doc = "Unsigned rounding shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -54835,14 +52163,12 @@ pub unsafe fn vrshrq_n_u16(a: uint16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrshr_n_u32(a: uint32x2_t) -> uint32x2_t { +pub fn vrshr_n_u32(a: uint32x2_t) -> uint32x2_t { static_assert!(N >= 1 && N <= 32); vrshl_u32(a, vdup_n_s32(-N as _)) } #[doc = "Unsigned rounding shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -54860,14 +52186,12 @@ pub unsafe fn vrshr_n_u32(a: uint32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrshrq_n_u32(a: uint32x4_t) -> uint32x4_t { +pub fn vrshrq_n_u32(a: uint32x4_t) -> uint32x4_t { static_assert!(N >= 1 && N <= 32); vrshlq_u32(a, vdupq_n_s32(-N as _)) } #[doc = "Unsigned rounding shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -54885,14 +52209,12 @@ pub unsafe fn vrshrq_n_u32(a: uint32x4_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrshr_n_u64(a: uint64x1_t) -> uint64x1_t { +pub fn vrshr_n_u64(a: uint64x1_t) -> uint64x1_t { static_assert!(N >= 1 && N <= 64); vrshl_u64(a, vdup_n_s64(-N as _)) } #[doc = "Unsigned rounding shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -54910,86 +52232,82 @@ pub unsafe fn vrshr_n_u64(a: uint64x1_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrshrq_n_u64(a: uint64x2_t) -> uint64x2_t { +pub fn vrshrq_n_u64(a: uint64x2_t) -> uint64x2_t { static_assert!(N >= 1 && N <= 64); vrshlq_u64(a, vdupq_n_s64(-N as _)) } #[doc = "Rounding shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vrshrn, N = 2))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vrshrn_n_s16(a: int16x8_t) -> int8x8_t { +pub fn vrshrn_n_s16(a: int16x8_t) -> int8x8_t { static_assert!(N >= 1 && N <= 8); unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftn.v8i8")] fn _vrshrn_n_s16(a: int16x8_t, n: int16x8_t) -> int8x8_t; } - _vrshrn_n_s16( - a, - const { - int16x8_t([ - -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, - -N as i16, - ]) - }, - ) + unsafe { + _vrshrn_n_s16( + a, + const { + int16x8_t([ + -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, + -N as i16, + ]) + }, + ) + } } #[doc = "Rounding shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vrshrn, N = 2))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vrshrn_n_s32(a: int32x4_t) -> int16x4_t { +pub fn vrshrn_n_s32(a: int32x4_t) -> int16x4_t { static_assert!(N >= 1 && N <= 16); unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftn.v4i16")] fn _vrshrn_n_s32(a: int32x4_t, n: int32x4_t) -> int16x4_t; } - _vrshrn_n_s32( - a, - const { int32x4_t([-N as i32, -N as i32, -N as i32, -N as i32]) }, - ) + unsafe { + _vrshrn_n_s32( + a, + const { int32x4_t([-N as i32, -N as i32, -N as i32, -N as i32]) }, + ) + } } #[doc = "Rounding shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[cfg_attr(test, assert_instr(vrshrn, N = 2))] #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vrshrn_n_s64(a: int64x2_t) -> int32x2_t { +pub fn vrshrn_n_s64(a: int64x2_t) -> int32x2_t { static_assert!(N >= 1 && N <= 32); unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftn.v2i32")] fn _vrshrn_n_s64(a: int64x2_t, n: int64x2_t) -> int32x2_t; } - _vrshrn_n_s64(a, const { int64x2_t([-N as i64, -N as i64]) }) + unsafe { _vrshrn_n_s64(a, const { int64x2_t([-N as i64, -N as i64]) }) } } #[doc = "Rounding shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(rshrn, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrshrn_n_s16(a: int16x8_t) -> int8x8_t { +pub fn vrshrn_n_s16(a: int16x8_t) -> int8x8_t { static_assert!(N >= 1 && N <= 8); unsafe extern "unadjusted" { #[cfg_attr( @@ -54998,19 +52316,17 @@ pub unsafe fn vrshrn_n_s16(a: int16x8_t) -> int8x8_t { )] fn _vrshrn_n_s16(a: int16x8_t, n: i32) -> int8x8_t; } - _vrshrn_n_s16(a, N) + unsafe { _vrshrn_n_s16(a, N) } } #[doc = "Rounding shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(rshrn, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrshrn_n_s32(a: int32x4_t) -> int16x4_t { +pub fn vrshrn_n_s32(a: int32x4_t) -> int16x4_t { static_assert!(N >= 1 && N <= 16); unsafe extern "unadjusted" { #[cfg_attr( @@ -55019,19 +52335,17 @@ pub unsafe fn vrshrn_n_s32(a: int32x4_t) -> int16x4_t { )] fn _vrshrn_n_s32(a: int32x4_t, n: i32) -> int16x4_t; } - _vrshrn_n_s32(a, N) + unsafe { _vrshrn_n_s32(a, N) } } #[doc = "Rounding shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(rshrn, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrshrn_n_s64(a: int64x2_t) -> int32x2_t { +pub fn vrshrn_n_s64(a: int64x2_t) -> int32x2_t { static_assert!(N >= 1 && N <= 32); unsafe extern "unadjusted" { #[cfg_attr( @@ -55040,12 +52354,10 @@ pub unsafe fn vrshrn_n_s64(a: int64x2_t) -> int32x2_t { )] fn _vrshrn_n_s64(a: int64x2_t, n: i32) -> int32x2_t; } - _vrshrn_n_s64(a, N) + unsafe { _vrshrn_n_s64(a, N) } } #[doc = "Rounding shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -55063,14 +52375,12 @@ pub unsafe fn vrshrn_n_s64(a: int64x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrshrn_n_u16(a: uint16x8_t) -> uint8x8_t { +pub fn vrshrn_n_u16(a: uint16x8_t) -> uint8x8_t { static_assert!(N >= 1 && N <= 8); - transmute(vrshrn_n_s16::(transmute(a))) + unsafe { transmute(vrshrn_n_s16::(transmute(a))) } } #[doc = "Rounding shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -55088,14 +52398,12 @@ pub unsafe fn vrshrn_n_u16(a: uint16x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrshrn_n_u32(a: uint32x4_t) -> uint16x4_t { +pub fn vrshrn_n_u32(a: uint32x4_t) -> uint16x4_t { static_assert!(N >= 1 && N <= 16); - transmute(vrshrn_n_s32::(transmute(a))) + unsafe { transmute(vrshrn_n_s32::(transmute(a))) } } #[doc = "Rounding shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -55113,14 +52421,12 @@ pub unsafe fn vrshrn_n_u32(a: uint32x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrshrn_n_u64(a: uint64x2_t) -> uint32x2_t { +pub fn vrshrn_n_u64(a: uint64x2_t) -> uint32x2_t { static_assert!(N >= 1 && N <= 32); - transmute(vrshrn_n_s64::(transmute(a))) + unsafe { transmute(vrshrn_n_s64::(transmute(a))) } } #[doc = "Reciprocal square-root estimate."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrte_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[target_feature(enable = "neon,fp16")] @@ -55130,7 +52436,7 @@ pub unsafe fn vrshrn_n_u64(a: uint64x2_t) -> uint32x2_t { assert_instr(frsqrte) )] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vrsqrte_f16(a: float16x4_t) -> float16x4_t { +pub fn vrsqrte_f16(a: float16x4_t) -> float16x4_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrte.v4f16")] #[cfg_attr( @@ -55139,12 +52445,10 @@ pub unsafe fn vrsqrte_f16(a: float16x4_t) -> float16x4_t { )] fn _vrsqrte_f16(a: float16x4_t) -> float16x4_t; } - _vrsqrte_f16(a) + unsafe { _vrsqrte_f16(a) } } #[doc = "Reciprocal square-root estimate."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrteq_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[target_feature(enable = "neon,fp16")] @@ -55154,7 +52458,7 @@ pub unsafe fn vrsqrte_f16(a: float16x4_t) -> float16x4_t { assert_instr(frsqrte) )] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vrsqrteq_f16(a: float16x8_t) -> float16x8_t { +pub fn vrsqrteq_f16(a: float16x8_t) -> float16x8_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrte.v8f16")] #[cfg_attr( @@ -55163,12 +52467,10 @@ pub unsafe fn vrsqrteq_f16(a: float16x8_t) -> float16x8_t { )] fn _vrsqrteq_f16(a: float16x8_t) -> float16x8_t; } - _vrsqrteq_f16(a) + unsafe { _vrsqrteq_f16(a) } } #[doc = "Reciprocal square-root estimate."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrte_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -55185,7 +52487,7 @@ pub unsafe fn vrsqrteq_f16(a: float16x8_t) -> float16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrsqrte_f32(a: float32x2_t) -> float32x2_t { +pub fn vrsqrte_f32(a: float32x2_t) -> float32x2_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrte.v2f32")] #[cfg_attr( @@ -55194,12 +52496,10 @@ pub unsafe fn vrsqrte_f32(a: float32x2_t) -> float32x2_t { )] fn _vrsqrte_f32(a: float32x2_t) -> float32x2_t; } - _vrsqrte_f32(a) + unsafe { _vrsqrte_f32(a) } } #[doc = "Reciprocal square-root estimate."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrteq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -55216,7 +52516,7 @@ pub unsafe fn vrsqrte_f32(a: float32x2_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrsqrteq_f32(a: float32x4_t) -> float32x4_t { +pub fn vrsqrteq_f32(a: float32x4_t) -> float32x4_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrte.v4f32")] #[cfg_attr( @@ -55225,12 +52525,10 @@ pub unsafe fn vrsqrteq_f32(a: float32x4_t) -> float32x4_t { )] fn _vrsqrteq_f32(a: float32x4_t) -> float32x4_t; } - _vrsqrteq_f32(a) + unsafe { _vrsqrteq_f32(a) } } #[doc = "Unsigned reciprocal square root estimate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrte_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -55247,7 +52545,7 @@ pub unsafe fn vrsqrteq_f32(a: float32x4_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrsqrte_u32(a: uint32x2_t) -> uint32x2_t { +pub fn vrsqrte_u32(a: uint32x2_t) -> uint32x2_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrte.v2i32")] #[cfg_attr( @@ -55256,12 +52554,10 @@ pub unsafe fn vrsqrte_u32(a: uint32x2_t) -> uint32x2_t { )] fn _vrsqrte_u32(a: uint32x2_t) -> uint32x2_t; } - _vrsqrte_u32(a) + unsafe { _vrsqrte_u32(a) } } #[doc = "Unsigned reciprocal square root estimate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrteq_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -55278,7 +52574,7 @@ pub unsafe fn vrsqrte_u32(a: uint32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrsqrteq_u32(a: uint32x4_t) -> uint32x4_t { +pub fn vrsqrteq_u32(a: uint32x4_t) -> uint32x4_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrte.v4i32")] #[cfg_attr( @@ -55287,12 +52583,10 @@ pub unsafe fn vrsqrteq_u32(a: uint32x4_t) -> uint32x4_t { )] fn _vrsqrteq_u32(a: uint32x4_t) -> uint32x4_t; } - _vrsqrteq_u32(a) + unsafe { _vrsqrteq_u32(a) } } #[doc = "Floating-point reciprocal square root step"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrts_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[target_feature(enable = "neon,fp16")] @@ -55302,7 +52596,7 @@ pub unsafe fn vrsqrteq_u32(a: uint32x4_t) -> uint32x4_t { assert_instr(frsqrts) )] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vrsqrts_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { +pub fn vrsqrts_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrts.v4f16")] #[cfg_attr( @@ -55311,12 +52605,10 @@ pub unsafe fn vrsqrts_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { )] fn _vrsqrts_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t; } - _vrsqrts_f16(a, b) + unsafe { _vrsqrts_f16(a, b) } } #[doc = "Floating-point reciprocal square root step"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrtsq_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[target_feature(enable = "neon,fp16")] @@ -55326,7 +52618,7 @@ pub unsafe fn vrsqrts_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { assert_instr(frsqrts) )] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vrsqrtsq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { +pub fn vrsqrtsq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrts.v8f16")] #[cfg_attr( @@ -55335,12 +52627,10 @@ pub unsafe fn vrsqrtsq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { )] fn _vrsqrtsq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t; } - _vrsqrtsq_f16(a, b) + unsafe { _vrsqrtsq_f16(a, b) } } #[doc = "Floating-point reciprocal square root step"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrts_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -55357,7 +52647,7 @@ pub unsafe fn vrsqrtsq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrsqrts_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { +pub fn vrsqrts_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrts.v2f32")] #[cfg_attr( @@ -55366,12 +52656,10 @@ pub unsafe fn vrsqrts_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { )] fn _vrsqrts_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t; } - _vrsqrts_f32(a, b) + unsafe { _vrsqrts_f32(a, b) } } #[doc = "Floating-point reciprocal square root step"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrtsq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -55388,7 +52676,7 @@ pub unsafe fn vrsqrts_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrsqrtsq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { +pub fn vrsqrtsq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrts.v4f32")] #[cfg_attr( @@ -55397,12 +52685,10 @@ pub unsafe fn vrsqrtsq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { )] fn _vrsqrtsq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t; } - _vrsqrtsq_f32(a, b) + unsafe { _vrsqrtsq_f32(a, b) } } #[doc = "Signed rounding shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -55420,14 +52706,12 @@ pub unsafe fn vrsqrtsq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrsra_n_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { +pub fn vrsra_n_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { static_assert!(N >= 1 && N <= 8); - simd_add(a, vrshr_n_s8::(b)) + unsafe { simd_add(a, vrshr_n_s8::(b)) } } #[doc = "Signed rounding shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -55445,14 +52729,12 @@ pub unsafe fn vrsra_n_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrsraq_n_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { +pub fn vrsraq_n_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { static_assert!(N >= 1 && N <= 8); - simd_add(a, vrshrq_n_s8::(b)) + unsafe { simd_add(a, vrshrq_n_s8::(b)) } } #[doc = "Signed rounding shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -55470,14 +52752,12 @@ pub unsafe fn vrsraq_n_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrsra_n_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { +pub fn vrsra_n_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { static_assert!(N >= 1 && N <= 16); - simd_add(a, vrshr_n_s16::(b)) + unsafe { simd_add(a, vrshr_n_s16::(b)) } } #[doc = "Signed rounding shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -55495,14 +52775,12 @@ pub unsafe fn vrsra_n_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrsraq_n_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { +pub fn vrsraq_n_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { static_assert!(N >= 1 && N <= 16); - simd_add(a, vrshrq_n_s16::(b)) + unsafe { simd_add(a, vrshrq_n_s16::(b)) } } #[doc = "Signed rounding shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -55520,14 +52798,12 @@ pub unsafe fn vrsraq_n_s16(a: int16x8_t, b: int16x8_t) -> int16x8_ target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrsra_n_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { +pub fn vrsra_n_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { static_assert!(N >= 1 && N <= 32); - simd_add(a, vrshr_n_s32::(b)) + unsafe { simd_add(a, vrshr_n_s32::(b)) } } #[doc = "Signed rounding shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -55545,14 +52821,12 @@ pub unsafe fn vrsra_n_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrsraq_n_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { +pub fn vrsraq_n_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { static_assert!(N >= 1 && N <= 32); - simd_add(a, vrshrq_n_s32::(b)) + unsafe { simd_add(a, vrshrq_n_s32::(b)) } } #[doc = "Signed rounding shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -55570,14 +52844,12 @@ pub unsafe fn vrsraq_n_s32(a: int32x4_t, b: int32x4_t) -> int32x4_ target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrsra_n_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { +pub fn vrsra_n_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { static_assert!(N >= 1 && N <= 64); - simd_add(a, vrshr_n_s64::(b)) + unsafe { simd_add(a, vrshr_n_s64::(b)) } } #[doc = "Signed rounding shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -55595,14 +52867,12 @@ pub unsafe fn vrsra_n_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrsraq_n_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { +pub fn vrsraq_n_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { static_assert!(N >= 1 && N <= 64); - simd_add(a, vrshrq_n_s64::(b)) + unsafe { simd_add(a, vrshrq_n_s64::(b)) } } #[doc = "Unsigned rounding shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -55620,14 +52890,12 @@ pub unsafe fn vrsraq_n_s64(a: int64x2_t, b: int64x2_t) -> int64x2_ target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrsra_n_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { +pub fn vrsra_n_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { static_assert!(N >= 1 && N <= 8); - simd_add(a, vrshr_n_u8::(b)) + unsafe { simd_add(a, vrshr_n_u8::(b)) } } #[doc = "Unsigned rounding shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -55645,14 +52913,12 @@ pub unsafe fn vrsra_n_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrsraq_n_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { +pub fn vrsraq_n_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { static_assert!(N >= 1 && N <= 8); - simd_add(a, vrshrq_n_u8::(b)) + unsafe { simd_add(a, vrshrq_n_u8::(b)) } } #[doc = "Unsigned rounding shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -55670,14 +52936,12 @@ pub unsafe fn vrsraq_n_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x1 target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrsra_n_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { +pub fn vrsra_n_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { static_assert!(N >= 1 && N <= 16); - simd_add(a, vrshr_n_u16::(b)) + unsafe { simd_add(a, vrshr_n_u16::(b)) } } #[doc = "Unsigned rounding shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -55695,14 +52959,12 @@ pub unsafe fn vrsra_n_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrsraq_n_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { +pub fn vrsraq_n_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { static_assert!(N >= 1 && N <= 16); - simd_add(a, vrshrq_n_u16::(b)) + unsafe { simd_add(a, vrshrq_n_u16::(b)) } } #[doc = "Unsigned rounding shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -55720,14 +52982,12 @@ pub unsafe fn vrsraq_n_u16(a: uint16x8_t, b: uint16x8_t) -> uint16 target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrsra_n_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { +pub fn vrsra_n_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { static_assert!(N >= 1 && N <= 32); - simd_add(a, vrshr_n_u32::(b)) + unsafe { simd_add(a, vrshr_n_u32::(b)) } } #[doc = "Unsigned rounding shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -55745,14 +53005,12 @@ pub unsafe fn vrsra_n_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrsraq_n_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { +pub fn vrsraq_n_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { static_assert!(N >= 1 && N <= 32); - simd_add(a, vrshrq_n_u32::(b)) + unsafe { simd_add(a, vrshrq_n_u32::(b)) } } #[doc = "Unsigned rounding shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -55770,14 +53028,12 @@ pub unsafe fn vrsraq_n_u32(a: uint32x4_t, b: uint32x4_t) -> uint32 target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrsra_n_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { +pub fn vrsra_n_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { static_assert!(N >= 1 && N <= 64); - simd_add(a, vrshr_n_u64::(b)) + unsafe { simd_add(a, vrshr_n_u64::(b)) } } #[doc = "Unsigned rounding shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -55795,14 +53051,12 @@ pub unsafe fn vrsra_n_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrsraq_n_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { +pub fn vrsraq_n_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { static_assert!(N >= 1 && N <= 64); - simd_add(a, vrshrq_n_u64::(b)) + unsafe { simd_add(a, vrshrq_n_u64::(b)) } } #[doc = "Rounding subtract returning high narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -55819,7 +53073,7 @@ pub unsafe fn vrsraq_n_u64(a: uint64x2_t, b: uint64x2_t) -> uint64 target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrsubhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t { +pub fn vrsubhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsubhn.v8i8")] #[cfg_attr( @@ -55828,12 +53082,10 @@ pub unsafe fn vrsubhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t { )] fn _vrsubhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t; } - _vrsubhn_s16(a, b) + unsafe { _vrsubhn_s16(a, b) } } #[doc = "Rounding subtract returning high narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -55850,7 +53102,7 @@ pub unsafe fn vrsubhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrsubhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t { +pub fn vrsubhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsubhn.v4i16")] #[cfg_attr( @@ -55859,12 +53111,10 @@ pub unsafe fn vrsubhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t { )] fn _vrsubhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t; } - _vrsubhn_s32(a, b) + unsafe { _vrsubhn_s32(a, b) } } #[doc = "Rounding subtract returning high narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -55881,7 +53131,7 @@ pub unsafe fn vrsubhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrsubhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t { +pub fn vrsubhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsubhn.v2i32")] #[cfg_attr( @@ -55890,12 +53140,10 @@ pub unsafe fn vrsubhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t { )] fn _vrsubhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t; } - _vrsubhn_s64(a, b) + unsafe { _vrsubhn_s64(a, b) } } #[doc = "Rounding subtract returning high narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -55913,13 +53161,11 @@ pub unsafe fn vrsubhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrsubhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t { - transmute(vrsubhn_s16(transmute(a), transmute(b))) +pub fn vrsubhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t { + unsafe { transmute(vrsubhn_s16(transmute(a), transmute(b))) } } #[doc = "Rounding subtract returning high narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -55937,16 +53183,16 @@ pub unsafe fn vrsubhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrsubhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t { +pub fn vrsubhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t { let a: uint16x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); let b: uint16x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: uint8x8_t = transmute(vrsubhn_s16(transmute(a), transmute(b))); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: uint8x8_t = transmute(vrsubhn_s16(transmute(a), transmute(b))); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Rounding subtract returning high narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -55964,13 +53210,11 @@ pub unsafe fn vrsubhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrsubhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t { - transmute(vrsubhn_s32(transmute(a), transmute(b))) +pub fn vrsubhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t { + unsafe { transmute(vrsubhn_s32(transmute(a), transmute(b))) } } #[doc = "Rounding subtract returning high narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -55988,16 +53232,16 @@ pub unsafe fn vrsubhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrsubhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t { +pub fn vrsubhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t { let a: uint32x4_t = simd_shuffle!(a, a, [3, 2, 1, 0]); let b: uint32x4_t = simd_shuffle!(b, b, [3, 2, 1, 0]); - let ret_val: uint16x4_t = transmute(vrsubhn_s32(transmute(a), transmute(b))); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + unsafe { + let ret_val: uint16x4_t = transmute(vrsubhn_s32(transmute(a), transmute(b))); + simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + } } #[doc = "Rounding subtract returning high narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -56015,13 +53259,11 @@ pub unsafe fn vrsubhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrsubhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t { - transmute(vrsubhn_s64(transmute(a), transmute(b))) +pub fn vrsubhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t { + unsafe { transmute(vrsubhn_s64(transmute(a), transmute(b))) } } #[doc = "Rounding subtract returning high narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -56039,16 +53281,16 @@ pub unsafe fn vrsubhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrsubhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t { +pub fn vrsubhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t { let a: uint64x2_t = simd_shuffle!(a, a, [1, 0]); let b: uint64x2_t = simd_shuffle!(b, b, [1, 0]); - let ret_val: uint32x2_t = transmute(vrsubhn_s64(transmute(a), transmute(b))); - simd_shuffle!(ret_val, ret_val, [1, 0]) + unsafe { + let ret_val: uint32x2_t = transmute(vrsubhn_s64(transmute(a), transmute(b))); + simd_shuffle!(ret_val, ret_val, [1, 0]) + } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] @@ -56059,14 +53301,12 @@ pub unsafe fn vrsubhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t { #[rustc_legacy_const_generics(2)] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vset_lane_f16(a: f16, b: float16x4_t) -> float16x4_t { +pub fn vset_lane_f16(a: f16, b: float16x4_t) -> float16x4_t { static_assert_uimm_bits!(LANE, 2); - simd_insert!(b, LANE as u32, a) + unsafe { simd_insert!(b, LANE as u32, a) } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] @@ -56077,14 +53317,12 @@ pub unsafe fn vset_lane_f16(a: f16, b: float16x4_t) -> float16x #[rustc_legacy_const_generics(2)] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vsetq_lane_f16(a: f16, b: float16x8_t) -> float16x8_t { +pub fn vsetq_lane_f16(a: f16, b: float16x8_t) -> float16x8_t { static_assert_uimm_bits!(LANE, 3); - simd_insert!(b, LANE as u32, a) + unsafe { simd_insert!(b, LANE as u32, a) } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -56102,14 +53340,12 @@ pub unsafe fn vsetq_lane_f16(a: f16, b: float16x8_t) -> float16 target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vset_lane_f32(a: f32, b: float32x2_t) -> float32x2_t { +pub fn vset_lane_f32(a: f32, b: float32x2_t) -> float32x2_t { static_assert_uimm_bits!(LANE, 1); - simd_insert!(b, LANE as u32, a) + unsafe { simd_insert!(b, LANE as u32, a) } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -56127,14 +53363,12 @@ pub unsafe fn vset_lane_f32(a: f32, b: float32x2_t) -> float32x target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vsetq_lane_f32(a: f32, b: float32x4_t) -> float32x4_t { +pub fn vsetq_lane_f32(a: f32, b: float32x4_t) -> float32x4_t { static_assert_uimm_bits!(LANE, 2); - simd_insert!(b, LANE as u32, a) + unsafe { simd_insert!(b, LANE as u32, a) } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -56152,14 +53386,12 @@ pub unsafe fn vsetq_lane_f32(a: f32, b: float32x4_t) -> float32 target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vset_lane_s8(a: i8, b: int8x8_t) -> int8x8_t { +pub fn vset_lane_s8(a: i8, b: int8x8_t) -> int8x8_t { static_assert_uimm_bits!(LANE, 3); - simd_insert!(b, LANE as u32, a) + unsafe { simd_insert!(b, LANE as u32, a) } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -56177,14 +53409,12 @@ pub unsafe fn vset_lane_s8(a: i8, b: int8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vsetq_lane_s8(a: i8, b: int8x16_t) -> int8x16_t { +pub fn vsetq_lane_s8(a: i8, b: int8x16_t) -> int8x16_t { static_assert_uimm_bits!(LANE, 4); - simd_insert!(b, LANE as u32, a) + unsafe { simd_insert!(b, LANE as u32, a) } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -56202,14 +53432,12 @@ pub unsafe fn vsetq_lane_s8(a: i8, b: int8x16_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vset_lane_s16(a: i16, b: int16x4_t) -> int16x4_t { +pub fn vset_lane_s16(a: i16, b: int16x4_t) -> int16x4_t { static_assert_uimm_bits!(LANE, 2); - simd_insert!(b, LANE as u32, a) + unsafe { simd_insert!(b, LANE as u32, a) } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -56227,14 +53455,12 @@ pub unsafe fn vset_lane_s16(a: i16, b: int16x4_t) -> int16x4_t target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vsetq_lane_s16(a: i16, b: int16x8_t) -> int16x8_t { +pub fn vsetq_lane_s16(a: i16, b: int16x8_t) -> int16x8_t { static_assert_uimm_bits!(LANE, 3); - simd_insert!(b, LANE as u32, a) + unsafe { simd_insert!(b, LANE as u32, a) } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -56252,14 +53478,12 @@ pub unsafe fn vsetq_lane_s16(a: i16, b: int16x8_t) -> int16x8_t target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vset_lane_s32(a: i32, b: int32x2_t) -> int32x2_t { +pub fn vset_lane_s32(a: i32, b: int32x2_t) -> int32x2_t { static_assert_uimm_bits!(LANE, 1); - simd_insert!(b, LANE as u32, a) + unsafe { simd_insert!(b, LANE as u32, a) } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -56277,14 +53501,12 @@ pub unsafe fn vset_lane_s32(a: i32, b: int32x2_t) -> int32x2_t target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vsetq_lane_s32(a: i32, b: int32x4_t) -> int32x4_t { +pub fn vsetq_lane_s32(a: i32, b: int32x4_t) -> int32x4_t { static_assert_uimm_bits!(LANE, 2); - simd_insert!(b, LANE as u32, a) + unsafe { simd_insert!(b, LANE as u32, a) } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -56302,14 +53524,12 @@ pub unsafe fn vsetq_lane_s32(a: i32, b: int32x4_t) -> int32x4_t target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vsetq_lane_s64(a: i64, b: int64x2_t) -> int64x2_t { +pub fn vsetq_lane_s64(a: i64, b: int64x2_t) -> int64x2_t { static_assert_uimm_bits!(LANE, 1); - simd_insert!(b, LANE as u32, a) + unsafe { simd_insert!(b, LANE as u32, a) } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -56327,14 +53547,12 @@ pub unsafe fn vsetq_lane_s64(a: i64, b: int64x2_t) -> int64x2_t target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vset_lane_u8(a: u8, b: uint8x8_t) -> uint8x8_t { +pub fn vset_lane_u8(a: u8, b: uint8x8_t) -> uint8x8_t { static_assert_uimm_bits!(LANE, 3); - simd_insert!(b, LANE as u32, a) + unsafe { simd_insert!(b, LANE as u32, a) } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -56352,14 +53570,12 @@ pub unsafe fn vset_lane_u8(a: u8, b: uint8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vsetq_lane_u8(a: u8, b: uint8x16_t) -> uint8x16_t { +pub fn vsetq_lane_u8(a: u8, b: uint8x16_t) -> uint8x16_t { static_assert_uimm_bits!(LANE, 4); - simd_insert!(b, LANE as u32, a) + unsafe { simd_insert!(b, LANE as u32, a) } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -56377,14 +53593,12 @@ pub unsafe fn vsetq_lane_u8(a: u8, b: uint8x16_t) -> uint8x16_t target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vset_lane_u16(a: u16, b: uint16x4_t) -> uint16x4_t { +pub fn vset_lane_u16(a: u16, b: uint16x4_t) -> uint16x4_t { static_assert_uimm_bits!(LANE, 2); - simd_insert!(b, LANE as u32, a) + unsafe { simd_insert!(b, LANE as u32, a) } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -56402,14 +53616,12 @@ pub unsafe fn vset_lane_u16(a: u16, b: uint16x4_t) -> uint16x4_ target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vsetq_lane_u16(a: u16, b: uint16x8_t) -> uint16x8_t { +pub fn vsetq_lane_u16(a: u16, b: uint16x8_t) -> uint16x8_t { static_assert_uimm_bits!(LANE, 3); - simd_insert!(b, LANE as u32, a) + unsafe { simd_insert!(b, LANE as u32, a) } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -56427,14 +53639,12 @@ pub unsafe fn vsetq_lane_u16(a: u16, b: uint16x8_t) -> uint16x8 target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vset_lane_u32(a: u32, b: uint32x2_t) -> uint32x2_t { +pub fn vset_lane_u32(a: u32, b: uint32x2_t) -> uint32x2_t { static_assert_uimm_bits!(LANE, 1); - simd_insert!(b, LANE as u32, a) + unsafe { simd_insert!(b, LANE as u32, a) } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -56452,14 +53662,12 @@ pub unsafe fn vset_lane_u32(a: u32, b: uint32x2_t) -> uint32x2_ target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vsetq_lane_u32(a: u32, b: uint32x4_t) -> uint32x4_t { +pub fn vsetq_lane_u32(a: u32, b: uint32x4_t) -> uint32x4_t { static_assert_uimm_bits!(LANE, 2); - simd_insert!(b, LANE as u32, a) + unsafe { simd_insert!(b, LANE as u32, a) } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -56477,14 +53685,12 @@ pub unsafe fn vsetq_lane_u32(a: u32, b: uint32x4_t) -> uint32x4 target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vsetq_lane_u64(a: u64, b: uint64x2_t) -> uint64x2_t { +pub fn vsetq_lane_u64(a: u64, b: uint64x2_t) -> uint64x2_t { static_assert_uimm_bits!(LANE, 1); - simd_insert!(b, LANE as u32, a) + unsafe { simd_insert!(b, LANE as u32, a) } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -56502,14 +53708,12 @@ pub unsafe fn vsetq_lane_u64(a: u64, b: uint64x2_t) -> uint64x2 target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vset_lane_p8(a: p8, b: poly8x8_t) -> poly8x8_t { +pub fn vset_lane_p8(a: p8, b: poly8x8_t) -> poly8x8_t { static_assert_uimm_bits!(LANE, 3); - simd_insert!(b, LANE as u32, a) + unsafe { simd_insert!(b, LANE as u32, a) } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -56527,14 +53731,12 @@ pub unsafe fn vset_lane_p8(a: p8, b: poly8x8_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vsetq_lane_p8(a: p8, b: poly8x16_t) -> poly8x16_t { +pub fn vsetq_lane_p8(a: p8, b: poly8x16_t) -> poly8x16_t { static_assert_uimm_bits!(LANE, 4); - simd_insert!(b, LANE as u32, a) + unsafe { simd_insert!(b, LANE as u32, a) } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -56552,14 +53754,12 @@ pub unsafe fn vsetq_lane_p8(a: p8, b: poly8x16_t) -> poly8x16_t target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vset_lane_p16(a: p16, b: poly16x4_t) -> poly16x4_t { +pub fn vset_lane_p16(a: p16, b: poly16x4_t) -> poly16x4_t { static_assert_uimm_bits!(LANE, 2); - simd_insert!(b, LANE as u32, a) + unsafe { simd_insert!(b, LANE as u32, a) } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -56577,14 +53777,12 @@ pub unsafe fn vset_lane_p16(a: p16, b: poly16x4_t) -> poly16x4_ target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vsetq_lane_p16(a: p16, b: poly16x8_t) -> poly16x8_t { +pub fn vsetq_lane_p16(a: p16, b: poly16x8_t) -> poly16x8_t { static_assert_uimm_bits!(LANE, 3); - simd_insert!(b, LANE as u32, a) + unsafe { simd_insert!(b, LANE as u32, a) } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] @@ -56602,14 +53800,12 @@ pub unsafe fn vsetq_lane_p16(a: p16, b: poly16x8_t) -> poly16x8 target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vset_lane_p64(a: p64, b: poly64x1_t) -> poly64x1_t { +pub fn vset_lane_p64(a: p64, b: poly64x1_t) -> poly64x1_t { static_assert!(LANE == 0); - simd_insert!(b, LANE as u32, a) + unsafe { simd_insert!(b, LANE as u32, a) } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -56627,14 +53823,12 @@ pub unsafe fn vset_lane_p64(a: p64, b: poly64x1_t) -> poly64x1_ target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vset_lane_s64(a: i64, b: int64x1_t) -> int64x1_t { +pub fn vset_lane_s64(a: i64, b: int64x1_t) -> int64x1_t { static_assert!(LANE == 0); - simd_insert!(b, LANE as u32, a) + unsafe { simd_insert!(b, LANE as u32, a) } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -56652,14 +53846,12 @@ pub unsafe fn vset_lane_s64(a: i64, b: int64x1_t) -> int64x1_t target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vset_lane_u64(a: u64, b: uint64x1_t) -> uint64x1_t { +pub fn vset_lane_u64(a: u64, b: uint64x1_t) -> uint64x1_t { static_assert!(LANE == 0); - simd_insert!(b, LANE as u32, a) + unsafe { simd_insert!(b, LANE as u32, a) } } #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_p64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] @@ -56677,14 +53869,12 @@ pub unsafe fn vset_lane_u64(a: u64, b: uint64x1_t) -> uint64x1_ target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vsetq_lane_p64(a: p64, b: poly64x2_t) -> poly64x2_t { +pub fn vsetq_lane_p64(a: p64, b: poly64x2_t) -> poly64x2_t { static_assert_uimm_bits!(LANE, 1); - simd_insert!(b, LANE as u32, a) + unsafe { simd_insert!(b, LANE as u32, a) } } #[doc = "SHA1 hash update accelerator, choose."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1cq_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "sha2")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] @@ -56697,7 +53887,7 @@ pub unsafe fn vsetq_lane_p64(a: p64, b: poly64x2_t) -> poly64x2 not(target_arch = "arm"), stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0") )] -pub unsafe fn vsha1cq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t { +pub fn vsha1cq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -56706,12 +53896,10 @@ pub unsafe fn vsha1cq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha1c")] fn _vsha1cq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t; } - _vsha1cq_u32(hash_abcd, hash_e, wk) + unsafe { _vsha1cq_u32(hash_abcd, hash_e, wk) } } #[doc = "SHA1 fixed rotate."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1h_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "sha2")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] @@ -56724,7 +53912,7 @@ pub unsafe fn vsha1cq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> not(target_arch = "arm"), stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0") )] -pub unsafe fn vsha1h_u32(hash_e: u32) -> u32 { +pub fn vsha1h_u32(hash_e: u32) -> u32 { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -56733,12 +53921,10 @@ pub unsafe fn vsha1h_u32(hash_e: u32) -> u32 { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha1h")] fn _vsha1h_u32(hash_e: u32) -> u32; } - _vsha1h_u32(hash_e) + unsafe { _vsha1h_u32(hash_e) } } #[doc = "SHA1 hash update accelerator, majority"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1mq_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "sha2")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] @@ -56751,7 +53937,7 @@ pub unsafe fn vsha1h_u32(hash_e: u32) -> u32 { not(target_arch = "arm"), stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0") )] -pub unsafe fn vsha1mq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t { +pub fn vsha1mq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -56760,12 +53946,10 @@ pub unsafe fn vsha1mq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha1m")] fn _vsha1mq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t; } - _vsha1mq_u32(hash_abcd, hash_e, wk) + unsafe { _vsha1mq_u32(hash_abcd, hash_e, wk) } } #[doc = "SHA1 hash update accelerator, parity"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1pq_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "sha2")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] @@ -56778,7 +53962,7 @@ pub unsafe fn vsha1mq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> not(target_arch = "arm"), stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0") )] -pub unsafe fn vsha1pq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t { +pub fn vsha1pq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -56787,12 +53971,10 @@ pub unsafe fn vsha1pq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha1p")] fn _vsha1pq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t; } - _vsha1pq_u32(hash_abcd, hash_e, wk) + unsafe { _vsha1pq_u32(hash_abcd, hash_e, wk) } } #[doc = "SHA1 schedule update accelerator, first part."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1su0q_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "sha2")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] @@ -56805,7 +53987,7 @@ pub unsafe fn vsha1pq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> not(target_arch = "arm"), stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0") )] -pub unsafe fn vsha1su0q_u32(w0_3: uint32x4_t, w4_7: uint32x4_t, w8_11: uint32x4_t) -> uint32x4_t { +pub fn vsha1su0q_u32(w0_3: uint32x4_t, w4_7: uint32x4_t, w8_11: uint32x4_t) -> uint32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -56814,12 +53996,10 @@ pub unsafe fn vsha1su0q_u32(w0_3: uint32x4_t, w4_7: uint32x4_t, w8_11: uint32x4_ #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha1su0")] fn _vsha1su0q_u32(w0_3: uint32x4_t, w4_7: uint32x4_t, w8_11: uint32x4_t) -> uint32x4_t; } - _vsha1su0q_u32(w0_3, w4_7, w8_11) + unsafe { _vsha1su0q_u32(w0_3, w4_7, w8_11) } } #[doc = "SHA1 schedule update accelerator, second part."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1su1q_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "sha2")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] @@ -56832,7 +54012,7 @@ pub unsafe fn vsha1su0q_u32(w0_3: uint32x4_t, w4_7: uint32x4_t, w8_11: uint32x4_ not(target_arch = "arm"), stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0") )] -pub unsafe fn vsha1su1q_u32(tw0_3: uint32x4_t, w12_15: uint32x4_t) -> uint32x4_t { +pub fn vsha1su1q_u32(tw0_3: uint32x4_t, w12_15: uint32x4_t) -> uint32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -56841,12 +54021,10 @@ pub unsafe fn vsha1su1q_u32(tw0_3: uint32x4_t, w12_15: uint32x4_t) -> uint32x4_t #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha1su1")] fn _vsha1su1q_u32(tw0_3: uint32x4_t, w12_15: uint32x4_t) -> uint32x4_t; } - _vsha1su1q_u32(tw0_3, w12_15) + unsafe { _vsha1su1q_u32(tw0_3, w12_15) } } #[doc = "SHA1 schedule update accelerator, upper part."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha256h2q_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "sha2")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] @@ -56859,11 +54037,7 @@ pub unsafe fn vsha1su1q_u32(tw0_3: uint32x4_t, w12_15: uint32x4_t) -> uint32x4_t not(target_arch = "arm"), stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0") )] -pub unsafe fn vsha256h2q_u32( - hash_abcd: uint32x4_t, - hash_efgh: uint32x4_t, - wk: uint32x4_t, -) -> uint32x4_t { +pub fn vsha256h2q_u32(hash_abcd: uint32x4_t, hash_efgh: uint32x4_t, wk: uint32x4_t) -> uint32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -56876,12 +54050,10 @@ pub unsafe fn vsha256h2q_u32( wk: uint32x4_t, ) -> uint32x4_t; } - _vsha256h2q_u32(hash_abcd, hash_efgh, wk) + unsafe { _vsha256h2q_u32(hash_abcd, hash_efgh, wk) } } #[doc = "SHA1 schedule update accelerator, first part."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha256hq_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "sha2")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] @@ -56894,11 +54066,7 @@ pub unsafe fn vsha256h2q_u32( not(target_arch = "arm"), stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0") )] -pub unsafe fn vsha256hq_u32( - hash_abcd: uint32x4_t, - hash_efgh: uint32x4_t, - wk: uint32x4_t, -) -> uint32x4_t { +pub fn vsha256hq_u32(hash_abcd: uint32x4_t, hash_efgh: uint32x4_t, wk: uint32x4_t) -> uint32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -56911,12 +54079,10 @@ pub unsafe fn vsha256hq_u32( wk: uint32x4_t, ) -> uint32x4_t; } - _vsha256hq_u32(hash_abcd, hash_efgh, wk) + unsafe { _vsha256hq_u32(hash_abcd, hash_efgh, wk) } } #[doc = "SHA256 schedule update accelerator, first part."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha256su0q_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "sha2")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] @@ -56929,7 +54095,7 @@ pub unsafe fn vsha256hq_u32( not(target_arch = "arm"), stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0") )] -pub unsafe fn vsha256su0q_u32(w0_3: uint32x4_t, w4_7: uint32x4_t) -> uint32x4_t { +pub fn vsha256su0q_u32(w0_3: uint32x4_t, w4_7: uint32x4_t) -> uint32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -56938,12 +54104,10 @@ pub unsafe fn vsha256su0q_u32(w0_3: uint32x4_t, w4_7: uint32x4_t) -> uint32x4_t #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha256su0")] fn _vsha256su0q_u32(w0_3: uint32x4_t, w4_7: uint32x4_t) -> uint32x4_t; } - _vsha256su0q_u32(w0_3, w4_7) + unsafe { _vsha256su0q_u32(w0_3, w4_7) } } #[doc = "SHA256 schedule update accelerator, second part."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha256su1q_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "sha2")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] @@ -56956,11 +54120,7 @@ pub unsafe fn vsha256su0q_u32(w0_3: uint32x4_t, w4_7: uint32x4_t) -> uint32x4_t not(target_arch = "arm"), stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0") )] -pub unsafe fn vsha256su1q_u32( - tw0_3: uint32x4_t, - w8_11: uint32x4_t, - w12_15: uint32x4_t, -) -> uint32x4_t { +pub fn vsha256su1q_u32(tw0_3: uint32x4_t, w8_11: uint32x4_t, w12_15: uint32x4_t) -> uint32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -56970,124 +54130,106 @@ pub unsafe fn vsha256su1q_u32( fn _vsha256su1q_u32(tw0_3: uint32x4_t, w8_11: uint32x4_t, w12_15: uint32x4_t) -> uint32x4_t; } - _vsha256su1q_u32(tw0_3, w8_11, w12_15) + unsafe { _vsha256su1q_u32(tw0_3, w8_11, w12_15) } } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftins_v16i8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -unsafe fn vshiftins_v16i8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t { +fn vshiftins_v16i8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v16i8")] fn _vshiftins_v16i8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t; } - _vshiftins_v16i8(a, b, c) + unsafe { _vshiftins_v16i8(a, b, c) } } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftins_v1i64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -unsafe fn vshiftins_v1i64(a: int64x1_t, b: int64x1_t, c: int64x1_t) -> int64x1_t { +fn vshiftins_v1i64(a: int64x1_t, b: int64x1_t, c: int64x1_t) -> int64x1_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v1i64")] fn _vshiftins_v1i64(a: int64x1_t, b: int64x1_t, c: int64x1_t) -> int64x1_t; } - _vshiftins_v1i64(a, b, c) + unsafe { _vshiftins_v1i64(a, b, c) } } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftins_v2i32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -unsafe fn vshiftins_v2i32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t { +fn vshiftins_v2i32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v2i32")] fn _vshiftins_v2i32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t; } - _vshiftins_v2i32(a, b, c) + unsafe { _vshiftins_v2i32(a, b, c) } } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftins_v2i64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -unsafe fn vshiftins_v2i64(a: int64x2_t, b: int64x2_t, c: int64x2_t) -> int64x2_t { +fn vshiftins_v2i64(a: int64x2_t, b: int64x2_t, c: int64x2_t) -> int64x2_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v2i64")] fn _vshiftins_v2i64(a: int64x2_t, b: int64x2_t, c: int64x2_t) -> int64x2_t; } - _vshiftins_v2i64(a, b, c) + unsafe { _vshiftins_v2i64(a, b, c) } } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftins_v4i16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -unsafe fn vshiftins_v4i16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t { +fn vshiftins_v4i16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v4i16")] fn _vshiftins_v4i16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t; } - _vshiftins_v4i16(a, b, c) + unsafe { _vshiftins_v4i16(a, b, c) } } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftins_v4i32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -unsafe fn vshiftins_v4i32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t { +fn vshiftins_v4i32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v4i32")] fn _vshiftins_v4i32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t; } - _vshiftins_v4i32(a, b, c) + unsafe { _vshiftins_v4i32(a, b, c) } } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftins_v8i16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -unsafe fn vshiftins_v8i16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t { +fn vshiftins_v8i16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v8i16")] fn _vshiftins_v8i16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t; } - _vshiftins_v8i16(a, b, c) + unsafe { _vshiftins_v8i16(a, b, c) } } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftins_v8i8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -unsafe fn vshiftins_v8i8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t { +fn vshiftins_v8i8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v8i8")] fn _vshiftins_v8i8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t; } - _vshiftins_v8i8(a, b, c) + unsafe { _vshiftins_v8i8(a, b, c) } } #[doc = "Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -57105,14 +54247,12 @@ unsafe fn vshiftins_v8i8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vshl_n_s8(a: int8x8_t) -> int8x8_t { +pub fn vshl_n_s8(a: int8x8_t) -> int8x8_t { static_assert_uimm_bits!(N, 3); - simd_shl(a, vdup_n_s8(N as _)) + unsafe { simd_shl(a, vdup_n_s8(N as _)) } } #[doc = "Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -57130,14 +54270,12 @@ pub unsafe fn vshl_n_s8(a: int8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vshlq_n_s8(a: int8x16_t) -> int8x16_t { +pub fn vshlq_n_s8(a: int8x16_t) -> int8x16_t { static_assert_uimm_bits!(N, 3); - simd_shl(a, vdupq_n_s8(N as _)) + unsafe { simd_shl(a, vdupq_n_s8(N as _)) } } #[doc = "Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -57155,14 +54293,12 @@ pub unsafe fn vshlq_n_s8(a: int8x16_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vshl_n_s16(a: int16x4_t) -> int16x4_t { +pub fn vshl_n_s16(a: int16x4_t) -> int16x4_t { static_assert_uimm_bits!(N, 4); - simd_shl(a, vdup_n_s16(N as _)) + unsafe { simd_shl(a, vdup_n_s16(N as _)) } } #[doc = "Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -57180,14 +54316,12 @@ pub unsafe fn vshl_n_s16(a: int16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vshlq_n_s16(a: int16x8_t) -> int16x8_t { +pub fn vshlq_n_s16(a: int16x8_t) -> int16x8_t { static_assert_uimm_bits!(N, 4); - simd_shl(a, vdupq_n_s16(N as _)) + unsafe { simd_shl(a, vdupq_n_s16(N as _)) } } #[doc = "Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -57205,14 +54339,12 @@ pub unsafe fn vshlq_n_s16(a: int16x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vshl_n_s32(a: int32x2_t) -> int32x2_t { +pub fn vshl_n_s32(a: int32x2_t) -> int32x2_t { static_assert_uimm_bits!(N, 5); - simd_shl(a, vdup_n_s32(N as _)) + unsafe { simd_shl(a, vdup_n_s32(N as _)) } } #[doc = "Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -57230,14 +54362,12 @@ pub unsafe fn vshl_n_s32(a: int32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vshlq_n_s32(a: int32x4_t) -> int32x4_t { +pub fn vshlq_n_s32(a: int32x4_t) -> int32x4_t { static_assert_uimm_bits!(N, 5); - simd_shl(a, vdupq_n_s32(N as _)) + unsafe { simd_shl(a, vdupq_n_s32(N as _)) } } #[doc = "Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -57255,14 +54385,12 @@ pub unsafe fn vshlq_n_s32(a: int32x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vshl_n_s64(a: int64x1_t) -> int64x1_t { +pub fn vshl_n_s64(a: int64x1_t) -> int64x1_t { static_assert_uimm_bits!(N, 6); - simd_shl(a, vdup_n_s64(N as _)) + unsafe { simd_shl(a, vdup_n_s64(N as _)) } } #[doc = "Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -57280,14 +54408,12 @@ pub unsafe fn vshl_n_s64(a: int64x1_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vshlq_n_s64(a: int64x2_t) -> int64x2_t { +pub fn vshlq_n_s64(a: int64x2_t) -> int64x2_t { static_assert_uimm_bits!(N, 6); - simd_shl(a, vdupq_n_s64(N as _)) + unsafe { simd_shl(a, vdupq_n_s64(N as _)) } } #[doc = "Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -57305,14 +54431,12 @@ pub unsafe fn vshlq_n_s64(a: int64x2_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vshl_n_u8(a: uint8x8_t) -> uint8x8_t { +pub fn vshl_n_u8(a: uint8x8_t) -> uint8x8_t { static_assert_uimm_bits!(N, 3); - simd_shl(a, vdup_n_u8(N as _)) + unsafe { simd_shl(a, vdup_n_u8(N as _)) } } #[doc = "Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -57330,14 +54454,12 @@ pub unsafe fn vshl_n_u8(a: uint8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vshlq_n_u8(a: uint8x16_t) -> uint8x16_t { +pub fn vshlq_n_u8(a: uint8x16_t) -> uint8x16_t { static_assert_uimm_bits!(N, 3); - simd_shl(a, vdupq_n_u8(N as _)) + unsafe { simd_shl(a, vdupq_n_u8(N as _)) } } #[doc = "Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -57355,14 +54477,12 @@ pub unsafe fn vshlq_n_u8(a: uint8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vshl_n_u16(a: uint16x4_t) -> uint16x4_t { +pub fn vshl_n_u16(a: uint16x4_t) -> uint16x4_t { static_assert_uimm_bits!(N, 4); - simd_shl(a, vdup_n_u16(N as _)) + unsafe { simd_shl(a, vdup_n_u16(N as _)) } } #[doc = "Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -57380,14 +54500,12 @@ pub unsafe fn vshl_n_u16(a: uint16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vshlq_n_u16(a: uint16x8_t) -> uint16x8_t { +pub fn vshlq_n_u16(a: uint16x8_t) -> uint16x8_t { static_assert_uimm_bits!(N, 4); - simd_shl(a, vdupq_n_u16(N as _)) + unsafe { simd_shl(a, vdupq_n_u16(N as _)) } } #[doc = "Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -57405,14 +54523,12 @@ pub unsafe fn vshlq_n_u16(a: uint16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vshl_n_u32(a: uint32x2_t) -> uint32x2_t { +pub fn vshl_n_u32(a: uint32x2_t) -> uint32x2_t { static_assert_uimm_bits!(N, 5); - simd_shl(a, vdup_n_u32(N as _)) + unsafe { simd_shl(a, vdup_n_u32(N as _)) } } #[doc = "Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -57430,14 +54546,12 @@ pub unsafe fn vshl_n_u32(a: uint32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vshlq_n_u32(a: uint32x4_t) -> uint32x4_t { +pub fn vshlq_n_u32(a: uint32x4_t) -> uint32x4_t { static_assert_uimm_bits!(N, 5); - simd_shl(a, vdupq_n_u32(N as _)) + unsafe { simd_shl(a, vdupq_n_u32(N as _)) } } #[doc = "Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -57455,14 +54569,12 @@ pub unsafe fn vshlq_n_u32(a: uint32x4_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vshl_n_u64(a: uint64x1_t) -> uint64x1_t { +pub fn vshl_n_u64(a: uint64x1_t) -> uint64x1_t { static_assert_uimm_bits!(N, 6); - simd_shl(a, vdup_n_u64(N as _)) + unsafe { simd_shl(a, vdup_n_u64(N as _)) } } #[doc = "Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -57480,14 +54592,12 @@ pub unsafe fn vshl_n_u64(a: uint64x1_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vshlq_n_u64(a: uint64x2_t) -> uint64x2_t { +pub fn vshlq_n_u64(a: uint64x2_t) -> uint64x2_t { static_assert_uimm_bits!(N, 6); - simd_shl(a, vdupq_n_u64(N as _)) + unsafe { simd_shl(a, vdupq_n_u64(N as _)) } } #[doc = "Signed Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -57504,7 +54614,7 @@ pub unsafe fn vshlq_n_u64(a: uint64x2_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { +pub fn vshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshifts.v8i8")] #[cfg_attr( @@ -57513,12 +54623,10 @@ pub unsafe fn vshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { )] fn _vshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t; } - _vshl_s8(a, b) + unsafe { _vshl_s8(a, b) } } #[doc = "Signed Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -57535,7 +54643,7 @@ pub unsafe fn vshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { +pub fn vshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshifts.v16i8")] #[cfg_attr( @@ -57544,12 +54652,10 @@ pub unsafe fn vshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { )] fn _vshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t; } - _vshlq_s8(a, b) + unsafe { _vshlq_s8(a, b) } } #[doc = "Signed Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -57566,7 +54672,7 @@ pub unsafe fn vshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { +pub fn vshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshifts.v4i16")] #[cfg_attr( @@ -57575,12 +54681,10 @@ pub unsafe fn vshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { )] fn _vshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t; } - _vshl_s16(a, b) + unsafe { _vshl_s16(a, b) } } #[doc = "Signed Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -57597,7 +54701,7 @@ pub unsafe fn vshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { +pub fn vshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshifts.v8i16")] #[cfg_attr( @@ -57606,12 +54710,10 @@ pub unsafe fn vshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { )] fn _vshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t; } - _vshlq_s16(a, b) + unsafe { _vshlq_s16(a, b) } } #[doc = "Signed Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -57628,7 +54730,7 @@ pub unsafe fn vshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { +pub fn vshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshifts.v2i32")] #[cfg_attr( @@ -57637,12 +54739,10 @@ pub unsafe fn vshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { )] fn _vshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t; } - _vshl_s32(a, b) + unsafe { _vshl_s32(a, b) } } #[doc = "Signed Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -57659,7 +54759,7 @@ pub unsafe fn vshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { +pub fn vshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshifts.v4i32")] #[cfg_attr( @@ -57668,12 +54768,10 @@ pub unsafe fn vshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { )] fn _vshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t; } - _vshlq_s32(a, b) + unsafe { _vshlq_s32(a, b) } } #[doc = "Signed Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -57690,7 +54788,7 @@ pub unsafe fn vshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { +pub fn vshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshifts.v1i64")] #[cfg_attr( @@ -57699,12 +54797,10 @@ pub unsafe fn vshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { )] fn _vshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t; } - _vshl_s64(a, b) + unsafe { _vshl_s64(a, b) } } #[doc = "Signed Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -57721,7 +54817,7 @@ pub unsafe fn vshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { +pub fn vshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshifts.v2i64")] #[cfg_attr( @@ -57730,12 +54826,10 @@ pub unsafe fn vshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { )] fn _vshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t; } - _vshlq_s64(a, b) + unsafe { _vshlq_s64(a, b) } } #[doc = "Unsigned Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -57752,7 +54846,7 @@ pub unsafe fn vshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t { +pub fn vshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftu.v8i8")] #[cfg_attr( @@ -57761,12 +54855,10 @@ pub unsafe fn vshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t { )] fn _vshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t; } - _vshl_u8(a, b) + unsafe { _vshl_u8(a, b) } } #[doc = "Unsigned Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -57783,7 +54875,7 @@ pub unsafe fn vshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t { +pub fn vshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftu.v16i8")] #[cfg_attr( @@ -57792,12 +54884,10 @@ pub unsafe fn vshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t { )] fn _vshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t; } - _vshlq_u8(a, b) + unsafe { _vshlq_u8(a, b) } } #[doc = "Unsigned Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -57814,7 +54904,7 @@ pub unsafe fn vshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t { +pub fn vshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftu.v4i16")] #[cfg_attr( @@ -57823,12 +54913,10 @@ pub unsafe fn vshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t { )] fn _vshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t; } - _vshl_u16(a, b) + unsafe { _vshl_u16(a, b) } } #[doc = "Unsigned Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -57845,7 +54933,7 @@ pub unsafe fn vshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t { +pub fn vshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftu.v8i16")] #[cfg_attr( @@ -57854,12 +54942,10 @@ pub unsafe fn vshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t { )] fn _vshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t; } - _vshlq_u16(a, b) + unsafe { _vshlq_u16(a, b) } } #[doc = "Unsigned Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -57876,7 +54962,7 @@ pub unsafe fn vshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t { +pub fn vshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftu.v2i32")] #[cfg_attr( @@ -57885,12 +54971,10 @@ pub unsafe fn vshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t { )] fn _vshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t; } - _vshl_u32(a, b) + unsafe { _vshl_u32(a, b) } } #[doc = "Unsigned Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -57907,7 +54991,7 @@ pub unsafe fn vshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t { +pub fn vshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftu.v4i32")] #[cfg_attr( @@ -57916,12 +55000,10 @@ pub unsafe fn vshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t { )] fn _vshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t; } - _vshlq_u32(a, b) + unsafe { _vshlq_u32(a, b) } } #[doc = "Unsigned Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -57938,7 +55020,7 @@ pub unsafe fn vshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t { +pub fn vshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftu.v1i64")] #[cfg_attr( @@ -57947,12 +55029,10 @@ pub unsafe fn vshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t { )] fn _vshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t; } - _vshl_u64(a, b) + unsafe { _vshl_u64(a, b) } } #[doc = "Unsigned Shift left"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -57969,7 +55049,7 @@ pub unsafe fn vshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t { +pub fn vshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftu.v2i64")] #[cfg_attr( @@ -57978,12 +55058,10 @@ pub unsafe fn vshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t { )] fn _vshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t; } - _vshlq_u64(a, b) + unsafe { _vshlq_u64(a, b) } } #[doc = "Signed shift left long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -58001,14 +55079,12 @@ pub unsafe fn vshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vshll_n_s16(a: int16x4_t) -> int32x4_t { +pub fn vshll_n_s16(a: int16x4_t) -> int32x4_t { static_assert!(N >= 0 && N <= 16); - simd_shl(simd_cast(a), vdupq_n_s32(N as _)) + unsafe { simd_shl(simd_cast(a), vdupq_n_s32(N as _)) } } #[doc = "Signed shift left long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -58026,14 +55102,12 @@ pub unsafe fn vshll_n_s16(a: int16x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vshll_n_s32(a: int32x2_t) -> int64x2_t { +pub fn vshll_n_s32(a: int32x2_t) -> int64x2_t { static_assert!(N >= 0 && N <= 32); - simd_shl(simd_cast(a), vdupq_n_s64(N as _)) + unsafe { simd_shl(simd_cast(a), vdupq_n_s64(N as _)) } } #[doc = "Signed shift left long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -58051,14 +55125,12 @@ pub unsafe fn vshll_n_s32(a: int32x2_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vshll_n_s8(a: int8x8_t) -> int16x8_t { +pub fn vshll_n_s8(a: int8x8_t) -> int16x8_t { static_assert!(N >= 0 && N <= 8); - simd_shl(simd_cast(a), vdupq_n_s16(N as _)) + unsafe { simd_shl(simd_cast(a), vdupq_n_s16(N as _)) } } #[doc = "Signed shift left long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -58076,14 +55148,12 @@ pub unsafe fn vshll_n_s8(a: int8x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vshll_n_u16(a: uint16x4_t) -> uint32x4_t { +pub fn vshll_n_u16(a: uint16x4_t) -> uint32x4_t { static_assert!(N >= 0 && N <= 16); - simd_shl(simd_cast(a), vdupq_n_u32(N as _)) + unsafe { simd_shl(simd_cast(a), vdupq_n_u32(N as _)) } } #[doc = "Signed shift left long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -58101,14 +55171,12 @@ pub unsafe fn vshll_n_u16(a: uint16x4_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vshll_n_u32(a: uint32x2_t) -> uint64x2_t { +pub fn vshll_n_u32(a: uint32x2_t) -> uint64x2_t { static_assert!(N >= 0 && N <= 32); - simd_shl(simd_cast(a), vdupq_n_u64(N as _)) + unsafe { simd_shl(simd_cast(a), vdupq_n_u64(N as _)) } } #[doc = "Signed shift left long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -58126,14 +55194,12 @@ pub unsafe fn vshll_n_u32(a: uint32x2_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vshll_n_u8(a: uint8x8_t) -> uint16x8_t { +pub fn vshll_n_u8(a: uint8x8_t) -> uint16x8_t { static_assert!(N >= 0 && N <= 8); - simd_shl(simd_cast(a), vdupq_n_u16(N as _)) + unsafe { simd_shl(simd_cast(a), vdupq_n_u16(N as _)) } } #[doc = "Shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -58151,15 +55217,13 @@ pub unsafe fn vshll_n_u8(a: uint8x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vshr_n_s8(a: int8x8_t) -> int8x8_t { +pub fn vshr_n_s8(a: int8x8_t) -> int8x8_t { static_assert!(N >= 1 && N <= 8); let n: i32 = if N == 8 { 7 } else { N }; - simd_shr(a, vdup_n_s8(n as _)) + unsafe { simd_shr(a, vdup_n_s8(n as _)) } } #[doc = "Shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -58177,15 +55241,13 @@ pub unsafe fn vshr_n_s8(a: int8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vshrq_n_s8(a: int8x16_t) -> int8x16_t { +pub fn vshrq_n_s8(a: int8x16_t) -> int8x16_t { static_assert!(N >= 1 && N <= 8); let n: i32 = if N == 8 { 7 } else { N }; - simd_shr(a, vdupq_n_s8(n as _)) + unsafe { simd_shr(a, vdupq_n_s8(n as _)) } } #[doc = "Shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -58203,15 +55265,13 @@ pub unsafe fn vshrq_n_s8(a: int8x16_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vshr_n_s16(a: int16x4_t) -> int16x4_t { +pub fn vshr_n_s16(a: int16x4_t) -> int16x4_t { static_assert!(N >= 1 && N <= 16); let n: i32 = if N == 16 { 15 } else { N }; - simd_shr(a, vdup_n_s16(n as _)) + unsafe { simd_shr(a, vdup_n_s16(n as _)) } } #[doc = "Shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -58229,15 +55289,13 @@ pub unsafe fn vshr_n_s16(a: int16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vshrq_n_s16(a: int16x8_t) -> int16x8_t { +pub fn vshrq_n_s16(a: int16x8_t) -> int16x8_t { static_assert!(N >= 1 && N <= 16); let n: i32 = if N == 16 { 15 } else { N }; - simd_shr(a, vdupq_n_s16(n as _)) + unsafe { simd_shr(a, vdupq_n_s16(n as _)) } } #[doc = "Shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -58255,15 +55313,13 @@ pub unsafe fn vshrq_n_s16(a: int16x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vshr_n_s32(a: int32x2_t) -> int32x2_t { +pub fn vshr_n_s32(a: int32x2_t) -> int32x2_t { static_assert!(N >= 1 && N <= 32); let n: i32 = if N == 32 { 31 } else { N }; - simd_shr(a, vdup_n_s32(n as _)) + unsafe { simd_shr(a, vdup_n_s32(n as _)) } } #[doc = "Shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -58281,15 +55337,13 @@ pub unsafe fn vshr_n_s32(a: int32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vshrq_n_s32(a: int32x4_t) -> int32x4_t { +pub fn vshrq_n_s32(a: int32x4_t) -> int32x4_t { static_assert!(N >= 1 && N <= 32); let n: i32 = if N == 32 { 31 } else { N }; - simd_shr(a, vdupq_n_s32(n as _)) + unsafe { simd_shr(a, vdupq_n_s32(n as _)) } } #[doc = "Shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -58307,15 +55361,13 @@ pub unsafe fn vshrq_n_s32(a: int32x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vshr_n_s64(a: int64x1_t) -> int64x1_t { +pub fn vshr_n_s64(a: int64x1_t) -> int64x1_t { static_assert!(N >= 1 && N <= 64); let n: i32 = if N == 64 { 63 } else { N }; - simd_shr(a, vdup_n_s64(n as _)) + unsafe { simd_shr(a, vdup_n_s64(n as _)) } } #[doc = "Shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -58333,15 +55385,13 @@ pub unsafe fn vshr_n_s64(a: int64x1_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vshrq_n_s64(a: int64x2_t) -> int64x2_t { +pub fn vshrq_n_s64(a: int64x2_t) -> int64x2_t { static_assert!(N >= 1 && N <= 64); let n: i32 = if N == 64 { 63 } else { N }; - simd_shr(a, vdupq_n_s64(n as _)) + unsafe { simd_shr(a, vdupq_n_s64(n as _)) } } #[doc = "Shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -58359,19 +55409,17 @@ pub unsafe fn vshrq_n_s64(a: int64x2_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vshr_n_u8(a: uint8x8_t) -> uint8x8_t { +pub fn vshr_n_u8(a: uint8x8_t) -> uint8x8_t { static_assert!(N >= 1 && N <= 8); let n: i32 = if N == 8 { return vdup_n_u8(0); } else { N }; - simd_shr(a, vdup_n_u8(n as _)) + unsafe { simd_shr(a, vdup_n_u8(n as _)) } } #[doc = "Shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -58389,19 +55437,17 @@ pub unsafe fn vshr_n_u8(a: uint8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vshrq_n_u8(a: uint8x16_t) -> uint8x16_t { +pub fn vshrq_n_u8(a: uint8x16_t) -> uint8x16_t { static_assert!(N >= 1 && N <= 8); let n: i32 = if N == 8 { return vdupq_n_u8(0); } else { N }; - simd_shr(a, vdupq_n_u8(n as _)) + unsafe { simd_shr(a, vdupq_n_u8(n as _)) } } #[doc = "Shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -58419,19 +55465,17 @@ pub unsafe fn vshrq_n_u8(a: uint8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vshr_n_u16(a: uint16x4_t) -> uint16x4_t { +pub fn vshr_n_u16(a: uint16x4_t) -> uint16x4_t { static_assert!(N >= 1 && N <= 16); let n: i32 = if N == 16 { return vdup_n_u16(0); } else { N }; - simd_shr(a, vdup_n_u16(n as _)) + unsafe { simd_shr(a, vdup_n_u16(n as _)) } } #[doc = "Shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -58449,19 +55493,17 @@ pub unsafe fn vshr_n_u16(a: uint16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vshrq_n_u16(a: uint16x8_t) -> uint16x8_t { +pub fn vshrq_n_u16(a: uint16x8_t) -> uint16x8_t { static_assert!(N >= 1 && N <= 16); let n: i32 = if N == 16 { return vdupq_n_u16(0); } else { N }; - simd_shr(a, vdupq_n_u16(n as _)) + unsafe { simd_shr(a, vdupq_n_u16(n as _)) } } #[doc = "Shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -58479,19 +55521,17 @@ pub unsafe fn vshrq_n_u16(a: uint16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vshr_n_u32(a: uint32x2_t) -> uint32x2_t { +pub fn vshr_n_u32(a: uint32x2_t) -> uint32x2_t { static_assert!(N >= 1 && N <= 32); let n: i32 = if N == 32 { return vdup_n_u32(0); } else { N }; - simd_shr(a, vdup_n_u32(n as _)) + unsafe { simd_shr(a, vdup_n_u32(n as _)) } } #[doc = "Shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -58509,19 +55549,17 @@ pub unsafe fn vshr_n_u32(a: uint32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vshrq_n_u32(a: uint32x4_t) -> uint32x4_t { +pub fn vshrq_n_u32(a: uint32x4_t) -> uint32x4_t { static_assert!(N >= 1 && N <= 32); let n: i32 = if N == 32 { return vdupq_n_u32(0); } else { N }; - simd_shr(a, vdupq_n_u32(n as _)) + unsafe { simd_shr(a, vdupq_n_u32(n as _)) } } #[doc = "Shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -58539,19 +55577,17 @@ pub unsafe fn vshrq_n_u32(a: uint32x4_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vshr_n_u64(a: uint64x1_t) -> uint64x1_t { +pub fn vshr_n_u64(a: uint64x1_t) -> uint64x1_t { static_assert!(N >= 1 && N <= 64); let n: i32 = if N == 64 { return vdup_n_u64(0); } else { N }; - simd_shr(a, vdup_n_u64(n as _)) + unsafe { simd_shr(a, vdup_n_u64(n as _)) } } #[doc = "Shift right"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -58569,19 +55605,17 @@ pub unsafe fn vshr_n_u64(a: uint64x1_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vshrq_n_u64(a: uint64x2_t) -> uint64x2_t { +pub fn vshrq_n_u64(a: uint64x2_t) -> uint64x2_t { static_assert!(N >= 1 && N <= 64); let n: i32 = if N == 64 { return vdupq_n_u64(0); } else { N }; - simd_shr(a, vdupq_n_u64(n as _)) + unsafe { simd_shr(a, vdupq_n_u64(n as _)) } } #[doc = "Shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -58599,14 +55633,12 @@ pub unsafe fn vshrq_n_u64(a: uint64x2_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vshrn_n_s16(a: int16x8_t) -> int8x8_t { +pub fn vshrn_n_s16(a: int16x8_t) -> int8x8_t { static_assert!(N >= 1 && N <= 8); - simd_cast(simd_shr(a, vdupq_n_s16(N as _))) + unsafe { simd_cast(simd_shr(a, vdupq_n_s16(N as _))) } } #[doc = "Shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -58624,14 +55656,12 @@ pub unsafe fn vshrn_n_s16(a: int16x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vshrn_n_s32(a: int32x4_t) -> int16x4_t { +pub fn vshrn_n_s32(a: int32x4_t) -> int16x4_t { static_assert!(N >= 1 && N <= 16); - simd_cast(simd_shr(a, vdupq_n_s32(N as _))) + unsafe { simd_cast(simd_shr(a, vdupq_n_s32(N as _))) } } #[doc = "Shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -58649,14 +55679,12 @@ pub unsafe fn vshrn_n_s32(a: int32x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vshrn_n_s64(a: int64x2_t) -> int32x2_t { +pub fn vshrn_n_s64(a: int64x2_t) -> int32x2_t { static_assert!(N >= 1 && N <= 32); - simd_cast(simd_shr(a, vdupq_n_s64(N as _))) + unsafe { simd_cast(simd_shr(a, vdupq_n_s64(N as _))) } } #[doc = "Shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -58674,14 +55702,12 @@ pub unsafe fn vshrn_n_s64(a: int64x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vshrn_n_u16(a: uint16x8_t) -> uint8x8_t { +pub fn vshrn_n_u16(a: uint16x8_t) -> uint8x8_t { static_assert!(N >= 1 && N <= 8); - simd_cast(simd_shr(a, vdupq_n_u16(N as _))) + unsafe { simd_cast(simd_shr(a, vdupq_n_u16(N as _))) } } #[doc = "Shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -58699,14 +55725,12 @@ pub unsafe fn vshrn_n_u16(a: uint16x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vshrn_n_u32(a: uint32x4_t) -> uint16x4_t { +pub fn vshrn_n_u32(a: uint32x4_t) -> uint16x4_t { static_assert!(N >= 1 && N <= 16); - simd_cast(simd_shr(a, vdupq_n_u32(N as _))) + unsafe { simd_cast(simd_shr(a, vdupq_n_u32(N as _))) } } #[doc = "Shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -58724,342 +55748,324 @@ pub unsafe fn vshrn_n_u32(a: uint32x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vshrn_n_u64(a: uint64x2_t) -> uint32x2_t { +pub fn vshrn_n_u64(a: uint64x2_t) -> uint32x2_t { static_assert!(N >= 1 && N <= 32); - simd_cast(simd_shr(a, vdupq_n_u64(N as _))) + unsafe { simd_cast(simd_shr(a, vdupq_n_u64(N as _))) } } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.8", N = 1))] #[rustc_legacy_const_generics(2)] -pub unsafe fn vsli_n_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { +pub fn vsli_n_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { static_assert_uimm_bits!(N, 3); vshiftins_v8i8(a, b, int8x8_t::splat(N as i8)) } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.8", N = 1))] #[rustc_legacy_const_generics(2)] -pub unsafe fn vsliq_n_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { +pub fn vsliq_n_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { static_assert_uimm_bits!(N, 3); vshiftins_v16i8(a, b, int8x16_t::splat(N as i8)) } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.16", N = 1))] #[rustc_legacy_const_generics(2)] -pub unsafe fn vsli_n_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { +pub fn vsli_n_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { static_assert_uimm_bits!(N, 4); vshiftins_v4i16(a, b, int16x4_t::splat(N as i16)) } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.16", N = 1))] #[rustc_legacy_const_generics(2)] -pub unsafe fn vsliq_n_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { +pub fn vsliq_n_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { static_assert_uimm_bits!(N, 4); vshiftins_v8i16(a, b, int16x8_t::splat(N as i16)) } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.32", N = 1))] #[rustc_legacy_const_generics(2)] -pub unsafe fn vsli_n_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { +pub fn vsli_n_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { static_assert!(N >= 0 && N <= 31); vshiftins_v2i32(a, b, int32x2_t::splat(N)) } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.32", N = 1))] #[rustc_legacy_const_generics(2)] -pub unsafe fn vsliq_n_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { +pub fn vsliq_n_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { static_assert!(N >= 0 && N <= 31); vshiftins_v4i32(a, b, int32x4_t::splat(N)) } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.64", N = 1))] #[rustc_legacy_const_generics(2)] -pub unsafe fn vsli_n_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { +pub fn vsli_n_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { static_assert!(N >= 0 && N <= 63); vshiftins_v1i64(a, b, int64x1_t::splat(N as i64)) } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.64", N = 1))] #[rustc_legacy_const_generics(2)] -pub unsafe fn vsliq_n_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { +pub fn vsliq_n_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { static_assert!(N >= 0 && N <= 63); vshiftins_v2i64(a, b, int64x2_t::splat(N as i64)) } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.8", N = 1))] #[rustc_legacy_const_generics(2)] -pub unsafe fn vsli_n_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { +pub fn vsli_n_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { static_assert_uimm_bits!(N, 3); - transmute(vshiftins_v8i8( - transmute(a), - transmute(b), - int8x8_t::splat(N as i8), - )) + unsafe { + transmute(vshiftins_v8i8( + transmute(a), + transmute(b), + int8x8_t::splat(N as i8), + )) + } } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.8", N = 1))] #[rustc_legacy_const_generics(2)] -pub unsafe fn vsliq_n_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { +pub fn vsliq_n_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { static_assert_uimm_bits!(N, 3); - transmute(vshiftins_v16i8( - transmute(a), - transmute(b), - int8x16_t::splat(N as i8), - )) + unsafe { + transmute(vshiftins_v16i8( + transmute(a), + transmute(b), + int8x16_t::splat(N as i8), + )) + } } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.16", N = 1))] #[rustc_legacy_const_generics(2)] -pub unsafe fn vsli_n_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { +pub fn vsli_n_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { static_assert_uimm_bits!(N, 4); - transmute(vshiftins_v4i16( - transmute(a), - transmute(b), - int16x4_t::splat(N as i16), - )) + unsafe { + transmute(vshiftins_v4i16( + transmute(a), + transmute(b), + int16x4_t::splat(N as i16), + )) + } } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.16", N = 1))] #[rustc_legacy_const_generics(2)] -pub unsafe fn vsliq_n_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { +pub fn vsliq_n_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { static_assert_uimm_bits!(N, 4); - transmute(vshiftins_v8i16( - transmute(a), - transmute(b), - int16x8_t::splat(N as i16), - )) + unsafe { + transmute(vshiftins_v8i16( + transmute(a), + transmute(b), + int16x8_t::splat(N as i16), + )) + } } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.32", N = 1))] #[rustc_legacy_const_generics(2)] -pub unsafe fn vsli_n_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { +pub fn vsli_n_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { static_assert!(N >= 0 && N <= 31); - transmute(vshiftins_v2i32( - transmute(a), - transmute(b), - int32x2_t::splat(N as i32), - )) + unsafe { + transmute(vshiftins_v2i32( + transmute(a), + transmute(b), + int32x2_t::splat(N as i32), + )) + } } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.32", N = 1))] #[rustc_legacy_const_generics(2)] -pub unsafe fn vsliq_n_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { +pub fn vsliq_n_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { static_assert!(N >= 0 && N <= 31); - transmute(vshiftins_v4i32( - transmute(a), - transmute(b), - int32x4_t::splat(N as i32), - )) + unsafe { + transmute(vshiftins_v4i32( + transmute(a), + transmute(b), + int32x4_t::splat(N as i32), + )) + } } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.64", N = 1))] #[rustc_legacy_const_generics(2)] -pub unsafe fn vsli_n_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { +pub fn vsli_n_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { static_assert!(N >= 0 && N <= 63); - transmute(vshiftins_v1i64( - transmute(a), - transmute(b), - int64x1_t::splat(N as i64), - )) + unsafe { + transmute(vshiftins_v1i64( + transmute(a), + transmute(b), + int64x1_t::splat(N as i64), + )) + } } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.64", N = 1))] #[rustc_legacy_const_generics(2)] -pub unsafe fn vsliq_n_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { +pub fn vsliq_n_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { static_assert!(N >= 0 && N <= 63); - transmute(vshiftins_v2i64( - transmute(a), - transmute(b), - int64x2_t::splat(N as i64), - )) + unsafe { + transmute(vshiftins_v2i64( + transmute(a), + transmute(b), + int64x2_t::splat(N as i64), + )) + } } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.8", N = 1))] #[rustc_legacy_const_generics(2)] -pub unsafe fn vsli_n_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { +pub fn vsli_n_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { static_assert_uimm_bits!(N, 3); - transmute(vshiftins_v8i8( - transmute(a), - transmute(b), - int8x8_t::splat(N as i8), - )) + unsafe { + transmute(vshiftins_v8i8( + transmute(a), + transmute(b), + int8x8_t::splat(N as i8), + )) + } } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.8", N = 1))] #[rustc_legacy_const_generics(2)] -pub unsafe fn vsliq_n_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { +pub fn vsliq_n_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { static_assert_uimm_bits!(N, 3); - transmute(vshiftins_v16i8( - transmute(a), - transmute(b), - int8x16_t::splat(N as i8), - )) + unsafe { + transmute(vshiftins_v16i8( + transmute(a), + transmute(b), + int8x16_t::splat(N as i8), + )) + } } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.16", N = 1))] #[rustc_legacy_const_generics(2)] -pub unsafe fn vsli_n_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { +pub fn vsli_n_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { static_assert_uimm_bits!(N, 4); - transmute(vshiftins_v4i16( - transmute(a), - transmute(b), - int16x4_t::splat(N as i16), - )) + unsafe { + transmute(vshiftins_v4i16( + transmute(a), + transmute(b), + int16x4_t::splat(N as i16), + )) + } } #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.16", N = 1))] #[rustc_legacy_const_generics(2)] -pub unsafe fn vsliq_n_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { +pub fn vsliq_n_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { static_assert_uimm_bits!(N, 4); - transmute(vshiftins_v8i16( - transmute(a), - transmute(b), - int16x8_t::splat(N as i16), - )) + unsafe { + transmute(vshiftins_v8i16( + transmute(a), + transmute(b), + int16x8_t::splat(N as i16), + )) + } } #[doc = "Signed shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -59077,14 +56083,12 @@ pub unsafe fn vsliq_n_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vsra_n_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { +pub fn vsra_n_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { static_assert!(N >= 1 && N <= 8); - simd_add(a, vshr_n_s8::(b)) + unsafe { simd_add(a, vshr_n_s8::(b)) } } #[doc = "Signed shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -59102,14 +56106,12 @@ pub unsafe fn vsra_n_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vsraq_n_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { +pub fn vsraq_n_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { static_assert!(N >= 1 && N <= 8); - simd_add(a, vshrq_n_s8::(b)) + unsafe { simd_add(a, vshrq_n_s8::(b)) } } #[doc = "Signed shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -59127,14 +56129,12 @@ pub unsafe fn vsraq_n_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vsra_n_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { +pub fn vsra_n_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { static_assert!(N >= 1 && N <= 16); - simd_add(a, vshr_n_s16::(b)) + unsafe { simd_add(a, vshr_n_s16::(b)) } } #[doc = "Signed shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -59152,14 +56152,12 @@ pub unsafe fn vsra_n_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vsraq_n_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { +pub fn vsraq_n_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { static_assert!(N >= 1 && N <= 16); - simd_add(a, vshrq_n_s16::(b)) + unsafe { simd_add(a, vshrq_n_s16::(b)) } } #[doc = "Signed shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -59177,14 +56175,12 @@ pub unsafe fn vsraq_n_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vsra_n_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { +pub fn vsra_n_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { static_assert!(N >= 1 && N <= 32); - simd_add(a, vshr_n_s32::(b)) + unsafe { simd_add(a, vshr_n_s32::(b)) } } #[doc = "Signed shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -59202,14 +56198,12 @@ pub unsafe fn vsra_n_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vsraq_n_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { +pub fn vsraq_n_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { static_assert!(N >= 1 && N <= 32); - simd_add(a, vshrq_n_s32::(b)) + unsafe { simd_add(a, vshrq_n_s32::(b)) } } #[doc = "Signed shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -59227,14 +56221,12 @@ pub unsafe fn vsraq_n_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vsra_n_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { +pub fn vsra_n_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { static_assert!(N >= 1 && N <= 64); - simd_add(a, vshr_n_s64::(b)) + unsafe { simd_add(a, vshr_n_s64::(b)) } } #[doc = "Signed shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -59252,14 +56244,12 @@ pub unsafe fn vsra_n_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vsraq_n_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { +pub fn vsraq_n_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { static_assert!(N >= 1 && N <= 64); - simd_add(a, vshrq_n_s64::(b)) + unsafe { simd_add(a, vshrq_n_s64::(b)) } } #[doc = "Unsigned shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -59277,14 +56267,12 @@ pub unsafe fn vsraq_n_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vsra_n_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { +pub fn vsra_n_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { static_assert!(N >= 1 && N <= 8); - simd_add(a, vshr_n_u8::(b)) + unsafe { simd_add(a, vshr_n_u8::(b)) } } #[doc = "Unsigned shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -59302,14 +56290,12 @@ pub unsafe fn vsra_n_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vsraq_n_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { +pub fn vsraq_n_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { static_assert!(N >= 1 && N <= 8); - simd_add(a, vshrq_n_u8::(b)) + unsafe { simd_add(a, vshrq_n_u8::(b)) } } #[doc = "Unsigned shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -59327,14 +56313,12 @@ pub unsafe fn vsraq_n_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16 target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vsra_n_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { +pub fn vsra_n_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { static_assert!(N >= 1 && N <= 16); - simd_add(a, vshr_n_u16::(b)) + unsafe { simd_add(a, vshr_n_u16::(b)) } } #[doc = "Unsigned shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -59352,14 +56336,12 @@ pub unsafe fn vsra_n_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4 target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vsraq_n_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { +pub fn vsraq_n_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { static_assert!(N >= 1 && N <= 16); - simd_add(a, vshrq_n_u16::(b)) + unsafe { simd_add(a, vshrq_n_u16::(b)) } } #[doc = "Unsigned shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -59377,14 +56359,12 @@ pub unsafe fn vsraq_n_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vsra_n_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { +pub fn vsra_n_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { static_assert!(N >= 1 && N <= 32); - simd_add(a, vshr_n_u32::(b)) + unsafe { simd_add(a, vshr_n_u32::(b)) } } #[doc = "Unsigned shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -59402,14 +56382,12 @@ pub unsafe fn vsra_n_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2 target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vsraq_n_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { +pub fn vsraq_n_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { static_assert!(N >= 1 && N <= 32); - simd_add(a, vshrq_n_u32::(b)) + unsafe { simd_add(a, vshrq_n_u32::(b)) } } #[doc = "Unsigned shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -59427,14 +56405,12 @@ pub unsafe fn vsraq_n_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vsra_n_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { +pub fn vsra_n_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { static_assert!(N >= 1 && N <= 64); - simd_add(a, vshr_n_u64::(b)) + unsafe { simd_add(a, vshr_n_u64::(b)) } } #[doc = "Unsigned shift right and accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -59452,337 +56428,321 @@ pub unsafe fn vsra_n_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1 target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vsraq_n_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { +pub fn vsraq_n_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { static_assert!(N >= 1 && N <= 64); - simd_add(a, vshrq_n_u64::(b)) + unsafe { simd_add(a, vshrq_n_u64::(b)) } } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.8", N = 1))] #[rustc_legacy_const_generics(2)] -pub unsafe fn vsri_n_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { +pub fn vsri_n_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { static_assert!(1 <= N && N <= 8); vshiftins_v8i8(a, b, int8x8_t::splat(-N as i8)) } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.8", N = 1))] #[rustc_legacy_const_generics(2)] -pub unsafe fn vsriq_n_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { +pub fn vsriq_n_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { static_assert!(1 <= N && N <= 8); vshiftins_v16i8(a, b, int8x16_t::splat(-N as i8)) } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.16", N = 1))] #[rustc_legacy_const_generics(2)] -pub unsafe fn vsri_n_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { +pub fn vsri_n_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { static_assert!(1 <= N && N <= 16); vshiftins_v4i16(a, b, int16x4_t::splat(-N as i16)) } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.16", N = 1))] #[rustc_legacy_const_generics(2)] -pub unsafe fn vsriq_n_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { +pub fn vsriq_n_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { static_assert!(1 <= N && N <= 16); vshiftins_v8i16(a, b, int16x8_t::splat(-N as i16)) } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.32", N = 1))] #[rustc_legacy_const_generics(2)] -pub unsafe fn vsri_n_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { +pub fn vsri_n_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { static_assert!(1 <= N && N <= 32); vshiftins_v2i32(a, b, int32x2_t::splat(-N as i32)) } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.32", N = 1))] #[rustc_legacy_const_generics(2)] -pub unsafe fn vsriq_n_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { +pub fn vsriq_n_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { static_assert!(1 <= N && N <= 32); vshiftins_v4i32(a, b, int32x4_t::splat(-N as i32)) } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.64", N = 1))] #[rustc_legacy_const_generics(2)] -pub unsafe fn vsri_n_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { +pub fn vsri_n_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { static_assert!(1 <= N && N <= 64); vshiftins_v1i64(a, b, int64x1_t::splat(-N as i64)) } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.64", N = 1))] #[rustc_legacy_const_generics(2)] -pub unsafe fn vsriq_n_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { +pub fn vsriq_n_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { static_assert!(1 <= N && N <= 64); vshiftins_v2i64(a, b, int64x2_t::splat(-N as i64)) } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.8", N = 1))] #[rustc_legacy_const_generics(2)] -pub unsafe fn vsri_n_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { +pub fn vsri_n_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { static_assert!(1 <= N && N <= 8); - transmute(vshiftins_v8i8( - transmute(a), - transmute(b), - int8x8_t::splat(-N as i8), - )) + unsafe { + transmute(vshiftins_v8i8( + transmute(a), + transmute(b), + int8x8_t::splat(-N as i8), + )) + } } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.8", N = 1))] #[rustc_legacy_const_generics(2)] -pub unsafe fn vsriq_n_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { +pub fn vsriq_n_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { static_assert!(1 <= N && N <= 8); - transmute(vshiftins_v16i8( - transmute(a), - transmute(b), - int8x16_t::splat(-N as i8), - )) + unsafe { + transmute(vshiftins_v16i8( + transmute(a), + transmute(b), + int8x16_t::splat(-N as i8), + )) + } } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.16", N = 1))] #[rustc_legacy_const_generics(2)] -pub unsafe fn vsri_n_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { +pub fn vsri_n_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { static_assert!(1 <= N && N <= 16); - transmute(vshiftins_v4i16( - transmute(a), - transmute(b), - int16x4_t::splat(-N as i16), - )) + unsafe { + transmute(vshiftins_v4i16( + transmute(a), + transmute(b), + int16x4_t::splat(-N as i16), + )) + } } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.16", N = 1))] #[rustc_legacy_const_generics(2)] -pub unsafe fn vsriq_n_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { +pub fn vsriq_n_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { static_assert!(1 <= N && N <= 16); - transmute(vshiftins_v8i16( - transmute(a), - transmute(b), - int16x8_t::splat(-N as i16), - )) + unsafe { + transmute(vshiftins_v8i16( + transmute(a), + transmute(b), + int16x8_t::splat(-N as i16), + )) + } } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.32", N = 1))] #[rustc_legacy_const_generics(2)] -pub unsafe fn vsri_n_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { +pub fn vsri_n_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { static_assert!(1 <= N && N <= 32); - transmute(vshiftins_v2i32( - transmute(a), - transmute(b), - int32x2_t::splat(-N), - )) + unsafe { + transmute(vshiftins_v2i32( + transmute(a), + transmute(b), + int32x2_t::splat(-N), + )) + } } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.32", N = 1))] #[rustc_legacy_const_generics(2)] -pub unsafe fn vsriq_n_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { +pub fn vsriq_n_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { static_assert!(1 <= N && N <= 32); - transmute(vshiftins_v4i32( - transmute(a), - transmute(b), - int32x4_t::splat(-N), - )) + unsafe { + transmute(vshiftins_v4i32( + transmute(a), + transmute(b), + int32x4_t::splat(-N), + )) + } } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.64", N = 1))] #[rustc_legacy_const_generics(2)] -pub unsafe fn vsri_n_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { +pub fn vsri_n_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { static_assert!(1 <= N && N <= 64); - transmute(vshiftins_v1i64( - transmute(a), - transmute(b), - int64x1_t::splat(-N as i64), - )) + unsafe { + transmute(vshiftins_v1i64( + transmute(a), + transmute(b), + int64x1_t::splat(-N as i64), + )) + } } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.64", N = 1))] #[rustc_legacy_const_generics(2)] -pub unsafe fn vsriq_n_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { +pub fn vsriq_n_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { static_assert!(1 <= N && N <= 64); - transmute(vshiftins_v2i64( - transmute(a), - transmute(b), - int64x2_t::splat(-N as i64), - )) + unsafe { + transmute(vshiftins_v2i64( + transmute(a), + transmute(b), + int64x2_t::splat(-N as i64), + )) + } } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.8", N = 1))] #[rustc_legacy_const_generics(2)] -pub unsafe fn vsri_n_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { +pub fn vsri_n_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { static_assert!(1 <= N && N <= 8); - transmute(vshiftins_v8i8( - transmute(a), - transmute(b), - int8x8_t::splat(-N as i8), - )) + unsafe { + transmute(vshiftins_v8i8( + transmute(a), + transmute(b), + int8x8_t::splat(-N as i8), + )) + } } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.8", N = 1))] #[rustc_legacy_const_generics(2)] -pub unsafe fn vsriq_n_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { +pub fn vsriq_n_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { static_assert!(1 <= N && N <= 8); - transmute(vshiftins_v16i8( - transmute(a), - transmute(b), - int8x16_t::splat(-N as i8), - )) + unsafe { + transmute(vshiftins_v16i8( + transmute(a), + transmute(b), + int8x16_t::splat(-N as i8), + )) + } } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.16", N = 1))] #[rustc_legacy_const_generics(2)] -pub unsafe fn vsri_n_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { +pub fn vsri_n_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { static_assert!(1 <= N && N <= 16); - transmute(vshiftins_v4i16( - transmute(a), - transmute(b), - int16x4_t::splat(-N as i16), - )) + unsafe { + transmute(vshiftins_v4i16( + transmute(a), + transmute(b), + int16x4_t::splat(-N as i16), + )) + } } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.16", N = 1))] #[rustc_legacy_const_generics(2)] -pub unsafe fn vsriq_n_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { +pub fn vsriq_n_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { static_assert!(1 <= N && N <= 16); - transmute(vshiftins_v8i16( - transmute(a), - transmute(b), - int16x8_t::splat(-N as i16), - )) + unsafe { + transmute(vshiftins_v8i16( + transmute(a), + transmute(b), + int16x8_t::splat(-N as i16), + )) + } } #[doc = "Store multiple single-element structures from one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16)"] @@ -67186,8 +64146,6 @@ pub unsafe fn vst4q_p16(a: *mut p16, b: poly16x8x4_t) { } #[doc = "Subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.f16"))] @@ -67197,13 +64155,11 @@ pub unsafe fn vst4q_p16(a: *mut p16, b: poly16x8x4_t) { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vsub_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { - simd_sub(a, b) +pub fn vsub_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { + unsafe { simd_sub(a, b) } } #[doc = "Subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.f16"))] @@ -67213,13 +64169,11 @@ pub unsafe fn vsub_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vsubq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { - simd_sub(a, b) +pub fn vsubq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { + unsafe { simd_sub(a, b) } } #[doc = "Subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67236,13 +64190,11 @@ pub unsafe fn vsubq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vsub_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { - simd_sub(a, b) +pub fn vsub_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { + unsafe { simd_sub(a, b) } } #[doc = "Subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67259,13 +64211,11 @@ pub unsafe fn vsub_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vsubq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { - simd_sub(a, b) +pub fn vsubq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { + unsafe { simd_sub(a, b) } } #[doc = "Subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67282,13 +64232,11 @@ pub unsafe fn vsubq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vsub_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { - simd_sub(a, b) +pub fn vsub_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + unsafe { simd_sub(a, b) } } #[doc = "Subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67305,13 +64253,11 @@ pub unsafe fn vsub_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vsubq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { - simd_sub(a, b) +pub fn vsubq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + unsafe { simd_sub(a, b) } } #[doc = "Subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67328,13 +64274,11 @@ pub unsafe fn vsubq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vsub_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { - simd_sub(a, b) +pub fn vsub_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + unsafe { simd_sub(a, b) } } #[doc = "Subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67351,13 +64295,11 @@ pub unsafe fn vsub_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vsubq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { - simd_sub(a, b) +pub fn vsubq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + unsafe { simd_sub(a, b) } } #[doc = "Subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67374,13 +64316,11 @@ pub unsafe fn vsubq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vsub_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { - simd_sub(a, b) +pub fn vsub_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + unsafe { simd_sub(a, b) } } #[doc = "Subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67397,13 +64337,11 @@ pub unsafe fn vsub_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vsubq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { - simd_sub(a, b) +pub fn vsubq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + unsafe { simd_sub(a, b) } } #[doc = "Subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67420,13 +64358,11 @@ pub unsafe fn vsubq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vsub_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { - simd_sub(a, b) +pub fn vsub_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + unsafe { simd_sub(a, b) } } #[doc = "Subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67443,13 +64379,11 @@ pub unsafe fn vsub_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vsubq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { - simd_sub(a, b) +pub fn vsubq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + unsafe { simd_sub(a, b) } } #[doc = "Subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67466,13 +64400,11 @@ pub unsafe fn vsubq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vsub_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { - simd_sub(a, b) +pub fn vsub_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { + unsafe { simd_sub(a, b) } } #[doc = "Subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67489,13 +64421,11 @@ pub unsafe fn vsub_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vsubq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { - simd_sub(a, b) +pub fn vsubq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { + unsafe { simd_sub(a, b) } } #[doc = "Subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67512,13 +64442,11 @@ pub unsafe fn vsubq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vsub_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { - simd_sub(a, b) +pub fn vsub_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { + unsafe { simd_sub(a, b) } } #[doc = "Subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67535,13 +64463,11 @@ pub unsafe fn vsub_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vsubq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { - simd_sub(a, b) +pub fn vsubq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { + unsafe { simd_sub(a, b) } } #[doc = "Subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67558,13 +64484,11 @@ pub unsafe fn vsubq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vsub_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { - simd_sub(a, b) +pub fn vsub_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { + unsafe { simd_sub(a, b) } } #[doc = "Subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67581,13 +64505,11 @@ pub unsafe fn vsub_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vsubq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { - simd_sub(a, b) +pub fn vsubq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { + unsafe { simd_sub(a, b) } } #[doc = "Subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67604,13 +64526,11 @@ pub unsafe fn vsubq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vsub_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { - simd_sub(a, b) +pub fn vsub_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + unsafe { simd_sub(a, b) } } #[doc = "Subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67627,13 +64547,11 @@ pub unsafe fn vsub_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vsubq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { - simd_sub(a, b) +pub fn vsubq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + unsafe { simd_sub(a, b) } } #[doc = "Subtract returning high narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67650,14 +64568,12 @@ pub unsafe fn vsubq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vsubhn_high_s16(a: int8x8_t, b: int16x8_t, c: int16x8_t) -> int8x16_t { +pub fn vsubhn_high_s16(a: int8x8_t, b: int16x8_t, c: int16x8_t) -> int8x16_t { let d: int8x8_t = vsubhn_s16(b, c); - simd_shuffle!(a, d, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) + unsafe { simd_shuffle!(a, d, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) } } #[doc = "Subtract returning high narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67674,14 +64590,12 @@ pub unsafe fn vsubhn_high_s16(a: int8x8_t, b: int16x8_t, c: int16x8_t) -> int8x1 target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vsubhn_high_s32(a: int16x4_t, b: int32x4_t, c: int32x4_t) -> int16x8_t { +pub fn vsubhn_high_s32(a: int16x4_t, b: int32x4_t, c: int32x4_t) -> int16x8_t { let d: int16x4_t = vsubhn_s32(b, c); - simd_shuffle!(a, d, [0, 1, 2, 3, 4, 5, 6, 7]) + unsafe { simd_shuffle!(a, d, [0, 1, 2, 3, 4, 5, 6, 7]) } } #[doc = "Subtract returning high narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67698,14 +64612,12 @@ pub unsafe fn vsubhn_high_s32(a: int16x4_t, b: int32x4_t, c: int32x4_t) -> int16 target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vsubhn_high_s64(a: int32x2_t, b: int64x2_t, c: int64x2_t) -> int32x4_t { +pub fn vsubhn_high_s64(a: int32x2_t, b: int64x2_t, c: int64x2_t) -> int32x4_t { let d: int32x2_t = vsubhn_s64(b, c); - simd_shuffle!(a, d, [0, 1, 2, 3]) + unsafe { simd_shuffle!(a, d, [0, 1, 2, 3]) } } #[doc = "Subtract returning high narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67722,14 +64634,12 @@ pub unsafe fn vsubhn_high_s64(a: int32x2_t, b: int64x2_t, c: int64x2_t) -> int32 target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vsubhn_high_u16(a: uint8x8_t, b: uint16x8_t, c: uint16x8_t) -> uint8x16_t { +pub fn vsubhn_high_u16(a: uint8x8_t, b: uint16x8_t, c: uint16x8_t) -> uint8x16_t { let d: uint8x8_t = vsubhn_u16(b, c); - simd_shuffle!(a, d, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) + unsafe { simd_shuffle!(a, d, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) } } #[doc = "Subtract returning high narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67746,14 +64656,12 @@ pub unsafe fn vsubhn_high_u16(a: uint8x8_t, b: uint16x8_t, c: uint16x8_t) -> uin target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vsubhn_high_u32(a: uint16x4_t, b: uint32x4_t, c: uint32x4_t) -> uint16x8_t { +pub fn vsubhn_high_u32(a: uint16x4_t, b: uint32x4_t, c: uint32x4_t) -> uint16x8_t { let d: uint16x4_t = vsubhn_u32(b, c); - simd_shuffle!(a, d, [0, 1, 2, 3, 4, 5, 6, 7]) + unsafe { simd_shuffle!(a, d, [0, 1, 2, 3, 4, 5, 6, 7]) } } #[doc = "Subtract returning high narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67770,14 +64678,12 @@ pub unsafe fn vsubhn_high_u32(a: uint16x4_t, b: uint32x4_t, c: uint32x4_t) -> ui target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vsubhn_high_u64(a: uint32x2_t, b: uint64x2_t, c: uint64x2_t) -> uint32x4_t { +pub fn vsubhn_high_u64(a: uint32x2_t, b: uint64x2_t, c: uint64x2_t) -> uint32x4_t { let d: uint32x2_t = vsubhn_u64(b, c); - simd_shuffle!(a, d, [0, 1, 2, 3]) + unsafe { simd_shuffle!(a, d, [0, 1, 2, 3]) } } #[doc = "Subtract returning high narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67794,14 +64700,12 @@ pub unsafe fn vsubhn_high_u64(a: uint32x2_t, b: uint64x2_t, c: uint64x2_t) -> ui target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vsubhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t { +pub fn vsubhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t { let c: i16x8 = i16x8::new(8, 8, 8, 8, 8, 8, 8, 8); - simd_cast(simd_shr(simd_sub(a, b), transmute(c))) + unsafe { simd_cast(simd_shr(simd_sub(a, b), transmute(c))) } } #[doc = "Subtract returning high narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67818,14 +64722,12 @@ pub unsafe fn vsubhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vsubhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t { +pub fn vsubhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t { let c: i32x4 = i32x4::new(16, 16, 16, 16); - simd_cast(simd_shr(simd_sub(a, b), transmute(c))) + unsafe { simd_cast(simd_shr(simd_sub(a, b), transmute(c))) } } #[doc = "Subtract returning high narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_s64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67842,14 +64744,12 @@ pub unsafe fn vsubhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vsubhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t { +pub fn vsubhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t { let c: i64x2 = i64x2::new(32, 32); - simd_cast(simd_shr(simd_sub(a, b), transmute(c))) + unsafe { simd_cast(simd_shr(simd_sub(a, b), transmute(c))) } } #[doc = "Subtract returning high narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67866,14 +64766,12 @@ pub unsafe fn vsubhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vsubhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t { +pub fn vsubhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t { let c: u16x8 = u16x8::new(8, 8, 8, 8, 8, 8, 8, 8); - simd_cast(simd_shr(simd_sub(a, b), transmute(c))) + unsafe { simd_cast(simd_shr(simd_sub(a, b), transmute(c))) } } #[doc = "Subtract returning high narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67890,14 +64788,12 @@ pub unsafe fn vsubhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vsubhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t { +pub fn vsubhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t { let c: u32x4 = u32x4::new(16, 16, 16, 16); - simd_cast(simd_shr(simd_sub(a, b), transmute(c))) + unsafe { simd_cast(simd_shr(simd_sub(a, b), transmute(c))) } } #[doc = "Subtract returning high narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67914,14 +64810,12 @@ pub unsafe fn vsubhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vsubhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t { +pub fn vsubhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t { let c: u64x2 = u64x2::new(32, 32); - simd_cast(simd_shr(simd_sub(a, b), transmute(c))) + unsafe { simd_cast(simd_shr(simd_sub(a, b), transmute(c))) } } #[doc = "Signed Subtract Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67938,15 +64832,15 @@ pub unsafe fn vsubhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vsubl_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t { - let c: int16x8_t = simd_cast(a); - let d: int16x8_t = simd_cast(b); - simd_sub(c, d) +pub fn vsubl_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t { + unsafe { + let c: int16x8_t = simd_cast(a); + let d: int16x8_t = simd_cast(b); + simd_sub(c, d) + } } #[doc = "Signed Subtract Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67963,15 +64857,15 @@ pub unsafe fn vsubl_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vsubl_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t { - let c: int32x4_t = simd_cast(a); - let d: int32x4_t = simd_cast(b); - simd_sub(c, d) +pub fn vsubl_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t { + unsafe { + let c: int32x4_t = simd_cast(a); + let d: int32x4_t = simd_cast(b); + simd_sub(c, d) + } } #[doc = "Signed Subtract Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -67988,15 +64882,15 @@ pub unsafe fn vsubl_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vsubl_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t { - let c: int64x2_t = simd_cast(a); - let d: int64x2_t = simd_cast(b); - simd_sub(c, d) +pub fn vsubl_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t { + unsafe { + let c: int64x2_t = simd_cast(a); + let d: int64x2_t = simd_cast(b); + simd_sub(c, d) + } } #[doc = "Unsigned Subtract Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -68013,15 +64907,15 @@ pub unsafe fn vsubl_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vsubl_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t { - let c: uint16x8_t = simd_cast(a); - let d: uint16x8_t = simd_cast(b); - simd_sub(c, d) +pub fn vsubl_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t { + unsafe { + let c: uint16x8_t = simd_cast(a); + let d: uint16x8_t = simd_cast(b); + simd_sub(c, d) + } } #[doc = "Unsigned Subtract Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -68038,15 +64932,15 @@ pub unsafe fn vsubl_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vsubl_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t { - let c: uint32x4_t = simd_cast(a); - let d: uint32x4_t = simd_cast(b); - simd_sub(c, d) +pub fn vsubl_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t { + unsafe { + let c: uint32x4_t = simd_cast(a); + let d: uint32x4_t = simd_cast(b); + simd_sub(c, d) + } } #[doc = "Unsigned Subtract Long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -68063,15 +64957,15 @@ pub unsafe fn vsubl_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vsubl_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t { - let c: uint64x2_t = simd_cast(a); - let d: uint64x2_t = simd_cast(b); - simd_sub(c, d) +pub fn vsubl_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t { + unsafe { + let c: uint64x2_t = simd_cast(a); + let d: uint64x2_t = simd_cast(b); + simd_sub(c, d) + } } #[doc = "Signed Subtract Wide"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -68088,13 +64982,11 @@ pub unsafe fn vsubl_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vsubw_s8(a: int16x8_t, b: int8x8_t) -> int16x8_t { - simd_sub(a, simd_cast(b)) +pub fn vsubw_s8(a: int16x8_t, b: int8x8_t) -> int16x8_t { + unsafe { simd_sub(a, simd_cast(b)) } } #[doc = "Signed Subtract Wide"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -68111,13 +65003,11 @@ pub unsafe fn vsubw_s8(a: int16x8_t, b: int8x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vsubw_s16(a: int32x4_t, b: int16x4_t) -> int32x4_t { - simd_sub(a, simd_cast(b)) +pub fn vsubw_s16(a: int32x4_t, b: int16x4_t) -> int32x4_t { + unsafe { simd_sub(a, simd_cast(b)) } } #[doc = "Signed Subtract Wide"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -68134,13 +65024,11 @@ pub unsafe fn vsubw_s16(a: int32x4_t, b: int16x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vsubw_s32(a: int64x2_t, b: int32x2_t) -> int64x2_t { - simd_sub(a, simd_cast(b)) +pub fn vsubw_s32(a: int64x2_t, b: int32x2_t) -> int64x2_t { + unsafe { simd_sub(a, simd_cast(b)) } } #[doc = "Unsigned Subtract Wide"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -68157,13 +65045,11 @@ pub unsafe fn vsubw_s32(a: int64x2_t, b: int32x2_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vsubw_u8(a: uint16x8_t, b: uint8x8_t) -> uint16x8_t { - simd_sub(a, simd_cast(b)) +pub fn vsubw_u8(a: uint16x8_t, b: uint8x8_t) -> uint16x8_t { + unsafe { simd_sub(a, simd_cast(b)) } } #[doc = "Unsigned Subtract Wide"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -68180,13 +65066,11 @@ pub unsafe fn vsubw_u8(a: uint16x8_t, b: uint8x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vsubw_u16(a: uint32x4_t, b: uint16x4_t) -> uint32x4_t { - simd_sub(a, simd_cast(b)) +pub fn vsubw_u16(a: uint32x4_t, b: uint16x4_t) -> uint32x4_t { + unsafe { simd_sub(a, simd_cast(b)) } } #[doc = "Unsigned Subtract Wide"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -68203,13 +65087,11 @@ pub unsafe fn vsubw_u16(a: uint32x4_t, b: uint16x4_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vsubw_u32(a: uint64x2_t, b: uint32x2_t) -> uint64x2_t { - simd_sub(a, simd_cast(b)) +pub fn vsubw_u32(a: uint64x2_t, b: uint32x2_t) -> uint64x2_t { + unsafe { simd_sub(a, simd_cast(b)) } } #[doc = "Dot product index form with signed and unsigned integers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudot_lane_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,i8mm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] @@ -68227,20 +65109,16 @@ pub unsafe fn vsubw_u32(a: uint64x2_t, b: uint32x2_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vsudot_lane_s32( - a: int32x2_t, - b: int8x8_t, - c: uint8x8_t, -) -> int32x2_t { +pub fn vsudot_lane_s32(a: int32x2_t, b: int8x8_t, c: uint8x8_t) -> int32x2_t { static_assert_uimm_bits!(LANE, 1); - let c: uint32x2_t = transmute(c); - let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); - vusdot_s32(a, transmute(c), b) + unsafe { + let c: uint32x2_t = transmute(c); + let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); + vusdot_s32(a, transmute(c), b) + } } #[doc = "Dot product index form with signed and unsigned integers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudotq_lane_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,i8mm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] @@ -68258,50 +65136,43 @@ pub unsafe fn vsudot_lane_s32( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vsudotq_lane_s32( - a: int32x4_t, - b: int8x16_t, - c: uint8x8_t, -) -> int32x4_t { +pub fn vsudotq_lane_s32(a: int32x4_t, b: int8x16_t, c: uint8x8_t) -> int32x4_t { static_assert_uimm_bits!(LANE, 1); - let c: uint32x2_t = transmute(c); - let c: uint32x4_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vusdotq_s32(a, transmute(c), b) + unsafe { + let c: uint32x2_t = transmute(c); + let c: uint32x4_t = + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); + vusdotq_s32(a, transmute(c), b) + } } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(test, assert_instr(vtbl))] -unsafe fn vtbl1(a: int8x8_t, b: int8x8_t) -> int8x8_t { +fn vtbl1(a: int8x8_t, b: int8x8_t) -> int8x8_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vtbl1")] fn _vtbl1(a: int8x8_t, b: int8x8_t) -> int8x8_t; } - _vtbl1(a, b) + unsafe { _vtbl1(a, b) } } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(test, assert_instr(vtbl))] -pub unsafe fn vtbl1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { +pub fn vtbl1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { vtbl1(a, b) } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -68309,13 +65180,11 @@ pub unsafe fn vtbl1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(test, assert_instr(vtbl))] -pub unsafe fn vtbl1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { - transmute(vtbl1(transmute(a), transmute(b))) +pub fn vtbl1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + unsafe { transmute(vtbl1(transmute(a), transmute(b))) } } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -68323,16 +65192,16 @@ pub unsafe fn vtbl1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(test, assert_instr(vtbl))] -pub unsafe fn vtbl1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { +pub fn vtbl1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: uint8x8_t = transmute(vtbl1(transmute(a), transmute(b))); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: uint8x8_t = transmute(vtbl1(transmute(a), transmute(b))); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -68340,13 +65209,11 @@ pub unsafe fn vtbl1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(test, assert_instr(vtbl))] -pub unsafe fn vtbl1_p8(a: poly8x8_t, b: uint8x8_t) -> poly8x8_t { - transmute(vtbl1(transmute(a), transmute(b))) +pub fn vtbl1_p8(a: poly8x8_t, b: uint8x8_t) -> poly8x8_t { + unsafe { transmute(vtbl1(transmute(a), transmute(b))) } } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -68354,46 +65221,42 @@ pub unsafe fn vtbl1_p8(a: poly8x8_t, b: uint8x8_t) -> poly8x8_t { #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(test, assert_instr(vtbl))] -pub unsafe fn vtbl1_p8(a: poly8x8_t, b: uint8x8_t) -> poly8x8_t { +pub fn vtbl1_p8(a: poly8x8_t, b: uint8x8_t) -> poly8x8_t { let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: poly8x8_t = transmute(vtbl1(transmute(a), transmute(b))); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: poly8x8_t = transmute(vtbl1(transmute(a), transmute(b))); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(test, assert_instr(vtbl))] -unsafe fn vtbl2(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t { +fn vtbl2(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vtbl2")] fn _vtbl2(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t; } - _vtbl2(a, b, c) + unsafe { _vtbl2(a, b, c) } } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(test, assert_instr(vtbl))] -pub unsafe fn vtbl2_s8(a: int8x8x2_t, b: int8x8_t) -> int8x8_t { +pub fn vtbl2_s8(a: int8x8x2_t, b: int8x8_t) -> int8x8_t { vtbl2(a.0, a.1, b) } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -68401,13 +65264,11 @@ pub unsafe fn vtbl2_s8(a: int8x8x2_t, b: int8x8_t) -> int8x8_t { #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(test, assert_instr(vtbl))] -pub unsafe fn vtbl2_u8(a: uint8x8x2_t, b: uint8x8_t) -> uint8x8_t { - transmute(vtbl2(transmute(a.0), transmute(a.1), transmute(b))) +pub fn vtbl2_u8(a: uint8x8x2_t, b: uint8x8_t) -> uint8x8_t { + unsafe { transmute(vtbl2(transmute(a.0), transmute(a.1), transmute(b))) } } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -68415,18 +65276,18 @@ pub unsafe fn vtbl2_u8(a: uint8x8x2_t, b: uint8x8_t) -> uint8x8_t { #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(test, assert_instr(vtbl))] -pub unsafe fn vtbl2_u8(a: uint8x8x2_t, b: uint8x8_t) -> uint8x8_t { +pub fn vtbl2_u8(a: uint8x8x2_t, b: uint8x8_t) -> uint8x8_t { let mut a: uint8x8x2_t = a; a.0 = simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]); a.1 = simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]); let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: uint8x8_t = transmute(vtbl2(transmute(a.0), transmute(a.1), transmute(b))); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: uint8x8_t = transmute(vtbl2(transmute(a.0), transmute(a.1), transmute(b))); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -68434,13 +65295,11 @@ pub unsafe fn vtbl2_u8(a: uint8x8x2_t, b: uint8x8_t) -> uint8x8_t { #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(test, assert_instr(vtbl))] -pub unsafe fn vtbl2_p8(a: poly8x8x2_t, b: uint8x8_t) -> poly8x8_t { - transmute(vtbl2(transmute(a.0), transmute(a.1), transmute(b))) +pub fn vtbl2_p8(a: poly8x8x2_t, b: uint8x8_t) -> poly8x8_t { + unsafe { transmute(vtbl2(transmute(a.0), transmute(a.1), transmute(b))) } } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -68448,48 +65307,44 @@ pub unsafe fn vtbl2_p8(a: poly8x8x2_t, b: uint8x8_t) -> poly8x8_t { #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(test, assert_instr(vtbl))] -pub unsafe fn vtbl2_p8(a: poly8x8x2_t, b: uint8x8_t) -> poly8x8_t { +pub fn vtbl2_p8(a: poly8x8x2_t, b: uint8x8_t) -> poly8x8_t { let mut a: poly8x8x2_t = a; a.0 = simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]); a.1 = simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]); let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: poly8x8_t = transmute(vtbl2(transmute(a.0), transmute(a.1), transmute(b))); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: poly8x8_t = transmute(vtbl2(transmute(a.0), transmute(a.1), transmute(b))); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(test, assert_instr(vtbl))] -unsafe fn vtbl3(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t) -> int8x8_t { +fn vtbl3(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t) -> int8x8_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vtbl3")] fn _vtbl3(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t) -> int8x8_t; } - _vtbl3(a, b, c, d) + unsafe { _vtbl3(a, b, c, d) } } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(test, assert_instr(vtbl))] -pub unsafe fn vtbl3_s8(a: int8x8x3_t, b: int8x8_t) -> int8x8_t { +pub fn vtbl3_s8(a: int8x8x3_t, b: int8x8_t) -> int8x8_t { vtbl3(a.0, a.1, a.2, b) } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -68497,18 +65352,18 @@ pub unsafe fn vtbl3_s8(a: int8x8x3_t, b: int8x8_t) -> int8x8_t { #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(test, assert_instr(vtbl))] -pub unsafe fn vtbl3_u8(a: uint8x8x3_t, b: uint8x8_t) -> uint8x8_t { - transmute(vtbl3( - transmute(a.0), - transmute(a.1), - transmute(a.2), - transmute(b), - )) +pub fn vtbl3_u8(a: uint8x8x3_t, b: uint8x8_t) -> uint8x8_t { + unsafe { + transmute(vtbl3( + transmute(a.0), + transmute(a.1), + transmute(a.2), + transmute(b), + )) + } } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -68516,24 +65371,24 @@ pub unsafe fn vtbl3_u8(a: uint8x8x3_t, b: uint8x8_t) -> uint8x8_t { #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(test, assert_instr(vtbl))] -pub unsafe fn vtbl3_u8(a: uint8x8x3_t, b: uint8x8_t) -> uint8x8_t { +pub fn vtbl3_u8(a: uint8x8x3_t, b: uint8x8_t) -> uint8x8_t { let mut a: uint8x8x3_t = a; a.0 = simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]); a.1 = simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]); a.2 = simd_shuffle!(a.2, a.2, [7, 6, 5, 4, 3, 2, 1, 0]); let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: uint8x8_t = transmute(vtbl3( - transmute(a.0), - transmute(a.1), - transmute(a.2), - transmute(b), - )); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: uint8x8_t = transmute(vtbl3( + transmute(a.0), + transmute(a.1), + transmute(a.2), + transmute(b), + )); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -68541,18 +65396,18 @@ pub unsafe fn vtbl3_u8(a: uint8x8x3_t, b: uint8x8_t) -> uint8x8_t { #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(test, assert_instr(vtbl))] -pub unsafe fn vtbl3_p8(a: poly8x8x3_t, b: uint8x8_t) -> poly8x8_t { - transmute(vtbl3( - transmute(a.0), - transmute(a.1), - transmute(a.2), - transmute(b), - )) +pub fn vtbl3_p8(a: poly8x8x3_t, b: uint8x8_t) -> poly8x8_t { + unsafe { + transmute(vtbl3( + transmute(a.0), + transmute(a.1), + transmute(a.2), + transmute(b), + )) + } } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -68560,54 +65415,50 @@ pub unsafe fn vtbl3_p8(a: poly8x8x3_t, b: uint8x8_t) -> poly8x8_t { #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(test, assert_instr(vtbl))] -pub unsafe fn vtbl3_p8(a: poly8x8x3_t, b: uint8x8_t) -> poly8x8_t { +pub fn vtbl3_p8(a: poly8x8x3_t, b: uint8x8_t) -> poly8x8_t { let mut a: poly8x8x3_t = a; a.0 = simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]); a.1 = simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]); a.2 = simd_shuffle!(a.2, a.2, [7, 6, 5, 4, 3, 2, 1, 0]); let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: poly8x8_t = transmute(vtbl3( - transmute(a.0), - transmute(a.1), - transmute(a.2), - transmute(b), - )); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: poly8x8_t = transmute(vtbl3( + transmute(a.0), + transmute(a.1), + transmute(a.2), + transmute(b), + )); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(test, assert_instr(vtbl))] -unsafe fn vtbl4(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, e: int8x8_t) -> int8x8_t { +fn vtbl4(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, e: int8x8_t) -> int8x8_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vtbl4")] fn _vtbl4(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, e: int8x8_t) -> int8x8_t; } - _vtbl4(a, b, c, d, e) + unsafe { _vtbl4(a, b, c, d, e) } } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(test, assert_instr(vtbl))] -pub unsafe fn vtbl4_s8(a: int8x8x4_t, b: int8x8_t) -> int8x8_t { +pub fn vtbl4_s8(a: int8x8x4_t, b: int8x8_t) -> int8x8_t { vtbl4(a.0, a.1, a.2, a.3, b) } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -68615,19 +65466,19 @@ pub unsafe fn vtbl4_s8(a: int8x8x4_t, b: int8x8_t) -> int8x8_t { #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(test, assert_instr(vtbl))] -pub unsafe fn vtbl4_u8(a: uint8x8x4_t, b: uint8x8_t) -> uint8x8_t { - transmute(vtbl4( - transmute(a.0), - transmute(a.1), - transmute(a.2), - transmute(a.3), - transmute(b), - )) +pub fn vtbl4_u8(a: uint8x8x4_t, b: uint8x8_t) -> uint8x8_t { + unsafe { + transmute(vtbl4( + transmute(a.0), + transmute(a.1), + transmute(a.2), + transmute(a.3), + transmute(b), + )) + } } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -68635,26 +65486,26 @@ pub unsafe fn vtbl4_u8(a: uint8x8x4_t, b: uint8x8_t) -> uint8x8_t { #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(test, assert_instr(vtbl))] -pub unsafe fn vtbl4_u8(a: uint8x8x4_t, b: uint8x8_t) -> uint8x8_t { +pub fn vtbl4_u8(a: uint8x8x4_t, b: uint8x8_t) -> uint8x8_t { let mut a: uint8x8x4_t = a; a.0 = simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]); a.1 = simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]); a.2 = simd_shuffle!(a.2, a.2, [7, 6, 5, 4, 3, 2, 1, 0]); a.3 = simd_shuffle!(a.3, a.3, [7, 6, 5, 4, 3, 2, 1, 0]); let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: uint8x8_t = transmute(vtbl4( - transmute(a.0), - transmute(a.1), - transmute(a.2), - transmute(a.3), - transmute(b), - )); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: uint8x8_t = transmute(vtbl4( + transmute(a.0), + transmute(a.1), + transmute(a.2), + transmute(a.3), + transmute(b), + )); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] @@ -68662,19 +65513,19 @@ pub unsafe fn vtbl4_u8(a: uint8x8x4_t, b: uint8x8_t) -> uint8x8_t { #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(test, assert_instr(vtbl))] -pub unsafe fn vtbl4_p8(a: poly8x8x4_t, b: uint8x8_t) -> poly8x8_t { - transmute(vtbl4( - transmute(a.0), - transmute(a.1), - transmute(a.2), - transmute(a.3), - transmute(b), - )) +pub fn vtbl4_p8(a: poly8x8x4_t, b: uint8x8_t) -> poly8x8_t { + unsafe { + transmute(vtbl4( + transmute(a.0), + transmute(a.1), + transmute(a.2), + transmute(a.3), + transmute(b), + )) + } } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] @@ -68682,357 +65533,334 @@ pub unsafe fn vtbl4_p8(a: poly8x8x4_t, b: uint8x8_t) -> poly8x8_t { #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(test, assert_instr(vtbl))] -pub unsafe fn vtbl4_p8(a: poly8x8x4_t, b: uint8x8_t) -> poly8x8_t { +pub fn vtbl4_p8(a: poly8x8x4_t, b: uint8x8_t) -> poly8x8_t { let mut a: poly8x8x4_t = a; a.0 = simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]); a.1 = simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]); a.2 = simd_shuffle!(a.2, a.2, [7, 6, 5, 4, 3, 2, 1, 0]); a.3 = simd_shuffle!(a.3, a.3, [7, 6, 5, 4, 3, 2, 1, 0]); let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: poly8x8_t = transmute(vtbl4( - transmute(a.0), - transmute(a.1), - transmute(a.2), - transmute(a.3), - transmute(b), - )); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: poly8x8_t = transmute(vtbl4( + transmute(a.0), + transmute(a.1), + transmute(a.2), + transmute(a.3), + transmute(b), + )); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(test, assert_instr(vtbx))] -unsafe fn vtbx1(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t { +fn vtbx1(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vtbx1")] fn _vtbx1(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t; } - _vtbx1(a, b, c) + unsafe { _vtbx1(a, b, c) } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(test, assert_instr(vtbx))] -pub unsafe fn vtbx1_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t { +pub fn vtbx1_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t { vtbx1(a, b, c) } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(test, assert_instr(vtbx))] -pub unsafe fn vtbx1_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t { - transmute(vtbx1(transmute(a), transmute(b), transmute(c))) +pub fn vtbx1_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t { + unsafe { transmute(vtbx1(transmute(a), transmute(b), transmute(c))) } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(test, assert_instr(vtbx))] -pub unsafe fn vtbx1_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t { +pub fn vtbx1_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t { let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); let b: uint8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); let c: uint8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: uint8x8_t = transmute(vtbx1(transmute(a), transmute(b), transmute(c))); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: uint8x8_t = transmute(vtbx1(transmute(a), transmute(b), transmute(c))); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(test, assert_instr(vtbx))] -pub unsafe fn vtbx1_p8(a: poly8x8_t, b: poly8x8_t, c: uint8x8_t) -> poly8x8_t { - transmute(vtbx1(transmute(a), transmute(b), transmute(c))) +pub fn vtbx1_p8(a: poly8x8_t, b: poly8x8_t, c: uint8x8_t) -> poly8x8_t { + unsafe { transmute(vtbx1(transmute(a), transmute(b), transmute(c))) } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(test, assert_instr(vtbx))] -pub unsafe fn vtbx1_p8(a: poly8x8_t, b: poly8x8_t, c: uint8x8_t) -> poly8x8_t { +pub fn vtbx1_p8(a: poly8x8_t, b: poly8x8_t, c: uint8x8_t) -> poly8x8_t { let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); let b: poly8x8_t = simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]); let c: uint8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: poly8x8_t = transmute(vtbx1(transmute(a), transmute(b), transmute(c))); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: poly8x8_t = transmute(vtbx1(transmute(a), transmute(b), transmute(c))); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(test, assert_instr(vtbx))] -unsafe fn vtbx2(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t) -> int8x8_t { +fn vtbx2(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t) -> int8x8_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vtbx2")] fn _vtbx2(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t) -> int8x8_t; } - _vtbx2(a, b, c, d) + unsafe { _vtbx2(a, b, c, d) } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(test, assert_instr(vtbx))] -pub unsafe fn vtbx2_s8(a: int8x8_t, b: int8x8x2_t, c: int8x8_t) -> int8x8_t { +pub fn vtbx2_s8(a: int8x8_t, b: int8x8x2_t, c: int8x8_t) -> int8x8_t { vtbx2(a, b.0, b.1, c) } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(test, assert_instr(vtbx))] -pub unsafe fn vtbx2_u8(a: uint8x8_t, b: uint8x8x2_t, c: uint8x8_t) -> uint8x8_t { - transmute(vtbx2( - transmute(a), - transmute(b.0), - transmute(b.1), - transmute(c), - )) +pub fn vtbx2_u8(a: uint8x8_t, b: uint8x8x2_t, c: uint8x8_t) -> uint8x8_t { + unsafe { + transmute(vtbx2( + transmute(a), + transmute(b.0), + transmute(b.1), + transmute(c), + )) + } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(test, assert_instr(vtbx))] -pub unsafe fn vtbx2_u8(a: uint8x8_t, b: uint8x8x2_t, c: uint8x8_t) -> uint8x8_t { +pub fn vtbx2_u8(a: uint8x8_t, b: uint8x8x2_t, c: uint8x8_t) -> uint8x8_t { let mut b: uint8x8x2_t = b; let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); b.0 = simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]); b.1 = simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]); let c: uint8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: uint8x8_t = transmute(vtbx2( - transmute(a), - transmute(b.0), - transmute(b.1), - transmute(c), - )); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: uint8x8_t = transmute(vtbx2( + transmute(a), + transmute(b.0), + transmute(b.1), + transmute(c), + )); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(test, assert_instr(vtbx))] -pub unsafe fn vtbx2_p8(a: poly8x8_t, b: poly8x8x2_t, c: uint8x8_t) -> poly8x8_t { - transmute(vtbx2( - transmute(a), - transmute(b.0), - transmute(b.1), - transmute(c), - )) +pub fn vtbx2_p8(a: poly8x8_t, b: poly8x8x2_t, c: uint8x8_t) -> poly8x8_t { + unsafe { + transmute(vtbx2( + transmute(a), + transmute(b.0), + transmute(b.1), + transmute(c), + )) + } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(test, assert_instr(vtbx))] -pub unsafe fn vtbx2_p8(a: poly8x8_t, b: poly8x8x2_t, c: uint8x8_t) -> poly8x8_t { +pub fn vtbx2_p8(a: poly8x8_t, b: poly8x8x2_t, c: uint8x8_t) -> poly8x8_t { let mut b: poly8x8x2_t = b; let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); b.0 = simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]); b.1 = simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]); let c: uint8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: poly8x8_t = transmute(vtbx2( - transmute(a), - transmute(b.0), - transmute(b.1), - transmute(c), - )); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: poly8x8_t = transmute(vtbx2( + transmute(a), + transmute(b.0), + transmute(b.1), + transmute(c), + )); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(test, assert_instr(vtbx))] -unsafe fn vtbx3(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, e: int8x8_t) -> int8x8_t { +fn vtbx3(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, e: int8x8_t) -> int8x8_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vtbx3")] fn _vtbx3(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, e: int8x8_t) -> int8x8_t; } - _vtbx3(a, b, c, d, e) + unsafe { _vtbx3(a, b, c, d, e) } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(test, assert_instr(vtbx))] -pub unsafe fn vtbx3_s8(a: int8x8_t, b: int8x8x3_t, c: int8x8_t) -> int8x8_t { +pub fn vtbx3_s8(a: int8x8_t, b: int8x8x3_t, c: int8x8_t) -> int8x8_t { vtbx3(a, b.0, b.1, b.2, c) } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(test, assert_instr(vtbx))] -pub unsafe fn vtbx3_u8(a: uint8x8_t, b: uint8x8x3_t, c: uint8x8_t) -> uint8x8_t { - transmute(vtbx3( - transmute(a), - transmute(b.0), - transmute(b.1), - transmute(b.2), - transmute(c), - )) +pub fn vtbx3_u8(a: uint8x8_t, b: uint8x8x3_t, c: uint8x8_t) -> uint8x8_t { + unsafe { + transmute(vtbx3( + transmute(a), + transmute(b.0), + transmute(b.1), + transmute(b.2), + transmute(c), + )) + } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(test, assert_instr(vtbx))] -pub unsafe fn vtbx3_u8(a: uint8x8_t, b: uint8x8x3_t, c: uint8x8_t) -> uint8x8_t { +pub fn vtbx3_u8(a: uint8x8_t, b: uint8x8x3_t, c: uint8x8_t) -> uint8x8_t { let mut b: uint8x8x3_t = b; let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); b.0 = simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]); b.1 = simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]); b.2 = simd_shuffle!(b.2, b.2, [7, 6, 5, 4, 3, 2, 1, 0]); let c: uint8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: uint8x8_t = transmute(vtbx3( - transmute(a), - transmute(b.0), - transmute(b.1), - transmute(b.2), - transmute(c), - )); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: uint8x8_t = transmute(vtbx3( + transmute(a), + transmute(b.0), + transmute(b.1), + transmute(b.2), + transmute(c), + )); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(test, assert_instr(vtbx))] -pub unsafe fn vtbx3_p8(a: poly8x8_t, b: poly8x8x3_t, c: uint8x8_t) -> poly8x8_t { - transmute(vtbx3( - transmute(a), - transmute(b.0), - transmute(b.1), - transmute(b.2), - transmute(c), - )) +pub fn vtbx3_p8(a: poly8x8_t, b: poly8x8x3_t, c: uint8x8_t) -> poly8x8_t { + unsafe { + transmute(vtbx3( + transmute(a), + transmute(b.0), + transmute(b.1), + transmute(b.2), + transmute(c), + )) + } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(test, assert_instr(vtbx))] -pub unsafe fn vtbx3_p8(a: poly8x8_t, b: poly8x8x3_t, c: uint8x8_t) -> poly8x8_t { +pub fn vtbx3_p8(a: poly8x8_t, b: poly8x8x3_t, c: uint8x8_t) -> poly8x8_t { let mut b: poly8x8x3_t = b; let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); b.0 = simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]); b.1 = simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]); b.2 = simd_shuffle!(b.2, b.2, [7, 6, 5, 4, 3, 2, 1, 0]); let c: uint8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: poly8x8_t = transmute(vtbx3( - transmute(a), - transmute(b.0), - transmute(b.1), - transmute(b.2), - transmute(c), - )); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: poly8x8_t = transmute(vtbx3( + transmute(a), + transmute(b.0), + transmute(b.1), + transmute(b.2), + transmute(c), + )); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(test, assert_instr(vtbx))] -unsafe fn vtbx4( - a: int8x8_t, - b: int8x8_t, - c: int8x8_t, - d: int8x8_t, - e: int8x8_t, - f: int8x8_t, -) -> int8x8_t { +fn vtbx4(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, e: int8x8_t, f: int8x8_t) -> int8x8_t { unsafe extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vtbx4")] fn _vtbx4( @@ -69044,39 +65872,37 @@ unsafe fn vtbx4( f: int8x8_t, ) -> int8x8_t; } - _vtbx4(a, b, c, d, e, f) + unsafe { _vtbx4(a, b, c, d, e, f) } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(test, assert_instr(vtbx))] -pub unsafe fn vtbx4_s8(a: int8x8_t, b: int8x8x4_t, c: int8x8_t) -> int8x8_t { - vtbx4( - a, - transmute(b.0), - transmute(b.1), - transmute(b.2), - transmute(b.3), - c, - ) +pub fn vtbx4_s8(a: int8x8_t, b: int8x8x4_t, c: int8x8_t) -> int8x8_t { + unsafe { + vtbx4( + a, + transmute(b.0), + transmute(b.1), + transmute(b.2), + transmute(b.3), + c, + ) + } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(test, assert_instr(vtbx))] -pub unsafe fn vtbx4_s8(a: int8x8_t, b: int8x8x4_t, c: int8x8_t) -> int8x8_t { +pub fn vtbx4_s8(a: int8x8_t, b: int8x8x4_t, c: int8x8_t) -> int8x8_t { let mut b: int8x8x4_t = b; let a: int8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); b.0 = simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]); @@ -69084,47 +65910,47 @@ pub unsafe fn vtbx4_s8(a: int8x8_t, b: int8x8x4_t, c: int8x8_t) -> int8x8_t { b.2 = simd_shuffle!(b.2, b.2, [7, 6, 5, 4, 3, 2, 1, 0]); b.3 = simd_shuffle!(b.3, b.3, [7, 6, 5, 4, 3, 2, 1, 0]); let c: int8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: int8x8_t = vtbx4( - a, - transmute(b.0), - transmute(b.1), - transmute(b.2), - transmute(b.3), - c, - ); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: int8x8_t = vtbx4( + a, + transmute(b.0), + transmute(b.1), + transmute(b.2), + transmute(b.3), + c, + ); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(test, assert_instr(vtbx))] -pub unsafe fn vtbx4_u8(a: uint8x8_t, b: uint8x8x4_t, c: uint8x8_t) -> uint8x8_t { - transmute(vtbx4( - transmute(a), - transmute(b.0), - transmute(b.1), - transmute(b.2), - transmute(b.3), - transmute(c), - )) +pub fn vtbx4_u8(a: uint8x8_t, b: uint8x8x4_t, c: uint8x8_t) -> uint8x8_t { + unsafe { + transmute(vtbx4( + transmute(a), + transmute(b.0), + transmute(b.1), + transmute(b.2), + transmute(b.3), + transmute(c), + )) + } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(test, assert_instr(vtbx))] -pub unsafe fn vtbx4_u8(a: uint8x8_t, b: uint8x8x4_t, c: uint8x8_t) -> uint8x8_t { +pub fn vtbx4_u8(a: uint8x8_t, b: uint8x8x4_t, c: uint8x8_t) -> uint8x8_t { let mut b: uint8x8x4_t = b; let a: uint8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); b.0 = simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]); @@ -69132,47 +65958,47 @@ pub unsafe fn vtbx4_u8(a: uint8x8_t, b: uint8x8x4_t, c: uint8x8_t) -> uint8x8_t b.2 = simd_shuffle!(b.2, b.2, [7, 6, 5, 4, 3, 2, 1, 0]); b.3 = simd_shuffle!(b.3, b.3, [7, 6, 5, 4, 3, 2, 1, 0]); let c: uint8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: uint8x8_t = transmute(vtbx4( - transmute(a), - transmute(b.0), - transmute(b.1), - transmute(b.2), - transmute(b.3), - transmute(c), - )); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: uint8x8_t = transmute(vtbx4( + transmute(a), + transmute(b.0), + transmute(b.1), + transmute(b.2), + transmute(b.3), + transmute(c), + )); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "little")] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(test, assert_instr(vtbx))] -pub unsafe fn vtbx4_p8(a: poly8x8_t, b: poly8x8x4_t, c: uint8x8_t) -> poly8x8_t { - transmute(vtbx4( - transmute(a), - transmute(b.0), - transmute(b.1), - transmute(b.2), - transmute(b.3), - transmute(c), - )) +pub fn vtbx4_p8(a: poly8x8_t, b: poly8x8x4_t, c: uint8x8_t) -> poly8x8_t { + unsafe { + transmute(vtbx4( + transmute(a), + transmute(b.0), + transmute(b.1), + transmute(b.2), + transmute(b.3), + transmute(c), + )) + } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_endian = "big")] #[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(test, assert_instr(vtbx))] -pub unsafe fn vtbx4_p8(a: poly8x8_t, b: poly8x8x4_t, c: uint8x8_t) -> poly8x8_t { +pub fn vtbx4_p8(a: poly8x8_t, b: poly8x8x4_t, c: uint8x8_t) -> poly8x8_t { let mut b: poly8x8x4_t = b; let a: poly8x8_t = simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]); b.0 = simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]); @@ -69180,20 +66006,20 @@ pub unsafe fn vtbx4_p8(a: poly8x8_t, b: poly8x8x4_t, c: uint8x8_t) -> poly8x8_t b.2 = simd_shuffle!(b.2, b.2, [7, 6, 5, 4, 3, 2, 1, 0]); b.3 = simd_shuffle!(b.3, b.3, [7, 6, 5, 4, 3, 2, 1, 0]); let c: uint8x8_t = simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]); - let ret_val: poly8x8_t = transmute(vtbx4( - transmute(a), - transmute(b.0), - transmute(b.1), - transmute(b.2), - transmute(b.3), - transmute(c), - )); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + unsafe { + let ret_val: poly8x8_t = transmute(vtbx4( + transmute(a), + transmute(b.0), + transmute(b.1), + transmute(b.2), + transmute(b.3), + transmute(c), + )); + simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + } } #[doc = "Transpose elements"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] @@ -69203,15 +66029,15 @@ pub unsafe fn vtbx4_p8(a: poly8x8_t, b: poly8x8x4_t, c: uint8x8_t) -> poly8x8_t )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vtrn_f16(a: float16x4_t, b: float16x4_t) -> float16x4x2_t { - let a1: float16x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]); - let b1: float16x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); - transmute((a1, b1)) +pub fn vtrn_f16(a: float16x4_t, b: float16x4_t) -> float16x4x2_t { + unsafe { + let a1: float16x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]); + let b1: float16x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); + transmute((a1, b1)) + } } #[doc = "Transpose elements"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] @@ -69221,15 +66047,15 @@ pub unsafe fn vtrn_f16(a: float16x4_t, b: float16x4_t) -> float16x4x2_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vtrnq_f16(a: float16x8_t, b: float16x8_t) -> float16x8x2_t { - let a1: float16x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]); - let b1: float16x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); - transmute((a1, b1)) +pub fn vtrnq_f16(a: float16x8_t, b: float16x8_t) -> float16x8x2_t { + unsafe { + let a1: float16x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]); + let b1: float16x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); + transmute((a1, b1)) + } } #[doc = "Transpose elements"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -69246,15 +66072,15 @@ pub unsafe fn vtrnq_f16(a: float16x8_t, b: float16x8_t) -> float16x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vtrn_f32(a: float32x2_t, b: float32x2_t) -> float32x2x2_t { - let a1: float32x2_t = simd_shuffle!(a, b, [0, 2]); - let b1: float32x2_t = simd_shuffle!(a, b, [1, 3]); - transmute((a1, b1)) +pub fn vtrn_f32(a: float32x2_t, b: float32x2_t) -> float32x2x2_t { + unsafe { + let a1: float32x2_t = simd_shuffle!(a, b, [0, 2]); + let b1: float32x2_t = simd_shuffle!(a, b, [1, 3]); + transmute((a1, b1)) + } } #[doc = "Transpose elements"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -69271,15 +66097,15 @@ pub unsafe fn vtrn_f32(a: float32x2_t, b: float32x2_t) -> float32x2x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vtrn_s32(a: int32x2_t, b: int32x2_t) -> int32x2x2_t { - let a1: int32x2_t = simd_shuffle!(a, b, [0, 2]); - let b1: int32x2_t = simd_shuffle!(a, b, [1, 3]); - transmute((a1, b1)) +pub fn vtrn_s32(a: int32x2_t, b: int32x2_t) -> int32x2x2_t { + unsafe { + let a1: int32x2_t = simd_shuffle!(a, b, [0, 2]); + let b1: int32x2_t = simd_shuffle!(a, b, [1, 3]); + transmute((a1, b1)) + } } #[doc = "Transpose elements"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -69296,15 +66122,15 @@ pub unsafe fn vtrn_s32(a: int32x2_t, b: int32x2_t) -> int32x2x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vtrn_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2x2_t { - let a1: uint32x2_t = simd_shuffle!(a, b, [0, 2]); - let b1: uint32x2_t = simd_shuffle!(a, b, [1, 3]); - transmute((a1, b1)) +pub fn vtrn_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2x2_t { + unsafe { + let a1: uint32x2_t = simd_shuffle!(a, b, [0, 2]); + let b1: uint32x2_t = simd_shuffle!(a, b, [1, 3]); + transmute((a1, b1)) + } } #[doc = "Transpose elements"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -69321,15 +66147,15 @@ pub unsafe fn vtrn_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vtrnq_f32(a: float32x4_t, b: float32x4_t) -> float32x4x2_t { - let a1: float32x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]); - let b1: float32x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); - transmute((a1, b1)) +pub fn vtrnq_f32(a: float32x4_t, b: float32x4_t) -> float32x4x2_t { + unsafe { + let a1: float32x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]); + let b1: float32x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); + transmute((a1, b1)) + } } #[doc = "Transpose elements"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -69346,15 +66172,15 @@ pub unsafe fn vtrnq_f32(a: float32x4_t, b: float32x4_t) -> float32x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vtrn_s8(a: int8x8_t, b: int8x8_t) -> int8x8x2_t { - let a1: int8x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]); - let b1: int8x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); - transmute((a1, b1)) +pub fn vtrn_s8(a: int8x8_t, b: int8x8_t) -> int8x8x2_t { + unsafe { + let a1: int8x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]); + let b1: int8x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); + transmute((a1, b1)) + } } #[doc = "Transpose elements"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -69371,23 +66197,23 @@ pub unsafe fn vtrn_s8(a: int8x8_t, b: int8x8_t) -> int8x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vtrnq_s8(a: int8x16_t, b: int8x16_t) -> int8x16x2_t { - let a1: int8x16_t = simd_shuffle!( - a, - b, - [0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30] - ); - let b1: int8x16_t = simd_shuffle!( - a, - b, - [1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31] - ); - transmute((a1, b1)) +pub fn vtrnq_s8(a: int8x16_t, b: int8x16_t) -> int8x16x2_t { + unsafe { + let a1: int8x16_t = simd_shuffle!( + a, + b, + [0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30] + ); + let b1: int8x16_t = simd_shuffle!( + a, + b, + [1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31] + ); + transmute((a1, b1)) + } } #[doc = "Transpose elements"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -69404,15 +66230,15 @@ pub unsafe fn vtrnq_s8(a: int8x16_t, b: int8x16_t) -> int8x16x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vtrn_s16(a: int16x4_t, b: int16x4_t) -> int16x4x2_t { - let a1: int16x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]); - let b1: int16x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); - transmute((a1, b1)) +pub fn vtrn_s16(a: int16x4_t, b: int16x4_t) -> int16x4x2_t { + unsafe { + let a1: int16x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]); + let b1: int16x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); + transmute((a1, b1)) + } } #[doc = "Transpose elements"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -69429,15 +66255,15 @@ pub unsafe fn vtrn_s16(a: int16x4_t, b: int16x4_t) -> int16x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vtrnq_s16(a: int16x8_t, b: int16x8_t) -> int16x8x2_t { - let a1: int16x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]); - let b1: int16x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); - transmute((a1, b1)) +pub fn vtrnq_s16(a: int16x8_t, b: int16x8_t) -> int16x8x2_t { + unsafe { + let a1: int16x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]); + let b1: int16x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); + transmute((a1, b1)) + } } #[doc = "Transpose elements"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -69454,15 +66280,15 @@ pub unsafe fn vtrnq_s16(a: int16x8_t, b: int16x8_t) -> int16x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vtrnq_s32(a: int32x4_t, b: int32x4_t) -> int32x4x2_t { - let a1: int32x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]); - let b1: int32x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); - transmute((a1, b1)) +pub fn vtrnq_s32(a: int32x4_t, b: int32x4_t) -> int32x4x2_t { + unsafe { + let a1: int32x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]); + let b1: int32x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); + transmute((a1, b1)) + } } #[doc = "Transpose elements"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -69479,15 +66305,15 @@ pub unsafe fn vtrnq_s32(a: int32x4_t, b: int32x4_t) -> int32x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vtrn_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8x2_t { - let a1: uint8x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]); - let b1: uint8x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); - transmute((a1, b1)) +pub fn vtrn_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8x2_t { + unsafe { + let a1: uint8x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]); + let b1: uint8x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); + transmute((a1, b1)) + } } #[doc = "Transpose elements"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -69504,23 +66330,23 @@ pub unsafe fn vtrn_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vtrnq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16x2_t { - let a1: uint8x16_t = simd_shuffle!( - a, - b, - [0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30] - ); - let b1: uint8x16_t = simd_shuffle!( - a, - b, - [1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31] - ); - transmute((a1, b1)) +pub fn vtrnq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16x2_t { + unsafe { + let a1: uint8x16_t = simd_shuffle!( + a, + b, + [0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30] + ); + let b1: uint8x16_t = simd_shuffle!( + a, + b, + [1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31] + ); + transmute((a1, b1)) + } } #[doc = "Transpose elements"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -69537,15 +66363,15 @@ pub unsafe fn vtrnq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vtrn_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4x2_t { - let a1: uint16x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]); - let b1: uint16x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); - transmute((a1, b1)) +pub fn vtrn_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4x2_t { + unsafe { + let a1: uint16x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]); + let b1: uint16x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); + transmute((a1, b1)) + } } #[doc = "Transpose elements"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -69562,15 +66388,15 @@ pub unsafe fn vtrn_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vtrnq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8x2_t { - let a1: uint16x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]); - let b1: uint16x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); - transmute((a1, b1)) +pub fn vtrnq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8x2_t { + unsafe { + let a1: uint16x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]); + let b1: uint16x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); + transmute((a1, b1)) + } } #[doc = "Transpose elements"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -69587,15 +66413,15 @@ pub unsafe fn vtrnq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vtrnq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4x2_t { - let a1: uint32x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]); - let b1: uint32x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); - transmute((a1, b1)) +pub fn vtrnq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4x2_t { + unsafe { + let a1: uint32x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]); + let b1: uint32x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); + transmute((a1, b1)) + } } #[doc = "Transpose elements"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -69612,15 +66438,15 @@ pub unsafe fn vtrnq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vtrn_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8x2_t { - let a1: poly8x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]); - let b1: poly8x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); - transmute((a1, b1)) +pub fn vtrn_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8x2_t { + unsafe { + let a1: poly8x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]); + let b1: poly8x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); + transmute((a1, b1)) + } } #[doc = "Transpose elements"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -69637,23 +66463,23 @@ pub unsafe fn vtrn_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vtrnq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16x2_t { - let a1: poly8x16_t = simd_shuffle!( - a, - b, - [0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30] - ); - let b1: poly8x16_t = simd_shuffle!( - a, - b, - [1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31] - ); - transmute((a1, b1)) +pub fn vtrnq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16x2_t { + unsafe { + let a1: poly8x16_t = simd_shuffle!( + a, + b, + [0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30] + ); + let b1: poly8x16_t = simd_shuffle!( + a, + b, + [1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31] + ); + transmute((a1, b1)) + } } #[doc = "Transpose elements"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -69670,15 +66496,15 @@ pub unsafe fn vtrnq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vtrn_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4x2_t { - let a1: poly16x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]); - let b1: poly16x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); - transmute((a1, b1)) +pub fn vtrn_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4x2_t { + unsafe { + let a1: poly16x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]); + let b1: poly16x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); + transmute((a1, b1)) + } } #[doc = "Transpose elements"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -69695,15 +66521,15 @@ pub unsafe fn vtrn_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vtrnq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8x2_t { - let a1: poly16x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]); - let b1: poly16x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); - transmute((a1, b1)) +pub fn vtrnq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8x2_t { + unsafe { + let a1: poly16x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]); + let b1: poly16x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); + transmute((a1, b1)) + } } #[doc = "Signed compare bitwise Test bits nonzero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -69720,15 +66546,15 @@ pub unsafe fn vtrnq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vtst_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t { - let c: int8x8_t = simd_and(a, b); - let d: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); - simd_ne(c, transmute(d)) +pub fn vtst_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t { + unsafe { + let c: int8x8_t = simd_and(a, b); + let d: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); + simd_ne(c, transmute(d)) + } } #[doc = "Signed compare bitwise Test bits nonzero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -69745,15 +66571,15 @@ pub unsafe fn vtst_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vtstq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t { - let c: int8x16_t = simd_and(a, b); - let d: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); - simd_ne(c, transmute(d)) +pub fn vtstq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t { + unsafe { + let c: int8x16_t = simd_and(a, b); + let d: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); + simd_ne(c, transmute(d)) + } } #[doc = "Signed compare bitwise Test bits nonzero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -69770,15 +66596,15 @@ pub unsafe fn vtstq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vtst_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t { - let c: int16x4_t = simd_and(a, b); - let d: i16x4 = i16x4::new(0, 0, 0, 0); - simd_ne(c, transmute(d)) +pub fn vtst_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t { + unsafe { + let c: int16x4_t = simd_and(a, b); + let d: i16x4 = i16x4::new(0, 0, 0, 0); + simd_ne(c, transmute(d)) + } } #[doc = "Signed compare bitwise Test bits nonzero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -69795,15 +66621,15 @@ pub unsafe fn vtst_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vtstq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t { - let c: int16x8_t = simd_and(a, b); - let d: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0); - simd_ne(c, transmute(d)) +pub fn vtstq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t { + unsafe { + let c: int16x8_t = simd_and(a, b); + let d: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0); + simd_ne(c, transmute(d)) + } } #[doc = "Signed compare bitwise Test bits nonzero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -69820,15 +66646,15 @@ pub unsafe fn vtstq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vtst_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t { - let c: int32x2_t = simd_and(a, b); - let d: i32x2 = i32x2::new(0, 0); - simd_ne(c, transmute(d)) +pub fn vtst_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t { + unsafe { + let c: int32x2_t = simd_and(a, b); + let d: i32x2 = i32x2::new(0, 0); + simd_ne(c, transmute(d)) + } } #[doc = "Signed compare bitwise Test bits nonzero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -69845,15 +66671,15 @@ pub unsafe fn vtst_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vtstq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t { - let c: int32x4_t = simd_and(a, b); - let d: i32x4 = i32x4::new(0, 0, 0, 0); - simd_ne(c, transmute(d)) +pub fn vtstq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t { + unsafe { + let c: int32x4_t = simd_and(a, b); + let d: i32x4 = i32x4::new(0, 0, 0, 0); + simd_ne(c, transmute(d)) + } } #[doc = "Signed compare bitwise Test bits nonzero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -69870,15 +66696,15 @@ pub unsafe fn vtstq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vtst_p8(a: poly8x8_t, b: poly8x8_t) -> uint8x8_t { - let c: poly8x8_t = simd_and(a, b); - let d: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); - simd_ne(c, transmute(d)) +pub fn vtst_p8(a: poly8x8_t, b: poly8x8_t) -> uint8x8_t { + unsafe { + let c: poly8x8_t = simd_and(a, b); + let d: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); + simd_ne(c, transmute(d)) + } } #[doc = "Signed compare bitwise Test bits nonzero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -69895,15 +66721,15 @@ pub unsafe fn vtst_p8(a: poly8x8_t, b: poly8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vtstq_p8(a: poly8x16_t, b: poly8x16_t) -> uint8x16_t { - let c: poly8x16_t = simd_and(a, b); - let d: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); - simd_ne(c, transmute(d)) +pub fn vtstq_p8(a: poly8x16_t, b: poly8x16_t) -> uint8x16_t { + unsafe { + let c: poly8x16_t = simd_and(a, b); + let d: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); + simd_ne(c, transmute(d)) + } } #[doc = "Signed compare bitwise Test bits nonzero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -69920,15 +66746,15 @@ pub unsafe fn vtstq_p8(a: poly8x16_t, b: poly8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vtst_p16(a: poly16x4_t, b: poly16x4_t) -> uint16x4_t { - let c: poly16x4_t = simd_and(a, b); - let d: i16x4 = i16x4::new(0, 0, 0, 0); - simd_ne(c, transmute(d)) +pub fn vtst_p16(a: poly16x4_t, b: poly16x4_t) -> uint16x4_t { + unsafe { + let c: poly16x4_t = simd_and(a, b); + let d: i16x4 = i16x4::new(0, 0, 0, 0); + simd_ne(c, transmute(d)) + } } #[doc = "Signed compare bitwise Test bits nonzero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -69945,15 +66771,15 @@ pub unsafe fn vtst_p16(a: poly16x4_t, b: poly16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vtstq_p16(a: poly16x8_t, b: poly16x8_t) -> uint16x8_t { - let c: poly16x8_t = simd_and(a, b); - let d: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0); - simd_ne(c, transmute(d)) +pub fn vtstq_p16(a: poly16x8_t, b: poly16x8_t) -> uint16x8_t { + unsafe { + let c: poly16x8_t = simd_and(a, b); + let d: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0); + simd_ne(c, transmute(d)) + } } #[doc = "Unsigned compare bitwise Test bits nonzero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -69970,15 +66796,15 @@ pub unsafe fn vtstq_p16(a: poly16x8_t, b: poly16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vtst_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { - let c: uint8x8_t = simd_and(a, b); - let d: u8x8 = u8x8::new(0, 0, 0, 0, 0, 0, 0, 0); - simd_ne(c, transmute(d)) +pub fn vtst_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + unsafe { + let c: uint8x8_t = simd_and(a, b); + let d: u8x8 = u8x8::new(0, 0, 0, 0, 0, 0, 0, 0); + simd_ne(c, transmute(d)) + } } #[doc = "Unsigned compare bitwise Test bits nonzero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -69995,15 +66821,15 @@ pub unsafe fn vtst_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vtstq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { - let c: uint8x16_t = simd_and(a, b); - let d: u8x16 = u8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); - simd_ne(c, transmute(d)) +pub fn vtstq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + unsafe { + let c: uint8x16_t = simd_and(a, b); + let d: u8x16 = u8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); + simd_ne(c, transmute(d)) + } } #[doc = "Unsigned compare bitwise Test bits nonzero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -70020,15 +66846,15 @@ pub unsafe fn vtstq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vtst_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { - let c: uint16x4_t = simd_and(a, b); - let d: u16x4 = u16x4::new(0, 0, 0, 0); - simd_ne(c, transmute(d)) +pub fn vtst_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + unsafe { + let c: uint16x4_t = simd_and(a, b); + let d: u16x4 = u16x4::new(0, 0, 0, 0); + simd_ne(c, transmute(d)) + } } #[doc = "Unsigned compare bitwise Test bits nonzero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -70045,15 +66871,15 @@ pub unsafe fn vtst_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vtstq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { - let c: uint16x8_t = simd_and(a, b); - let d: u16x8 = u16x8::new(0, 0, 0, 0, 0, 0, 0, 0); - simd_ne(c, transmute(d)) +pub fn vtstq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + unsafe { + let c: uint16x8_t = simd_and(a, b); + let d: u16x8 = u16x8::new(0, 0, 0, 0, 0, 0, 0, 0); + simd_ne(c, transmute(d)) + } } #[doc = "Unsigned compare bitwise Test bits nonzero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -70070,15 +66896,15 @@ pub unsafe fn vtstq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vtst_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { - let c: uint32x2_t = simd_and(a, b); - let d: u32x2 = u32x2::new(0, 0); - simd_ne(c, transmute(d)) +pub fn vtst_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + unsafe { + let c: uint32x2_t = simd_and(a, b); + let d: u32x2 = u32x2::new(0, 0); + simd_ne(c, transmute(d)) + } } #[doc = "Unsigned compare bitwise Test bits nonzero"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -70095,15 +66921,15 @@ pub unsafe fn vtst_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vtstq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { - let c: uint32x4_t = simd_and(a, b); - let d: u32x4 = u32x4::new(0, 0, 0, 0); - simd_ne(c, transmute(d)) +pub fn vtstq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + unsafe { + let c: uint32x4_t = simd_and(a, b); + let d: u32x4 = u32x4::new(0, 0, 0, 0); + simd_ne(c, transmute(d)) + } } #[doc = "Dot product index form with unsigned and signed integers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdot_lane_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,i8mm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] @@ -70121,20 +66947,16 @@ pub unsafe fn vtstq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vusdot_lane_s32( - a: int32x2_t, - b: uint8x8_t, - c: int8x8_t, -) -> int32x2_t { +pub fn vusdot_lane_s32(a: int32x2_t, b: uint8x8_t, c: int8x8_t) -> int32x2_t { static_assert_uimm_bits!(LANE, 1); - let c: int32x2_t = transmute(c); - let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); - vusdot_s32(a, b, transmute(c)) + unsafe { + let c: int32x2_t = transmute(c); + let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); + vusdot_s32(a, b, transmute(c)) + } } #[doc = "Dot product index form with unsigned and signed integers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdotq_lane_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,i8mm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] @@ -70152,20 +66974,17 @@ pub unsafe fn vusdot_lane_s32( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vusdotq_lane_s32( - a: int32x4_t, - b: uint8x16_t, - c: int8x8_t, -) -> int32x4_t { +pub fn vusdotq_lane_s32(a: int32x4_t, b: uint8x16_t, c: int8x8_t) -> int32x4_t { static_assert_uimm_bits!(LANE, 1); - let c: int32x2_t = transmute(c); - let c: int32x4_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vusdotq_s32(a, b, transmute(c)) + unsafe { + let c: int32x2_t = transmute(c); + let c: int32x4_t = + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); + vusdotq_s32(a, b, transmute(c)) + } } #[doc = "Dot product vector form with unsigned and signed integers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdot_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,i8mm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] @@ -70182,7 +67001,7 @@ pub unsafe fn vusdotq_lane_s32( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vusdot_s32(a: int32x2_t, b: uint8x8_t, c: int8x8_t) -> int32x2_t { +pub fn vusdot_s32(a: int32x2_t, b: uint8x8_t, c: int8x8_t) -> int32x2_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -70191,12 +67010,10 @@ pub unsafe fn vusdot_s32(a: int32x2_t, b: uint8x8_t, c: int8x8_t) -> int32x2_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.usdot.v2i32.v8i8")] fn _vusdot_s32(a: int32x2_t, b: uint8x8_t, c: int8x8_t) -> int32x2_t; } - _vusdot_s32(a, b, c) + unsafe { _vusdot_s32(a, b, c) } } #[doc = "Dot product vector form with unsigned and signed integers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdotq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,i8mm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] @@ -70213,7 +67030,7 @@ pub unsafe fn vusdot_s32(a: int32x2_t, b: uint8x8_t, c: int8x8_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vusdotq_s32(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t { +pub fn vusdotq_s32(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -70222,12 +67039,10 @@ pub unsafe fn vusdotq_s32(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_ #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.usdot.v4i32.v16i8")] fn _vusdotq_s32(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t; } - _vusdotq_s32(a, b, c) + unsafe { _vusdotq_s32(a, b, c) } } #[doc = "Unsigned and signed 8-bit integer matrix multiply-accumulate"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusmmlaq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,i8mm")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] @@ -70244,7 +67059,7 @@ pub unsafe fn vusdotq_s32(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_ target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vusmmlaq_s32(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t { +pub fn vusmmlaq_s32(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t { unsafe extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), @@ -70253,12 +67068,10 @@ pub unsafe fn vusmmlaq_s32(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.usmmla.v4i32.v16i8")] fn _vusmmlaq_s32(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t; } - _vusmmlaq_s32(a, b, c) + unsafe { _vusmmlaq_s32(a, b, c) } } #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] @@ -70268,15 +67081,15 @@ pub unsafe fn vusmmlaq_s32(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4 )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vuzp_f16(a: float16x4_t, b: float16x4_t) -> float16x4x2_t { - let a0: float16x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]); - let b0: float16x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); - transmute((a0, b0)) +pub fn vuzp_f16(a: float16x4_t, b: float16x4_t) -> float16x4x2_t { + unsafe { + let a0: float16x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]); + let b0: float16x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); + transmute((a0, b0)) + } } #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] @@ -70286,15 +67099,15 @@ pub unsafe fn vuzp_f16(a: float16x4_t, b: float16x4_t) -> float16x4x2_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vuzpq_f16(a: float16x8_t, b: float16x8_t) -> float16x8x2_t { - let a0: float16x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); - let b0: float16x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); - transmute((a0, b0)) +pub fn vuzpq_f16(a: float16x8_t, b: float16x8_t) -> float16x8x2_t { + unsafe { + let a0: float16x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); + let b0: float16x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); + transmute((a0, b0)) + } } #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -70311,15 +67124,15 @@ pub unsafe fn vuzpq_f16(a: float16x8_t, b: float16x8_t) -> float16x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vuzp_f32(a: float32x2_t, b: float32x2_t) -> float32x2x2_t { - let a0: float32x2_t = simd_shuffle!(a, b, [0, 2]); - let b0: float32x2_t = simd_shuffle!(a, b, [1, 3]); - transmute((a0, b0)) +pub fn vuzp_f32(a: float32x2_t, b: float32x2_t) -> float32x2x2_t { + unsafe { + let a0: float32x2_t = simd_shuffle!(a, b, [0, 2]); + let b0: float32x2_t = simd_shuffle!(a, b, [1, 3]); + transmute((a0, b0)) + } } #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -70336,15 +67149,15 @@ pub unsafe fn vuzp_f32(a: float32x2_t, b: float32x2_t) -> float32x2x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vuzp_s32(a: int32x2_t, b: int32x2_t) -> int32x2x2_t { - let a0: int32x2_t = simd_shuffle!(a, b, [0, 2]); - let b0: int32x2_t = simd_shuffle!(a, b, [1, 3]); - transmute((a0, b0)) +pub fn vuzp_s32(a: int32x2_t, b: int32x2_t) -> int32x2x2_t { + unsafe { + let a0: int32x2_t = simd_shuffle!(a, b, [0, 2]); + let b0: int32x2_t = simd_shuffle!(a, b, [1, 3]); + transmute((a0, b0)) + } } #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -70361,15 +67174,15 @@ pub unsafe fn vuzp_s32(a: int32x2_t, b: int32x2_t) -> int32x2x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vuzp_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2x2_t { - let a0: uint32x2_t = simd_shuffle!(a, b, [0, 2]); - let b0: uint32x2_t = simd_shuffle!(a, b, [1, 3]); - transmute((a0, b0)) +pub fn vuzp_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2x2_t { + unsafe { + let a0: uint32x2_t = simd_shuffle!(a, b, [0, 2]); + let b0: uint32x2_t = simd_shuffle!(a, b, [1, 3]); + transmute((a0, b0)) + } } #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -70386,15 +67199,15 @@ pub unsafe fn vuzp_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vuzpq_f32(a: float32x4_t, b: float32x4_t) -> float32x4x2_t { - let a0: float32x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]); - let b0: float32x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); - transmute((a0, b0)) +pub fn vuzpq_f32(a: float32x4_t, b: float32x4_t) -> float32x4x2_t { + unsafe { + let a0: float32x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]); + let b0: float32x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); + transmute((a0, b0)) + } } #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -70411,15 +67224,15 @@ pub unsafe fn vuzpq_f32(a: float32x4_t, b: float32x4_t) -> float32x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vuzp_s8(a: int8x8_t, b: int8x8_t) -> int8x8x2_t { - let a0: int8x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); - let b0: int8x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); - transmute((a0, b0)) +pub fn vuzp_s8(a: int8x8_t, b: int8x8_t) -> int8x8x2_t { + unsafe { + let a0: int8x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); + let b0: int8x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); + transmute((a0, b0)) + } } #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -70436,23 +67249,23 @@ pub unsafe fn vuzp_s8(a: int8x8_t, b: int8x8_t) -> int8x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vuzpq_s8(a: int8x16_t, b: int8x16_t) -> int8x16x2_t { - let a0: int8x16_t = simd_shuffle!( - a, - b, - [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30] - ); - let b0: int8x16_t = simd_shuffle!( - a, - b, - [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31] - ); - transmute((a0, b0)) +pub fn vuzpq_s8(a: int8x16_t, b: int8x16_t) -> int8x16x2_t { + unsafe { + let a0: int8x16_t = simd_shuffle!( + a, + b, + [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30] + ); + let b0: int8x16_t = simd_shuffle!( + a, + b, + [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31] + ); + transmute((a0, b0)) + } } #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -70469,15 +67282,15 @@ pub unsafe fn vuzpq_s8(a: int8x16_t, b: int8x16_t) -> int8x16x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vuzp_s16(a: int16x4_t, b: int16x4_t) -> int16x4x2_t { - let a0: int16x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]); - let b0: int16x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); - transmute((a0, b0)) +pub fn vuzp_s16(a: int16x4_t, b: int16x4_t) -> int16x4x2_t { + unsafe { + let a0: int16x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]); + let b0: int16x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); + transmute((a0, b0)) + } } #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -70494,15 +67307,15 @@ pub unsafe fn vuzp_s16(a: int16x4_t, b: int16x4_t) -> int16x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vuzpq_s16(a: int16x8_t, b: int16x8_t) -> int16x8x2_t { - let a0: int16x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); - let b0: int16x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); - transmute((a0, b0)) +pub fn vuzpq_s16(a: int16x8_t, b: int16x8_t) -> int16x8x2_t { + unsafe { + let a0: int16x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); + let b0: int16x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); + transmute((a0, b0)) + } } #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -70519,15 +67332,15 @@ pub unsafe fn vuzpq_s16(a: int16x8_t, b: int16x8_t) -> int16x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vuzpq_s32(a: int32x4_t, b: int32x4_t) -> int32x4x2_t { - let a0: int32x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]); - let b0: int32x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); - transmute((a0, b0)) +pub fn vuzpq_s32(a: int32x4_t, b: int32x4_t) -> int32x4x2_t { + unsafe { + let a0: int32x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]); + let b0: int32x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); + transmute((a0, b0)) + } } #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -70544,15 +67357,15 @@ pub unsafe fn vuzpq_s32(a: int32x4_t, b: int32x4_t) -> int32x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vuzp_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8x2_t { - let a0: uint8x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); - let b0: uint8x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); - transmute((a0, b0)) +pub fn vuzp_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8x2_t { + unsafe { + let a0: uint8x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); + let b0: uint8x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); + transmute((a0, b0)) + } } #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -70569,23 +67382,23 @@ pub unsafe fn vuzp_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vuzpq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16x2_t { - let a0: uint8x16_t = simd_shuffle!( - a, - b, - [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30] - ); - let b0: uint8x16_t = simd_shuffle!( - a, - b, - [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31] - ); - transmute((a0, b0)) +pub fn vuzpq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16x2_t { + unsafe { + let a0: uint8x16_t = simd_shuffle!( + a, + b, + [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30] + ); + let b0: uint8x16_t = simd_shuffle!( + a, + b, + [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31] + ); + transmute((a0, b0)) + } } #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -70602,15 +67415,15 @@ pub unsafe fn vuzpq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vuzp_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4x2_t { - let a0: uint16x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]); - let b0: uint16x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); - transmute((a0, b0)) +pub fn vuzp_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4x2_t { + unsafe { + let a0: uint16x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]); + let b0: uint16x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); + transmute((a0, b0)) + } } #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -70627,15 +67440,15 @@ pub unsafe fn vuzp_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vuzpq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8x2_t { - let a0: uint16x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); - let b0: uint16x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); - transmute((a0, b0)) +pub fn vuzpq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8x2_t { + unsafe { + let a0: uint16x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); + let b0: uint16x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); + transmute((a0, b0)) + } } #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -70652,15 +67465,15 @@ pub unsafe fn vuzpq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vuzpq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4x2_t { - let a0: uint32x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]); - let b0: uint32x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); - transmute((a0, b0)) +pub fn vuzpq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4x2_t { + unsafe { + let a0: uint32x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]); + let b0: uint32x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); + transmute((a0, b0)) + } } #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -70677,15 +67490,15 @@ pub unsafe fn vuzpq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vuzp_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8x2_t { - let a0: poly8x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); - let b0: poly8x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); - transmute((a0, b0)) +pub fn vuzp_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8x2_t { + unsafe { + let a0: poly8x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); + let b0: poly8x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); + transmute((a0, b0)) + } } #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -70702,23 +67515,23 @@ pub unsafe fn vuzp_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vuzpq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16x2_t { - let a0: poly8x16_t = simd_shuffle!( - a, - b, - [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30] - ); - let b0: poly8x16_t = simd_shuffle!( - a, - b, - [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31] - ); - transmute((a0, b0)) +pub fn vuzpq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16x2_t { + unsafe { + let a0: poly8x16_t = simd_shuffle!( + a, + b, + [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30] + ); + let b0: poly8x16_t = simd_shuffle!( + a, + b, + [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31] + ); + transmute((a0, b0)) + } } #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -70735,15 +67548,15 @@ pub unsafe fn vuzpq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vuzp_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4x2_t { - let a0: poly16x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]); - let b0: poly16x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); - transmute((a0, b0)) +pub fn vuzp_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4x2_t { + unsafe { + let a0: poly16x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]); + let b0: poly16x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); + transmute((a0, b0)) + } } #[doc = "Unzip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -70760,15 +67573,15 @@ pub unsafe fn vuzp_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vuzpq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8x2_t { - let a0: poly16x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); - let b0: poly16x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); - transmute((a0, b0)) +pub fn vuzpq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8x2_t { + unsafe { + let a0: poly16x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); + let b0: poly16x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); + transmute((a0, b0)) + } } #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vzip.16"))] @@ -70778,15 +67591,15 @@ pub unsafe fn vuzpq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8x2_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vzip_f16(a: float16x4_t, b: float16x4_t) -> float16x4x2_t { - let a0: float16x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]); - let b0: float16x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); - transmute((a0, b0)) +pub fn vzip_f16(a: float16x4_t, b: float16x4_t) -> float16x4x2_t { + unsafe { + let a0: float16x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]); + let b0: float16x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); + transmute((a0, b0)) + } } #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_f16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vzip.16"))] @@ -70796,15 +67609,15 @@ pub unsafe fn vzip_f16(a: float16x4_t, b: float16x4_t) -> float16x4x2_t { )] #[target_feature(enable = "neon,fp16")] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vzipq_f16(a: float16x8_t, b: float16x8_t) -> float16x8x2_t { - let a0: float16x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]); - let b0: float16x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]); - transmute((a0, b0)) +pub fn vzipq_f16(a: float16x8_t, b: float16x8_t) -> float16x8x2_t { + unsafe { + let a0: float16x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]); + let b0: float16x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]); + transmute((a0, b0)) + } } #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -70821,15 +67634,15 @@ pub unsafe fn vzipq_f16(a: float16x8_t, b: float16x8_t) -> float16x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vzip_f32(a: float32x2_t, b: float32x2_t) -> float32x2x2_t { - let a0: float32x2_t = simd_shuffle!(a, b, [0, 2]); - let b0: float32x2_t = simd_shuffle!(a, b, [1, 3]); - transmute((a0, b0)) +pub fn vzip_f32(a: float32x2_t, b: float32x2_t) -> float32x2x2_t { + unsafe { + let a0: float32x2_t = simd_shuffle!(a, b, [0, 2]); + let b0: float32x2_t = simd_shuffle!(a, b, [1, 3]); + transmute((a0, b0)) + } } #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -70846,15 +67659,15 @@ pub unsafe fn vzip_f32(a: float32x2_t, b: float32x2_t) -> float32x2x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vzip_s32(a: int32x2_t, b: int32x2_t) -> int32x2x2_t { - let a0: int32x2_t = simd_shuffle!(a, b, [0, 2]); - let b0: int32x2_t = simd_shuffle!(a, b, [1, 3]); - transmute((a0, b0)) +pub fn vzip_s32(a: int32x2_t, b: int32x2_t) -> int32x2x2_t { + unsafe { + let a0: int32x2_t = simd_shuffle!(a, b, [0, 2]); + let b0: int32x2_t = simd_shuffle!(a, b, [1, 3]); + transmute((a0, b0)) + } } #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -70871,15 +67684,15 @@ pub unsafe fn vzip_s32(a: int32x2_t, b: int32x2_t) -> int32x2x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vzip_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2x2_t { - let a0: uint32x2_t = simd_shuffle!(a, b, [0, 2]); - let b0: uint32x2_t = simd_shuffle!(a, b, [1, 3]); - transmute((a0, b0)) +pub fn vzip_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2x2_t { + unsafe { + let a0: uint32x2_t = simd_shuffle!(a, b, [0, 2]); + let b0: uint32x2_t = simd_shuffle!(a, b, [1, 3]); + transmute((a0, b0)) + } } #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -70896,15 +67709,15 @@ pub unsafe fn vzip_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vzip_s8(a: int8x8_t, b: int8x8_t) -> int8x8x2_t { - let a0: int8x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]); - let b0: int8x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]); - transmute((a0, b0)) +pub fn vzip_s8(a: int8x8_t, b: int8x8_t) -> int8x8x2_t { + unsafe { + let a0: int8x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]); + let b0: int8x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]); + transmute((a0, b0)) + } } #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -70921,15 +67734,15 @@ pub unsafe fn vzip_s8(a: int8x8_t, b: int8x8_t) -> int8x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vzip_s16(a: int16x4_t, b: int16x4_t) -> int16x4x2_t { - let a0: int16x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]); - let b0: int16x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); - transmute((a0, b0)) +pub fn vzip_s16(a: int16x4_t, b: int16x4_t) -> int16x4x2_t { + unsafe { + let a0: int16x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]); + let b0: int16x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); + transmute((a0, b0)) + } } #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -70946,15 +67759,15 @@ pub unsafe fn vzip_s16(a: int16x4_t, b: int16x4_t) -> int16x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vzip_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8x2_t { - let a0: uint8x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]); - let b0: uint8x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]); - transmute((a0, b0)) +pub fn vzip_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8x2_t { + unsafe { + let a0: uint8x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]); + let b0: uint8x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]); + transmute((a0, b0)) + } } #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -70971,15 +67784,15 @@ pub unsafe fn vzip_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vzip_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4x2_t { - let a0: uint16x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]); - let b0: uint16x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); - transmute((a0, b0)) +pub fn vzip_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4x2_t { + unsafe { + let a0: uint16x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]); + let b0: uint16x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); + transmute((a0, b0)) + } } #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -70996,15 +67809,15 @@ pub unsafe fn vzip_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vzip_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8x2_t { - let a0: poly8x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]); - let b0: poly8x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]); - transmute((a0, b0)) +pub fn vzip_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8x2_t { + unsafe { + let a0: poly8x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]); + let b0: poly8x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]); + transmute((a0, b0)) + } } #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -71021,15 +67834,15 @@ pub unsafe fn vzip_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vzip_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4x2_t { - let a0: poly16x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]); - let b0: poly16x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); - transmute((a0, b0)) +pub fn vzip_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4x2_t { + unsafe { + let a0: poly16x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]); + let b0: poly16x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); + transmute((a0, b0)) + } } #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_f32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -71046,15 +67859,15 @@ pub unsafe fn vzip_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vzipq_f32(a: float32x4_t, b: float32x4_t) -> float32x4x2_t { - let a0: float32x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]); - let b0: float32x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); - transmute((a0, b0)) +pub fn vzipq_f32(a: float32x4_t, b: float32x4_t) -> float32x4x2_t { + unsafe { + let a0: float32x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]); + let b0: float32x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); + transmute((a0, b0)) + } } #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_s8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -71071,23 +67884,23 @@ pub unsafe fn vzipq_f32(a: float32x4_t, b: float32x4_t) -> float32x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vzipq_s8(a: int8x16_t, b: int8x16_t) -> int8x16x2_t { - let a0: int8x16_t = simd_shuffle!( - a, - b, - [0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23] - ); - let b0: int8x16_t = simd_shuffle!( - a, - b, - [8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31] - ); - transmute((a0, b0)) +pub fn vzipq_s8(a: int8x16_t, b: int8x16_t) -> int8x16x2_t { + unsafe { + let a0: int8x16_t = simd_shuffle!( + a, + b, + [0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23] + ); + let b0: int8x16_t = simd_shuffle!( + a, + b, + [8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31] + ); + transmute((a0, b0)) + } } #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_s16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -71104,15 +67917,15 @@ pub unsafe fn vzipq_s8(a: int8x16_t, b: int8x16_t) -> int8x16x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vzipq_s16(a: int16x8_t, b: int16x8_t) -> int16x8x2_t { - let a0: int16x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]); - let b0: int16x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]); - transmute((a0, b0)) +pub fn vzipq_s16(a: int16x8_t, b: int16x8_t) -> int16x8x2_t { + unsafe { + let a0: int16x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]); + let b0: int16x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]); + transmute((a0, b0)) + } } #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_s32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -71129,15 +67942,15 @@ pub unsafe fn vzipq_s16(a: int16x8_t, b: int16x8_t) -> int16x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vzipq_s32(a: int32x4_t, b: int32x4_t) -> int32x4x2_t { - let a0: int32x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]); - let b0: int32x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); - transmute((a0, b0)) +pub fn vzipq_s32(a: int32x4_t, b: int32x4_t) -> int32x4x2_t { + unsafe { + let a0: int32x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]); + let b0: int32x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); + transmute((a0, b0)) + } } #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -71154,23 +67967,23 @@ pub unsafe fn vzipq_s32(a: int32x4_t, b: int32x4_t) -> int32x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vzipq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16x2_t { - let a0: uint8x16_t = simd_shuffle!( - a, - b, - [0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23] - ); - let b0: uint8x16_t = simd_shuffle!( - a, - b, - [8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31] - ); - transmute((a0, b0)) +pub fn vzipq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16x2_t { + unsafe { + let a0: uint8x16_t = simd_shuffle!( + a, + b, + [0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23] + ); + let b0: uint8x16_t = simd_shuffle!( + a, + b, + [8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31] + ); + transmute((a0, b0)) + } } #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -71187,15 +68000,15 @@ pub unsafe fn vzipq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vzipq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8x2_t { - let a0: uint16x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]); - let b0: uint16x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]); - transmute((a0, b0)) +pub fn vzipq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8x2_t { + unsafe { + let a0: uint16x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]); + let b0: uint16x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]); + transmute((a0, b0)) + } } #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -71212,15 +68025,15 @@ pub unsafe fn vzipq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vzipq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4x2_t { - let a0: uint32x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]); - let b0: uint32x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); - transmute((a0, b0)) +pub fn vzipq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4x2_t { + unsafe { + let a0: uint32x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]); + let b0: uint32x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); + transmute((a0, b0)) + } } #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -71237,23 +68050,23 @@ pub unsafe fn vzipq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vzipq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16x2_t { - let a0: poly8x16_t = simd_shuffle!( - a, - b, - [0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23] - ); - let b0: poly8x16_t = simd_shuffle!( - a, - b, - [8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31] - ); - transmute((a0, b0)) +pub fn vzipq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16x2_t { + unsafe { + let a0: poly8x16_t = simd_shuffle!( + a, + b, + [0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23] + ); + let b0: poly8x16_t = simd_shuffle!( + a, + b, + [8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31] + ); + transmute((a0, b0)) + } } #[doc = "Zip vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] @@ -71270,8 +68083,10 @@ pub unsafe fn vzipq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vzipq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8x2_t { - let a0: poly16x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]); - let b0: poly16x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]); - transmute((a0, b0)) +pub fn vzipq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8x2_t { + unsafe { + let a0: poly16x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]); + let b0: poly16x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]); + transmute((a0, b0)) + } } diff --git a/crates/core_arch/src/arm_shared/neon/mod.rs b/crates/core_arch/src/arm_shared/neon/mod.rs index cf24be9a74..e424f0eb0f 100644 --- a/crates/core_arch/src/arm_shared/neon/mod.rs +++ b/crates/core_arch/src/arm_shared/neon/mod.rs @@ -2313,8 +2313,8 @@ pub unsafe fn vld1q_dup_f32(ptr: *const f32) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vaba_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t { - simd_add(a, vabd_s8(b, c)) +pub fn vaba_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t { + unsafe { simd_add(a, vabd_s8(b, c)) } } #[inline] #[target_feature(enable = "neon")] @@ -2332,8 +2332,8 @@ pub unsafe fn vaba_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vaba_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t { - simd_add(a, vabd_s16(b, c)) +pub fn vaba_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t { + unsafe { simd_add(a, vabd_s16(b, c)) } } #[inline] #[target_feature(enable = "neon")] @@ -2351,8 +2351,8 @@ pub unsafe fn vaba_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vaba_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t { - simd_add(a, vabd_s32(b, c)) +pub fn vaba_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t { + unsafe { simd_add(a, vabd_s32(b, c)) } } #[inline] #[target_feature(enable = "neon")] @@ -2370,8 +2370,8 @@ pub unsafe fn vaba_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vaba_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t { - simd_add(a, vabd_u8(b, c)) +pub fn vaba_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t { + unsafe { simd_add(a, vabd_u8(b, c)) } } #[inline] #[target_feature(enable = "neon")] @@ -2389,8 +2389,8 @@ pub unsafe fn vaba_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vaba_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_t { - simd_add(a, vabd_u16(b, c)) +pub fn vaba_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_t { + unsafe { simd_add(a, vabd_u16(b, c)) } } #[inline] #[target_feature(enable = "neon")] @@ -2408,8 +2408,8 @@ pub unsafe fn vaba_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_ target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vaba_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_t { - simd_add(a, vabd_u32(b, c)) +pub fn vaba_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_t { + unsafe { simd_add(a, vabd_u32(b, c)) } } // signed absolute difference and accumulate (128-bit) #[inline] @@ -2428,8 +2428,8 @@ pub unsafe fn vaba_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_ target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vabaq_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t { - simd_add(a, vabdq_s8(b, c)) +pub fn vabaq_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t { + unsafe { simd_add(a, vabdq_s8(b, c)) } } #[inline] #[target_feature(enable = "neon")] @@ -2447,8 +2447,8 @@ pub unsafe fn vabaq_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vabaq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t { - simd_add(a, vabdq_s16(b, c)) +pub fn vabaq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t { + unsafe { simd_add(a, vabdq_s16(b, c)) } } #[inline] #[target_feature(enable = "neon")] @@ -2466,8 +2466,8 @@ pub unsafe fn vabaq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vabaq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t { - simd_add(a, vabdq_s32(b, c)) +pub fn vabaq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t { + unsafe { simd_add(a, vabdq_s32(b, c)) } } #[inline] #[target_feature(enable = "neon")] @@ -2485,8 +2485,8 @@ pub unsafe fn vabaq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vabaq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t { - simd_add(a, vabdq_u8(b, c)) +pub fn vabaq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t { + unsafe { simd_add(a, vabdq_u8(b, c)) } } #[inline] #[target_feature(enable = "neon")] @@ -2504,8 +2504,8 @@ pub unsafe fn vabaq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_ target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vabaq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t { - simd_add(a, vabdq_u16(b, c)) +pub fn vabaq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t { + unsafe { simd_add(a, vabdq_u16(b, c)) } } #[inline] #[target_feature(enable = "neon")] @@ -2523,8 +2523,8 @@ pub unsafe fn vabaq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8 target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vabaq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t { - simd_add(a, vabdq_u32(b, c)) +pub fn vabaq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t { + unsafe { simd_add(a, vabdq_u32(b, c)) } } /// Vector add. @@ -2544,8 +2544,8 @@ pub unsafe fn vabaq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4 target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { - simd_add(a, b) +pub fn vadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { + unsafe { simd_add(a, b) } } /// Vector add. @@ -2565,8 +2565,8 @@ pub unsafe fn vadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { - simd_add(a, b) +pub fn vaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { + unsafe { simd_add(a, b) } } /// Vector add. @@ -2586,8 +2586,8 @@ pub unsafe fn vaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { - simd_add(a, b) +pub fn vadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + unsafe { simd_add(a, b) } } /// Vector add. @@ -2607,8 +2607,8 @@ pub unsafe fn vadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { - simd_add(a, b) +pub fn vaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + unsafe { simd_add(a, b) } } /// Vector add. @@ -2628,8 +2628,8 @@ pub unsafe fn vaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { - simd_add(a, b) +pub fn vadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + unsafe { simd_add(a, b) } } /// Vector add. @@ -2649,8 +2649,8 @@ pub unsafe fn vadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { - simd_add(a, b) +pub fn vaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + unsafe { simd_add(a, b) } } /// Vector add. @@ -2670,8 +2670,8 @@ pub unsafe fn vaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vaddq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { - simd_add(a, b) +pub fn vaddq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { + unsafe { simd_add(a, b) } } /// Vector add. @@ -2691,8 +2691,8 @@ pub unsafe fn vaddq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { - simd_add(a, b) +pub fn vadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + unsafe { simd_add(a, b) } } /// Vector add. @@ -2712,8 +2712,8 @@ pub unsafe fn vadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { - simd_add(a, b) +pub fn vaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + unsafe { simd_add(a, b) } } /// Vector add. @@ -2733,8 +2733,8 @@ pub unsafe fn vaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { - simd_add(a, b) +pub fn vadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + unsafe { simd_add(a, b) } } /// Vector add. @@ -2754,8 +2754,8 @@ pub unsafe fn vadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { - simd_add(a, b) +pub fn vaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + unsafe { simd_add(a, b) } } /// Vector add. @@ -2775,8 +2775,8 @@ pub unsafe fn vaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { - simd_add(a, b) +pub fn vadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + unsafe { simd_add(a, b) } } /// Vector add. @@ -2796,8 +2796,8 @@ pub unsafe fn vadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { - simd_add(a, b) +pub fn vaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + unsafe { simd_add(a, b) } } /// Vector add. @@ -2817,8 +2817,8 @@ pub unsafe fn vaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vaddq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { - simd_add(a, b) +pub fn vaddq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { + unsafe { simd_add(a, b) } } /// Vector add. @@ -2838,8 +2838,8 @@ pub unsafe fn vaddq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vadd_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { - simd_add(a, b) +pub fn vadd_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { + unsafe { simd_add(a, b) } } /// Vector add. @@ -2859,8 +2859,8 @@ pub unsafe fn vadd_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vaddq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { - simd_add(a, b) +pub fn vaddq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { + unsafe { simd_add(a, b) } } /// Signed Add Long (vector). @@ -2880,10 +2880,12 @@ pub unsafe fn vaddq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vaddl_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t { - let a: int16x8_t = simd_cast(a); - let b: int16x8_t = simd_cast(b); - simd_add(a, b) +pub fn vaddl_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t { + unsafe { + let a: int16x8_t = simd_cast(a); + let b: int16x8_t = simd_cast(b); + simd_add(a, b) + } } /// Signed Add Long (vector). @@ -2903,10 +2905,12 @@ pub unsafe fn vaddl_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vaddl_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t { - let a: int32x4_t = simd_cast(a); - let b: int32x4_t = simd_cast(b); - simd_add(a, b) +pub fn vaddl_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t { + unsafe { + let a: int32x4_t = simd_cast(a); + let b: int32x4_t = simd_cast(b); + simd_add(a, b) + } } /// Signed Add Long (vector). @@ -2926,10 +2930,12 @@ pub unsafe fn vaddl_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vaddl_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t { - let a: int64x2_t = simd_cast(a); - let b: int64x2_t = simd_cast(b); - simd_add(a, b) +pub fn vaddl_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t { + unsafe { + let a: int64x2_t = simd_cast(a); + let b: int64x2_t = simd_cast(b); + simd_add(a, b) + } } /// Unsigned Add Long (vector). @@ -2949,10 +2955,12 @@ pub unsafe fn vaddl_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vaddl_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t { - let a: uint16x8_t = simd_cast(a); - let b: uint16x8_t = simd_cast(b); - simd_add(a, b) +pub fn vaddl_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t { + unsafe { + let a: uint16x8_t = simd_cast(a); + let b: uint16x8_t = simd_cast(b); + simd_add(a, b) + } } /// Unsigned Add Long (vector). @@ -2972,10 +2980,12 @@ pub unsafe fn vaddl_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vaddl_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t { - let a: uint32x4_t = simd_cast(a); - let b: uint32x4_t = simd_cast(b); - simd_add(a, b) +pub fn vaddl_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t { + unsafe { + let a: uint32x4_t = simd_cast(a); + let b: uint32x4_t = simd_cast(b); + simd_add(a, b) + } } /// Unsigned Add Long (vector). @@ -2995,10 +3005,12 @@ pub unsafe fn vaddl_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vaddl_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t { - let a: uint64x2_t = simd_cast(a); - let b: uint64x2_t = simd_cast(b); - simd_add(a, b) +pub fn vaddl_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t { + unsafe { + let a: uint64x2_t = simd_cast(a); + let b: uint64x2_t = simd_cast(b); + simd_add(a, b) + } } /// Signed Add Long (vector, high half). @@ -3018,12 +3030,14 @@ pub unsafe fn vaddl_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vaddl_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t { - let a: int8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); - let b: int8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); - let a: int16x8_t = simd_cast(a); - let b: int16x8_t = simd_cast(b); - simd_add(a, b) +pub fn vaddl_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t { + unsafe { + let a: int8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); + let b: int8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); + let a: int16x8_t = simd_cast(a); + let b: int16x8_t = simd_cast(b); + simd_add(a, b) + } } /// Signed Add Long (vector, high half). @@ -3043,12 +3057,14 @@ pub unsafe fn vaddl_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vaddl_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t { - let a: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); - let b: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); - let a: int32x4_t = simd_cast(a); - let b: int32x4_t = simd_cast(b); - simd_add(a, b) +pub fn vaddl_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t { + unsafe { + let a: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); + let b: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); + let a: int32x4_t = simd_cast(a); + let b: int32x4_t = simd_cast(b); + simd_add(a, b) + } } /// Signed Add Long (vector, high half). @@ -3068,12 +3084,14 @@ pub unsafe fn vaddl_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vaddl_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t { - let a: int32x2_t = simd_shuffle!(a, a, [2, 3]); - let b: int32x2_t = simd_shuffle!(b, b, [2, 3]); - let a: int64x2_t = simd_cast(a); - let b: int64x2_t = simd_cast(b); - simd_add(a, b) +pub fn vaddl_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t { + unsafe { + let a: int32x2_t = simd_shuffle!(a, a, [2, 3]); + let b: int32x2_t = simd_shuffle!(b, b, [2, 3]); + let a: int64x2_t = simd_cast(a); + let b: int64x2_t = simd_cast(b); + simd_add(a, b) + } } /// Unsigned Add Long (vector, high half). @@ -3093,12 +3111,14 @@ pub unsafe fn vaddl_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vaddl_high_u8(a: uint8x16_t, b: uint8x16_t) -> uint16x8_t { - let a: uint8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); - let b: uint8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); - let a: uint16x8_t = simd_cast(a); - let b: uint16x8_t = simd_cast(b); - simd_add(a, b) +pub fn vaddl_high_u8(a: uint8x16_t, b: uint8x16_t) -> uint16x8_t { + unsafe { + let a: uint8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); + let b: uint8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); + let a: uint16x8_t = simd_cast(a); + let b: uint16x8_t = simd_cast(b); + simd_add(a, b) + } } /// Unsigned Add Long (vector, high half). @@ -3118,12 +3138,14 @@ pub unsafe fn vaddl_high_u8(a: uint8x16_t, b: uint8x16_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vaddl_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t { - let a: uint16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); - let b: uint16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); - let a: uint32x4_t = simd_cast(a); - let b: uint32x4_t = simd_cast(b); - simd_add(a, b) +pub fn vaddl_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t { + unsafe { + let a: uint16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); + let b: uint16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); + let a: uint32x4_t = simd_cast(a); + let b: uint32x4_t = simd_cast(b); + simd_add(a, b) + } } /// Unsigned Add Long (vector, high half). @@ -3143,12 +3165,14 @@ pub unsafe fn vaddl_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vaddl_high_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t { - let a: uint32x2_t = simd_shuffle!(a, a, [2, 3]); - let b: uint32x2_t = simd_shuffle!(b, b, [2, 3]); - let a: uint64x2_t = simd_cast(a); - let b: uint64x2_t = simd_cast(b); - simd_add(a, b) +pub fn vaddl_high_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t { + unsafe { + let a: uint32x2_t = simd_shuffle!(a, a, [2, 3]); + let b: uint32x2_t = simd_shuffle!(b, b, [2, 3]); + let a: uint64x2_t = simd_cast(a); + let b: uint64x2_t = simd_cast(b); + simd_add(a, b) + } } /// Signed Add Wide. @@ -3168,9 +3192,11 @@ pub unsafe fn vaddl_high_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vaddw_s8(a: int16x8_t, b: int8x8_t) -> int16x8_t { - let b: int16x8_t = simd_cast(b); - simd_add(a, b) +pub fn vaddw_s8(a: int16x8_t, b: int8x8_t) -> int16x8_t { + unsafe { + let b: int16x8_t = simd_cast(b); + simd_add(a, b) + } } /// Signed Add Wide. @@ -3190,9 +3216,11 @@ pub unsafe fn vaddw_s8(a: int16x8_t, b: int8x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vaddw_s16(a: int32x4_t, b: int16x4_t) -> int32x4_t { - let b: int32x4_t = simd_cast(b); - simd_add(a, b) +pub fn vaddw_s16(a: int32x4_t, b: int16x4_t) -> int32x4_t { + unsafe { + let b: int32x4_t = simd_cast(b); + simd_add(a, b) + } } /// Signed Add Wide. @@ -3212,9 +3240,11 @@ pub unsafe fn vaddw_s16(a: int32x4_t, b: int16x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vaddw_s32(a: int64x2_t, b: int32x2_t) -> int64x2_t { - let b: int64x2_t = simd_cast(b); - simd_add(a, b) +pub fn vaddw_s32(a: int64x2_t, b: int32x2_t) -> int64x2_t { + unsafe { + let b: int64x2_t = simd_cast(b); + simd_add(a, b) + } } /// Unsigned Add Wide. @@ -3234,9 +3264,11 @@ pub unsafe fn vaddw_s32(a: int64x2_t, b: int32x2_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vaddw_u8(a: uint16x8_t, b: uint8x8_t) -> uint16x8_t { - let b: uint16x8_t = simd_cast(b); - simd_add(a, b) +pub fn vaddw_u8(a: uint16x8_t, b: uint8x8_t) -> uint16x8_t { + unsafe { + let b: uint16x8_t = simd_cast(b); + simd_add(a, b) + } } /// Unsigned Add Wide. @@ -3256,9 +3288,11 @@ pub unsafe fn vaddw_u8(a: uint16x8_t, b: uint8x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vaddw_u16(a: uint32x4_t, b: uint16x4_t) -> uint32x4_t { - let b: uint32x4_t = simd_cast(b); - simd_add(a, b) +pub fn vaddw_u16(a: uint32x4_t, b: uint16x4_t) -> uint32x4_t { + unsafe { + let b: uint32x4_t = simd_cast(b); + simd_add(a, b) + } } /// Unsigned Add Wide. @@ -3278,9 +3312,11 @@ pub unsafe fn vaddw_u16(a: uint32x4_t, b: uint16x4_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vaddw_u32(a: uint64x2_t, b: uint32x2_t) -> uint64x2_t { - let b: uint64x2_t = simd_cast(b); - simd_add(a, b) +pub fn vaddw_u32(a: uint64x2_t, b: uint32x2_t) -> uint64x2_t { + unsafe { + let b: uint64x2_t = simd_cast(b); + simd_add(a, b) + } } /// Signed Add Wide (high half). @@ -3300,10 +3336,12 @@ pub unsafe fn vaddw_u32(a: uint64x2_t, b: uint32x2_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vaddw_high_s8(a: int16x8_t, b: int8x16_t) -> int16x8_t { - let b: int8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); - let b: int16x8_t = simd_cast(b); - simd_add(a, b) +pub fn vaddw_high_s8(a: int16x8_t, b: int8x16_t) -> int16x8_t { + unsafe { + let b: int8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); + let b: int16x8_t = simd_cast(b); + simd_add(a, b) + } } /// Signed Add Wide (high half). @@ -3323,10 +3361,12 @@ pub unsafe fn vaddw_high_s8(a: int16x8_t, b: int8x16_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vaddw_high_s16(a: int32x4_t, b: int16x8_t) -> int32x4_t { - let b: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); - let b: int32x4_t = simd_cast(b); - simd_add(a, b) +pub fn vaddw_high_s16(a: int32x4_t, b: int16x8_t) -> int32x4_t { + unsafe { + let b: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); + let b: int32x4_t = simd_cast(b); + simd_add(a, b) + } } /// Signed Add Wide (high half). @@ -3346,10 +3386,12 @@ pub unsafe fn vaddw_high_s16(a: int32x4_t, b: int16x8_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vaddw_high_s32(a: int64x2_t, b: int32x4_t) -> int64x2_t { - let b: int32x2_t = simd_shuffle!(b, b, [2, 3]); - let b: int64x2_t = simd_cast(b); - simd_add(a, b) +pub fn vaddw_high_s32(a: int64x2_t, b: int32x4_t) -> int64x2_t { + unsafe { + let b: int32x2_t = simd_shuffle!(b, b, [2, 3]); + let b: int64x2_t = simd_cast(b); + simd_add(a, b) + } } /// Unsigned Add Wide (high half). @@ -3369,10 +3411,12 @@ pub unsafe fn vaddw_high_s32(a: int64x2_t, b: int32x4_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vaddw_high_u8(a: uint16x8_t, b: uint8x16_t) -> uint16x8_t { - let b: uint8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); - let b: uint16x8_t = simd_cast(b); - simd_add(a, b) +pub fn vaddw_high_u8(a: uint16x8_t, b: uint8x16_t) -> uint16x8_t { + unsafe { + let b: uint8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); + let b: uint16x8_t = simd_cast(b); + simd_add(a, b) + } } /// Unsigned Add Wide (high half). @@ -3392,10 +3436,12 @@ pub unsafe fn vaddw_high_u8(a: uint16x8_t, b: uint8x16_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vaddw_high_u16(a: uint32x4_t, b: uint16x8_t) -> uint32x4_t { - let b: uint16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); - let b: uint32x4_t = simd_cast(b); - simd_add(a, b) +pub fn vaddw_high_u16(a: uint32x4_t, b: uint16x8_t) -> uint32x4_t { + unsafe { + let b: uint16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); + let b: uint32x4_t = simd_cast(b); + simd_add(a, b) + } } /// Unsigned Add Wide (high half). @@ -3415,10 +3461,12 @@ pub unsafe fn vaddw_high_u16(a: uint32x4_t, b: uint16x8_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vaddw_high_u32(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t { - let b: uint32x2_t = simd_shuffle!(b, b, [2, 3]); - let b: uint64x2_t = simd_cast(b); - simd_add(a, b) +pub fn vaddw_high_u32(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t { + unsafe { + let b: uint32x2_t = simd_shuffle!(b, b, [2, 3]); + let b: uint64x2_t = simd_cast(b); + simd_add(a, b) + } } /// Add returning High Narrow. @@ -3438,8 +3486,8 @@ pub unsafe fn vaddw_high_u32(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vaddhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t { - simd_cast(simd_shr(simd_add(a, b), int16x8_t::splat(8))) +pub fn vaddhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t { + unsafe { simd_cast(simd_shr(simd_add(a, b), int16x8_t::splat(8))) } } /// Add returning High Narrow. @@ -3459,8 +3507,8 @@ pub unsafe fn vaddhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vaddhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t { - simd_cast(simd_shr(simd_add(a, b), int32x4_t::splat(16))) +pub fn vaddhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t { + unsafe { simd_cast(simd_shr(simd_add(a, b), int32x4_t::splat(16))) } } /// Add returning High Narrow. @@ -3480,8 +3528,8 @@ pub unsafe fn vaddhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vaddhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t { - simd_cast(simd_shr(simd_add(a, b), int64x2_t::splat(32))) +pub fn vaddhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t { + unsafe { simd_cast(simd_shr(simd_add(a, b), int64x2_t::splat(32))) } } /// Add returning High Narrow. @@ -3501,8 +3549,8 @@ pub unsafe fn vaddhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vaddhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t { - simd_cast(simd_shr(simd_add(a, b), uint16x8_t::splat(8))) +pub fn vaddhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t { + unsafe { simd_cast(simd_shr(simd_add(a, b), uint16x8_t::splat(8))) } } /// Add returning High Narrow. @@ -3522,8 +3570,8 @@ pub unsafe fn vaddhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vaddhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t { - simd_cast(simd_shr(simd_add(a, b), uint32x4_t::splat(16))) +pub fn vaddhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t { + unsafe { simd_cast(simd_shr(simd_add(a, b), uint32x4_t::splat(16))) } } /// Add returning High Narrow. @@ -3543,8 +3591,8 @@ pub unsafe fn vaddhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vaddhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t { - simd_cast(simd_shr(simd_add(a, b), uint64x2_t::splat(32))) +pub fn vaddhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t { + unsafe { simd_cast(simd_shr(simd_add(a, b), uint64x2_t::splat(32))) } } /// Add returning High Narrow (high half). @@ -3564,9 +3612,11 @@ pub unsafe fn vaddhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vaddhn_high_s16(r: int8x8_t, a: int16x8_t, b: int16x8_t) -> int8x16_t { - let x = simd_cast(simd_shr(simd_add(a, b), int16x8_t::splat(8))); - simd_shuffle!(r, x, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) +pub fn vaddhn_high_s16(r: int8x8_t, a: int16x8_t, b: int16x8_t) -> int8x16_t { + unsafe { + let x = simd_cast(simd_shr(simd_add(a, b), int16x8_t::splat(8))); + simd_shuffle!(r, x, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) + } } /// Add returning High Narrow (high half). @@ -3586,9 +3636,11 @@ pub unsafe fn vaddhn_high_s16(r: int8x8_t, a: int16x8_t, b: int16x8_t) -> int8x1 target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vaddhn_high_s32(r: int16x4_t, a: int32x4_t, b: int32x4_t) -> int16x8_t { - let x = simd_cast(simd_shr(simd_add(a, b), int32x4_t::splat(16))); - simd_shuffle!(r, x, [0, 1, 2, 3, 4, 5, 6, 7]) +pub fn vaddhn_high_s32(r: int16x4_t, a: int32x4_t, b: int32x4_t) -> int16x8_t { + unsafe { + let x = simd_cast(simd_shr(simd_add(a, b), int32x4_t::splat(16))); + simd_shuffle!(r, x, [0, 1, 2, 3, 4, 5, 6, 7]) + } } /// Add returning High Narrow (high half). @@ -3608,9 +3660,11 @@ pub unsafe fn vaddhn_high_s32(r: int16x4_t, a: int32x4_t, b: int32x4_t) -> int16 target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vaddhn_high_s64(r: int32x2_t, a: int64x2_t, b: int64x2_t) -> int32x4_t { - let x = simd_cast(simd_shr(simd_add(a, b), int64x2_t::splat(32))); - simd_shuffle!(r, x, [0, 1, 2, 3]) +pub fn vaddhn_high_s64(r: int32x2_t, a: int64x2_t, b: int64x2_t) -> int32x4_t { + unsafe { + let x = simd_cast(simd_shr(simd_add(a, b), int64x2_t::splat(32))); + simd_shuffle!(r, x, [0, 1, 2, 3]) + } } /// Add returning High Narrow (high half). @@ -3630,9 +3684,11 @@ pub unsafe fn vaddhn_high_s64(r: int32x2_t, a: int64x2_t, b: int64x2_t) -> int32 target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vaddhn_high_u16(r: uint8x8_t, a: uint16x8_t, b: uint16x8_t) -> uint8x16_t { - let x = simd_cast(simd_shr(simd_add(a, b), uint16x8_t::splat(8))); - simd_shuffle!(r, x, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) +pub fn vaddhn_high_u16(r: uint8x8_t, a: uint16x8_t, b: uint16x8_t) -> uint8x16_t { + unsafe { + let x = simd_cast(simd_shr(simd_add(a, b), uint16x8_t::splat(8))); + simd_shuffle!(r, x, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) + } } /// Add returning High Narrow (high half). @@ -3652,9 +3708,11 @@ pub unsafe fn vaddhn_high_u16(r: uint8x8_t, a: uint16x8_t, b: uint16x8_t) -> uin target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vaddhn_high_u32(r: uint16x4_t, a: uint32x4_t, b: uint32x4_t) -> uint16x8_t { - let x = simd_cast(simd_shr(simd_add(a, b), uint32x4_t::splat(16))); - simd_shuffle!(r, x, [0, 1, 2, 3, 4, 5, 6, 7]) +pub fn vaddhn_high_u32(r: uint16x4_t, a: uint32x4_t, b: uint32x4_t) -> uint16x8_t { + unsafe { + let x = simd_cast(simd_shr(simd_add(a, b), uint32x4_t::splat(16))); + simd_shuffle!(r, x, [0, 1, 2, 3, 4, 5, 6, 7]) + } } /// Add returning High Narrow (high half). @@ -3674,9 +3732,11 @@ pub unsafe fn vaddhn_high_u32(r: uint16x4_t, a: uint32x4_t, b: uint32x4_t) -> ui target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vaddhn_high_u64(r: uint32x2_t, a: uint64x2_t, b: uint64x2_t) -> uint32x4_t { - let x = simd_cast(simd_shr(simd_add(a, b), uint64x2_t::splat(32))); - simd_shuffle!(r, x, [0, 1, 2, 3]) +pub fn vaddhn_high_u64(r: uint32x2_t, a: uint64x2_t, b: uint64x2_t) -> uint32x4_t { + unsafe { + let x = simd_cast(simd_shr(simd_add(a, b), uint64x2_t::splat(32))); + simd_shuffle!(r, x, [0, 1, 2, 3]) + } } /// Vector narrow integer. @@ -3696,8 +3756,8 @@ pub unsafe fn vaddhn_high_u64(r: uint32x2_t, a: uint64x2_t, b: uint64x2_t) -> ui target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmovn_s16(a: int16x8_t) -> int8x8_t { - simd_cast(a) +pub fn vmovn_s16(a: int16x8_t) -> int8x8_t { + unsafe { simd_cast(a) } } /// Vector narrow integer. @@ -3717,8 +3777,8 @@ pub unsafe fn vmovn_s16(a: int16x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmovn_s32(a: int32x4_t) -> int16x4_t { - simd_cast(a) +pub fn vmovn_s32(a: int32x4_t) -> int16x4_t { + unsafe { simd_cast(a) } } /// Vector narrow integer. @@ -3738,8 +3798,8 @@ pub unsafe fn vmovn_s32(a: int32x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmovn_s64(a: int64x2_t) -> int32x2_t { - simd_cast(a) +pub fn vmovn_s64(a: int64x2_t) -> int32x2_t { + unsafe { simd_cast(a) } } /// Vector narrow integer. @@ -3759,8 +3819,8 @@ pub unsafe fn vmovn_s64(a: int64x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmovn_u16(a: uint16x8_t) -> uint8x8_t { - simd_cast(a) +pub fn vmovn_u16(a: uint16x8_t) -> uint8x8_t { + unsafe { simd_cast(a) } } /// Vector narrow integer. @@ -3780,8 +3840,8 @@ pub unsafe fn vmovn_u16(a: uint16x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmovn_u32(a: uint32x4_t) -> uint16x4_t { - simd_cast(a) +pub fn vmovn_u32(a: uint32x4_t) -> uint16x4_t { + unsafe { simd_cast(a) } } /// Vector narrow integer. @@ -3801,8 +3861,8 @@ pub unsafe fn vmovn_u32(a: uint32x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmovn_u64(a: uint64x2_t) -> uint32x2_t { - simd_cast(a) +pub fn vmovn_u64(a: uint64x2_t) -> uint32x2_t { + unsafe { simd_cast(a) } } /// Vector long move. @@ -3822,8 +3882,8 @@ pub unsafe fn vmovn_u64(a: uint64x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmovl_s8(a: int8x8_t) -> int16x8_t { - simd_cast(a) +pub fn vmovl_s8(a: int8x8_t) -> int16x8_t { + unsafe { simd_cast(a) } } /// Vector long move. @@ -3843,8 +3903,8 @@ pub unsafe fn vmovl_s8(a: int8x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmovl_s16(a: int16x4_t) -> int32x4_t { - simd_cast(a) +pub fn vmovl_s16(a: int16x4_t) -> int32x4_t { + unsafe { simd_cast(a) } } /// Vector long move. @@ -3864,8 +3924,8 @@ pub unsafe fn vmovl_s16(a: int16x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmovl_s32(a: int32x2_t) -> int64x2_t { - simd_cast(a) +pub fn vmovl_s32(a: int32x2_t) -> int64x2_t { + unsafe { simd_cast(a) } } /// Vector long move. @@ -3885,8 +3945,8 @@ pub unsafe fn vmovl_s32(a: int32x2_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmovl_u8(a: uint8x8_t) -> uint16x8_t { - simd_cast(a) +pub fn vmovl_u8(a: uint8x8_t) -> uint16x8_t { + unsafe { simd_cast(a) } } /// Vector long move. @@ -3906,8 +3966,8 @@ pub unsafe fn vmovl_u8(a: uint8x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmovl_u16(a: uint16x4_t) -> uint32x4_t { - simd_cast(a) +pub fn vmovl_u16(a: uint16x4_t) -> uint32x4_t { + unsafe { simd_cast(a) } } /// Vector long move. @@ -3927,8 +3987,8 @@ pub unsafe fn vmovl_u16(a: uint16x4_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmovl_u32(a: uint32x2_t) -> uint64x2_t { - simd_cast(a) +pub fn vmovl_u32(a: uint32x2_t) -> uint64x2_t { + unsafe { simd_cast(a) } } /// Vector bitwise not. @@ -3948,9 +4008,9 @@ pub unsafe fn vmovl_u32(a: uint32x2_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmvn_s8(a: int8x8_t) -> int8x8_t { +pub fn vmvn_s8(a: int8x8_t) -> int8x8_t { let b = int8x8_t::splat(-1); - simd_xor(a, b) + unsafe { simd_xor(a, b) } } /// Vector bitwise not. @@ -3970,9 +4030,9 @@ pub unsafe fn vmvn_s8(a: int8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmvnq_s8(a: int8x16_t) -> int8x16_t { +pub fn vmvnq_s8(a: int8x16_t) -> int8x16_t { let b = int8x16_t::splat(-1); - simd_xor(a, b) + unsafe { simd_xor(a, b) } } /// Vector bitwise not. @@ -3992,9 +4052,9 @@ pub unsafe fn vmvnq_s8(a: int8x16_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmvn_s16(a: int16x4_t) -> int16x4_t { +pub fn vmvn_s16(a: int16x4_t) -> int16x4_t { let b = int16x4_t::splat(-1); - simd_xor(a, b) + unsafe { simd_xor(a, b) } } /// Vector bitwise not. @@ -4014,9 +4074,9 @@ pub unsafe fn vmvn_s16(a: int16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmvnq_s16(a: int16x8_t) -> int16x8_t { +pub fn vmvnq_s16(a: int16x8_t) -> int16x8_t { let b = int16x8_t::splat(-1); - simd_xor(a, b) + unsafe { simd_xor(a, b) } } /// Vector bitwise not. @@ -4036,9 +4096,9 @@ pub unsafe fn vmvnq_s16(a: int16x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmvn_s32(a: int32x2_t) -> int32x2_t { +pub fn vmvn_s32(a: int32x2_t) -> int32x2_t { let b = int32x2_t::splat(-1); - simd_xor(a, b) + unsafe { simd_xor(a, b) } } /// Vector bitwise not. @@ -4058,9 +4118,9 @@ pub unsafe fn vmvn_s32(a: int32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmvnq_s32(a: int32x4_t) -> int32x4_t { +pub fn vmvnq_s32(a: int32x4_t) -> int32x4_t { let b = int32x4_t::splat(-1); - simd_xor(a, b) + unsafe { simd_xor(a, b) } } /// Vector bitwise not. @@ -4080,9 +4140,9 @@ pub unsafe fn vmvnq_s32(a: int32x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmvn_u8(a: uint8x8_t) -> uint8x8_t { +pub fn vmvn_u8(a: uint8x8_t) -> uint8x8_t { let b = uint8x8_t::splat(255); - simd_xor(a, b) + unsafe { simd_xor(a, b) } } /// Vector bitwise not. @@ -4102,9 +4162,9 @@ pub unsafe fn vmvn_u8(a: uint8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmvnq_u8(a: uint8x16_t) -> uint8x16_t { +pub fn vmvnq_u8(a: uint8x16_t) -> uint8x16_t { let b = uint8x16_t::splat(255); - simd_xor(a, b) + unsafe { simd_xor(a, b) } } /// Vector bitwise not. @@ -4124,9 +4184,9 @@ pub unsafe fn vmvnq_u8(a: uint8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmvn_u16(a: uint16x4_t) -> uint16x4_t { +pub fn vmvn_u16(a: uint16x4_t) -> uint16x4_t { let b = uint16x4_t::splat(65_535); - simd_xor(a, b) + unsafe { simd_xor(a, b) } } /// Vector bitwise not. @@ -4146,9 +4206,9 @@ pub unsafe fn vmvn_u16(a: uint16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmvnq_u16(a: uint16x8_t) -> uint16x8_t { +pub fn vmvnq_u16(a: uint16x8_t) -> uint16x8_t { let b = uint16x8_t::splat(65_535); - simd_xor(a, b) + unsafe { simd_xor(a, b) } } /// Vector bitwise not. @@ -4168,9 +4228,9 @@ pub unsafe fn vmvnq_u16(a: uint16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmvn_u32(a: uint32x2_t) -> uint32x2_t { +pub fn vmvn_u32(a: uint32x2_t) -> uint32x2_t { let b = uint32x2_t::splat(4_294_967_295); - simd_xor(a, b) + unsafe { simd_xor(a, b) } } /// Vector bitwise not. @@ -4190,9 +4250,9 @@ pub unsafe fn vmvn_u32(a: uint32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmvnq_u32(a: uint32x4_t) -> uint32x4_t { +pub fn vmvnq_u32(a: uint32x4_t) -> uint32x4_t { let b = uint32x4_t::splat(4_294_967_295); - simd_xor(a, b) + unsafe { simd_xor(a, b) } } /// Vector bitwise not. @@ -4212,9 +4272,9 @@ pub unsafe fn vmvnq_u32(a: uint32x4_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmvn_p8(a: poly8x8_t) -> poly8x8_t { +pub fn vmvn_p8(a: poly8x8_t) -> poly8x8_t { let b = poly8x8_t::splat(255); - simd_xor(a, b) + unsafe { simd_xor(a, b) } } /// Vector bitwise not. @@ -4234,9 +4294,9 @@ pub unsafe fn vmvn_p8(a: poly8x8_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmvnq_p8(a: poly8x16_t) -> poly8x16_t { +pub fn vmvnq_p8(a: poly8x16_t) -> poly8x16_t { let b = poly8x16_t::splat(255); - simd_xor(a, b) + unsafe { simd_xor(a, b) } } /// Vector bitwise bit clear @@ -4256,9 +4316,9 @@ pub unsafe fn vmvnq_p8(a: poly8x16_t) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vbic_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { +pub fn vbic_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { let c = int8x8_t::splat(-1); - simd_and(simd_xor(b, c), a) + unsafe { simd_and(simd_xor(b, c), a) } } /// Vector bitwise bit clear @@ -4278,9 +4338,9 @@ pub unsafe fn vbic_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vbicq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { +pub fn vbicq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { let c = int8x16_t::splat(-1); - simd_and(simd_xor(b, c), a) + unsafe { simd_and(simd_xor(b, c), a) } } /// Vector bitwise bit clear @@ -4300,9 +4360,9 @@ pub unsafe fn vbicq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vbic_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { +pub fn vbic_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { let c = int16x4_t::splat(-1); - simd_and(simd_xor(b, c), a) + unsafe { simd_and(simd_xor(b, c), a) } } /// Vector bitwise bit clear @@ -4322,9 +4382,9 @@ pub unsafe fn vbic_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vbicq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { +pub fn vbicq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { let c = int16x8_t::splat(-1); - simd_and(simd_xor(b, c), a) + unsafe { simd_and(simd_xor(b, c), a) } } /// Vector bitwise bit clear @@ -4344,9 +4404,9 @@ pub unsafe fn vbicq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vbic_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { +pub fn vbic_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { let c = int32x2_t::splat(-1); - simd_and(simd_xor(b, c), a) + unsafe { simd_and(simd_xor(b, c), a) } } /// Vector bitwise bit clear @@ -4366,9 +4426,9 @@ pub unsafe fn vbic_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vbicq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { +pub fn vbicq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { let c = int32x4_t::splat(-1); - simd_and(simd_xor(b, c), a) + unsafe { simd_and(simd_xor(b, c), a) } } /// Vector bitwise bit clear @@ -4388,9 +4448,9 @@ pub unsafe fn vbicq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vbic_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { +pub fn vbic_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { let c = int64x1_t::splat(-1); - simd_and(simd_xor(b, c), a) + unsafe { simd_and(simd_xor(b, c), a) } } /// Vector bitwise bit clear @@ -4410,9 +4470,9 @@ pub unsafe fn vbic_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vbicq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { +pub fn vbicq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { let c = int64x2_t::splat(-1); - simd_and(simd_xor(b, c), a) + unsafe { simd_and(simd_xor(b, c), a) } } /// Vector bitwise bit clear @@ -4432,9 +4492,9 @@ pub unsafe fn vbicq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vbic_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { +pub fn vbic_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { let c = int8x8_t::splat(-1); - simd_and(simd_xor(b, transmute(c)), a) + unsafe { simd_and(simd_xor(b, transmute(c)), a) } } /// Vector bitwise bit clear @@ -4454,9 +4514,9 @@ pub unsafe fn vbic_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vbicq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { +pub fn vbicq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { let c = int8x16_t::splat(-1); - simd_and(simd_xor(b, transmute(c)), a) + unsafe { simd_and(simd_xor(b, transmute(c)), a) } } /// Vector bitwise bit clear @@ -4476,9 +4536,9 @@ pub unsafe fn vbicq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vbic_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { +pub fn vbic_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { let c = int16x4_t::splat(-1); - simd_and(simd_xor(b, transmute(c)), a) + unsafe { simd_and(simd_xor(b, transmute(c)), a) } } /// Vector bitwise bit clear @@ -4498,9 +4558,9 @@ pub unsafe fn vbic_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vbicq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { +pub fn vbicq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { let c = int16x8_t::splat(-1); - simd_and(simd_xor(b, transmute(c)), a) + unsafe { simd_and(simd_xor(b, transmute(c)), a) } } /// Vector bitwise bit clear @@ -4520,9 +4580,9 @@ pub unsafe fn vbicq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vbic_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { +pub fn vbic_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { let c = int32x2_t::splat(-1); - simd_and(simd_xor(b, transmute(c)), a) + unsafe { simd_and(simd_xor(b, transmute(c)), a) } } /// Vector bitwise bit clear @@ -4542,9 +4602,9 @@ pub unsafe fn vbic_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vbicq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { +pub fn vbicq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { let c = int32x4_t::splat(-1); - simd_and(simd_xor(b, transmute(c)), a) + unsafe { simd_and(simd_xor(b, transmute(c)), a) } } /// Vector bitwise bit clear @@ -4564,9 +4624,9 @@ pub unsafe fn vbicq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vbic_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { +pub fn vbic_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { let c = int64x1_t::splat(-1); - simd_and(simd_xor(b, transmute(c)), a) + unsafe { simd_and(simd_xor(b, transmute(c)), a) } } /// Vector bitwise bit clear @@ -4586,9 +4646,9 @@ pub unsafe fn vbic_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vbicq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { +pub fn vbicq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { let c = int64x2_t::splat(-1); - simd_and(simd_xor(b, transmute(c)), a) + unsafe { simd_and(simd_xor(b, transmute(c)), a) } } /// Bitwise Select instructions. This instruction sets each bit in the destination SIMD&FP register @@ -4612,12 +4672,14 @@ pub unsafe fn vbicq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vbsl_s8(a: uint8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t { +pub fn vbsl_s8(a: uint8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t { let not = int8x8_t::splat(-1); - transmute(simd_or( - simd_and(a, transmute(b)), - simd_and(simd_xor(a, transmute(not)), transmute(c)), - )) + unsafe { + transmute(simd_or( + simd_and(a, transmute(b)), + simd_and(simd_xor(a, transmute(not)), transmute(c)), + )) + } } /// Bitwise Select. @@ -4637,12 +4699,14 @@ pub unsafe fn vbsl_s8(a: uint8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vbsl_s16(a: uint16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t { +pub fn vbsl_s16(a: uint16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t { let not = int16x4_t::splat(-1); - transmute(simd_or( - simd_and(a, transmute(b)), - simd_and(simd_xor(a, transmute(not)), transmute(c)), - )) + unsafe { + transmute(simd_or( + simd_and(a, transmute(b)), + simd_and(simd_xor(a, transmute(not)), transmute(c)), + )) + } } /// Bitwise Select. @@ -4662,12 +4726,14 @@ pub unsafe fn vbsl_s16(a: uint16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vbsl_s32(a: uint32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t { +pub fn vbsl_s32(a: uint32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t { let not = int32x2_t::splat(-1); - transmute(simd_or( - simd_and(a, transmute(b)), - simd_and(simd_xor(a, transmute(not)), transmute(c)), - )) + unsafe { + transmute(simd_or( + simd_and(a, transmute(b)), + simd_and(simd_xor(a, transmute(not)), transmute(c)), + )) + } } /// Bitwise Select. @@ -4687,12 +4753,14 @@ pub unsafe fn vbsl_s32(a: uint32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vbsl_s64(a: uint64x1_t, b: int64x1_t, c: int64x1_t) -> int64x1_t { +pub fn vbsl_s64(a: uint64x1_t, b: int64x1_t, c: int64x1_t) -> int64x1_t { let not = int64x1_t::splat(-1); - transmute(simd_or( - simd_and(a, transmute(b)), - simd_and(simd_xor(a, transmute(not)), transmute(c)), - )) + unsafe { + transmute(simd_or( + simd_and(a, transmute(b)), + simd_and(simd_xor(a, transmute(not)), transmute(c)), + )) + } } /// Bitwise Select. @@ -4712,9 +4780,9 @@ pub unsafe fn vbsl_s64(a: uint64x1_t, b: int64x1_t, c: int64x1_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vbsl_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t { +pub fn vbsl_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t { let not = int8x8_t::splat(-1); - simd_or(simd_and(a, b), simd_and(simd_xor(a, transmute(not)), c)) + unsafe { simd_or(simd_and(a, b), simd_and(simd_xor(a, transmute(not)), c)) } } /// Bitwise Select. @@ -4734,9 +4802,9 @@ pub unsafe fn vbsl_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vbsl_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_t { +pub fn vbsl_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_t { let not = int16x4_t::splat(-1); - simd_or(simd_and(a, b), simd_and(simd_xor(a, transmute(not)), c)) + unsafe { simd_or(simd_and(a, b), simd_and(simd_xor(a, transmute(not)), c)) } } /// Bitwise Select. @@ -4756,9 +4824,9 @@ pub unsafe fn vbsl_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_ target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vbsl_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_t { +pub fn vbsl_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_t { let not = int32x2_t::splat(-1); - simd_or(simd_and(a, b), simd_and(simd_xor(a, transmute(not)), c)) + unsafe { simd_or(simd_and(a, b), simd_and(simd_xor(a, transmute(not)), c)) } } /// Bitwise Select. @@ -4778,9 +4846,9 @@ pub unsafe fn vbsl_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_ target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vbsl_u64(a: uint64x1_t, b: uint64x1_t, c: uint64x1_t) -> uint64x1_t { +pub fn vbsl_u64(a: uint64x1_t, b: uint64x1_t, c: uint64x1_t) -> uint64x1_t { let not = int64x1_t::splat(-1); - simd_or(simd_and(a, b), simd_and(simd_xor(a, transmute(not)), c)) + unsafe { simd_or(simd_and(a, b), simd_and(simd_xor(a, transmute(not)), c)) } } /// Bitwise Select. @@ -4793,12 +4861,14 @@ pub unsafe fn vbsl_u64(a: uint64x1_t, b: uint64x1_t, c: uint64x1_t) -> uint64x1_ assert_instr(bsl) )] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vbsl_f16(a: uint16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t { +pub fn vbsl_f16(a: uint16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t { let not = int16x4_t::splat(-1); - transmute(simd_or( - simd_and(a, transmute(b)), - simd_and(simd_xor(a, transmute(not)), transmute(c)), - )) + unsafe { + transmute(simd_or( + simd_and(a, transmute(b)), + simd_and(simd_xor(a, transmute(not)), transmute(c)), + )) + } } /// Bitwise Select. @@ -4818,12 +4888,14 @@ pub unsafe fn vbsl_f16(a: uint16x4_t, b: float16x4_t, c: float16x4_t) -> float16 target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vbsl_f32(a: uint32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t { +pub fn vbsl_f32(a: uint32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t { let not = int32x2_t::splat(-1); - transmute(simd_or( - simd_and(a, transmute(b)), - simd_and(simd_xor(a, transmute(not)), transmute(c)), - )) + unsafe { + transmute(simd_or( + simd_and(a, transmute(b)), + simd_and(simd_xor(a, transmute(not)), transmute(c)), + )) + } } /// Bitwise Select. @@ -4843,12 +4915,14 @@ pub unsafe fn vbsl_f32(a: uint32x2_t, b: float32x2_t, c: float32x2_t) -> float32 target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vbsl_p8(a: uint8x8_t, b: poly8x8_t, c: poly8x8_t) -> poly8x8_t { +pub fn vbsl_p8(a: uint8x8_t, b: poly8x8_t, c: poly8x8_t) -> poly8x8_t { let not = int8x8_t::splat(-1); - transmute(simd_or( - simd_and(a, transmute(b)), - simd_and(simd_xor(a, transmute(not)), transmute(c)), - )) + unsafe { + transmute(simd_or( + simd_and(a, transmute(b)), + simd_and(simd_xor(a, transmute(not)), transmute(c)), + )) + } } /// Bitwise Select. @@ -4868,12 +4942,14 @@ pub unsafe fn vbsl_p8(a: uint8x8_t, b: poly8x8_t, c: poly8x8_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vbsl_p16(a: uint16x4_t, b: poly16x4_t, c: poly16x4_t) -> poly16x4_t { +pub fn vbsl_p16(a: uint16x4_t, b: poly16x4_t, c: poly16x4_t) -> poly16x4_t { let not = int16x4_t::splat(-1); - transmute(simd_or( - simd_and(a, transmute(b)), - simd_and(simd_xor(a, transmute(not)), transmute(c)), - )) + unsafe { + transmute(simd_or( + simd_and(a, transmute(b)), + simd_and(simd_xor(a, transmute(not)), transmute(c)), + )) + } } /// Bitwise Select. (128-bit) @@ -4893,12 +4969,14 @@ pub unsafe fn vbsl_p16(a: uint16x4_t, b: poly16x4_t, c: poly16x4_t) -> poly16x4_ target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vbslq_s8(a: uint8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t { +pub fn vbslq_s8(a: uint8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t { let not = int8x16_t::splat(-1); - transmute(simd_or( - simd_and(a, transmute(b)), - simd_and(simd_xor(a, transmute(not)), transmute(c)), - )) + unsafe { + transmute(simd_or( + simd_and(a, transmute(b)), + simd_and(simd_xor(a, transmute(not)), transmute(c)), + )) + } } /// Bitwise Select. (128-bit) @@ -4918,12 +4996,14 @@ pub unsafe fn vbslq_s8(a: uint8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vbslq_s16(a: uint16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t { +pub fn vbslq_s16(a: uint16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t { let not = int16x8_t::splat(-1); - transmute(simd_or( - simd_and(a, transmute(b)), - simd_and(simd_xor(a, transmute(not)), transmute(c)), - )) + unsafe { + transmute(simd_or( + simd_and(a, transmute(b)), + simd_and(simd_xor(a, transmute(not)), transmute(c)), + )) + } } /// Bitwise Select. (128-bit) @@ -4943,12 +5023,14 @@ pub unsafe fn vbslq_s16(a: uint16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vbslq_s32(a: uint32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t { +pub fn vbslq_s32(a: uint32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t { let not = int32x4_t::splat(-1); - transmute(simd_or( - simd_and(a, transmute(b)), - simd_and(simd_xor(a, transmute(not)), transmute(c)), - )) + unsafe { + transmute(simd_or( + simd_and(a, transmute(b)), + simd_and(simd_xor(a, transmute(not)), transmute(c)), + )) + } } /// Bitwise Select. (128-bit) @@ -4968,12 +5050,14 @@ pub unsafe fn vbslq_s32(a: uint32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vbslq_s64(a: uint64x2_t, b: int64x2_t, c: int64x2_t) -> int64x2_t { +pub fn vbslq_s64(a: uint64x2_t, b: int64x2_t, c: int64x2_t) -> int64x2_t { let not = int64x2_t::splat(-1); - transmute(simd_or( - simd_and(a, transmute(b)), - simd_and(simd_xor(a, transmute(not)), transmute(c)), - )) + unsafe { + transmute(simd_or( + simd_and(a, transmute(b)), + simd_and(simd_xor(a, transmute(not)), transmute(c)), + )) + } } /// Bitwise Select. (128-bit) @@ -4993,9 +5077,9 @@ pub unsafe fn vbslq_s64(a: uint64x2_t, b: int64x2_t, c: int64x2_t) -> int64x2_t target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vbslq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t { +pub fn vbslq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t { let not = int8x16_t::splat(-1); - simd_or(simd_and(a, b), simd_and(simd_xor(a, transmute(not)), c)) + unsafe { simd_or(simd_and(a, b), simd_and(simd_xor(a, transmute(not)), c)) } } /// Bitwise Select. (128-bit) @@ -5015,9 +5099,9 @@ pub unsafe fn vbslq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_ target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vbslq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t { +pub fn vbslq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t { let not = int16x8_t::splat(-1); - simd_or(simd_and(a, b), simd_and(simd_xor(a, transmute(not)), c)) + unsafe { simd_or(simd_and(a, b), simd_and(simd_xor(a, transmute(not)), c)) } } /// Bitwise Select. (128-bit) @@ -5037,9 +5121,9 @@ pub unsafe fn vbslq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8 target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vbslq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t { +pub fn vbslq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t { let not = int32x4_t::splat(-1); - simd_or(simd_and(a, b), simd_and(simd_xor(a, transmute(not)), c)) + unsafe { simd_or(simd_and(a, b), simd_and(simd_xor(a, transmute(not)), c)) } } /// Bitwise Select. (128-bit) @@ -5059,9 +5143,9 @@ pub unsafe fn vbslq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4 target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vbslq_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t { +pub fn vbslq_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t { let not = int64x2_t::splat(-1); - simd_or(simd_and(a, b), simd_and(simd_xor(a, transmute(not)), c)) + unsafe { simd_or(simd_and(a, b), simd_and(simd_xor(a, transmute(not)), c)) } } /// Bitwise Select. (128-bit) @@ -5081,12 +5165,14 @@ pub unsafe fn vbslq_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2 target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vbslq_p8(a: uint8x16_t, b: poly8x16_t, c: poly8x16_t) -> poly8x16_t { +pub fn vbslq_p8(a: uint8x16_t, b: poly8x16_t, c: poly8x16_t) -> poly8x16_t { let not = int8x16_t::splat(-1); - transmute(simd_or( - simd_and(a, transmute(b)), - simd_and(simd_xor(a, transmute(not)), transmute(c)), - )) + unsafe { + transmute(simd_or( + simd_and(a, transmute(b)), + simd_and(simd_xor(a, transmute(not)), transmute(c)), + )) + } } /// Bitwise Select. (128-bit) @@ -5106,12 +5192,14 @@ pub unsafe fn vbslq_p8(a: uint8x16_t, b: poly8x16_t, c: poly8x16_t) -> poly8x16_ target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vbslq_p16(a: uint16x8_t, b: poly16x8_t, c: poly16x8_t) -> poly16x8_t { +pub fn vbslq_p16(a: uint16x8_t, b: poly16x8_t, c: poly16x8_t) -> poly16x8_t { let not = int16x8_t::splat(-1); - transmute(simd_or( - simd_and(a, transmute(b)), - simd_and(simd_xor(a, transmute(not)), transmute(c)), - )) + unsafe { + transmute(simd_or( + simd_and(a, transmute(b)), + simd_and(simd_xor(a, transmute(not)), transmute(c)), + )) + } } /// Bitwise Select. @@ -5124,12 +5212,14 @@ pub unsafe fn vbslq_p16(a: uint16x8_t, b: poly16x8_t, c: poly16x8_t) -> poly16x8 assert_instr(bsl) )] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] -pub unsafe fn vbslq_f16(a: uint16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t { +pub fn vbslq_f16(a: uint16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t { let not = int16x8_t::splat(-1); - transmute(simd_or( - simd_and(a, transmute(b)), - simd_and(simd_xor(a, transmute(not)), transmute(c)), - )) + unsafe { + transmute(simd_or( + simd_and(a, transmute(b)), + simd_and(simd_xor(a, transmute(not)), transmute(c)), + )) + } } /// Bitwise Select. (128-bit) @@ -5149,12 +5239,14 @@ pub unsafe fn vbslq_f16(a: uint16x8_t, b: float16x8_t, c: float16x8_t) -> float1 target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vbslq_f32(a: uint32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t { +pub fn vbslq_f32(a: uint32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t { let not = int32x4_t::splat(-1); - transmute(simd_or( - simd_and(a, transmute(b)), - simd_and(simd_xor(a, transmute(not)), transmute(c)), - )) + unsafe { + transmute(simd_or( + simd_and(a, transmute(b)), + simd_and(simd_xor(a, transmute(not)), transmute(c)), + )) + } } /// Vector bitwise inclusive OR NOT @@ -5174,9 +5266,9 @@ pub unsafe fn vbslq_f32(a: uint32x4_t, b: float32x4_t, c: float32x4_t) -> float3 target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vorn_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { +pub fn vorn_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { let c = int8x8_t::splat(-1); - simd_or(simd_xor(b, c), a) + unsafe { simd_or(simd_xor(b, c), a) } } /// Vector bitwise inclusive OR NOT @@ -5196,9 +5288,9 @@ pub unsafe fn vorn_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vornq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { +pub fn vornq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { let c = int8x16_t::splat(-1); - simd_or(simd_xor(b, c), a) + unsafe { simd_or(simd_xor(b, c), a) } } /// Vector bitwise inclusive OR NOT @@ -5218,9 +5310,9 @@ pub unsafe fn vornq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vorn_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { +pub fn vorn_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { let c = int16x4_t::splat(-1); - simd_or(simd_xor(b, c), a) + unsafe { simd_or(simd_xor(b, c), a) } } /// Vector bitwise inclusive OR NOT @@ -5240,9 +5332,9 @@ pub unsafe fn vorn_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vornq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { +pub fn vornq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { let c = int16x8_t::splat(-1); - simd_or(simd_xor(b, c), a) + unsafe { simd_or(simd_xor(b, c), a) } } /// Vector bitwise inclusive OR NOT @@ -5262,9 +5354,9 @@ pub unsafe fn vornq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vorn_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { +pub fn vorn_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { let c = int32x2_t::splat(-1); - simd_or(simd_xor(b, c), a) + unsafe { simd_or(simd_xor(b, c), a) } } /// Vector bitwise inclusive OR NOT @@ -5284,9 +5376,9 @@ pub unsafe fn vorn_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vornq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { +pub fn vornq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { let c = int32x4_t::splat(-1); - simd_or(simd_xor(b, c), a) + unsafe { simd_or(simd_xor(b, c), a) } } /// Vector bitwise inclusive OR NOT @@ -5306,9 +5398,9 @@ pub unsafe fn vornq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vorn_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { +pub fn vorn_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { let c = int64x1_t::splat(-1); - simd_or(simd_xor(b, c), a) + unsafe { simd_or(simd_xor(b, c), a) } } /// Vector bitwise inclusive OR NOT @@ -5328,9 +5420,9 @@ pub unsafe fn vorn_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vornq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { +pub fn vornq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { let c = int64x2_t::splat(-1); - simd_or(simd_xor(b, c), a) + unsafe { simd_or(simd_xor(b, c), a) } } /// Vector bitwise inclusive OR NOT @@ -5350,9 +5442,9 @@ pub unsafe fn vornq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vorn_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { +pub fn vorn_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { let c = int8x8_t::splat(-1); - simd_or(simd_xor(b, transmute(c)), a) + unsafe { simd_or(simd_xor(b, transmute(c)), a) } } /// Vector bitwise inclusive OR NOT @@ -5372,9 +5464,9 @@ pub unsafe fn vorn_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vornq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { +pub fn vornq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { let c = int8x16_t::splat(-1); - simd_or(simd_xor(b, transmute(c)), a) + unsafe { simd_or(simd_xor(b, transmute(c)), a) } } /// Vector bitwise inclusive OR NOT @@ -5394,9 +5486,9 @@ pub unsafe fn vornq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vorn_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { +pub fn vorn_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { let c = int16x4_t::splat(-1); - simd_or(simd_xor(b, transmute(c)), a) + unsafe { simd_or(simd_xor(b, transmute(c)), a) } } /// Vector bitwise inclusive OR NOT @@ -5416,9 +5508,9 @@ pub unsafe fn vorn_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vornq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { +pub fn vornq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { let c = int16x8_t::splat(-1); - simd_or(simd_xor(b, transmute(c)), a) + unsafe { simd_or(simd_xor(b, transmute(c)), a) } } /// Vector bitwise inclusive OR NOT @@ -5438,9 +5530,9 @@ pub unsafe fn vornq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vorn_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { +pub fn vorn_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { let c = int32x2_t::splat(-1); - simd_or(simd_xor(b, transmute(c)), a) + unsafe { simd_or(simd_xor(b, transmute(c)), a) } } /// Vector bitwise inclusive OR NOT @@ -5460,9 +5552,9 @@ pub unsafe fn vorn_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vornq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { +pub fn vornq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { let c = int32x4_t::splat(-1); - simd_or(simd_xor(b, transmute(c)), a) + unsafe { simd_or(simd_xor(b, transmute(c)), a) } } /// Vector bitwise inclusive OR NOT @@ -5482,9 +5574,9 @@ pub unsafe fn vornq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vorn_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { +pub fn vorn_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { let c = int64x1_t::splat(-1); - simd_or(simd_xor(b, transmute(c)), a) + unsafe { simd_or(simd_xor(b, transmute(c)), a) } } /// Vector bitwise inclusive OR NOT @@ -5504,9 +5596,9 @@ pub unsafe fn vorn_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vornq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { +pub fn vornq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { let c = int64x2_t::splat(-1); - simd_or(simd_xor(b, transmute(c)), a) + unsafe { simd_or(simd_xor(b, transmute(c)), a) } } /// Move vector element to general-purpose register @@ -5523,9 +5615,9 @@ pub unsafe fn vornq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vgetq_lane_u64(v: uint64x2_t) -> u64 { +pub fn vgetq_lane_u64(v: uint64x2_t) -> u64 { static_assert_uimm_bits!(IMM5, 1); - simd_extract!(v, IMM5 as u32) + unsafe { simd_extract!(v, IMM5 as u32) } } /// Move vector element to general-purpose register @@ -5542,9 +5634,9 @@ pub unsafe fn vgetq_lane_u64(v: uint64x2_t) -> u64 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vget_lane_u64(v: uint64x1_t) -> u64 { +pub fn vget_lane_u64(v: uint64x1_t) -> u64 { static_assert!(IMM5 == 0); - simd_extract!(v, 0) + unsafe { simd_extract!(v, 0) } } /// Move vector element to general-purpose register @@ -5561,9 +5653,9 @@ pub unsafe fn vget_lane_u64(v: uint64x1_t) -> u64 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vget_lane_u16(v: uint16x4_t) -> u16 { +pub fn vget_lane_u16(v: uint16x4_t) -> u16 { static_assert_uimm_bits!(IMM5, 2); - simd_extract!(v, IMM5 as u32) + unsafe { simd_extract!(v, IMM5 as u32) } } /// Move vector element to general-purpose register @@ -5580,9 +5672,9 @@ pub unsafe fn vget_lane_u16(v: uint16x4_t) -> u16 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vget_lane_s16(v: int16x4_t) -> i16 { +pub fn vget_lane_s16(v: int16x4_t) -> i16 { static_assert_uimm_bits!(IMM5, 2); - simd_extract!(v, IMM5 as u32) + unsafe { simd_extract!(v, IMM5 as u32) } } /// Move vector element to general-purpose register @@ -5599,9 +5691,9 @@ pub unsafe fn vget_lane_s16(v: int16x4_t) -> i16 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vget_lane_p16(v: poly16x4_t) -> p16 { +pub fn vget_lane_p16(v: poly16x4_t) -> p16 { static_assert_uimm_bits!(IMM5, 2); - simd_extract!(v, IMM5 as u32) + unsafe { simd_extract!(v, IMM5 as u32) } } /// Move vector element to general-purpose register @@ -5618,9 +5710,9 @@ pub unsafe fn vget_lane_p16(v: poly16x4_t) -> p16 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vget_lane_u32(v: uint32x2_t) -> u32 { +pub fn vget_lane_u32(v: uint32x2_t) -> u32 { static_assert_uimm_bits!(IMM5, 1); - simd_extract!(v, IMM5 as u32) + unsafe { simd_extract!(v, IMM5 as u32) } } /// Move vector element to general-purpose register @@ -5637,9 +5729,9 @@ pub unsafe fn vget_lane_u32(v: uint32x2_t) -> u32 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vget_lane_s32(v: int32x2_t) -> i32 { +pub fn vget_lane_s32(v: int32x2_t) -> i32 { static_assert_uimm_bits!(IMM5, 1); - simd_extract!(v, IMM5 as u32) + unsafe { simd_extract!(v, IMM5 as u32) } } /// Duplicate vector element to vector or scalar @@ -5656,9 +5748,9 @@ pub unsafe fn vget_lane_s32(v: int32x2_t) -> i32 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vget_lane_f32(v: float32x2_t) -> f32 { +pub fn vget_lane_f32(v: float32x2_t) -> f32 { static_assert_uimm_bits!(IMM5, 1); - simd_extract!(v, IMM5 as u32) + unsafe { simd_extract!(v, IMM5 as u32) } } /// Duplicate vector element to vector or scalar @@ -5675,9 +5767,9 @@ pub unsafe fn vget_lane_f32(v: float32x2_t) -> f32 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vgetq_lane_f32(v: float32x4_t) -> f32 { +pub fn vgetq_lane_f32(v: float32x4_t) -> f32 { static_assert_uimm_bits!(IMM5, 2); - simd_extract!(v, IMM5 as u32) + unsafe { simd_extract!(v, IMM5 as u32) } } /// Move vector element to general-purpose register @@ -5694,9 +5786,9 @@ pub unsafe fn vgetq_lane_f32(v: float32x4_t) -> f32 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vget_lane_p64(v: poly64x1_t) -> p64 { +pub fn vget_lane_p64(v: poly64x1_t) -> p64 { static_assert!(IMM5 == 0); - simd_extract!(v, IMM5 as u32) + unsafe { simd_extract!(v, IMM5 as u32) } } /// Move vector element to general-purpose register @@ -5713,9 +5805,9 @@ pub unsafe fn vget_lane_p64(v: poly64x1_t) -> p64 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vgetq_lane_p64(v: poly64x2_t) -> p64 { +pub fn vgetq_lane_p64(v: poly64x2_t) -> p64 { static_assert_uimm_bits!(IMM5, 1); - simd_extract!(v, IMM5 as u32) + unsafe { simd_extract!(v, IMM5 as u32) } } /// Move vector element to general-purpose register @@ -5732,9 +5824,9 @@ pub unsafe fn vgetq_lane_p64(v: poly64x2_t) -> p64 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vget_lane_s64(v: int64x1_t) -> i64 { +pub fn vget_lane_s64(v: int64x1_t) -> i64 { static_assert!(IMM5 == 0); - simd_extract!(v, IMM5 as u32) + unsafe { simd_extract!(v, IMM5 as u32) } } /// Move vector element to general-purpose register @@ -5751,9 +5843,9 @@ pub unsafe fn vget_lane_s64(v: int64x1_t) -> i64 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vgetq_lane_s64(v: int64x2_t) -> i64 { +pub fn vgetq_lane_s64(v: int64x2_t) -> i64 { static_assert_uimm_bits!(IMM5, 1); - simd_extract!(v, IMM5 as u32) + unsafe { simd_extract!(v, IMM5 as u32) } } /// Move vector element to general-purpose register @@ -5770,9 +5862,9 @@ pub unsafe fn vgetq_lane_s64(v: int64x2_t) -> i64 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vgetq_lane_u16(v: uint16x8_t) -> u16 { +pub fn vgetq_lane_u16(v: uint16x8_t) -> u16 { static_assert_uimm_bits!(IMM5, 3); - simd_extract!(v, IMM5 as u32) + unsafe { simd_extract!(v, IMM5 as u32) } } /// Move vector element to general-purpose register @@ -5789,9 +5881,9 @@ pub unsafe fn vgetq_lane_u16(v: uint16x8_t) -> u16 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vgetq_lane_u32(v: uint32x4_t) -> u32 { +pub fn vgetq_lane_u32(v: uint32x4_t) -> u32 { static_assert_uimm_bits!(IMM5, 2); - simd_extract!(v, IMM5 as u32) + unsafe { simd_extract!(v, IMM5 as u32) } } /// Move vector element to general-purpose register @@ -5808,9 +5900,9 @@ pub unsafe fn vgetq_lane_u32(v: uint32x4_t) -> u32 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vgetq_lane_s16(v: int16x8_t) -> i16 { +pub fn vgetq_lane_s16(v: int16x8_t) -> i16 { static_assert_uimm_bits!(IMM5, 3); - simd_extract!(v, IMM5 as u32) + unsafe { simd_extract!(v, IMM5 as u32) } } /// Move vector element to general-purpose register @@ -5827,9 +5919,9 @@ pub unsafe fn vgetq_lane_s16(v: int16x8_t) -> i16 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vgetq_lane_p16(v: poly16x8_t) -> p16 { +pub fn vgetq_lane_p16(v: poly16x8_t) -> p16 { static_assert_uimm_bits!(IMM5, 3); - simd_extract!(v, IMM5 as u32) + unsafe { simd_extract!(v, IMM5 as u32) } } /// Move vector element to general-purpose register @@ -5846,9 +5938,9 @@ pub unsafe fn vgetq_lane_p16(v: poly16x8_t) -> p16 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vgetq_lane_s32(v: int32x4_t) -> i32 { +pub fn vgetq_lane_s32(v: int32x4_t) -> i32 { static_assert_uimm_bits!(IMM5, 2); - simd_extract!(v, IMM5 as u32) + unsafe { simd_extract!(v, IMM5 as u32) } } /// Move vector element to general-purpose register @@ -5865,9 +5957,9 @@ pub unsafe fn vgetq_lane_s32(v: int32x4_t) -> i32 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vget_lane_u8(v: uint8x8_t) -> u8 { +pub fn vget_lane_u8(v: uint8x8_t) -> u8 { static_assert_uimm_bits!(IMM5, 3); - simd_extract!(v, IMM5 as u32) + unsafe { simd_extract!(v, IMM5 as u32) } } /// Move vector element to general-purpose register @@ -5884,9 +5976,9 @@ pub unsafe fn vget_lane_u8(v: uint8x8_t) -> u8 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vget_lane_s8(v: int8x8_t) -> i8 { +pub fn vget_lane_s8(v: int8x8_t) -> i8 { static_assert_uimm_bits!(IMM5, 3); - simd_extract!(v, IMM5 as u32) + unsafe { simd_extract!(v, IMM5 as u32) } } /// Move vector element to general-purpose register @@ -5903,9 +5995,9 @@ pub unsafe fn vget_lane_s8(v: int8x8_t) -> i8 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vget_lane_p8(v: poly8x8_t) -> p8 { +pub fn vget_lane_p8(v: poly8x8_t) -> p8 { static_assert_uimm_bits!(IMM5, 3); - simd_extract!(v, IMM5 as u32) + unsafe { simd_extract!(v, IMM5 as u32) } } /// Move vector element to general-purpose register @@ -5922,9 +6014,9 @@ pub unsafe fn vget_lane_p8(v: poly8x8_t) -> p8 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vgetq_lane_u8(v: uint8x16_t) -> u8 { +pub fn vgetq_lane_u8(v: uint8x16_t) -> u8 { static_assert_uimm_bits!(IMM5, 4); - simd_extract!(v, IMM5 as u32) + unsafe { simd_extract!(v, IMM5 as u32) } } /// Move vector element to general-purpose register @@ -5941,9 +6033,9 @@ pub unsafe fn vgetq_lane_u8(v: uint8x16_t) -> u8 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vgetq_lane_s8(v: int8x16_t) -> i8 { +pub fn vgetq_lane_s8(v: int8x16_t) -> i8 { static_assert_uimm_bits!(IMM5, 4); - simd_extract!(v, IMM5 as u32) + unsafe { simd_extract!(v, IMM5 as u32) } } /// Move vector element to general-purpose register @@ -5960,9 +6052,9 @@ pub unsafe fn vgetq_lane_s8(v: int8x16_t) -> i8 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vgetq_lane_p8(v: poly8x16_t) -> p8 { +pub fn vgetq_lane_p8(v: poly8x16_t) -> p8 { static_assert_uimm_bits!(IMM5, 4); - simd_extract!(v, IMM5 as u32) + unsafe { simd_extract!(v, IMM5 as u32) } } /// Duplicate vector element to vector or scalar @@ -5982,8 +6074,8 @@ pub unsafe fn vgetq_lane_p8(v: poly8x16_t) -> p8 { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vget_high_s8(a: int8x16_t) -> int8x8_t { - simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]) +pub fn vget_high_s8(a: int8x16_t) -> int8x8_t { + unsafe { simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]) } } /// Duplicate vector element to vector or scalar @@ -6003,8 +6095,8 @@ pub unsafe fn vget_high_s8(a: int8x16_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vget_high_s16(a: int16x8_t) -> int16x4_t { - simd_shuffle!(a, a, [4, 5, 6, 7]) +pub fn vget_high_s16(a: int16x8_t) -> int16x4_t { + unsafe { simd_shuffle!(a, a, [4, 5, 6, 7]) } } /// Duplicate vector element to vector or scalar @@ -6024,8 +6116,8 @@ pub unsafe fn vget_high_s16(a: int16x8_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vget_high_s32(a: int32x4_t) -> int32x2_t { - simd_shuffle!(a, a, [2, 3]) +pub fn vget_high_s32(a: int32x4_t) -> int32x2_t { + unsafe { simd_shuffle!(a, a, [2, 3]) } } /// Duplicate vector element to vector or scalar @@ -6045,8 +6137,8 @@ pub unsafe fn vget_high_s32(a: int32x4_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vget_high_s64(a: int64x2_t) -> int64x1_t { - int64x1_t([simd_extract!(a, 1)]) +pub fn vget_high_s64(a: int64x2_t) -> int64x1_t { + unsafe { int64x1_t([simd_extract!(a, 1)]) } } /// Duplicate vector element to vector or scalar @@ -6066,8 +6158,8 @@ pub unsafe fn vget_high_s64(a: int64x2_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vget_high_u8(a: uint8x16_t) -> uint8x8_t { - simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]) +pub fn vget_high_u8(a: uint8x16_t) -> uint8x8_t { + unsafe { simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]) } } /// Duplicate vector element to vector or scalar @@ -6087,8 +6179,8 @@ pub unsafe fn vget_high_u8(a: uint8x16_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vget_high_u16(a: uint16x8_t) -> uint16x4_t { - simd_shuffle!(a, a, [4, 5, 6, 7]) +pub fn vget_high_u16(a: uint16x8_t) -> uint16x4_t { + unsafe { simd_shuffle!(a, a, [4, 5, 6, 7]) } } /// Duplicate vector element to vector or scalar @@ -6108,8 +6200,8 @@ pub unsafe fn vget_high_u16(a: uint16x8_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vget_high_u32(a: uint32x4_t) -> uint32x2_t { - simd_shuffle!(a, a, [2, 3]) +pub fn vget_high_u32(a: uint32x4_t) -> uint32x2_t { + unsafe { simd_shuffle!(a, a, [2, 3]) } } /// Duplicate vector element to vector or scalar @@ -6129,8 +6221,8 @@ pub unsafe fn vget_high_u32(a: uint32x4_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vget_high_u64(a: uint64x2_t) -> uint64x1_t { - uint64x1_t([simd_extract!(a, 1)]) +pub fn vget_high_u64(a: uint64x2_t) -> uint64x1_t { + unsafe { uint64x1_t([simd_extract!(a, 1)]) } } /// Duplicate vector element to vector or scalar @@ -6150,8 +6242,8 @@ pub unsafe fn vget_high_u64(a: uint64x2_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vget_high_p8(a: poly8x16_t) -> poly8x8_t { - simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]) +pub fn vget_high_p8(a: poly8x16_t) -> poly8x8_t { + unsafe { simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]) } } /// Duplicate vector element to vector or scalar @@ -6171,8 +6263,8 @@ pub unsafe fn vget_high_p8(a: poly8x16_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vget_high_p16(a: poly16x8_t) -> poly16x4_t { - simd_shuffle!(a, a, [4, 5, 6, 7]) +pub fn vget_high_p16(a: poly16x8_t) -> poly16x4_t { + unsafe { simd_shuffle!(a, a, [4, 5, 6, 7]) } } /// Duplicate vector element to vector or scalar @@ -6192,8 +6284,8 @@ pub unsafe fn vget_high_p16(a: poly16x8_t) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vget_high_f32(a: float32x4_t) -> float32x2_t { - simd_shuffle!(a, a, [2, 3]) +pub fn vget_high_f32(a: float32x4_t) -> float32x2_t { + unsafe { simd_shuffle!(a, a, [2, 3]) } } /// Duplicate vector element to vector or scalar @@ -6209,8 +6301,8 @@ pub unsafe fn vget_high_f32(a: float32x4_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vget_low_s8(a: int8x16_t) -> int8x8_t { - simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]) +pub fn vget_low_s8(a: int8x16_t) -> int8x8_t { + unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]) } } /// Duplicate vector element to vector or scalar @@ -6226,8 +6318,8 @@ pub unsafe fn vget_low_s8(a: int8x16_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vget_low_s16(a: int16x8_t) -> int16x4_t { - simd_shuffle!(a, a, [0, 1, 2, 3]) +pub fn vget_low_s16(a: int16x8_t) -> int16x4_t { + unsafe { simd_shuffle!(a, a, [0, 1, 2, 3]) } } /// Duplicate vector element to vector or scalar @@ -6243,8 +6335,8 @@ pub unsafe fn vget_low_s16(a: int16x8_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vget_low_s32(a: int32x4_t) -> int32x2_t { - simd_shuffle!(a, a, [0, 1]) +pub fn vget_low_s32(a: int32x4_t) -> int32x2_t { + unsafe { simd_shuffle!(a, a, [0, 1]) } } /// Duplicate vector element to vector or scalar @@ -6260,8 +6352,8 @@ pub unsafe fn vget_low_s32(a: int32x4_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vget_low_s64(a: int64x2_t) -> int64x1_t { - int64x1_t([simd_extract!(a, 0)]) +pub fn vget_low_s64(a: int64x2_t) -> int64x1_t { + unsafe { int64x1_t([simd_extract!(a, 0)]) } } /// Duplicate vector element to vector or scalar @@ -6277,8 +6369,8 @@ pub unsafe fn vget_low_s64(a: int64x2_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vget_low_u8(a: uint8x16_t) -> uint8x8_t { - simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]) +pub fn vget_low_u8(a: uint8x16_t) -> uint8x8_t { + unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]) } } /// Duplicate vector element to vector or scalar @@ -6294,8 +6386,8 @@ pub unsafe fn vget_low_u8(a: uint8x16_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vget_low_u16(a: uint16x8_t) -> uint16x4_t { - simd_shuffle!(a, a, [0, 1, 2, 3]) +pub fn vget_low_u16(a: uint16x8_t) -> uint16x4_t { + unsafe { simd_shuffle!(a, a, [0, 1, 2, 3]) } } /// Duplicate vector element to vector or scalar @@ -6311,8 +6403,8 @@ pub unsafe fn vget_low_u16(a: uint16x8_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vget_low_u32(a: uint32x4_t) -> uint32x2_t { - simd_shuffle!(a, a, [0, 1]) +pub fn vget_low_u32(a: uint32x4_t) -> uint32x2_t { + unsafe { simd_shuffle!(a, a, [0, 1]) } } /// Duplicate vector element to vector or scalar @@ -6328,8 +6420,8 @@ pub unsafe fn vget_low_u32(a: uint32x4_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vget_low_u64(a: uint64x2_t) -> uint64x1_t { - uint64x1_t([simd_extract!(a, 0)]) +pub fn vget_low_u64(a: uint64x2_t) -> uint64x1_t { + unsafe { uint64x1_t([simd_extract!(a, 0)]) } } /// Duplicate vector element to vector or scalar @@ -6345,8 +6437,8 @@ pub unsafe fn vget_low_u64(a: uint64x2_t) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vget_low_p8(a: poly8x16_t) -> poly8x8_t { - simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]) +pub fn vget_low_p8(a: poly8x16_t) -> poly8x8_t { + unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]) } } /// Duplicate vector element to vector or scalar @@ -6362,8 +6454,8 @@ pub unsafe fn vget_low_p8(a: poly8x16_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vget_low_p16(a: poly16x8_t) -> poly16x4_t { - simd_shuffle!(a, a, [0, 1, 2, 3]) +pub fn vget_low_p16(a: poly16x8_t) -> poly16x4_t { + unsafe { simd_shuffle!(a, a, [0, 1, 2, 3]) } } /// Duplicate vector element to vector or scalar @@ -6379,8 +6471,8 @@ pub unsafe fn vget_low_p16(a: poly16x8_t) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vget_low_f32(a: float32x4_t) -> float32x2_t { - simd_shuffle!(a, a, [0, 1]) +pub fn vget_low_f32(a: float32x4_t) -> float32x2_t { + unsafe { simd_shuffle!(a, a, [0, 1]) } } /// Duplicate vector element to vector or scalar @@ -6400,7 +6492,7 @@ pub unsafe fn vget_low_f32(a: float32x4_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vdupq_n_s8(value: i8) -> int8x16_t { +pub fn vdupq_n_s8(value: i8) -> int8x16_t { int8x16_t::splat(value) } @@ -6421,7 +6513,7 @@ pub unsafe fn vdupq_n_s8(value: i8) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vdupq_n_s16(value: i16) -> int16x8_t { +pub fn vdupq_n_s16(value: i16) -> int16x8_t { int16x8_t::splat(value) } @@ -6442,7 +6534,7 @@ pub unsafe fn vdupq_n_s16(value: i16) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vdupq_n_s32(value: i32) -> int32x4_t { +pub fn vdupq_n_s32(value: i32) -> int32x4_t { int32x4_t::splat(value) } @@ -6463,7 +6555,7 @@ pub unsafe fn vdupq_n_s32(value: i32) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vdupq_n_s64(value: i64) -> int64x2_t { +pub fn vdupq_n_s64(value: i64) -> int64x2_t { int64x2_t::splat(value) } @@ -6484,7 +6576,7 @@ pub unsafe fn vdupq_n_s64(value: i64) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vdupq_n_u8(value: u8) -> uint8x16_t { +pub fn vdupq_n_u8(value: u8) -> uint8x16_t { uint8x16_t::splat(value) } @@ -6505,7 +6597,7 @@ pub unsafe fn vdupq_n_u8(value: u8) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vdupq_n_u16(value: u16) -> uint16x8_t { +pub fn vdupq_n_u16(value: u16) -> uint16x8_t { uint16x8_t::splat(value) } @@ -6526,7 +6618,7 @@ pub unsafe fn vdupq_n_u16(value: u16) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vdupq_n_u32(value: u32) -> uint32x4_t { +pub fn vdupq_n_u32(value: u32) -> uint32x4_t { uint32x4_t::splat(value) } @@ -6547,7 +6639,7 @@ pub unsafe fn vdupq_n_u32(value: u32) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vdupq_n_u64(value: u64) -> uint64x2_t { +pub fn vdupq_n_u64(value: u64) -> uint64x2_t { uint64x2_t::splat(value) } @@ -6568,7 +6660,7 @@ pub unsafe fn vdupq_n_u64(value: u64) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vdupq_n_p8(value: p8) -> poly8x16_t { +pub fn vdupq_n_p8(value: p8) -> poly8x16_t { poly8x16_t::splat(value) } @@ -6589,7 +6681,7 @@ pub unsafe fn vdupq_n_p8(value: p8) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vdupq_n_p16(value: p16) -> poly16x8_t { +pub fn vdupq_n_p16(value: p16) -> poly16x8_t { poly16x8_t::splat(value) } @@ -6610,7 +6702,7 @@ pub unsafe fn vdupq_n_p16(value: p16) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vdupq_n_f32(value: f32) -> float32x4_t { +pub fn vdupq_n_f32(value: f32) -> float32x4_t { float32x4_t::splat(value) } @@ -6630,7 +6722,7 @@ pub unsafe fn vdupq_n_f32(value: f32) -> float32x4_t { not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") )] -unsafe fn vdupq_n_f32_vfp4(value: f32) -> float32x4_t { +fn vdupq_n_f32_vfp4(value: f32) -> float32x4_t { float32x4_t::splat(value) } @@ -6651,7 +6743,7 @@ unsafe fn vdupq_n_f32_vfp4(value: f32) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vdup_n_s8(value: i8) -> int8x8_t { +pub fn vdup_n_s8(value: i8) -> int8x8_t { int8x8_t::splat(value) } @@ -6672,7 +6764,7 @@ pub unsafe fn vdup_n_s8(value: i8) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vdup_n_s16(value: i16) -> int16x4_t { +pub fn vdup_n_s16(value: i16) -> int16x4_t { int16x4_t::splat(value) } @@ -6693,7 +6785,7 @@ pub unsafe fn vdup_n_s16(value: i16) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vdup_n_s32(value: i32) -> int32x2_t { +pub fn vdup_n_s32(value: i32) -> int32x2_t { int32x2_t::splat(value) } @@ -6714,7 +6806,7 @@ pub unsafe fn vdup_n_s32(value: i32) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vdup_n_s64(value: i64) -> int64x1_t { +pub fn vdup_n_s64(value: i64) -> int64x1_t { int64x1_t::splat(value) } @@ -6735,7 +6827,7 @@ pub unsafe fn vdup_n_s64(value: i64) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vdup_n_u8(value: u8) -> uint8x8_t { +pub fn vdup_n_u8(value: u8) -> uint8x8_t { uint8x8_t::splat(value) } @@ -6756,7 +6848,7 @@ pub unsafe fn vdup_n_u8(value: u8) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vdup_n_u16(value: u16) -> uint16x4_t { +pub fn vdup_n_u16(value: u16) -> uint16x4_t { uint16x4_t::splat(value) } @@ -6777,7 +6869,7 @@ pub unsafe fn vdup_n_u16(value: u16) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vdup_n_u32(value: u32) -> uint32x2_t { +pub fn vdup_n_u32(value: u32) -> uint32x2_t { uint32x2_t::splat(value) } @@ -6798,7 +6890,7 @@ pub unsafe fn vdup_n_u32(value: u32) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vdup_n_u64(value: u64) -> uint64x1_t { +pub fn vdup_n_u64(value: u64) -> uint64x1_t { uint64x1_t::splat(value) } @@ -6819,7 +6911,7 @@ pub unsafe fn vdup_n_u64(value: u64) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vdup_n_p8(value: p8) -> poly8x8_t { +pub fn vdup_n_p8(value: p8) -> poly8x8_t { poly8x8_t::splat(value) } @@ -6840,7 +6932,7 @@ pub unsafe fn vdup_n_p8(value: p8) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vdup_n_p16(value: p16) -> poly16x4_t { +pub fn vdup_n_p16(value: p16) -> poly16x4_t { poly16x4_t::splat(value) } @@ -6861,7 +6953,7 @@ pub unsafe fn vdup_n_p16(value: p16) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vdup_n_f32(value: f32) -> float32x2_t { +pub fn vdup_n_f32(value: f32) -> float32x2_t { float32x2_t::splat(value) } @@ -6881,7 +6973,7 @@ pub unsafe fn vdup_n_f32(value: f32) -> float32x2_t { not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0") )] -unsafe fn vdup_n_f32_vfp4(value: f32) -> float32x2_t { +fn vdup_n_f32_vfp4(value: f32) -> float32x2_t { float32x2_t::splat(value) } @@ -6944,7 +7036,7 @@ pub unsafe fn vstrq_p128(a: *mut p128, b: p128) { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmov_n_s8(value: i8) -> int8x8_t { +pub fn vmov_n_s8(value: i8) -> int8x8_t { vdup_n_s8(value) } @@ -6965,7 +7057,7 @@ pub unsafe fn vmov_n_s8(value: i8) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmov_n_s16(value: i16) -> int16x4_t { +pub fn vmov_n_s16(value: i16) -> int16x4_t { vdup_n_s16(value) } @@ -6986,7 +7078,7 @@ pub unsafe fn vmov_n_s16(value: i16) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmov_n_s32(value: i32) -> int32x2_t { +pub fn vmov_n_s32(value: i32) -> int32x2_t { vdup_n_s32(value) } @@ -7007,7 +7099,7 @@ pub unsafe fn vmov_n_s32(value: i32) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmov_n_s64(value: i64) -> int64x1_t { +pub fn vmov_n_s64(value: i64) -> int64x1_t { vdup_n_s64(value) } @@ -7028,7 +7120,7 @@ pub unsafe fn vmov_n_s64(value: i64) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmov_n_u8(value: u8) -> uint8x8_t { +pub fn vmov_n_u8(value: u8) -> uint8x8_t { vdup_n_u8(value) } @@ -7049,7 +7141,7 @@ pub unsafe fn vmov_n_u8(value: u8) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmov_n_u16(value: u16) -> uint16x4_t { +pub fn vmov_n_u16(value: u16) -> uint16x4_t { vdup_n_u16(value) } @@ -7070,7 +7162,7 @@ pub unsafe fn vmov_n_u16(value: u16) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmov_n_u32(value: u32) -> uint32x2_t { +pub fn vmov_n_u32(value: u32) -> uint32x2_t { vdup_n_u32(value) } @@ -7091,7 +7183,7 @@ pub unsafe fn vmov_n_u32(value: u32) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmov_n_u64(value: u64) -> uint64x1_t { +pub fn vmov_n_u64(value: u64) -> uint64x1_t { vdup_n_u64(value) } @@ -7112,7 +7204,7 @@ pub unsafe fn vmov_n_u64(value: u64) -> uint64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmov_n_p8(value: p8) -> poly8x8_t { +pub fn vmov_n_p8(value: p8) -> poly8x8_t { vdup_n_p8(value) } @@ -7133,7 +7225,7 @@ pub unsafe fn vmov_n_p8(value: p8) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmov_n_p16(value: p16) -> poly16x4_t { +pub fn vmov_n_p16(value: p16) -> poly16x4_t { vdup_n_p16(value) } @@ -7154,7 +7246,7 @@ pub unsafe fn vmov_n_p16(value: p16) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmov_n_f32(value: f32) -> float32x2_t { +pub fn vmov_n_f32(value: f32) -> float32x2_t { vdup_n_f32(value) } @@ -7175,7 +7267,7 @@ pub unsafe fn vmov_n_f32(value: f32) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmovq_n_s8(value: i8) -> int8x16_t { +pub fn vmovq_n_s8(value: i8) -> int8x16_t { vdupq_n_s8(value) } @@ -7196,7 +7288,7 @@ pub unsafe fn vmovq_n_s8(value: i8) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmovq_n_s16(value: i16) -> int16x8_t { +pub fn vmovq_n_s16(value: i16) -> int16x8_t { vdupq_n_s16(value) } @@ -7217,7 +7309,7 @@ pub unsafe fn vmovq_n_s16(value: i16) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmovq_n_s32(value: i32) -> int32x4_t { +pub fn vmovq_n_s32(value: i32) -> int32x4_t { vdupq_n_s32(value) } @@ -7238,7 +7330,7 @@ pub unsafe fn vmovq_n_s32(value: i32) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmovq_n_s64(value: i64) -> int64x2_t { +pub fn vmovq_n_s64(value: i64) -> int64x2_t { vdupq_n_s64(value) } @@ -7259,7 +7351,7 @@ pub unsafe fn vmovq_n_s64(value: i64) -> int64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmovq_n_u8(value: u8) -> uint8x16_t { +pub fn vmovq_n_u8(value: u8) -> uint8x16_t { vdupq_n_u8(value) } @@ -7280,7 +7372,7 @@ pub unsafe fn vmovq_n_u8(value: u8) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmovq_n_u16(value: u16) -> uint16x8_t { +pub fn vmovq_n_u16(value: u16) -> uint16x8_t { vdupq_n_u16(value) } @@ -7301,7 +7393,7 @@ pub unsafe fn vmovq_n_u16(value: u16) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmovq_n_u32(value: u32) -> uint32x4_t { +pub fn vmovq_n_u32(value: u32) -> uint32x4_t { vdupq_n_u32(value) } @@ -7322,7 +7414,7 @@ pub unsafe fn vmovq_n_u32(value: u32) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmovq_n_u64(value: u64) -> uint64x2_t { +pub fn vmovq_n_u64(value: u64) -> uint64x2_t { vdupq_n_u64(value) } @@ -7343,7 +7435,7 @@ pub unsafe fn vmovq_n_u64(value: u64) -> uint64x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmovq_n_p8(value: p8) -> poly8x16_t { +pub fn vmovq_n_p8(value: p8) -> poly8x16_t { vdupq_n_p8(value) } @@ -7364,7 +7456,7 @@ pub unsafe fn vmovq_n_p8(value: p8) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmovq_n_p16(value: p16) -> poly16x8_t { +pub fn vmovq_n_p16(value: p16) -> poly16x8_t { vdupq_n_p16(value) } @@ -7385,7 +7477,7 @@ pub unsafe fn vmovq_n_p16(value: p16) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vmovq_n_f32(value: f32) -> float32x4_t { +pub fn vmovq_n_f32(value: f32) -> float32x4_t { vdupq_n_f32(value) } @@ -7407,7 +7499,7 @@ pub unsafe fn vmovq_n_f32(value: f32) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vext_s64(a: int64x1_t, _b: int64x1_t) -> int64x1_t { +pub fn vext_s64(a: int64x1_t, _b: int64x1_t) -> int64x1_t { static_assert!(N == 0); a } @@ -7430,7 +7522,7 @@ pub unsafe fn vext_s64(a: int64x1_t, _b: int64x1_t) -> int64x1_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vext_u64(a: uint64x1_t, _b: uint64x1_t) -> uint64x1_t { +pub fn vext_u64(a: uint64x1_t, _b: uint64x1_t) -> uint64x1_t { static_assert!(N == 0); a } @@ -7452,8 +7544,8 @@ pub unsafe fn vext_u64(a: uint64x1_t, _b: uint64x1_t) -> uint64x1_ target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrev16_s8(a: int8x8_t) -> int8x8_t { - simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6]) +pub fn vrev16_s8(a: int8x8_t) -> int8x8_t { + unsafe { simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6]) } } /// Reversing vector elements (swap endianness) @@ -7473,8 +7565,8 @@ pub unsafe fn vrev16_s8(a: int8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrev16q_s8(a: int8x16_t) -> int8x16_t { - simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14]) +pub fn vrev16q_s8(a: int8x16_t) -> int8x16_t { + unsafe { simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14]) } } /// Reversing vector elements (swap endianness) @@ -7494,8 +7586,8 @@ pub unsafe fn vrev16q_s8(a: int8x16_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrev16_u8(a: uint8x8_t) -> uint8x8_t { - simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6]) +pub fn vrev16_u8(a: uint8x8_t) -> uint8x8_t { + unsafe { simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6]) } } /// Reversing vector elements (swap endianness) @@ -7515,8 +7607,8 @@ pub unsafe fn vrev16_u8(a: uint8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrev16q_u8(a: uint8x16_t) -> uint8x16_t { - simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14]) +pub fn vrev16q_u8(a: uint8x16_t) -> uint8x16_t { + unsafe { simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14]) } } /// Reversing vector elements (swap endianness) @@ -7536,8 +7628,8 @@ pub unsafe fn vrev16q_u8(a: uint8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrev16_p8(a: poly8x8_t) -> poly8x8_t { - simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6]) +pub fn vrev16_p8(a: poly8x8_t) -> poly8x8_t { + unsafe { simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6]) } } /// Reversing vector elements (swap endianness) @@ -7557,8 +7649,8 @@ pub unsafe fn vrev16_p8(a: poly8x8_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrev16q_p8(a: poly8x16_t) -> poly8x16_t { - simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14]) +pub fn vrev16q_p8(a: poly8x16_t) -> poly8x16_t { + unsafe { simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14]) } } /// Reversing vector elements (swap endianness) @@ -7578,8 +7670,8 @@ pub unsafe fn vrev16q_p8(a: poly8x16_t) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrev32_s8(a: int8x8_t) -> int8x8_t { - simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]) +pub fn vrev32_s8(a: int8x8_t) -> int8x8_t { + unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]) } } /// Reversing vector elements (swap endianness) @@ -7599,8 +7691,8 @@ pub unsafe fn vrev32_s8(a: int8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrev32q_s8(a: int8x16_t) -> int8x16_t { - simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12]) +pub fn vrev32q_s8(a: int8x16_t) -> int8x16_t { + unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12]) } } /// Reversing vector elements (swap endianness) @@ -7620,8 +7712,8 @@ pub unsafe fn vrev32q_s8(a: int8x16_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrev32_u8(a: uint8x8_t) -> uint8x8_t { - simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]) +pub fn vrev32_u8(a: uint8x8_t) -> uint8x8_t { + unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]) } } /// Reversing vector elements (swap endianness) @@ -7641,8 +7733,8 @@ pub unsafe fn vrev32_u8(a: uint8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrev32q_u8(a: uint8x16_t) -> uint8x16_t { - simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12]) +pub fn vrev32q_u8(a: uint8x16_t) -> uint8x16_t { + unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12]) } } /// Reversing vector elements (swap endianness) @@ -7662,8 +7754,8 @@ pub unsafe fn vrev32q_u8(a: uint8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrev32_s16(a: int16x4_t) -> int16x4_t { - simd_shuffle!(a, a, [1, 0, 3, 2]) +pub fn vrev32_s16(a: int16x4_t) -> int16x4_t { + unsafe { simd_shuffle!(a, a, [1, 0, 3, 2]) } } /// Reversing vector elements (swap endianness) @@ -7683,8 +7775,8 @@ pub unsafe fn vrev32_s16(a: int16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrev32q_s16(a: int16x8_t) -> int16x8_t { - simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6]) +pub fn vrev32q_s16(a: int16x8_t) -> int16x8_t { + unsafe { simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6]) } } /// Reversing vector elements (swap endianness) @@ -7704,8 +7796,8 @@ pub unsafe fn vrev32q_s16(a: int16x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrev32_p16(a: poly16x4_t) -> poly16x4_t { - simd_shuffle!(a, a, [1, 0, 3, 2]) +pub fn vrev32_p16(a: poly16x4_t) -> poly16x4_t { + unsafe { simd_shuffle!(a, a, [1, 0, 3, 2]) } } /// Reversing vector elements (swap endianness) @@ -7725,8 +7817,8 @@ pub unsafe fn vrev32_p16(a: poly16x4_t) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrev32q_p16(a: poly16x8_t) -> poly16x8_t { - simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6]) +pub fn vrev32q_p16(a: poly16x8_t) -> poly16x8_t { + unsafe { simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6]) } } /// Reversing vector elements (swap endianness) @@ -7746,8 +7838,8 @@ pub unsafe fn vrev32q_p16(a: poly16x8_t) -> poly16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrev32_u16(a: uint16x4_t) -> uint16x4_t { - simd_shuffle!(a, a, [1, 0, 3, 2]) +pub fn vrev32_u16(a: uint16x4_t) -> uint16x4_t { + unsafe { simd_shuffle!(a, a, [1, 0, 3, 2]) } } /// Reversing vector elements (swap endianness) @@ -7767,8 +7859,8 @@ pub unsafe fn vrev32_u16(a: uint16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrev32q_u16(a: uint16x8_t) -> uint16x8_t { - simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6]) +pub fn vrev32q_u16(a: uint16x8_t) -> uint16x8_t { + unsafe { simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6]) } } /// Reversing vector elements (swap endianness) @@ -7788,8 +7880,8 @@ pub unsafe fn vrev32q_u16(a: uint16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrev32_p8(a: poly8x8_t) -> poly8x8_t { - simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]) +pub fn vrev32_p8(a: poly8x8_t) -> poly8x8_t { + unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]) } } /// Reversing vector elements (swap endianness) @@ -7809,8 +7901,8 @@ pub unsafe fn vrev32_p8(a: poly8x8_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrev32q_p8(a: poly8x16_t) -> poly8x16_t { - simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12]) +pub fn vrev32q_p8(a: poly8x16_t) -> poly8x16_t { + unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12]) } } /// Reversing vector elements (swap endianness) @@ -7830,8 +7922,8 @@ pub unsafe fn vrev32q_p8(a: poly8x16_t) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrev64_s8(a: int8x8_t) -> int8x8_t { - simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) +pub fn vrev64_s8(a: int8x8_t) -> int8x8_t { + unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) } } /// Reversing vector elements (swap endianness) @@ -7851,8 +7943,8 @@ pub unsafe fn vrev64_s8(a: int8x8_t) -> int8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrev64q_s8(a: int8x16_t) -> int8x16_t { - simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8]) +pub fn vrev64q_s8(a: int8x16_t) -> int8x16_t { + unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8]) } } /// Reversing vector elements (swap endianness) @@ -7872,8 +7964,8 @@ pub unsafe fn vrev64q_s8(a: int8x16_t) -> int8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrev64_s16(a: int16x4_t) -> int16x4_t { - simd_shuffle!(a, a, [3, 2, 1, 0]) +pub fn vrev64_s16(a: int16x4_t) -> int16x4_t { + unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) } } /// Reversing vector elements (swap endianness) @@ -7893,8 +7985,8 @@ pub unsafe fn vrev64_s16(a: int16x4_t) -> int16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrev64q_s16(a: int16x8_t) -> int16x8_t { - simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]) +pub fn vrev64q_s16(a: int16x8_t) -> int16x8_t { + unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]) } } /// Reversing vector elements (swap endianness) @@ -7914,8 +8006,8 @@ pub unsafe fn vrev64q_s16(a: int16x8_t) -> int16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrev64_s32(a: int32x2_t) -> int32x2_t { - simd_shuffle!(a, a, [1, 0]) +pub fn vrev64_s32(a: int32x2_t) -> int32x2_t { + unsafe { simd_shuffle!(a, a, [1, 0]) } } /// Reversing vector elements (swap endianness) @@ -7935,8 +8027,8 @@ pub unsafe fn vrev64_s32(a: int32x2_t) -> int32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrev64q_s32(a: int32x4_t) -> int32x4_t { - simd_shuffle!(a, a, [1, 0, 3, 2]) +pub fn vrev64q_s32(a: int32x4_t) -> int32x4_t { + unsafe { simd_shuffle!(a, a, [1, 0, 3, 2]) } } /// Reversing vector elements (swap endianness) @@ -7956,8 +8048,8 @@ pub unsafe fn vrev64q_s32(a: int32x4_t) -> int32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrev64_u8(a: uint8x8_t) -> uint8x8_t { - simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) +pub fn vrev64_u8(a: uint8x8_t) -> uint8x8_t { + unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) } } /// Reversing vector elements (swap endianness) @@ -7977,8 +8069,8 @@ pub unsafe fn vrev64_u8(a: uint8x8_t) -> uint8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrev64q_u8(a: uint8x16_t) -> uint8x16_t { - simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8]) +pub fn vrev64q_u8(a: uint8x16_t) -> uint8x16_t { + unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8]) } } /// Reversing vector elements (swap endianness) @@ -7998,8 +8090,8 @@ pub unsafe fn vrev64q_u8(a: uint8x16_t) -> uint8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrev64_u16(a: uint16x4_t) -> uint16x4_t { - simd_shuffle!(a, a, [3, 2, 1, 0]) +pub fn vrev64_u16(a: uint16x4_t) -> uint16x4_t { + unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) } } /// Reversing vector elements (swap endianness) @@ -8019,8 +8111,8 @@ pub unsafe fn vrev64_u16(a: uint16x4_t) -> uint16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrev64q_u16(a: uint16x8_t) -> uint16x8_t { - simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]) +pub fn vrev64q_u16(a: uint16x8_t) -> uint16x8_t { + unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]) } } /// Reversing vector elements (swap endianness) @@ -8040,8 +8132,8 @@ pub unsafe fn vrev64q_u16(a: uint16x8_t) -> uint16x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrev64_u32(a: uint32x2_t) -> uint32x2_t { - simd_shuffle!(a, a, [1, 0]) +pub fn vrev64_u32(a: uint32x2_t) -> uint32x2_t { + unsafe { simd_shuffle!(a, a, [1, 0]) } } /// Reversing vector elements (swap endianness) @@ -8061,8 +8153,8 @@ pub unsafe fn vrev64_u32(a: uint32x2_t) -> uint32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrev64q_u32(a: uint32x4_t) -> uint32x4_t { - simd_shuffle!(a, a, [1, 0, 3, 2]) +pub fn vrev64q_u32(a: uint32x4_t) -> uint32x4_t { + unsafe { simd_shuffle!(a, a, [1, 0, 3, 2]) } } /// Reversing vector elements (swap endianness) @@ -8082,8 +8174,8 @@ pub unsafe fn vrev64q_u32(a: uint32x4_t) -> uint32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrev64_f32(a: float32x2_t) -> float32x2_t { - simd_shuffle!(a, a, [1, 0]) +pub fn vrev64_f32(a: float32x2_t) -> float32x2_t { + unsafe { simd_shuffle!(a, a, [1, 0]) } } /// Reversing vector elements (swap endianness) @@ -8103,8 +8195,8 @@ pub unsafe fn vrev64_f32(a: float32x2_t) -> float32x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrev64q_f32(a: float32x4_t) -> float32x4_t { - simd_shuffle!(a, a, [1, 0, 3, 2]) +pub fn vrev64q_f32(a: float32x4_t) -> float32x4_t { + unsafe { simd_shuffle!(a, a, [1, 0, 3, 2]) } } /// Reversing vector elements (swap endianness) @@ -8124,8 +8216,8 @@ pub unsafe fn vrev64q_f32(a: float32x4_t) -> float32x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrev64_p8(a: poly8x8_t) -> poly8x8_t { - simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) +pub fn vrev64_p8(a: poly8x8_t) -> poly8x8_t { + unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) } } /// Reversing vector elements (swap endianness) @@ -8145,8 +8237,8 @@ pub unsafe fn vrev64_p8(a: poly8x8_t) -> poly8x8_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrev64q_p8(a: poly8x16_t) -> poly8x16_t { - simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8]) +pub fn vrev64q_p8(a: poly8x16_t) -> poly8x16_t { + unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8]) } } /// Reversing vector elements (swap endianness) @@ -8166,8 +8258,8 @@ pub unsafe fn vrev64q_p8(a: poly8x16_t) -> poly8x16_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrev64_p16(a: poly16x4_t) -> poly16x4_t { - simd_shuffle!(a, a, [3, 2, 1, 0]) +pub fn vrev64_p16(a: poly16x4_t) -> poly16x4_t { + unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) } } /// Reversing vector elements (swap endianness) @@ -8187,8 +8279,8 @@ pub unsafe fn vrev64_p16(a: poly16x4_t) -> poly16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vrev64q_p16(a: poly16x8_t) -> poly16x8_t { - simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]) +pub fn vrev64q_p16(a: poly16x8_t) -> poly16x8_t { + unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]) } } /* FIXME: 16-bit float @@ -8200,8 +8292,8 @@ pub unsafe fn vrev64q_p16(a: poly16x8_t) -> poly16x8_t { #[cfg_attr( target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] pub unsafe fn vcombine_f16 ( low: float16x4_t, high: float16x4_t) -> float16x8_t { - simd_shuffle!(low, high, [0, 1, 2, 3, 4, 5, 6, 7]) +)] pub fn vcombine_f16 ( low: float16x4_t, high: float16x4_t) -> float16x8_t { + unsafe { simd_shuffle!(low, high, [0, 1, 2, 3, 4, 5, 6, 7]) } } */ diff --git a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml index c0e1b2e313..9fe113ce01 100644 --- a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml +++ b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml @@ -96,8 +96,7 @@ intrinsics: return_type: "{type}" attr: [*neon-stable] assert_instr: [nop] - safety: - unsafe: [neon] + safety: safe types: - i64 - u64 @@ -115,8 +114,7 @@ intrinsics: - FnCall: [target_feature, ['enable = "neon,sha3"']] - FnCall: [stable, ['feature = "stdarch_neon_sha3"', 'since = "1.79.0"']] assert_instr: [eor3] - safety: - unsafe: [neon] + safety: safe types: - int8x16_t - int16x8_t @@ -137,8 +135,7 @@ intrinsics: - FnCall: [target_feature, ['enable = "neon,sha3"']] - FnCall: [stable, ['feature = "stdarch_neon_sha3"', 'since = "1.79.0"']] assert_instr: [eor3] - safety: - unsafe: [neon] + safety: safe types: - uint8x16_t - uint16x8_t @@ -157,8 +154,7 @@ intrinsics: return_type: "{neon_type}" attr: [*neon-stable] assert_instr: [fabd] - safety: - unsafe: [neon] + safety: safe types: - float64x1_t - float64x2_t @@ -175,8 +171,7 @@ intrinsics: return_type: "{type[1]}" attr: [*neon-stable] assert_instr: [fabd] - safety: - unsafe: [neon] + safety: safe types: - ['s_f32', 'f32'] - ['d_f64', 'f64'] @@ -197,8 +192,7 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 assert_instr: [fabd] - safety: - unsafe: [neon] + safety: safe types: - ['h_f16', 'f16'] compose: @@ -216,8 +210,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: [*neon-stable] assert_instr: [sabdl] - safety: - unsafe: [neon] + safety: safe types: - [int8x16_t, int16x8_t, int8x8_t, uint8x8_t] compose: @@ -260,8 +253,7 @@ intrinsics: - - 'feature = "neon_intrinsics"' - 'since = "1.59.0"' assert_instr: [sabdl] - safety: - unsafe: [neon] + safety: safe types: - [int16x8_t, int32x4_t, int16x4_t, uint16x4_t] compose: @@ -304,8 +296,7 @@ intrinsics: - - 'feature = "neon_intrinsics"' - 'since = "1.59.0"' assert_instr: [sabdl] - safety: - unsafe: [neon] + safety: safe types: - [int32x4_t, int64x2_t, int32x2_t, uint32x2_t] compose: @@ -345,8 +336,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmeq]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [uint64x1_t, uint64x1_t] - [uint64x2_t, uint64x2_t] @@ -364,8 +354,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmeq]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [float64x1_t, uint64x1_t] - [float64x2_t, uint64x2_t] @@ -379,8 +368,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmp]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - ["s_f32", "f32", "u32"] - ["d_f64", "f64", "u64"] @@ -402,8 +390,7 @@ intrinsics: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmp]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - ["h_f16", "f16", "u16"] compose: @@ -422,8 +409,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmp]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - ["i64", "u64", "s64"] - ["u64", "u64", "u64"] @@ -442,8 +428,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmtst]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [int64x1_t, uint64x1_t, 'i64x1', 'i64x1::new(0)'] - [int64x2_t, uint64x2_t, 'i64x2', 'i64x2::new(0, 0)'] @@ -461,8 +446,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tst]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - ["i64", "u64", "s64"] - ["u64", "u64", "u64"] @@ -481,8 +465,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [suqadd]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - ["s_s32", "i32", "u32"] - ["d_s64", "i64", "u64"] @@ -500,8 +483,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [suqadd]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - ["b_s8", "i8", "u8", "s8"] - ["h_s16", "i16", "u16", "s16"] @@ -521,8 +503,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fabs]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - float64x1_t - float64x2_t @@ -536,8 +517,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmgt]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [int64x1_t, uint64x1_t] - [int64x2_t, uint64x2_t] @@ -551,8 +531,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmhi]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - uint64x1_t - uint64x2_t @@ -566,8 +545,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmgt]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [float64x1_t, uint64x1_t] - [float64x2_t, uint64x2_t] @@ -581,8 +559,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmp]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - ["s_f32", "f32", "u32"] - ["d_f64", "f64", "u64"] @@ -604,8 +581,7 @@ intrinsics: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmp]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - ["h_f16", "f16", "u16"] compose: @@ -624,8 +600,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmgt]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [int64x1_t, uint64x1_t] - [int64x2_t, uint64x2_t] @@ -639,8 +614,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmge]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [int64x1_t, uint64x1_t] - [int64x2_t, uint64x2_t] @@ -654,8 +628,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmge]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [float64x1_t, uint64x1_t] - [float64x2_t, uint64x2_t] @@ -669,8 +642,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmp]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - ["s_f32", "f32", "u32"] - ["d_f64", "f64", "u64"] @@ -692,8 +664,7 @@ intrinsics: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmp]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - ["h_f16", "f16", "u16"] compose: @@ -712,8 +683,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmge]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [int64x1_t, uint64x1_t] - [int64x2_t, uint64x2_t] @@ -727,8 +697,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmge]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [int8x8_t, uint8x8_t, i8x8, 'i8x8::new(0, 0, 0, 0, 0, 0, 0, 0)'] - [int8x16_t, uint8x16_t, i8x16, 'i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)'] @@ -749,8 +718,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - ["i64", "u64"] compose: @@ -767,8 +735,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmle]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [int8x8_t, uint8x8_t, i8x8, 'i8x8::new(0, 0, 0, 0, 0, 0, 0, 0)'] - [int8x16_t, uint8x16_t, i8x16, 'i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)'] @@ -792,8 +759,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmle]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [float32x2_t, uint32x2_t, f32x2, 'f32x2::new(0.0, 0.0)'] - [float32x4_t, uint32x4_t, f32x4, 'f32x4::new(0.0, 0.0, 0.0, 0.0)'] @@ -813,8 +779,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmp]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - ["s_f32", "f32", "u32"] - ["d_f64", "f64", "u64"] @@ -834,8 +799,7 @@ intrinsics: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmp]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - ["h_f16", "f16", "u16"] compose: @@ -853,8 +817,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmlt]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [int8x8_t, uint8x8_t, i8x8, 'i8x8::new(0, 0, 0, 0, 0, 0, 0, 0)'] - [int8x16_t, uint8x16_t, i8x16, 'i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)'] @@ -878,8 +841,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmlt]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [float32x2_t, uint32x2_t, f32x2, 'f32x2::new(0.0, 0.0)'] - [float32x4_t, uint32x4_t, f32x4, 'f32x4::new(0.0, 0.0, 0.0, 0.0)'] @@ -899,8 +861,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmp]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - ["s_f32", "f32", "u32"] - ["d_f64", "f64", "u64"] @@ -920,8 +881,7 @@ intrinsics: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmp]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - ["h_f16", "f16", "u16"] compose: @@ -939,8 +899,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [asr]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - ["i64", "u64"] compose: @@ -957,8 +916,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [facgt]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [float64x1_t, uint64x1_t] - [float64x2_t, uint64x2_t] @@ -976,8 +934,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [facgt]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - ["s_f32", "f32", "u32", i32] - ["d_f64", "f64", "u64", i64] @@ -996,8 +953,7 @@ intrinsics: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [facgt]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - ["h_f16", "f16", "u16", i32] compose: @@ -1007,7 +963,7 @@ intrinsics: links: - link: "llvm.aarch64.neon.facgt.{type[3]}.{type[1]}" arch: aarch64,arm64ec - - '_vcagth_f16(a, b) as u16' + - 'unsafe {{ _vcagth_f16(a, b) as u16 }}' - name: "vcage{neon_type[0].no}" doc: "Floating-point absolute compare greater than or equal" @@ -1016,8 +972,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [facge]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [float64x1_t, uint64x1_t] - [float64x2_t, uint64x2_t] @@ -1035,8 +990,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [facge]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - ["s_f32", "f32", "u32", i32] - ["d_f64", "f64", "u64", i64] @@ -1056,8 +1010,7 @@ intrinsics: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [facge]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - ["h_f16", "f16", "u16", i32] compose: @@ -1067,7 +1020,7 @@ intrinsics: links: - link: "llvm.aarch64.neon.facge.{type[3]}.{type[1]}" arch: aarch64,arm64ec - - "_vcageh_f16(a, b) as u16" + - "unsafe {{ _vcageh_f16(a, b) as u16 }}" - name: "vcalt{neon_type[0].no}" doc: "Floating-point absolute compare less than" @@ -1076,8 +1029,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [facgt]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [float64x1_t, uint64x1_t] - [float64x2_t, uint64x2_t] @@ -1091,8 +1043,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [facgt]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - ["s_f32", "f32", "u32"] - ["d_f64", "f64", "u64"] @@ -1107,8 +1058,7 @@ intrinsics: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [facgt]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - ["h_f16", "f16", "u16"] compose: @@ -1121,8 +1071,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [facge]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [float64x1_t, uint64x1_t] - [float64x2_t, uint64x2_t] @@ -1136,8 +1085,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [facge]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - ["s_f32", "f32", "u32"] - ["d_f64", "f64", "u64"] @@ -1152,8 +1100,7 @@ intrinsics: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [facge]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - ["h_f16", "f16", "u16"] compose: @@ -1166,8 +1113,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [scvtf]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [int64x1_t, float64x1_t] - [int64x2_t, float64x2_t] @@ -1181,8 +1127,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [scvtf]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - ["s_f32", "i32", "f32", s32] - ["d_f64", "i64", "f64", s64] @@ -1196,8 +1141,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ucvtf]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [uint64x1_t, float64x1_t] - [uint64x2_t, float64x2_t] @@ -1211,8 +1155,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ucvtf]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - ["u32", "f32", "s_f32"] - ["u64", "f64", "d_f64"] @@ -1228,8 +1171,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['1']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [int64x1_t, float64x1_t] - [int64x2_t, float64x2_t] @@ -1243,7 +1185,7 @@ intrinsics: links: - link: "llvm.aarch64.neon.vcvtfxs2fp.{neon_type[1]}.{neon_type[0]}" arch: aarch64,arm64ec - - FnCall: ["_vcvt{neon_type[1].N}_{neon_type[0]}", [a, N]] + - FnCall: ["_vcvt{neon_type[1].N}_{neon_type[0]}", [a, N], [], true] - name: "vcvt{type[2]}_n_{type[1]}_{type[0]}" @@ -1256,8 +1198,7 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [i32, f16, 'h'] - [i64, f16, 'h'] @@ -1271,7 +1212,7 @@ intrinsics: links: - link: "llvm.aarch64.neon.vcvtfxs2fp.{type[1]}.{type[0]}" arch: aarch64,arm64ec - - FnCall: ["_vcvt{type[2]}_n_{type[1]}_{type[0]}", [a, N]] + - FnCall: ["_vcvt{type[2]}_n_{type[1]}_{type[0]}", [a, N], [], true] - name: "vcvt{type[2]}_n_{type[1]}_{type[0]}" @@ -1284,8 +1225,7 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [f16, s16, 'h', i32, i16] compose: @@ -1302,8 +1242,7 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [u32, f16, 'h'] - [u64, f16, 'h'] @@ -1317,7 +1256,7 @@ intrinsics: links: - link: "llvm.aarch64.neon.vcvtfxu2fp.{type[1]}.{type[0]}" arch: aarch64,arm64ec - - FnCall: ["_vcvt{type[2]}_n_{type[1]}_{type[0]}", [a, N]] + - FnCall: ["_vcvt{type[2]}_n_{type[1]}_{type[0]}", [a, N], [], true] - name: "vcvt{type[2]}_n_{type[1]}_{type[0]}" @@ -1330,8 +1269,7 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [i16, f16, 'h', 'i32', 'as i32'] compose: @@ -1349,8 +1287,7 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [u16, f16, 'h', u32] compose: @@ -1367,8 +1304,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['1']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - ["i32", "f32", 's_n_f32_s32', 'N >= 1 && N <= 32'] - ["i64", "f64", 'd_n_f64_s64', 'N >= 1 && N <= 64'] @@ -1382,7 +1318,7 @@ intrinsics: links: - link: "llvm.aarch64.neon.vcvtfxs2fp.{type[1]}.{type[0]}" arch: aarch64,arm64ec - - FnCall: ["_vcvt{type[2]}", [a, N]] + - FnCall: ["_vcvt{type[2]}", [a, N], [], true] - name: "vcvt{neon_type[1].N}_{neon_type[0]}" @@ -1394,8 +1330,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['1']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [uint64x1_t, float64x1_t] - [uint64x2_t, float64x2_t] @@ -1409,7 +1344,7 @@ intrinsics: links: - link: "llvm.aarch64.neon.vcvtfxu2fp.{neon_type[1]}.{neon_type[0]}" arch: aarch64,arm64ec - - FnCall: ["_vcvt{neon_type[1].N}_{neon_type[0]}", ["a", N]] + - FnCall: ["_vcvt{neon_type[1].N}_{neon_type[0]}", ["a", N], [], true] - name: "vcvt{type[2]}" doc: "Fixed-point convert to floating-point" @@ -1420,8 +1355,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['1']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - ["u32", "f32", 's_n_f32_u32', 'N >= 1 && N <= 32'] - ["u64", "f64", 'd_n_f64_u64', 'N >= 1 && N <= 64'] @@ -1435,7 +1369,7 @@ intrinsics: links: - link: "llvm.aarch64.neon.vcvtfxu2fp.{type[1]}.{type[0]}" arch: aarch64,arm64ec - - FnCall: ["_vcvt{type[2]}", ["a", N]] + - FnCall: ["_vcvt{type[2]}", ["a", N], [], true] - name: "vcvt{type[2]}" doc: "Fixed-point convert to floating-point" @@ -1444,8 +1378,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtzs]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - ["f32", "i32", "s_s32_f32", "32"] - ["f64", "i64", "d_s64_f64", "64"] @@ -1459,8 +1392,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtzu]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - ["f32", "u32", "s_u32_f32"] - ["f64", "u64", "d_u64_f64"] @@ -1476,8 +1408,7 @@ intrinsics: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [scvtf]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - ["s16", "f16", "h_f16_s16", i16] - ["s32", "f16", "h_f16_s32", i32] @@ -1493,8 +1424,7 @@ intrinsics: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtzs]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - ["f16", "s16", "h", i16, 'a as i16'] - ["f16", "s32", "h", i32, 'a as i32'] @@ -1510,8 +1440,7 @@ intrinsics: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtzu]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - ["f16", "u16", "h", 'a as u16'] - ["f16", "u32", "h", 'a as u32'] @@ -1528,8 +1457,7 @@ intrinsics: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ucvtf]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - ["u16", "f16", "h_f16_u16"] - ["u32", "f16", "h_f16_u32"] @@ -1545,8 +1473,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtl]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [float32x2_t, float64x2_t] compose: @@ -1559,8 +1486,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtl]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [float32x4_t, float64x2_t] compose: @@ -1582,8 +1508,7 @@ intrinsics: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtn2]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - [float16x8_t, float16x4_t, float32x4_t] compose: @@ -1600,8 +1525,7 @@ intrinsics: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtl2]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - [float32x4_t, float16x8_t] compose: @@ -1617,8 +1541,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtn]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [float64x2_t, float32x2_t] compose: @@ -1631,8 +1554,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtn]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [float32x2_t, float64x2_t, float32x4_t] compose: @@ -1649,8 +1571,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtxn]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [float64x2_t, float32x2_t] compose: @@ -1667,8 +1588,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtxn]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - ["f64", "f32"] compose: @@ -1686,8 +1606,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtxn]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [float32x2_t, float64x2_t, float32x4_t] compose: @@ -1706,8 +1625,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['1']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [float64x1_t, int64x1_t, _n_s64_f64, '64'] - [float64x2_t, int64x2_t, q_n_s64_f64, '64'] @@ -1719,7 +1637,7 @@ intrinsics: links: - link: "llvm.aarch64.neon.vcvtfp2fxs.{type[1]}.{type[0]}" arch: aarch64,arm64ec - - FnCall: ["_vcvt{type[2]}", [a, N]] + - FnCall: ["_vcvt{type[2]}", [a, N], [], true] - name: "vcvt{type[2]}" doc: "Floating-point convert to fixed-point, rounding toward zero" @@ -1730,8 +1648,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['1']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - ["f32", "i32", s_n_s32_f32, '32'] - ["f64", "i64", d_n_s64_f64, '64'] @@ -1743,7 +1660,7 @@ intrinsics: links: - link: "llvm.aarch64.neon.vcvtfp2fxs.{type[1]}.{type[0]}" arch: aarch64,arm64ec - - FnCall: ["_vcvt{type[2]}", [a, N]] + - FnCall: ["_vcvt{type[2]}", [a, N], [], true] - name: "vcvt{type[2]}_n_{type[1]}_{type[0]}" @@ -1756,8 +1673,7 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - ["f16", "i32", 'h', '16'] - ["f16", "i64", 'h', '16'] @@ -1769,7 +1685,7 @@ intrinsics: links: - link: "llvm.aarch64.neon.vcvtfp2fxs.{type[1]}.{type[0]}" arch: aarch64,arm64ec - - FnCall: ["_vcvt{type[2]}_n_{type[1]}_{type[0]}", [a, N]] + - FnCall: ["_vcvt{type[2]}_n_{type[1]}_{type[0]}", [a, N], [], true] - name: "vcvt{type[2]}_n_{type[1]}_{type[0]}" @@ -1782,8 +1698,7 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [f16, u16, 'h', u32] compose: @@ -1801,8 +1716,7 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - ["f16", "u32", 'h', '16'] - ["f16", "u64", 'h', '16'] @@ -1814,7 +1728,7 @@ intrinsics: links: - link: "llvm.aarch64.neon.vcvtfp2fxu.{type[1]}.{type[0]}" arch: aarch64,arm64ec - - FnCall: ["_vcvt{type[2]}_n_{type[1]}_{type[0]}", [a, N]] + - FnCall: ["_vcvt{type[2]}_n_{type[1]}_{type[0]}", [a, N], [], true] - name: "vcvt{type[2]}" doc: "Floating-point convert to fixed-point, rounding toward zero" @@ -1825,8 +1739,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['1']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [float64x1_t, uint64x1_t, _n_u64_f64, '64'] - [float64x2_t, uint64x2_t, q_n_u64_f64, '64'] @@ -1838,7 +1751,7 @@ intrinsics: links: - link: "llvm.aarch64.neon.vcvtfp2fxu.{type[1]}.{type[0]}" arch: aarch64,arm64ec - - FnCall: ["_vcvt{type[2]}", [a, N]] + - FnCall: ["_vcvt{type[2]}", [a, N], [], true] - name: "vcvt{type[2]}" doc: "Floating-point convert to fixed-point, rounding toward zero" @@ -1849,8 +1762,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['1']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - ["f32", "u32", s_n_u32_f32, '32'] - ["f64", "u64", d_n_u64_f64, '64'] @@ -1862,7 +1774,7 @@ intrinsics: links: - link: "llvm.aarch64.neon.vcvtfp2fxu.{type[1]}.{type[0]}" arch: aarch64,arm64ec - - FnCall: ["_vcvt{type[2]}", [a, N]] + - FnCall: ["_vcvt{type[2]}", [a, N], [], true] - name: "vcvta{type[2]}" doc: "Floating-point convert to signed integer, rounding to nearest with ties to away" @@ -1871,8 +1783,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtas]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [float32x2_t, int32x2_t, _s32_f32] - [float32x4_t, int32x4_t, q_s32_f32] @@ -1894,8 +1805,7 @@ intrinsics: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtas]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - [float16x4_t, int16x4_t] - [float16x8_t, int16x8_t] @@ -1913,8 +1823,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtas]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - ["f32", "i32", 's_s32_f32'] - ["f64", "i64", 'd_s64_f64'] @@ -1934,8 +1843,7 @@ intrinsics: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtau]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - ["f16", "u32", 'h_u32_f16'] - ["f16", "u64", 'h_u64_f16'] @@ -1956,8 +1864,7 @@ intrinsics: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtas]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - ["f16", "i32", 'h_s32_f16'] - ["f16", "i64", 'h_s64_f16'] @@ -1978,8 +1885,7 @@ intrinsics: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtas]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - ["f16", "i16", 'h_s16_f16', 's32'] compose: @@ -1993,8 +1899,7 @@ intrinsics: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtau]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - ["f16", "u16", 'h_u16_f16', 'u32'] compose: @@ -2007,8 +1912,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtau]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - ["f32", "u32", 's_u32_f32'] - ["f64", "u64", 'd_u64_f64'] @@ -2026,8 +1930,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtns]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [float32x2_t, int32x2_t] - [float32x4_t, int32x4_t] @@ -2047,8 +1950,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtns]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - ["f32", "i32", 's_s32_f32'] - ["f64", "i64", 'd_s64_f64'] @@ -2068,8 +1970,7 @@ intrinsics: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtns]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - [float16x4_t, int16x4_t] - [float16x8_t, int16x8_t] @@ -2089,8 +1990,7 @@ intrinsics: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtnu]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - [float16x4_t, uint16x4_t] - [float16x8_t, uint16x8_t] @@ -2109,8 +2009,7 @@ intrinsics: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtns]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - ["f16", "i32", 'h'] - ["f16", "i64", 'h'] @@ -2130,8 +2029,7 @@ intrinsics: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtns]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - ["f16", "i16", 'h', 'i32'] compose: @@ -2146,8 +2044,7 @@ intrinsics: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtnu]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - ["f16", "u32", 'h'] - ["f16", "u64", 'h'] @@ -2167,8 +2064,7 @@ intrinsics: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtnu]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - ["f16", "u16", 'h', 'u32'] compose: @@ -2181,8 +2077,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtms]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [float32x2_t, int32x2_t] - [float32x4_t, int32x4_t] @@ -2204,8 +2099,7 @@ intrinsics: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtms]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - [float16x4_t, int16x4_t] - [float16x8_t, int16x8_t] @@ -2225,8 +2119,7 @@ intrinsics: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtmu]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - [float16x4_t, uint16x4_t] - [float16x8_t, uint16x8_t] @@ -2245,8 +2138,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtms]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - ["f32", "i32", 's_s32_f32'] - ["f64", "i64", 'd_s64_f64'] @@ -2264,8 +2156,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtps]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [float32x2_t, int32x2_t] - [float32x4_t, int32x4_t] @@ -2285,8 +2176,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtps]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - ["f32", "i32", 's_s32_f32'] - ["f64", "i64", 'd_s64_f64'] @@ -2304,8 +2194,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtnu]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [float32x2_t, uint32x2_t] - [float32x4_t, uint32x4_t] @@ -2325,8 +2214,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtnu]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - ["f32", "u32", 's_u32_f32'] - ["f64", "u64", 'd_u64_f64'] @@ -2344,8 +2232,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtmu]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [float32x2_t, uint32x2_t] - [float32x4_t, uint32x4_t] @@ -2365,8 +2252,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtmu]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - ["f32", "u32", s_u32_f32] - ["f64", "u64", d_u64_f64] @@ -2384,8 +2270,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtpu]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [float32x2_t, uint32x2_t] - [float32x4_t, uint32x4_t] @@ -2405,8 +2290,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtpu]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - ["f32", "u32", s_u32_f32, 'i32'] - ["f64", "u64", d_u64_f64, 'u64'] @@ -2429,8 +2313,7 @@ intrinsics: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtps]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - [float16x4_t, int16x4_t] - [float16x8_t, int16x8_t] @@ -2450,8 +2333,7 @@ intrinsics: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtpu]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - [float16x4_t, uint16x4_t] - [float16x8_t, uint16x8_t] @@ -2471,8 +2353,7 @@ intrinsics: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtps]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - ["f16", "i32", 'h'] - ["f16", "i64", 'h'] @@ -2492,8 +2373,7 @@ intrinsics: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtps]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - ["f16", "i16", 'h', 'i32'] compose: @@ -2507,8 +2387,7 @@ intrinsics: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtpu]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - ["f16", "u32", 'h'] - ["f16", "u64", 'h'] @@ -2528,8 +2407,7 @@ intrinsics: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtpu]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - ["f16", "u16", 'h', 'u32'] compose: @@ -2544,8 +2422,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['1']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - poly64x2_t - float64x2_t @@ -2562,8 +2439,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['1']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [poly64x1_t, poly64x2_t] - [float64x1_t, float64x2_t] @@ -2580,8 +2456,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['1']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - poly64x1_t - float64x1_t @@ -2598,8 +2473,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['1']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [int64x1_t, "i64"] - [uint64x1_t, "u64"] @@ -2617,8 +2491,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['1']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [poly64x2_t, poly64x1_t, 'u64'] - [float64x2_t, float64x1_t, 'f64'] @@ -2637,8 +2510,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['1']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [int32x2_t, "i32", s_lane_s32] - [int64x2_t, "i64", d_laneq_s64] @@ -2659,8 +2531,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['1']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [int8x8_t, "i8", b_lane_s8] - [int16x8_t, "i16", h_laneq_s16] @@ -2683,8 +2554,7 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [float16x4_t, "f16", h_lane_f16] compose: @@ -2702,8 +2572,7 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [float16x8_t, "f16", h_laneq_f16] compose: @@ -2720,8 +2589,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['1']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [int8x16_t, "i8", b_laneq_s8] - [uint8x16_t, "u8", b_laneq_u8] @@ -2739,8 +2607,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['1']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [int16x4_t, "i16", h_lane_s16] - [int32x4_t, "i32", s_laneq_s32] @@ -2761,11 +2628,10 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['2']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - - [poly64x2_t, ' static_assert_uimm_bits!(N, 1);', 'match N & 0b1 { 0 => simd_shuffle!(a, b, [0, 1]), 1 => simd_shuffle!(a, b, [1, 2]), _ => unreachable_unchecked(), }'] - - [float64x2_t, ' static_assert_uimm_bits!(N, 1);', 'match N & 0b1 { 0 => simd_shuffle!(a, b, [0, 1]), 1 => simd_shuffle!(a, b, [1, 2]), _ => unreachable_unchecked(), }'] + - [poly64x2_t, ' static_assert_uimm_bits!(N, 1);', 'unsafe { match N & 0b1 { 0 => simd_shuffle!(a, b, [0, 1]), 1 => simd_shuffle!(a, b, [1, 2]), _ => unreachable_unchecked(), } }'] + - [float64x2_t, ' static_assert_uimm_bits!(N, 1);', 'unsafe { match N & 0b1 { 0 => simd_shuffle!(a, b, [0, 1]), 1 => simd_shuffle!(a, b, [1, 2]), _ => unreachable_unchecked(), } }'] compose: - Identifier: ["{type[1]}", Symbol] - Identifier: ["{type[2]}", Symbol] @@ -2777,8 +2643,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmul]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - float64x1_t - float64x2_t @@ -2792,8 +2657,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [smlal2]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [int16x8_t, int8x16_t, int8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]', '[8, 9, 10, 11, 12, 13, 14, 15]'] - [int32x4_t, int16x8_t, int16x4_t, '[4, 5, 6, 7]', '[4, 5, 6, 7]'] @@ -2810,8 +2674,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [umlal2]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [uint16x8_t, uint8x16_t, uint8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]'] - [uint32x4_t, uint16x8_t, uint16x4_t, '[4, 5, 6, 7]'] @@ -2834,8 +2697,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [smlsl2]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [int16x8_t, int8x16_t, int8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]'] - [int32x4_t, int16x8_t, int16x4_t, '[4, 5, 6, 7]'] @@ -2858,8 +2720,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [umlsl2]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [uint16x8_t, uint8x16_t, uint8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]'] - [uint32x4_t, uint16x8_t, uint16x4_t, '[4, 5, 6, 7]'] @@ -2875,8 +2736,7 @@ intrinsics: return_type: "{neon_type[2]}" attr: [*neon-stable] assert_instr: [xtn2] - safety: - unsafe: [neon] + safety: safe types: - [int8x8_t, int16x8_t, int8x16_t, '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]'] - [int16x4_t, int32x4_t, int16x8_t, '[0, 1, 2, 3, 4, 5, 6, 7]'] @@ -2903,8 +2763,7 @@ intrinsics: return_type: "{neon_type}" attr: [*neon-stable] assert_instr: [neg] - safety: - unsafe: [neon] + safety: safe types: - int64x1_t - int64x2_t @@ -2919,8 +2778,7 @@ intrinsics: return_type: "{type}" attr: [*neon-stable] assert_instr: [neg] - safety: - unsafe: [neon] + safety: safe types: - i64 compose: @@ -2935,8 +2793,7 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 assert_instr: [fneg] - safety: - unsafe: [neon] + safety: safe types: - f16 compose: @@ -2952,8 +2809,7 @@ intrinsics: - - 'feature = "neon_intrinsics"' - 'since = "1.59.0"' assert_instr: [fneg] - safety: - unsafe: [neon] + safety: safe types: - float64x1_t - float64x2_t @@ -2968,8 +2824,7 @@ intrinsics: return_type: "{type[0]}" attr: [*neon-stable] assert_instr: [sqneg] - safety: - unsafe: [neon] + safety: safe types: - [i8, 'b_s8', 's8'] - [i16, 'h_s16', 's16'] @@ -2989,8 +2844,7 @@ intrinsics: return_type: "{type[0]}" attr: [*neon-stable] assert_instr: [sqneg] - safety: - unsafe: [neon] + safety: safe types: - [int64x1_t, 'i64'] - [int64x2_t, 'i64'] @@ -3007,8 +2861,7 @@ intrinsics: return_type: "{type[0]}" attr: [*neon-stable] assert_instr: [sqsub] - safety: - unsafe: [neon] + safety: safe types: - [i32, 's_s32', 'i32'] - [i64, 'd_s64', 'i64'] @@ -3025,8 +2878,7 @@ intrinsics: return_type: "{type[0]}" attr: [*neon-stable] assert_instr: [uqsub] - safety: - unsafe: [neon] + safety: safe types: - [u32, 's_u32', 'i32'] - [u64, 'd_u64', 'i64'] @@ -3043,8 +2895,7 @@ intrinsics: return_type: "{type[0]}" attr: [*neon-stable] assert_instr: [sqsub] - safety: - unsafe: [neon] + safety: safe types: - [i8, int8x8_t, s8, 'b_s8'] - [i16, int16x4_t, s16, 'h_s16'] @@ -3075,8 +2926,7 @@ intrinsics: return_type: "{type[0]}" attr: [*neon-stable] assert_instr: [uqsub] - safety: - unsafe: [neon] + safety: safe types: - [u8, uint8x8_t, u8, 'b_u8'] - [u16, uint16x4_t, u16, 'h_u16'] @@ -3107,8 +2957,7 @@ intrinsics: return_type: "{neon_type}" attr: [*neon-stable] assert_instr: [rbit] - safety: - unsafe: [neon] + safety: safe types: - int8x8_t - int8x16_t @@ -3125,8 +2974,7 @@ intrinsics: return_type: "{neon_type[0]}" attr: [*neon-stable] assert_instr: [rbit] - safety: - unsafe: [neon] + safety: safe types: - [uint8x8_t, int8x8_t] - [uint8x16_t, int8x16_t] @@ -3145,8 +2993,7 @@ intrinsics: return_type: "{neon_type}" attr: [*neon-stable] assert_instr: [frintx] - safety: - unsafe: [neon] + safety: safe types: - float32x2_t - float32x4_t @@ -3168,8 +3015,7 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 assert_instr: [frintx] - safety: - unsafe: [neon] + safety: safe types: - float16x4_t - float16x8_t @@ -3189,8 +3035,7 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 assert_instr: [frintx] - safety: - unsafe: [neon] + safety: safe types: - [f16, 'h_'] compose: @@ -3207,8 +3052,7 @@ intrinsics: return_type: "{neon_type}" attr: [*neon-stable] assert_instr: [frinta] - safety: - unsafe: [neon] + safety: safe types: - float32x2_t - float32x4_t @@ -3230,8 +3074,7 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 assert_instr: [frinta] - safety: - unsafe: [neon] + safety: safe types: - float16x4_t - float16x8_t @@ -3251,8 +3094,7 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 assert_instr: [frinta] - safety: - unsafe: [neon] + safety: safe types: - [f16, 'h_'] compose: @@ -3268,8 +3110,7 @@ intrinsics: return_type: "{neon_type}" attr: [*neon-stable] assert_instr: [frintn] - safety: - unsafe: [neon] + safety: safe types: - float64x1_t - float64x2_t @@ -3286,8 +3127,7 @@ intrinsics: return_type: "{type}" attr: [*neon-stable] assert_instr: [frintn] - safety: - unsafe: [neon] + safety: safe types: - f32 compose: @@ -3305,8 +3145,7 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 assert_instr: [frintn] - safety: - unsafe: [neon] + safety: safe types: - [f16, 'h_'] compose: @@ -3322,8 +3161,7 @@ intrinsics: return_type: "{neon_type}" attr: [*neon-stable] assert_instr: [frintm] - safety: - unsafe: [neon] + safety: safe types: - float32x2_t - float32x4_t @@ -3345,8 +3183,7 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 assert_instr: [frintm] - safety: - unsafe: [neon] + safety: safe types: - float16x4_t - float16x8_t @@ -3366,8 +3203,7 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 assert_instr: [frintm] - safety: - unsafe: [neon] + safety: safe types: - [f16, 'h_'] compose: @@ -3385,8 +3221,7 @@ intrinsics: return_type: "{neon_type}" attr: [*neon-stable] assert_instr: [frintp] - safety: - unsafe: [neon] + safety: safe types: - float32x2_t - float32x4_t @@ -3408,8 +3243,7 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 assert_instr: [frintp] - safety: - unsafe: [neon] + safety: safe types: - float16x4_t - float16x8_t @@ -3428,8 +3262,7 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 assert_instr: [frintp] - safety: - unsafe: [neon] + safety: safe types: - [f16, 'h_'] compose: @@ -3445,8 +3278,7 @@ intrinsics: return_type: "{neon_type}" attr: [*neon-stable] assert_instr: [frintz] - safety: - unsafe: [neon] + safety: safe types: - float32x2_t - float32x4_t @@ -3467,8 +3299,7 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 assert_instr: [frintz] - safety: - unsafe: [neon] + safety: safe types: - float16x4_t - float16x8_t @@ -3488,8 +3319,7 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 assert_instr: [frintz] - safety: - unsafe: [neon] + safety: safe types: - [f16, 'h_'] compose: @@ -3506,8 +3336,7 @@ intrinsics: return_type: "{neon_type}" attr: [*neon-stable] assert_instr: [frinti] - safety: - unsafe: [neon] + safety: safe types: - float32x2_t - float32x4_t @@ -3529,8 +3358,7 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 assert_instr: [frinti] - safety: - unsafe: [neon] + safety: safe types: - float16x4_t - float16x8_t @@ -3551,8 +3379,7 @@ intrinsics: - *neon-unstable-f16 # TODO: double check me assert_instr: [frinti] - safety: - unsafe: [neon] + safety: safe types: - [f16, 'h_'] compose: @@ -3568,8 +3395,7 @@ intrinsics: return_type: "{type[0]}" attr: [*neon-stable] assert_instr: [uqadd] - safety: - unsafe: [neon] + safety: safe types: - [u32, 's_u32', i32] - [u64, 'd_u64', i64] @@ -3586,8 +3412,7 @@ intrinsics: return_type: "{type[0]}" attr: [*neon-stable] assert_instr: [sqadd] - safety: - unsafe: [neon] + safety: safe types: - [i32, 's_s32', i32] - [i64, 'd_s64', i64] @@ -3604,8 +3429,7 @@ intrinsics: return_type: "{type[0]}" attr: [*neon-stable] assert_instr: [sqadd] - safety: - unsafe: [neon] + safety: safe types: - [i8, int8x8_t, 'b_s8'] - [i16, int16x4_t, 'h_s16'] @@ -3636,8 +3460,7 @@ intrinsics: return_type: "{type[0]}" attr: [*neon-stable] assert_instr: [uqadd] - safety: - unsafe: [neon] + safety: safe types: - [u8, uint8x8_t, 'b_u8'] - [u16, uint16x4_t, 'h_u16'] @@ -5288,8 +5111,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['3']] - FnCall: [unstable, ['feature = "stdarch_neon_i8mm"', 'issue = "117223"']] static_defs: ["const LANE: i32"] - safety: - unsafe: [neon] + safety: safe types: - [int32x2_t, uint8x8_t, int8x16_t, '[LANE as u32, LANE as u32]'] - [int32x4_t, uint8x16_t, int8x16_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] @@ -5309,8 +5131,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['3']] - FnCall: [unstable, ['feature = "stdarch_neon_i8mm"', 'issue = "117223"']] static_defs: ["const LANE: i32"] - safety: - unsafe: [neon] + safety: safe types: - [int32x2_t, int8x8_t, uint8x16_t, '[LANE as u32, LANE as u32]', uint32x2_t] - [int32x4_t, int8x16_t, uint8x16_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]', uint32x4_t] @@ -5332,8 +5153,7 @@ intrinsics: return_type: "{neon_type}" attr: [*neon-stable] assert_instr: [fmul] - safety: - unsafe: [neon] + safety: safe types: - float64x1_t - float64x2_t @@ -5346,8 +5166,7 @@ intrinsics: return_type: "{neon_type[3]}" attr: [*neon-stable] assert_instr: [smull2] - safety: - unsafe: [neon] + safety: safe types: - [int8x16_t, int8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]', int16x8_t] - [int16x8_t, int16x4_t, '[4, 5, 6, 7]', int32x4_t] @@ -5369,8 +5188,7 @@ intrinsics: return_type: "{neon_type[3]}" attr: [*neon-stable] assert_instr: [umull2] - safety: - unsafe: [neon] + safety: safe types: - [uint8x16_t, uint8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]', uint16x8_t] - [uint16x8_t, uint16x4_t, '[4, 5, 6, 7]', uint32x4_t] @@ -5393,8 +5211,7 @@ intrinsics: attr: - *neon-aes - *neon-stable - safety: - unsafe: [neon] + safety: safe assert_instr: [pmull] types: - ["p64", "p128"] @@ -5413,8 +5230,7 @@ intrinsics: return_type: "{neon_type[3]}" attr: - *neon-stable - safety: - unsafe: [neon] + safety: safe assert_instr: [pmull] types: - [poly8x16_t, poly8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]', poly16x8_t] @@ -5436,8 +5252,7 @@ intrinsics: attr: - *neon-aes - *neon-stable - safety: - unsafe: [neon] + safety: safe assert_instr: [pmull] types: - [poly64x2_t, "p128"] @@ -5453,8 +5268,7 @@ intrinsics: return_type: "{neon_type}" attr: [*neon-stable] assert_instr: [fmulx] - safety: - unsafe: [neon] + safety: safe types: - float32x2_t - float32x4_t @@ -5476,8 +5290,7 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 assert_instr: [fmulx] - safety: - unsafe: [neon] + safety: safe types: - float16x4_t - float16x8_t @@ -5495,8 +5308,7 @@ intrinsics: return_type: "{type[1]}" attr: [*neon-stable] assert_instr: [fmulx] - safety: - unsafe: [neon] + safety: safe types: - ["s_f32", "f32"] - ["d_f64", "f64"] @@ -5516,8 +5328,7 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 assert_instr: [fmulx] - safety: - unsafe: [neon] + safety: safe types: - ["h_f16", "f16"] compose: @@ -5537,8 +5348,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['2']] - *neon-stable static_defs: ["const LANE: i32"] - safety: - unsafe: [neon] + safety: safe types: - float64x1_t compose: @@ -5562,8 +5372,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['2']] - *neon-stable static_defs: ["const LANE: i32"] - safety: - unsafe: [neon] + safety: safe types: - ["q_lane_f64", float64x2_t, float64x1_t, "q_f64", '[LANE as u32, LANE as u32]'] compose: @@ -5586,8 +5395,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['2']] - *neon-stable static_defs: ["const LANE: i32"] - safety: - unsafe: [neon] + safety: safe types: - ["d_lane_f64", "f64", float64x1_t, "d_f64", 'LANE as u32'] compose: @@ -5609,8 +5417,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['2']] - *neon-stable static_defs: ["const LANE: i32"] - safety: - unsafe: [neon] + safety: safe types: - [float64x1_t, float64x2_t] compose: @@ -5634,8 +5441,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['2']] - *neon-stable static_defs: ["const LANE: i32"] - safety: - unsafe: [neon] + safety: safe types: - ['_lane_f32', float32x2_t, float32x2_t, '1', '_f32', '[LANE as u32, LANE as u32]'] - ['_laneq_f32', float32x2_t, float32x4_t, '2', '_f32', '[LANE as u32, LANE as u32]'] @@ -5664,8 +5470,7 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 static_defs: ["const LANE: i32"] - safety: - unsafe: [neon] + safety: safe types: - ['_lane_f16', float16x4_t, float16x4_t, '2', '_f16', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - ['_laneq_f16', float16x4_t, float16x8_t, '3', '_f16', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] @@ -5692,8 +5497,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['2']] - *neon-stable static_defs: ["const LANE: i32"] - safety: - unsafe: [neon] + safety: safe types: - ['s_lane_f32', f32, float32x2_t, '1', 's_f32', 'LANE as u32'] - ['s_laneq_f32', f32, float32x4_t, '2', 's_f32', 'LANE as u32'] @@ -5719,8 +5523,7 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 static_defs: ["const LANE: i32"] - safety: - unsafe: [neon] + safety: safe types: - ['h_lane_f16', f16, float16x4_t, '2', 'h_f16', "LANE as u32"] - ['h_laneq_f16', f16, float16x8_t, '3', 'h_f16', "LANE as u32"] @@ -5743,8 +5546,7 @@ intrinsics: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmulx]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - [float16x4_t, "f16"] - [float16x8_t, "f16"] @@ -5761,8 +5563,7 @@ intrinsics: attr: - *neon-stable assert_instr: [fmadd] - safety: - unsafe: [neon] + safety: safe types: - float64x1_t compose: @@ -5772,7 +5573,7 @@ intrinsics: links: - link: "llvm.fma.{neon_type}" arch: aarch64,arm64ec - - FnCall: ["_vfma{neon_type.no}", [b, c, a]] + - FnCall: ["_vfma{neon_type.no}", [b, c, a], [], true] - name: "vfma{neon_type.no}" doc: Floating-point fused Multiply-Add to accumulator(vector) @@ -5781,8 +5582,7 @@ intrinsics: attr: - *neon-stable assert_instr: [fmla] - safety: - unsafe: [neon] + safety: safe types: - float64x2_t compose: @@ -5792,7 +5592,7 @@ intrinsics: links: - link: "llvm.fma.{neon_type}" arch: aarch64,arm64ec - - FnCall: ["_vfma{neon_type.no}", [b, c, a]] + - FnCall: ["_vfma{neon_type.no}", [b, c, a], [], true] - name: "vfma_n_f64" doc: Floating-point fused Multiply-Add to accumulator(vector) @@ -5801,8 +5601,7 @@ intrinsics: attr: - *neon-stable assert_instr: [fmadd] - safety: - unsafe: [neon] + safety: safe types: - [float64x1_t, f64] compose: @@ -5824,8 +5623,7 @@ intrinsics: - - 'feature = "neon_intrinsics"' - 'since = "1.59.0"' assert_instr: [fmla] - safety: - unsafe: [neon] + safety: safe types: - [float64x2_t, f64] compose: @@ -5845,8 +5643,7 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 assert_instr: [fmla] - safety: - unsafe: [neon] + safety: safe types: - [float16x4_t, f16] - [float16x8_t, f16] @@ -5865,8 +5662,7 @@ intrinsics: return_type: "{neon_type}" attr: [*neon-stable] assert_instr: [fdiv] - safety: - unsafe: [neon] + safety: safe types: - float32x2_t - float32x4_t @@ -5883,8 +5679,7 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 assert_instr: [fdiv] - safety: - unsafe: [neon] + safety: safe types: - float16x4_t - float16x8_t @@ -5899,8 +5694,7 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 assert_instr: [nop] - safety: - unsafe: [neon] + safety: safe types: - [f16, 'h'] compose: @@ -5912,8 +5706,7 @@ intrinsics: return_type: "{neon_type}" attr: [*neon-stable] assert_instr: [fsub] - safety: - unsafe: [neon] + safety: safe types: - float64x1_t - float64x2_t @@ -5926,8 +5719,7 @@ intrinsics: return_type: "{type[1]}" attr: [*neon-stable] assert_instr: [nop] - safety: - unsafe: [neon] + safety: safe types: - ['d_s64', 'i64'] - ['d_u64', 'u64'] @@ -5942,8 +5734,7 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 assert_instr: [nop] - safety: - unsafe: [neon] + safety: safe types: - ['h_f16', 'f16'] compose: @@ -5959,8 +5750,7 @@ intrinsics: - - 'feature = "neon_intrinsics"' - 'since = "1.59.0"' assert_instr: [faddp] - safety: - unsafe: [neon] + safety: safe types: - [float32x2_t, f32] - [float32x4_t, f32] @@ -5978,8 +5768,7 @@ intrinsics: return_type: "{type[1]}" attr: [*neon-stable] assert_instr: [saddlv] - safety: - unsafe: [neon] + safety: safe types: - [int16x4_t, i32] - [int16x8_t, i32] @@ -5997,8 +5786,7 @@ intrinsics: return_type: "i64" attr: [*neon-stable] assert_instr: [saddlp] - safety: - unsafe: [neon] + safety: safe types: - int32x2_t compose: @@ -6014,8 +5802,7 @@ intrinsics: return_type: "{type[1]}" attr: [*neon-stable] assert_instr: [uaddlv] - safety: - unsafe: [neon] + safety: safe types: - [uint16x4_t, u32, i32] - [uint16x8_t, u32, i32] @@ -6026,7 +5813,7 @@ intrinsics: links: - link: "llvm.aarch64.neon.uaddlv.{type[2]}.{neon_type[0]}" arch: aarch64,arm64ec - - FnCall: ['_vaddlv{neon_type[0].no}', ['a']] + - FnCall: ['_vaddlv{neon_type[0].no}', ['a'], [], true] - name: "vaddlv{neon_type[0].no}" doc: Unsigned Add Long across Vector @@ -6034,8 +5821,7 @@ intrinsics: return_type: "{type[1]}" attr: [*neon-stable] assert_instr: [uaddlp] - safety: - unsafe: [neon] + safety: safe types: - [uint32x2_t, u64, i64] compose: @@ -6044,7 +5830,7 @@ intrinsics: links: - link: "llvm.aarch64.neon.uaddlv.{type[2]}.{neon_type[0]}" arch: aarch64,arm64ec - - FnCall: ['_vaddlv{neon_type[0].no}', ['a']] + - FnCall: ['_vaddlv{neon_type[0].no}', ['a'], [], true] - name: "vsubw_high{neon_type[1].noq}" doc: Signed Subtract Wide @@ -6052,8 +5838,7 @@ intrinsics: return_type: "{neon_type[0]}" attr: [*neon-stable] assert_instr: [ssubw] - safety: - unsafe: [neon] + safety: safe types: - [int16x8_t, int8x16_t, int8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]'] - [int32x4_t, int16x8_t, int16x4_t, '[4, 5, 6, 7]'] @@ -6074,8 +5859,7 @@ intrinsics: return_type: "{neon_type[0]}" attr: [*neon-stable] assert_instr: [usubw] - safety: - unsafe: [neon] + safety: safe types: - [uint16x8_t, uint8x16_t, uint8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]'] - [uint32x4_t, uint16x8_t, uint16x4_t, '[4, 5, 6, 7]'] @@ -6096,8 +5880,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: [*neon-stable] assert_instr: [ssubl] - safety: - unsafe: [neon] + safety: safe types: - [int8x16_t, int16x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]', int8x8_t] - [int16x8_t, int32x4_t, '[4, 5, 6, 7]', int16x4_t] @@ -6127,8 +5910,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: [*neon-stable] assert_instr: [usubl] - safety: - unsafe: [neon] + safety: safe types: - [uint8x16_t, uint16x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]', uint8x8_t] - [uint16x8_t, uint32x4_t, '[4, 5, 6, 7]', uint16x4_t] @@ -6160,8 +5942,7 @@ intrinsics: - FnCall: [target_feature, ['enable = "neon,sha3"']] - FnCall: [stable, ['feature = "stdarch_neon_sha3"', 'since = "1.79.0"']] assert_instr: [bcax] - safety: - unsafe: [neon] + safety: safe types: - int8x16_t - int16x8_t @@ -6182,8 +5963,7 @@ intrinsics: - FnCall: [target_feature, ['enable = "neon,sha3"']] - FnCall: [stable, ['feature = "stdarch_neon_sha3"', 'since = "1.79.0"']] assert_instr: [bcax] - safety: - unsafe: [neon] + safety: safe types: - uint8x16_t - uint16x8_t @@ -6204,8 +5984,7 @@ intrinsics: - FnCall: [target_feature, ['enable = "neon,fcma"']] - *neon-unstable-fcma assert_instr: [fcadd] - safety: - unsafe: [neon] + safety: safe types: - float32x2_t - float32x4_t @@ -6224,9 +6003,8 @@ intrinsics: attr: - FnCall: [target_feature, ['enable = "neon,fcma"']] - *neon-unstable-fcma - assert_instr: [fcadd] - safety: - unsafe: [neon] + assert_instr: [fcadd] + safety: safe types: - float32x2_t - float32x4_t @@ -6247,8 +6025,7 @@ intrinsics: - *enable-fcma - *neon-unstable-f16 assert_instr: [fcadd] - safety: - unsafe: [neon] + safety: safe types: - float16x4_t - float16x8_t @@ -6268,8 +6045,7 @@ intrinsics: - *enable-fcma - *neon-unstable-f16 assert_instr: [fcadd] - safety: - unsafe: [neon] + safety: safe types: - float16x4_t - float16x8_t @@ -6288,8 +6064,7 @@ intrinsics: - FnCall: [target_feature, ['enable = "neon,fcma"']] - *neon-unstable-fcma assert_instr: [fcmla] - safety: - unsafe: [neon] + safety: safe types: - float32x2_t - float32x4_t @@ -6310,8 +6085,7 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 assert_instr: [fcmla] - safety: - unsafe: [neon] + safety: safe types: - float16x4_t - float16x8_t @@ -6330,8 +6104,7 @@ intrinsics: - FnCall: [target_feature, ['enable = "neon,fcma"']] - *neon-unstable-fcma assert_instr: [fcmla] - safety: - unsafe: [neon] + safety: safe types: - float32x2_t - float32x4_t @@ -6352,8 +6125,7 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 assert_instr: [fcmla] - safety: - unsafe: [neon] + safety: safe types: - float16x4_t - float16x8_t @@ -6372,8 +6144,7 @@ intrinsics: - FnCall: [target_feature, ['enable = "neon,fcma"']] - *neon-unstable-fcma assert_instr: [fcmla] - safety: - unsafe: [neon] + safety: safe types: - float32x2_t - float32x4_t @@ -6395,8 +6166,7 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 assert_instr: [fcmla] - safety: - unsafe: [neon] + safety: safe types: - float16x4_t - float16x8_t @@ -6417,8 +6187,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['3']] - *neon-unstable-fcma static_defs: ["const LANE: i32"] - safety: - unsafe: [neon] + safety: safe types: - [float32x2_t, float32x4_t, '[2 * LANE as u32, 2 * LANE as u32 + 1]'] - [float32x4_t, float32x4_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]'] @@ -6441,8 +6210,7 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 static_defs: ["const LANE: i32"] - safety: - unsafe: [neon] + safety: safe types: - [float16x4_t, float16x8_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]'] - [float16x8_t, float16x8_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]'] @@ -6464,8 +6232,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['3']] - *neon-unstable-fcma static_defs: ["const LANE: i32"] - safety: - unsafe: [neon] + safety: safe types: - [float32x2_t, float32x4_t, '[2 * LANE as u32, 2 * LANE as u32 + 1]'] - [float32x4_t, float32x4_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]'] @@ -6488,8 +6255,7 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 static_defs: ["const LANE: i32"] - safety: - unsafe: [neon] + safety: safe types: - [float16x4_t, float16x8_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]'] - [float16x8_t, float16x8_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]'] @@ -6511,8 +6277,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['3']] - *neon-unstable-fcma static_defs: ["const LANE: i32"] - safety: - unsafe: [neon] + safety: safe types: - [float32x2_t, float32x2_t, '[2 * LANE as u32, 2 * LANE as u32 + 1]'] - [float32x4_t, float32x2_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]'] @@ -6535,8 +6300,7 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 static_defs: ["const LANE: i32"] - safety: - unsafe: [neon] + safety: safe types: - [float16x4_t, float16x4_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]'] - [float16x8_t, float16x4_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]'] @@ -6556,8 +6320,7 @@ intrinsics: - FnCall: [target_feature, ['enable = "neon,fcma"']] - *neon-unstable-fcma assert_instr: [fcmla] - safety: - unsafe: [neon] + safety: safe types: - float32x2_t - float32x4_t @@ -6579,8 +6342,7 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 assert_instr: [fcmla] - safety: - unsafe: [neon] + safety: safe types: - float16x4_t - float16x8_t @@ -6602,8 +6364,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['3']] - *neon-unstable-fcma static_defs: ["const LANE: i32"] - safety: - unsafe: [neon] + safety: safe types: - [float32x2_t, float32x4_t, '[2 * LANE as u32, 2 * LANE as u32 + 1]'] - [float32x4_t, float32x4_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]'] @@ -6626,8 +6387,7 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 static_defs: ["const LANE: i32"] - safety: - unsafe: [neon] + safety: safe types: - [float16x4_t, float16x8_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]'] - [float16x8_t, float16x8_t, @@ -6651,8 +6411,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['3']] - *neon-unstable-fcma static_defs: ["const LANE: i32"] - safety: - unsafe: [neon] + safety: safe types: - [float32x2_t, float32x2_t, '[2 * LANE as u32, 2 * LANE as u32 + 1]', '_rot180_lane_f32'] - [float32x4_t, float32x2_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]', 'q_rot180_lane_f32'] @@ -6675,8 +6434,7 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 static_defs: ["const LANE: i32"] - safety: - unsafe: [neon] + safety: safe types: - [float16x4_t, float16x4_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]', '_rot180_lane_f16'] - [float16x8_t, float16x4_t, @@ -6700,8 +6458,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['3']] - *neon-unstable-fcma static_defs: ["const LANE: i32"] - safety: - unsafe: [neon] + safety: safe types: - [float32x2_t, float32x4_t, '[2 * LANE as u32, 2 * LANE as u32 + 1]'] - [float32x4_t, float32x4_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]'] @@ -6724,8 +6481,7 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 static_defs: ["const LANE: i32"] - safety: - unsafe: [neon] + safety: safe types: - [float16x4_t, float16x8_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]'] - [float16x8_t, float16x8_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]'] @@ -6747,8 +6503,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['3']] - *neon-unstable-fcma static_defs: ["const LANE: i32"] - safety: - unsafe: [neon] + safety: safe types: - [float32x2_t, float32x2_t, '[2 * LANE as u32, 2 * LANE as u32 + 1]'] - [float32x4_t, float32x2_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]'] @@ -6772,8 +6527,7 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 static_defs: ["const LANE: i32"] - safety: - unsafe: [neon] + safety: safe types: - [float16x4_t, float16x4_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]'] - [float16x8_t, float16x4_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]'] @@ -6795,8 +6549,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['3']] - *neon-unstable-fcma static_defs: ["const LANE: i32"] - safety: - unsafe: [neon] + safety: safe types: - [float32x2_t, float32x2_t, '[2 * LANE as u32, 2 * LANE as u32 + 1]'] - [float32x4_t, float32x2_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]'] @@ -6817,8 +6570,7 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 static_defs: ["const LANE: i32"] - safety: - unsafe: [neon] + safety: safe types: - [float16x4_t, float16x4_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]'] - [float16x8_t, float16x4_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]'] @@ -6837,8 +6589,7 @@ intrinsics: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sdot, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['3']] - FnCall: [unstable, ['feature = "stdarch_neon_dotprod"', 'issue = "117224"']] - safety: - unsafe: [neon] + safety: safe types: - [int32x2_t, int8x8_t, int8x16_t, int32x4_t, '[LANE as u32, LANE as u32]'] - [int32x4_t, int8x16_t, int8x16_t, int32x4_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] @@ -6868,8 +6619,7 @@ intrinsics: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [udot, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['3']] - FnCall: [unstable, ['feature = "stdarch_neon_dotprod"', 'issue = "117224"']] - safety: - unsafe: [neon] + safety: safe types: - [uint32x2_t, uint8x8_t, uint8x16_t, uint32x4_t, '[LANE as u32, LANE as u32]'] - [uint32x4_t, uint8x16_t, uint8x16_t, uint32x4_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] @@ -6895,8 +6645,7 @@ intrinsics: return_type: "{neon_type}" attr: [*neon-stable] assert_instr: [fmax] - safety: - unsafe: [neon] + safety: safe types: - float64x1_t - float64x2_t @@ -6916,8 +6665,7 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 assert_instr: [fmax] - safety: - unsafe: [neon] + safety: safe types: - f16 compose: @@ -6935,8 +6683,7 @@ intrinsics: return_type: "{neon_type}" attr: [*neon-stable] assert_instr: [fmaxnm] - safety: - unsafe: [neon] + safety: safe types: - float64x1_t - float64x2_t @@ -6956,8 +6703,7 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 assert_instr: [fmaxnm] - safety: - unsafe: [neon] + safety: safe types: - f16 compose: @@ -6976,8 +6722,7 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 assert_instr: [fminnm] - safety: - unsafe: [neon] + safety: safe types: - f16 compose: @@ -6994,8 +6739,7 @@ intrinsics: return_type: "{type[1]}" attr: [*neon-stable] assert_instr: [fmaxnmp] - safety: - unsafe: [neon] + safety: safe types: - [float32x2_t, f32] - [float64x2_t, f64] @@ -7012,8 +6756,7 @@ intrinsics: return_type: "{type[1]}" attr: [*neon-stable] assert_instr: [fmaxnmv] - safety: - unsafe: [neon] + safety: safe types: - [float32x4_t, f32] compose: @@ -7032,8 +6775,7 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 assert_instr: [fmaxnmv] - safety: - unsafe: [neon] + safety: safe types: - [float16x4_t, f16] - [float16x8_t, f16] @@ -7053,8 +6795,7 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 assert_instr: [fminnmv] - safety: - unsafe: [neon] + safety: safe types: - [float16x4_t, f16] - [float16x8_t, f16] @@ -7074,8 +6815,7 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 assert_instr: [fmaxv] - safety: - unsafe: [neon] + safety: safe types: - [float16x4_t, f16] - [float16x8_t, f16] @@ -7094,8 +6834,7 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 assert_instr: [fminv] - safety: - unsafe: [neon] + safety: safe types: - [float16x4_t, f16] - [float16x8_t, f16] @@ -7112,8 +6851,7 @@ intrinsics: return_type: "{type[2]}" attr: [*neon-stable] assert_instr: [fmaxp] - safety: - unsafe: [neon] + safety: safe types: - ["s_f32", float32x2_t, f32] - ["qd_f64", float64x2_t, f64] @@ -7130,8 +6868,7 @@ intrinsics: return_type: "{neon_type}" attr: [*neon-stable] assert_instr: [fmin] - safety: - unsafe: [neon] + safety: safe types: - float64x1_t - float64x2_t @@ -7151,8 +6888,7 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 assert_instr: [fmin] - safety: - unsafe: [neon] + safety: safe types: - f16 compose: @@ -7169,8 +6905,7 @@ intrinsics: return_type: "{neon_type}" attr: [*neon-stable] assert_instr: [fminnm] - safety: - unsafe: [neon] + safety: safe types: - float64x1_t - float64x2_t @@ -7188,8 +6923,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fminnmp]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [float32x2_t, "f32"] - [float64x2_t, "f64"] @@ -7207,8 +6941,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fminnmv]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [float32x4_t, "f32"] compose: @@ -7224,8 +6957,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: [*neon-stable] assert_instr: [sxtl2] - safety: - unsafe: [neon] + safety: safe types: - [int8x16_t, int16x8_t, int8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]'] - [int16x8_t, int32x4_t, int16x4_t, '[4, 5, 6, 7]'] @@ -7243,8 +6975,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: [*neon-stable] assert_instr: [uxtl2] - safety: - unsafe: [neon] + safety: safe types: - [uint8x16_t, uint16x8_t, uint8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]'] - [uint16x8_t, uint32x4_t, uint16x4_t, '[4, 5, 6, 7]'] @@ -7262,8 +6993,7 @@ intrinsics: return_type: "{type}" attr: [*neon-stable] assert_instr: [faddp] - safety: - unsafe: [neon] + safety: safe types: - float32x4_t - float64x2_t @@ -7283,8 +7013,7 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 assert_instr: [faddp] - safety: - unsafe: [neon] + safety: safe types: - float16x8_t compose: @@ -7303,8 +7032,7 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 assert_instr: [fmaxp] - safety: - unsafe: [neon] + safety: safe types: - float16x4_t - float16x8_t @@ -7324,8 +7052,7 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 assert_instr: [fmaxnmp] - safety: - unsafe: [neon] + safety: safe types: - float16x4_t - float16x8_t @@ -7345,8 +7072,7 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 assert_instr: [fminp] - safety: - unsafe: [neon] + safety: safe types: - float16x4_t - float16x8_t @@ -7366,8 +7092,7 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 assert_instr: [fminnmp] - safety: - unsafe: [neon] + safety: safe types: - float16x4_t - float16x8_t @@ -7385,8 +7110,7 @@ intrinsics: return_type: "{type[2]}" attr: [*neon-stable] assert_instr: [nop] - safety: - unsafe: [neon] + safety: safe types: - ["s_f32", float32x2_t, f32] - ["d_f64", float64x2_t, f64] @@ -7407,8 +7131,7 @@ intrinsics: return_type: "{type[2]}" attr: [*neon-stable] assert_instr: [fminp] - safety: - unsafe: [neon] + safety: safe types: - ["s_f32", float32x2_t, f32] - ["qd_f64", float64x2_t, f64] @@ -7426,8 +7149,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmull]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - ["i16", "i32"] compose: @@ -7442,8 +7164,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmull]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - ["i32", "i64"] compose: @@ -7460,8 +7181,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmull2]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [int16x8_t, int32x4_t, int16x4_t, '[4, 5, 6, 7]'] - [int32x4_t, int64x2_t, int32x2_t, '[2, 3]'] @@ -7477,8 +7197,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmull2]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [int16x8_t, "i16", int32x4_t, int16x4_t, '[4, 5, 6, 7]'] - [int32x4_t, "i32", int64x2_t, int32x2_t, '[2, 3]'] @@ -7496,8 +7215,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['2']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - ["i16", int16x4_t, "i32", 'h_lane_s16', 'h_s16'] - ["i32", int32x4_t, "i64", 's_laneq_s32', 's_s32'] @@ -7515,8 +7233,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['2']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - ["i16", int16x8_t, "i32"] compose: @@ -7533,8 +7250,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['2']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - ["i32", int32x2_t, "i64"] compose: @@ -7551,8 +7267,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['2']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [int16x8_t, int16x4_t, int32x4_t, int16x4_t, '[4, 5, 6, 7]', '[N as u32, N as u32, N as u32, N as u32]', '_high_lane_s16'] - [int32x4_t, int32x4_t, int64x2_t, int32x2_t, '[2, 3]', '[N as u32, N as u32]', '_high_laneq_s32'] @@ -7571,8 +7286,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['2']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [int32x4_t, int32x2_t, int64x2_t, int32x2_t, '[2, 3]', '[N as u32, N as u32]'] compose: @@ -7590,8 +7304,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['2']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [int16x8_t, int16x8_t, int32x4_t, int16x4_t, '[4, 5, 6, 7]', '[N as u32, N as u32, N as u32, N as u32]'] compose: @@ -7609,8 +7322,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['2']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [int16x4_t, int16x8_t, int32x4_t, '[N as u32, N as u32, N as u32, N as u32]'] compose: @@ -7627,8 +7339,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['2']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [int32x2_t, int32x4_t, int64x2_t, '[N as u32, N as u32]'] compose: @@ -7643,8 +7354,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlal2]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [int32x4_t, int16x8_t, int16x8_t, int32x4_t, _high_s16] - [int64x2_t, int32x4_t, int32x4_t, int64x2_t, _high_s32] @@ -7662,8 +7372,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['3']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [int32x4_t, int16x8_t, int16x4_t, int32x4_t, _high_lane_s16, '2'] - [int32x4_t, int16x8_t, int16x8_t, int32x4_t, _high_laneq_s16, '3'] @@ -7680,8 +7389,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlal]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - ["i32", "i16", "s16"] compose: @@ -7695,8 +7403,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlal]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - ["i64", "i32", "i32", "i64"] compose: @@ -7712,8 +7419,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['3']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const LANE: i32'] - safety: - unsafe: [neon] + safety: safe types: - ["i32", "i16", int16x4_t, "i32", h_lane_s16, '2', h_s16] - ["i32", "i16", int16x8_t, "i32", h_laneq_s16, '3', h_s16] @@ -7732,8 +7438,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['3']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [int32x4_t, int16x4_t, int16x8_t, int32x4_t] compose: @@ -7749,8 +7454,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['3']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [int64x2_t, int32x2_t, int32x4_t, int64x2_t] compose: @@ -7764,8 +7468,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlsl2]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [int32x4_t, int16x8_t, int16x8_t, int32x4_t, _high_s16] - [int64x2_t, int32x4_t, int32x4_t, int64x2_t, _high_s32] @@ -7783,8 +7486,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['3']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [int32x4_t, int16x8_t, int16x4_t, int32x4_t, '_high_lane_s16', '2'] - [int32x4_t, int16x8_t, int16x8_t, int32x4_t, '_high_laneq_s16', '3'] @@ -7801,8 +7503,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlsl]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - ["i32", "i16"] compose: @@ -7816,8 +7517,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlsl]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - ["i64", "i32", "i32", "i64"] compose: @@ -7833,8 +7533,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['3']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const LANE: i32'] - safety: - unsafe: [neon] + safety: safe types: - ["i32", "i16", int16x4_t, "i32", 'h_lane_s16', '2', 'h_s16'] - ["i32", "i16", int16x8_t, "i32", 'h_laneq_s16', '3', 'h_s16'] @@ -7853,8 +7552,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['3']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [int32x4_t, int16x4_t, int16x8_t, int32x4_t] compose: @@ -7870,8 +7568,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['3']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [int64x2_t, int32x2_t, int32x4_t, int64x2_t] compose: @@ -7885,8 +7582,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmulh]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - ["i16", "i16", "i16", int16x4_t, 'h_s16'] - ["i32", "i32", "i32", int32x2_t, 's_s32'] @@ -7904,8 +7600,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['2']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - ["i16", int16x4_t, "i16", '_lane_s16', '2'] - ["i16", int16x8_t, "i16", '_laneq_s16', '3'] @@ -7923,8 +7618,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['2']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - ["i32", int32x2_t, "i32", "_lane_s32", '1'] - ["i32", int32x4_t, "i32", "_laneq_s32", '2'] @@ -7940,8 +7634,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqxtn2]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [int8x8_t, int16x8_t, int8x16_t, '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]'] - [int16x4_t, int32x4_t, int16x8_t, '[0, 1, 2, 3, 4, 5, 6, 7]'] @@ -7956,8 +7649,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [uqxtn2]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [uint8x8_t, uint16x8_t, uint8x16_t, '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]'] - [uint16x4_t, uint32x4_t, uint16x8_t, '[0, 1, 2, 3, 4, 5, 6, 7]'] @@ -7972,8 +7664,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqxtn]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - ["i16", "i8", 'h_s16', s16] - ["i32", "i16", 's_s32', s32] @@ -7987,8 +7678,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [uqxtn]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - ["u16", "u8", 'h_u16', 'u16'] - ["u32", "u16", 's_u32', 'u32'] @@ -8002,8 +7692,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqxtn]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - ["i64", "i32"] compose: @@ -8020,8 +7709,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [uqxtn]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - ["u64", "u32"] compose: @@ -8038,8 +7726,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqxtun]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - ["i16", "u8", 'h_s16', s16] - ["i32", "u16", 's_s32', s32] @@ -8054,8 +7741,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqxtun2]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [uint8x8_t, int16x8_t, uint8x16_t, s16, '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]'] - [uint16x4_t, int32x4_t, uint16x8_t, s32, '[0, 1, 2, 3, 4, 5, 6, 7]'] @@ -8070,8 +7756,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqrdmulh]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - ["i16", 'h_s16', 's16'] - ["i32", 's_s32', 's32'] @@ -8087,8 +7772,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['2']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const LANE: i32'] - safety: - unsafe: [neon] + safety: safe types: - ["i16", int16x4_t, 'h_lane_s16', 'h_s16', '2'] - ["i16", int16x8_t, 'h_laneq_s16', 'h_s16', '3'] @@ -8106,8 +7790,7 @@ intrinsics: - FnCall: [target_feature, ['enable = "rdm"']] - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqrdmlah]]}]] - FnCall: [stable, ['feature = "rdm_intrinsics"', 'since = "1.62.0"']] - safety: - unsafe: [neon] + safety: safe types: - int16x4_t - int16x8_t @@ -8128,8 +7811,7 @@ intrinsics: - FnCall: [target_feature, ['enable = "rdm"']] - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqrdmlah]]}]] - FnCall: [stable, ['feature = "rdm_intrinsics"', 'since = "1.62.0"']] - safety: - unsafe: [neon] + safety: safe types: - ["i16", int16x4_t, s16, 'h_s16'] - ["i32", int32x2_t, s32, 's_s32'] @@ -8149,8 +7831,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['3']] - FnCall: [stable, ['feature = "rdm_intrinsics"', 'since = "1.62.0"']] static_defs: ['const LANE: i32'] - safety: - unsafe: [neon] + safety: safe types: - [_lane_s16, int16x4_t, int16x4_t, int16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - [_laneq_s16, int16x4_t, int16x4_t, int16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] @@ -8175,8 +7856,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['3']] - FnCall: [stable, ['feature = "rdm_intrinsics"', 'since = "1.62.0"']] static_defs: ['const LANE: i32'] - safety: - unsafe: [neon] + safety: safe types: - ["i16", int16x4_t, '2', "h_s16", h_lane_s16, h_s16] - ["i16", int16x8_t, '3', "h_s16", h_laneq_s16, h_s16] @@ -8194,8 +7874,7 @@ intrinsics: - FnCall: [target_feature, ['enable = "rdm"']] - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqrdmlsh]]}]] - FnCall: [stable, ['feature = "rdm_intrinsics"', 'since = "1.62.0"']] - safety: - unsafe: [neon] + safety: safe types: - int16x4_t - int16x8_t @@ -8216,8 +7895,7 @@ intrinsics: - FnCall: [target_feature, ['enable = "rdm"']] - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqrdmlsh]]}]] - FnCall: [stable, ['feature = "rdm_intrinsics"', 'since = "1.62.0"']] - safety: - unsafe: [neon] + safety: safe types: - ["i16", "h_s16", int16x4_t, s16] - ["i32", "s_s32", int32x2_t, s32] @@ -8237,8 +7915,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['3']] - FnCall: [stable, ['feature = "rdm_intrinsics"', 'since = "1.62.0"']] static_defs: ['const LANE: i32'] - safety: - unsafe: [neon] + safety: safe types: - [_lane_s16, int16x4_t, int16x4_t, int16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - [_laneq_s16, int16x4_t, int16x4_t, int16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] @@ -8263,8 +7940,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['3']] - FnCall: [stable, ['feature = "rdm_intrinsics"', 'since = "1.62.0"']] static_defs: ['const LANE: i32'] - safety: - unsafe: [neon] + safety: safe types: - ["i16", int16x4_t, '2', h_lane_s16, h_s16] - ["i16", int16x8_t, '3', h_laneq_s16, h_s16] @@ -8281,8 +7957,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqrshl]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - ['s_s32', "i32"] - ['d_s64', "i64"] @@ -8300,8 +7975,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqrshl]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - ["i8", 'b_s8', int8x8_t, s8] - ["i16", 'h_s16', int16x4_t, s16] @@ -8317,8 +7991,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [uqrshl]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - ["u32", "i32", 's_u32'] - ["u64", "i64", 'd_u64'] @@ -8336,8 +8009,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [uqrshl]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - ["u8", "i8", "b_u8", uint8x8_t, int8x8_t, s8] - ["u16", "i16", "h_u16", uint16x4_t, int16x4_t, s16] @@ -8355,8 +8027,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['1']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - ["i16", "i8", 'h_n_s16', 'N >= 1 && N <= 8', int16x8_t, q_n_s16] - ["i32", "i16", 's_n_s32', 'N >= 1 && N <= 16', int32x4_t, q_n_s32] @@ -8375,8 +8046,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['2']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [int8x8_t, int16x8_t, int8x16_t, '_high_n_s16', '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]', 'N >= 1 && N <= 8'] - [int16x4_t, int32x4_t, int16x8_t, '_high_n_s32', '[0, 1, 2, 3, 4, 5, 6, 7]', 'N >= 1 && N <= 16'] @@ -8394,8 +8064,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['1']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [h_n_u16, u16, u8, 'N >= 1 && N <= 8', uint16x8_t, q_n_u16, _n_u16] - [s_n_u32, u32, u16, 'N >= 1 && N <= 16', uint32x4_t, q_n_u32, _n_u32] @@ -8414,8 +8083,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['2']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [uint8x8_t, uint16x8_t, uint8x16_t, 'N >= 1 && N <= 8', '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]'] - [uint16x4_t, uint32x4_t, uint16x8_t, 'N >= 1 && N <= 16', '[0, 1, 2, 3, 4, 5, 6, 7]'] @@ -8439,8 +8107,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['1']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [h_n_s16, "i16", "u8", 'N >= 1 && N <= 8', int16x8_t, s16] - [s_n_s32, "i32", "u16", 'N >= 1 && N <= 16', int32x4_t, s32] @@ -8467,8 +8134,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['2']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [uint8x8_t, int16x8_t, uint8x16_t, 'N >= 1 && N <= 8', s16, '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]'] - [uint16x4_t, int32x4_t, uint16x8_t, 'N >= 1 && N <= 16', s32, '[0, 1, 2, 3, 4, 5, 6, 7]'] @@ -8490,8 +8156,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqshl]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - i64 compose: @@ -8508,8 +8173,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqshl]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [b_s8, "i8", int8x8_t] - [h_s16, "i16", int16x4_t] @@ -8533,8 +8197,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['1']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [b_n_s8, "i8", "3", s8] - [h_n_s16, "i16", "4", s16] @@ -8556,8 +8219,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [uqshl]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - ["u64", "i64"] compose: @@ -8574,8 +8236,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [uqshl]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [b_u8, "u8", "i8", uint8x8_t, int8x8_t] - [h_u16, "u16", "i16", uint16x4_t, int16x4_t] @@ -8599,8 +8260,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['1']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [b_n_u8, "u8", '3'] - [h_n_u16, "u16", '4'] @@ -8622,8 +8282,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['1']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - ["i64", "i32"] compose: @@ -8636,7 +8295,7 @@ intrinsics: links: - link: "llvm.aarch64.neon.sqshrn.{type[1]}" arch: aarch64,arm64ec - - FnCall: ["_vqshrnd_n_s64", [a, N]] + - FnCall: ["_vqshrnd_n_s64", [a, N], [], true] - name: "vqshrn{type[0]}" doc: "Signed saturating shift right narrow" @@ -8647,8 +8306,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['1']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [h_n_s16, "i16", "i8", 'N >= 1 && N <= 8', s16] - [s_n_s32, "i32", "i16", 'N >= 1 && N <= 16', s32] @@ -8670,8 +8328,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['2']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [_high_n_s16, int8x8_t, int16x8_t, int8x16_t, 'N >= 1 && N <= 8', '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]', s16] - [_high_n_s32, int16x4_t, int32x4_t, int16x8_t, 'N >= 1 && N <= 16', '[0, 1, 2, 3, 4, 5, 6, 7]', s32] @@ -8693,8 +8350,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['1']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - ["u64", "u32"] compose: @@ -8707,7 +8363,7 @@ intrinsics: links: - link: "llvm.aarch64.neon.uqshrn.i32" arch: aarch64,arm64ec - - FnCall: ["_vqshrnd_n_u64", ["a", N]] + - FnCall: ["_vqshrnd_n_u64", ["a", N], [], true] - name: "vqshrn{type[0]}" doc: "Unsigned saturating shift right narrow" @@ -8718,8 +8374,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['1']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - ['h_n_u16', "u16", "u8", 'N >= 1 && N <= 8'] - ['s_n_u32', "u32", "u16", 'N >= 1 && N <= 16'] @@ -8741,8 +8396,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['2']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [_high_n_u16, uint8x8_t, uint16x8_t, uint8x16_t, 'N >= 1 && N <= 8', '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]'] - [_high_n_u32, uint16x4_t, uint32x4_t, uint16x8_t, 'N >= 1 && N <= 16', '[0, 1, 2, 3, 4, 5, 6, 7]'] @@ -8764,8 +8418,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['1']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [h_n_s16, "i16", "u8", 'N >= 1 && N <= 8', s16] - [s_n_s32, "i32", "u16", 'N >= 1 && N <= 16', s32] @@ -8788,8 +8441,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['2']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [uint8x8_t, int16x8_t, uint8x16_t, 'N >= 1 && N <= 8', '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]'] - [uint16x4_t, int32x4_t, uint16x8_t, 'N >= 1 && N <= 16', '[0, 1, 2, 3, 4, 5, 6, 7]'] @@ -8808,9 +8460,8 @@ intrinsics: return_type: "{type[1]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [usqadd]]}]] - - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: safe types: - [b_u8, "u8", "i8", s8] - [h_u16, "u16", "i16", s16] @@ -8830,8 +8481,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [usqadd]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [s_u32, "u32", "i32"] - [d_u64, "u64", "i64"] @@ -8849,8 +8499,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fsqrt]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - float32x2_t - float32x4_t @@ -8867,8 +8516,7 @@ intrinsics: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fsqrt]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - float16x4_t - float16x8_t @@ -8883,8 +8531,7 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 assert_instr: [fsqrt] - safety: - unsafe: [neon] + safety: safe types: - [f16, 'h_'] compose: @@ -8901,8 +8548,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [frsqrts]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [_f64, float64x1_t, v1f64] - [q_f64, float64x2_t, v2f64] @@ -8920,8 +8566,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [frsqrts]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [s_f32, "f32"] - [d_f64, "f64"] @@ -8941,8 +8586,7 @@ intrinsics: - *neon-fp16 - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [frsqrts]]}]] - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - [h_f16, "f16"] compose: @@ -8960,8 +8604,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [frecpe]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [_f64, float64x1_t, v1f64] - [q_f64, float64x2_t, v2f64] @@ -8979,8 +8622,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [frecpe]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [s_f32, "f32"] - [d_f64, "f64"] @@ -9000,8 +8642,7 @@ intrinsics: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [frecpe]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - [h_f16, "f16"] compose: @@ -9019,8 +8660,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [frecps]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [_f64, float64x1_t, v1f64] - [q_f64, float64x2_t, v2f64] @@ -9038,8 +8678,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [frecps]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [s_f32, "f32"] - [d_f64, "f64"] @@ -9059,8 +8698,7 @@ intrinsics: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [frecps]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - [h_f16, "f16"] compose: @@ -9078,8 +8716,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [frecpx]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [s_f32, "f32"] - [d_f64, "f64"] @@ -9099,8 +8736,7 @@ intrinsics: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [frecpx]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - [h_f16, "f16"] compose: @@ -9117,8 +8753,7 @@ intrinsics: return_type: "{type[1]}" attr: [*neon-stable] assert_instr: [nop] - safety: - unsafe: [neon] + safety: safe types: - [poly64x1_t, int64x1_t] - [poly64x1_t, uint64x1_t] @@ -9194,8 +8829,7 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 assert_instr: [nop] - safety: - unsafe: [neon] + safety: safe types: - [float64x1_t, float16x4_t] - [float16x4_t, float64x1_t] @@ -9213,8 +8847,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [srshl]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - "i64" compose: @@ -9231,8 +8864,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [urshl]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - ["u64", "i64"] compose: @@ -9251,8 +8883,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['1']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - ["i64", 'N >= 1 && N <= 64', '-N as i64'] compose: @@ -9268,8 +8899,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['1']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - "u64" compose: @@ -9285,8 +8915,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['2']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [int8x8_t, int16x8_t, int8x16_t, 'N >= 1 && N <= 8', '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]'] - [int16x4_t, int32x4_t, int16x8_t, 'N >= 1 && N <= 16', '[0, 1, 2, 3, 4, 5, 6, 7]'] @@ -9309,8 +8938,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [rsubhn2]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [int8x8_t, int16x8_t, int16x8_t, int8x16_t, '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]'] - [int16x4_t, int32x4_t, int32x4_t, int16x8_t, '[0, 1, 2, 3, 4, 5, 6, 7]'] @@ -9334,18 +8962,17 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['1', '3']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const LANE1: i32, const LANE2: i32'] - safety: - unsafe: [neon] - types: - - [int8x8_t, int8x8_t, int8x8_t, '3', '3', ' match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), _ => unreachable_unchecked(), }'] - - [int16x4_t, int16x4_t, int16x4_t, '2', '2', ' match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), _ => unreachable_unchecked(), }'] - - [int32x2_t, int32x2_t, int32x2_t, '1', '1', ' match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), }'] - - [uint8x8_t, uint8x8_t, uint8x8_t, '3', '3', ' match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), _ => unreachable_unchecked(), }'] - - [uint16x4_t, uint16x4_t, uint16x4_t, '2', '2', ' match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), _ => unreachable_unchecked(), }'] - - [uint32x2_t, uint32x2_t, uint32x2_t, '1', '1', ' match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), }'] - - [poly8x8_t, poly8x8_t, poly8x8_t, '3', '3', ' match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), _ => unreachable_unchecked(), }'] - - [poly16x4_t, poly16x4_t, poly16x4_t, '2', '2', ' match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), _ => unreachable_unchecked(), }'] - - [float32x2_t, float32x2_t, float32x2_t, '1', '1', ' match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), }'] + safety: safe + types: + - [int8x8_t, int8x8_t, int8x8_t, '3', '3', ' unsafe { match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] + - [int16x4_t, int16x4_t, int16x4_t, '2', '2', ' unsafe { match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] + - [int32x2_t, int32x2_t, int32x2_t, '1', '1', ' unsafe { match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] + - [uint8x8_t, uint8x8_t, uint8x8_t, '3', '3', ' unsafe { match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] + - [uint16x4_t, uint16x4_t, uint16x4_t, '2', '2', ' unsafe { match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] + - [uint32x2_t, uint32x2_t, uint32x2_t, '1', '1', ' unsafe { match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] + - [poly8x8_t, poly8x8_t, poly8x8_t, '3', '3', ' unsafe { match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] + - [poly16x4_t, poly16x4_t, poly16x4_t, '2', '2', ' unsafe { match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] + - [float32x2_t, float32x2_t, float32x2_t, '1', '1', ' unsafe { match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] compose: - FnCall: [static_assert_uimm_bits!, [LANE1, '{type[3]}']] - FnCall: [static_assert_uimm_bits!, [LANE2, '{type[4]}']] @@ -9360,17 +8987,16 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['1', '3']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const LANE1: i32, const LANE2: i32'] - safety: - unsafe: [neon] + safety: safe types: - - [int8x16_t, int8x8_t, int8x16_t, '4', '3', ' let b: int8x16_t = simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]);', 'match LANE1 & 0b1111 { 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32, 8, 9, 10, 11, 12, 13, 14, 15]), 8 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 16 + LANE2 as u32, 9, 10, 11, 12, 13, 14, 15]), 9 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 16 + LANE2 as u32, 10, 11, 12, 13, 14, 15]), 10 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 16 + LANE2 as u32, 11, 12, 13, 14, 15]), 11 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 16 + LANE2 as u32, 12, 13, 14, 15]), 12 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 16 + LANE2 as u32, 13, 14, 15]), 13 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16 + LANE2 as u32, 14, 15]), 14 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 16 + LANE2 as u32, 15]), 15 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16 + LANE2 as u32]), _ => unreachable_unchecked(), }'] - - [int16x8_t, int16x4_t, int16x8_t, '3', '2', ' let b: int16x8_t = simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7]);', 'match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), _ => unreachable_unchecked(), }'] - - [int32x4_t, int32x2_t, int32x4_t, '2', '1', ' let b: int32x4_t = simd_shuffle!(b, b, [0, 1, 2, 3]);', 'match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), _ => unreachable_unchecked(), }'] - - [uint8x16_t, uint8x8_t, uint8x16_t, '4', '3', ' let b: uint8x16_t = simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]);', 'match LANE1 & 0b1111 { 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32, 8, 9, 10, 11, 12, 13, 14, 15]), 8 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 16 + LANE2 as u32, 9, 10, 11, 12, 13, 14, 15]), 9 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 16 + LANE2 as u32, 10, 11, 12, 13, 14, 15]), 10 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 16 + LANE2 as u32, 11, 12, 13, 14, 15]), 11 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 16 + LANE2 as u32, 12, 13, 14, 15]), 12 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 16 + LANE2 as u32, 13, 14, 15]), 13 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16 + LANE2 as u32, 14, 15]), 14 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 16 + LANE2 as u32, 15]), 15 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16 + LANE2 as u32]), _ => unreachable_unchecked(), }'] - - [uint16x8_t, uint16x4_t, uint16x8_t, '3', '2', ' let b: uint16x8_t = simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7]);', 'match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), _ => unreachable_unchecked(), }'] - - [uint32x4_t, uint32x2_t, uint32x4_t, '2', '1', ' let b: uint32x4_t = simd_shuffle!(b, b, [0, 1, 2, 3]);', 'match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), _ => unreachable_unchecked(), }'] - - [poly8x16_t, poly8x8_t, poly8x16_t, '4', '3', ' let b: poly8x16_t = simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]);', 'match LANE1 & 0b1111 { 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32, 8, 9, 10, 11, 12, 13, 14, 15]), 8 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 16 + LANE2 as u32, 9, 10, 11, 12, 13, 14, 15]), 9 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 16 + LANE2 as u32, 10, 11, 12, 13, 14, 15]), 10 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 16 + LANE2 as u32, 11, 12, 13, 14, 15]), 11 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 16 + LANE2 as u32, 12, 13, 14, 15]), 12 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 16 + LANE2 as u32, 13, 14, 15]), 13 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16 + LANE2 as u32, 14, 15]), 14 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 16 + LANE2 as u32, 15]), 15 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16 + LANE2 as u32]), _ => unreachable_unchecked(), }'] - - [poly16x8_t, poly16x4_t, poly16x8_t, '3', '2', ' let b: poly16x8_t = simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7]);', 'match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), _ => unreachable_unchecked(), }'] + - [int8x16_t, int8x8_t, int8x16_t, '4', '3', ' let b: int8x16_t = unsafe { simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) };', 'unsafe { match LANE1 & 0b1111 { 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32, 8, 9, 10, 11, 12, 13, 14, 15]), 8 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 16 + LANE2 as u32, 9, 10, 11, 12, 13, 14, 15]), 9 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 16 + LANE2 as u32, 10, 11, 12, 13, 14, 15]), 10 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 16 + LANE2 as u32, 11, 12, 13, 14, 15]), 11 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 16 + LANE2 as u32, 12, 13, 14, 15]), 12 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 16 + LANE2 as u32, 13, 14, 15]), 13 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16 + LANE2 as u32, 14, 15]), 14 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 16 + LANE2 as u32, 15]), 15 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] + - [int16x8_t, int16x4_t, int16x8_t, '3', '2', ' let b: int16x8_t = unsafe { simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7]) };', 'unsafe { match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] + - [int32x4_t, int32x2_t, int32x4_t, '2', '1', ' let b: int32x4_t = unsafe { simd_shuffle!(b, b, [0, 1, 2, 3]) };', 'unsafe { match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] + - [uint8x16_t, uint8x8_t, uint8x16_t, '4', '3', ' let b: uint8x16_t = unsafe { simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) };', 'unsafe { match LANE1 & 0b1111 { 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32, 8, 9, 10, 11, 12, 13, 14, 15]), 8 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 16 + LANE2 as u32, 9, 10, 11, 12, 13, 14, 15]), 9 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 16 + LANE2 as u32, 10, 11, 12, 13, 14, 15]), 10 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 16 + LANE2 as u32, 11, 12, 13, 14, 15]), 11 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 16 + LANE2 as u32, 12, 13, 14, 15]), 12 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 16 + LANE2 as u32, 13, 14, 15]), 13 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16 + LANE2 as u32, 14, 15]), 14 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 16 + LANE2 as u32, 15]), 15 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] + - [uint16x8_t, uint16x4_t, uint16x8_t, '3', '2', ' let b: uint16x8_t = unsafe { simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7]) };', 'unsafe { match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] + - [uint32x4_t, uint32x2_t, uint32x4_t, '2', '1', ' let b: uint32x4_t = unsafe { simd_shuffle!(b, b, [0, 1, 2, 3]) };', 'unsafe { match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] + - [poly8x16_t, poly8x8_t, poly8x16_t, '4', '3', ' let b: poly8x16_t = unsafe { simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) };', 'unsafe { match LANE1 & 0b1111 { 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32, 8, 9, 10, 11, 12, 13, 14, 15]), 8 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 16 + LANE2 as u32, 9, 10, 11, 12, 13, 14, 15]), 9 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 16 + LANE2 as u32, 10, 11, 12, 13, 14, 15]), 10 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 16 + LANE2 as u32, 11, 12, 13, 14, 15]), 11 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 16 + LANE2 as u32, 12, 13, 14, 15]), 12 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 16 + LANE2 as u32, 13, 14, 15]), 13 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16 + LANE2 as u32, 14, 15]), 14 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 16 + LANE2 as u32, 15]), 15 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] + - [poly16x8_t, poly16x4_t, poly16x8_t, '3', '2', ' let b: poly16x8_t = unsafe { simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7]) };', 'unsafe { match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] compose: - FnCall: [static_assert_uimm_bits!, [LANE1, '{type[3]}']] - FnCall: [static_assert_uimm_bits!, [LANE2, '{type[4]}']] @@ -9386,22 +9012,21 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['1', '3']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const LANE1: i32, const LANE2: i32'] - safety: - unsafe: [neon] - types: - - [int8x16_t, int8x16_t, int8x16_t, '4', '4', ' match LANE1 & 0b1111 { 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32, 8, 9, 10, 11, 12, 13, 14, 15]), 8 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 16 + LANE2 as u32, 9, 10, 11, 12, 13, 14, 15]), 9 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 16 + LANE2 as u32, 10, 11, 12, 13, 14, 15]), 10 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 16 + LANE2 as u32, 11, 12, 13, 14, 15]), 11 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 16 + LANE2 as u32, 12, 13, 14, 15]), 12 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 16 + LANE2 as u32, 13, 14, 15]), 13 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16 + LANE2 as u32, 14, 15]), 14 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 16 + LANE2 as u32, 15]), 15 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16 + LANE2 as u32]), _ => unreachable_unchecked(), }'] - - [int16x8_t, int16x8_t, int16x8_t, '3', '3', ' match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), _ => unreachable_unchecked(), }'] - - [int32x4_t, int32x4_t, int32x4_t, '2', '2', ' match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), _ => unreachable_unchecked(), }'] - - [int64x2_t, int64x2_t, int64x2_t, '1', '1', ' match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), }'] - - [uint8x16_t, uint8x16_t, uint8x16_t, '4', '4', ' match LANE1 & 0b1111 { 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32, 8, 9, 10, 11, 12, 13, 14, 15]), 8 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 16 + LANE2 as u32, 9, 10, 11, 12, 13, 14, 15]), 9 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 16 + LANE2 as u32, 10, 11, 12, 13, 14, 15]), 10 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 16 + LANE2 as u32, 11, 12, 13, 14, 15]), 11 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 16 + LANE2 as u32, 12, 13, 14, 15]), 12 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 16 + LANE2 as u32, 13, 14, 15]), 13 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16 + LANE2 as u32, 14, 15]), 14 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 16 + LANE2 as u32, 15]), 15 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16 + LANE2 as u32]), _ => unreachable_unchecked(), }'] - - [uint16x8_t, uint16x8_t, uint16x8_t, '3', '3', ' match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), _ => unreachable_unchecked(), }'] - - [uint32x4_t, uint32x4_t, uint32x4_t, '2', '2', ' match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), _ => unreachable_unchecked(), }'] - - [uint64x2_t, uint64x2_t, uint64x2_t, '1', '1', ' match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), }'] - - [poly8x16_t, poly8x16_t, poly8x16_t, '4', '4', ' match LANE1 & 0b1111 { 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32, 8, 9, 10, 11, 12, 13, 14, 15]), 8 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 16 + LANE2 as u32, 9, 10, 11, 12, 13, 14, 15]), 9 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 16 + LANE2 as u32, 10, 11, 12, 13, 14, 15]), 10 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 16 + LANE2 as u32, 11, 12, 13, 14, 15]), 11 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 16 + LANE2 as u32, 12, 13, 14, 15]), 12 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 16 + LANE2 as u32, 13, 14, 15]), 13 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16 + LANE2 as u32, 14, 15]), 14 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 16 + LANE2 as u32, 15]), 15 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16 + LANE2 as u32]), _ => unreachable_unchecked(), }'] - - [poly16x8_t, poly16x8_t, poly16x8_t, '3', '3', ' match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), _ => unreachable_unchecked(), }'] - - [poly64x2_t, poly64x2_t, poly64x2_t, '1', '1', ' match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), }'] - - [float32x4_t, float32x4_t, float32x4_t, '2', '2', ' match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), _ => unreachable_unchecked(), }'] - - [float64x2_t, float64x2_t, float64x2_t, '1', '1', ' match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), }'] + safety: safe + types: + - [int8x16_t, int8x16_t, int8x16_t, '4', '4', ' unsafe { match LANE1 & 0b1111 { 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32, 8, 9, 10, 11, 12, 13, 14, 15]), 8 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 16 + LANE2 as u32, 9, 10, 11, 12, 13, 14, 15]), 9 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 16 + LANE2 as u32, 10, 11, 12, 13, 14, 15]), 10 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 16 + LANE2 as u32, 11, 12, 13, 14, 15]), 11 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 16 + LANE2 as u32, 12, 13, 14, 15]), 12 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 16 + LANE2 as u32, 13, 14, 15]), 13 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16 + LANE2 as u32, 14, 15]), 14 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 16 + LANE2 as u32, 15]), 15 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] + - [int16x8_t, int16x8_t, int16x8_t, '3', '3', ' unsafe { match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] + - [int32x4_t, int32x4_t, int32x4_t, '2', '2', ' unsafe { match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] + - [int64x2_t, int64x2_t, int64x2_t, '1', '1', ' unsafe { match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] + - [uint8x16_t, uint8x16_t, uint8x16_t, '4', '4', ' unsafe { match LANE1 & 0b1111 { 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32, 8, 9, 10, 11, 12, 13, 14, 15]), 8 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 16 + LANE2 as u32, 9, 10, 11, 12, 13, 14, 15]), 9 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 16 + LANE2 as u32, 10, 11, 12, 13, 14, 15]), 10 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 16 + LANE2 as u32, 11, 12, 13, 14, 15]), 11 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 16 + LANE2 as u32, 12, 13, 14, 15]), 12 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 16 + LANE2 as u32, 13, 14, 15]), 13 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16 + LANE2 as u32, 14, 15]), 14 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 16 + LANE2 as u32, 15]), 15 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] + - [uint16x8_t, uint16x8_t, uint16x8_t, '3', '3', ' unsafe { match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] + - [uint32x4_t, uint32x4_t, uint32x4_t, '2', '2', ' unsafe { match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] + - [uint64x2_t, uint64x2_t, uint64x2_t, '1', '1', ' unsafe { match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] + - [poly8x16_t, poly8x16_t, poly8x16_t, '4', '4', ' unsafe { match LANE1 & 0b1111 { 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32, 8, 9, 10, 11, 12, 13, 14, 15]), 8 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 16 + LANE2 as u32, 9, 10, 11, 12, 13, 14, 15]), 9 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 16 + LANE2 as u32, 10, 11, 12, 13, 14, 15]), 10 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 16 + LANE2 as u32, 11, 12, 13, 14, 15]), 11 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 16 + LANE2 as u32, 12, 13, 14, 15]), 12 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 16 + LANE2 as u32, 13, 14, 15]), 13 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16 + LANE2 as u32, 14, 15]), 14 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 16 + LANE2 as u32, 15]), 15 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] + - [poly16x8_t, poly16x8_t, poly16x8_t, '3', '3', ' unsafe { match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] + - [poly64x2_t, poly64x2_t, poly64x2_t, '1', '1', ' unsafe { match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] + - [float32x4_t, float32x4_t, float32x4_t, '2', '2', ' unsafe { match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] + - [float64x2_t, float64x2_t, float64x2_t, '1', '1', ' unsafe { match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] compose: - FnCall: [static_assert_uimm_bits!, [LANE1, '{type[3]}']] - FnCall: [static_assert_uimm_bits!, [LANE2, '{type[4]}']] @@ -9416,18 +9041,17 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['1', '3']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const LANE1: i32, const LANE2: i32'] - safety: - unsafe: [neon] - types: - - [int8x8_t, int8x16_t, int8x8_t, '3', '4', ' let a: int8x16_t = simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]);', 'match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32]), _ => unreachable_unchecked(), }'] - - [int16x4_t, int16x8_t, int16x4_t, '2', '3', ' let a: int16x8_t = simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]);', 'match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32]), _ => unreachable_unchecked(), }'] - - [int32x2_t, int32x4_t, int32x2_t, '1', '2', ' let a: int32x4_t = simd_shuffle!(a, a, [0, 1, 2, 3]);', 'match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32]), _ => unreachable_unchecked(), }'] - - [uint8x8_t, uint8x16_t, uint8x8_t, '3', '4', ' let a: uint8x16_t = simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]);', 'match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32]), _ => unreachable_unchecked(), }'] - - [uint16x4_t, uint16x8_t, uint16x4_t, '2', '3', ' let a: uint16x8_t = simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]);', 'match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32]), _ => unreachable_unchecked(), }'] - - [uint32x2_t, uint32x4_t, uint32x2_t, '1', '2', 'let a: uint32x4_t = simd_shuffle!(a, a, [0, 1, 2, 3]);', 'match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32]), _ => unreachable_unchecked(), }'] - - [poly8x8_t, poly8x16_t, poly8x8_t, '3', '4', ' let a: poly8x16_t = simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]);', 'match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32]), _ => unreachable_unchecked(), }'] - - [poly16x4_t, poly16x8_t, poly16x4_t, '2', '3', ' let a: poly16x8_t = simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]);', 'match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32]), _ => unreachable_unchecked(), }'] - - [float32x2_t, float32x4_t, float32x2_t, '1', '2', ' let a: float32x4_t = simd_shuffle!(a, a, [0, 1, 2, 3]);', 'match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32]), _ => unreachable_unchecked(), }'] + safety: safe + types: + - [int8x8_t, int8x16_t, int8x8_t, '3', '4', ' let a: int8x16_t = unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) };', 'unsafe { match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] + - [int16x4_t, int16x8_t, int16x4_t, '2', '3', ' let a: int16x8_t = unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]) };', 'unsafe { match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] + - [int32x2_t, int32x4_t, int32x2_t, '1', '2', ' let a: int32x4_t = unsafe { simd_shuffle!(a, a, [0, 1, 2, 3]) };', 'unsafe { match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] + - [uint8x8_t, uint8x16_t, uint8x8_t, '3', '4', ' let a: uint8x16_t = unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) };', 'unsafe { match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] + - [uint16x4_t, uint16x8_t, uint16x4_t, '2', '3', ' let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]) };', 'unsafe { match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] + - [uint32x2_t, uint32x4_t, uint32x2_t, '1', '2', 'let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [0, 1, 2, 3]) };', 'unsafe { match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] + - [poly8x8_t, poly8x16_t, poly8x8_t, '3', '4', ' let a: poly8x16_t = unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) };', 'unsafe { match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] + - [poly16x4_t, poly16x8_t, poly16x4_t, '2', '3', ' let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]) };', 'unsafe { match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] + - [float32x2_t, float32x4_t, float32x2_t, '1', '2', ' let a: float32x4_t = unsafe { simd_shuffle!(a, a, [0, 1, 2, 3]) };', 'unsafe { match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] compose: - FnCall: [static_assert_uimm_bits!, [LANE1, '{type[3]}']] - FnCall: [static_assert_uimm_bits!, [LANE2, '{type[4]}']] @@ -9443,13 +9067,12 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['1', '3']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const LANE1: i32, const LANE2: i32'] - safety: - unsafe: [neon] + safety: safe types: - - [int64x2_t, int64x1_t, 'let b: int64x2_t = simd_shuffle!(b, b, [0, 1]);', 'match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), }'] - - [uint64x2_t, uint64x1_t, 'let b: uint64x2_t = simd_shuffle!(b, b, [0, 1]);', 'match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), }'] - - [poly64x2_t, poly64x1_t, 'let b: poly64x2_t = simd_shuffle!(b, b, [0, 1]);', 'match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), }'] - - [float64x2_t, float64x1_t, ' let b: float64x2_t = simd_shuffle!(b, b, [0, 1]);', 'match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), }'] + - [int64x2_t, int64x1_t, ' let b: int64x2_t = unsafe { simd_shuffle!(b, b, [0, 1]) };', 'unsafe { match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] + - [uint64x2_t, uint64x1_t, ' let b: uint64x2_t = unsafe { simd_shuffle!(b, b, [0, 1]) };', 'unsafe { match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] + - [poly64x2_t, poly64x1_t, ' let b: poly64x2_t = unsafe { simd_shuffle!(b, b, [0, 1]) };', 'unsafe { match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] + - [float64x2_t, float64x1_t, ' let b: float64x2_t = unsafe { simd_shuffle!(b, b, [0, 1]) };', 'unsafe { match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] compose: - FnCall: [static_assert_uimm_bits!, [LANE1, '1']] - FnCall: [static_assert!, ['LANE2 == 0']] @@ -9465,10 +9088,9 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['1', '3']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const LANE1: i32, const LANE2: i32'] - safety: - unsafe: [neon] + safety: safe types: - - [float32x4_t, float32x2_t, ' let b: float32x4_t = simd_shuffle!(b, b, [0, 1, 2, 3]);', 'match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), _ => unreachable_unchecked(), }'] + - [float32x4_t, float32x2_t, ' let b: float32x4_t = unsafe { simd_shuffle!(b, b, [0, 1, 2, 3]) };', 'unsafe { match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), _ => unreachable_unchecked(), } }'] compose: - FnCall: [static_assert_uimm_bits!, [LANE1, 2]] - FnCall: [static_assert_uimm_bits!, [LANE2, 1]] @@ -9482,8 +9104,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - ["u64", float64x1_t] compose: @@ -9498,8 +9119,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['2']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const LANE: i32'] - safety: - unsafe: [neon] + safety: safe types: - ["f64", float64x1_t, float64x1_t] compose: @@ -9515,8 +9135,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['2']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const LANE: i32'] - safety: - unsafe: [neon] + safety: safe types: - ["f64", float64x2_t, float64x2_t] compose: @@ -9530,8 +9149,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sshl]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - "i64" compose: @@ -9549,8 +9167,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ushl]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - ["u64", "i64"] compose: @@ -9570,8 +9187,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['1']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [int8x16_t, int16x8_t, int8x8_t, 'N >= 0 && N <= 8', '[8, 9, 10, 11, 12, 13, 14, 15]'] - [int16x8_t, int32x4_t, int16x4_t, 'N >= 0 && N <= 16', '[4, 5, 6, 7]'] @@ -9590,8 +9206,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['1']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [uint8x16_t, uint16x8_t, uint8x8_t, 'N >= 0 && N <= 8', '[8, 9, 10, 11, 12, 13, 14, 15]'] - [uint16x8_t, uint32x4_t, uint16x4_t, 'N >= 0 && N <= 16', '[4, 5, 6, 7]'] @@ -9610,8 +9225,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['2']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [int8x8_t, int16x8_t, int8x16_t, 'N >= 1 && N <= 8', '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]'] - [int16x4_t, int32x4_t, int16x8_t, 'N >= 1 && N <= 16', '[0, 1, 2, 3, 4, 5, 6, 7]'] @@ -9635,8 +9249,7 @@ intrinsics: - FnCall: [target_feature, ['enable = "neon,sm4"']] - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sm3partw1]]}]] - FnCall: [unstable, ['feature = "stdarch_neon_sm4"', 'issue = "117226"']] - safety: - unsafe: [neon] + safety: safe types: - uint32x4_t compose: @@ -9654,8 +9267,7 @@ intrinsics: - FnCall: [target_feature, ['enable = "neon,sm4"']] - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sm3partw2]]}]] - FnCall: [unstable, ['feature = "stdarch_neon_sm4"', 'issue = "117226"']] - safety: - unsafe: [neon] + safety: safe types: - uint32x4_t compose: @@ -9673,8 +9285,7 @@ intrinsics: - FnCall: [target_feature, ['enable = "neon,sm4"']] - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sm3ss1]]}]] - FnCall: [unstable, ['feature = "stdarch_neon_sm4"', 'issue = "117226"']] - safety: - unsafe: [neon] + safety: safe types: - uint32x4_t compose: @@ -9692,8 +9303,7 @@ intrinsics: - FnCall: [target_feature, ['enable = "neon,sm4"']] - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sm4ekey]]}]] - FnCall: [unstable, ['feature = "stdarch_neon_sm4"', 'issue = "117226"']] - safety: - unsafe: [neon] + safety: safe types: - uint32x4_t compose: @@ -9711,8 +9321,7 @@ intrinsics: - FnCall: [target_feature, ['enable = "neon,sm4"']] - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sm4e]]}]] - FnCall: [unstable, ['feature = "stdarch_neon_sm4"', 'issue = "117226"']] - safety: - unsafe: [neon] + safety: safe types: - uint32x4_t compose: @@ -9730,8 +9339,7 @@ intrinsics: - FnCall: [target_feature, ['enable = "neon,sha3"']] - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [rax1]]}]] - FnCall: [stable, ['feature = "stdarch_neon_sha3"', 'since = "1.79.0"']] - safety: - unsafe: [neon] + safety: safe types: - uint64x2_t compose: @@ -9749,8 +9357,7 @@ intrinsics: - FnCall: [target_feature, ['enable = "neon,sha3"']] - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sha512h]]}]] - FnCall: [stable, ['feature = "stdarch_neon_sha3"', 'since = "1.79.0"']] - safety: - unsafe: [neon] + safety: safe types: - uint64x2_t compose: @@ -9768,8 +9375,7 @@ intrinsics: - FnCall: [target_feature, ['enable = "neon,sha3"']] - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sha512h2]]}]] - FnCall: [stable, ['feature = "stdarch_neon_sha3"', 'since = "1.79.0"']] - safety: - unsafe: [neon] + safety: safe types: - uint64x2_t compose: @@ -9787,8 +9393,7 @@ intrinsics: - FnCall: [target_feature, ['enable = "neon,sha3"']] - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sha512su0]]}]] - FnCall: [stable, ['feature = "stdarch_neon_sha3"', 'since = "1.79.0"']] - safety: - unsafe: [neon] + safety: safe types: - uint64x2_t compose: @@ -9806,8 +9411,7 @@ intrinsics: - FnCall: [target_feature, ['enable = "neon,sha3"']] - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sha512su1]]}]] - FnCall: [stable, ['feature = "stdarch_neon_sha3"', 'since = "1.79.0"']] - safety: - unsafe: [neon] + safety: safe types: - uint64x2_t compose: @@ -9827,8 +9431,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['3']] - FnCall: [unstable, ['feature = "stdarch_neon_sm4"', 'issue = "117226"']] static_defs: ["const IMM2: i32"] - safety: - unsafe: [neon] + safety: safe types: - ['1aq_u32', uint32x4_t, 'sm3tt1a', 'SM3TT1A'] - ['1bq_u32', uint32x4_t, 'sm3tt1b', 'SM3TT1B'] @@ -9852,6 +9455,8 @@ intrinsics: - "b" - "c" - "IMM2 as i64" + - [] + - true - name: "vxarq_u64" doc: "Exclusive OR and rotate" @@ -9863,8 +9468,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['2']] - FnCall: [stable, ['feature = "stdarch_neon_sha3"', 'since = "1.79.0"']] static_defs: ["const IMM6: i32"] - safety: - unsafe: [neon] + safety: safe types: - uint64x2_t compose: @@ -9883,6 +9487,8 @@ intrinsics: - - "a" - "b" - "IMM6 as i64" + - [] + - true - name: "vrnd32x{neon_type.no}" doc: "Floating-point round to 32-bit integer, using current rounding mode" @@ -9892,8 +9498,7 @@ intrinsics: - FnCall: [target_feature, ['enable = "neon,frintts"']] - FnCall: [unstable, ['feature = "stdarch_neon_ftts"', 'issue = "117227"']] - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [frint32x]]}]] - safety: - unsafe: [neon] + safety: safe types: - float32x2_t - float32x4_t @@ -9913,8 +9518,7 @@ intrinsics: - FnCall: [target_feature, ['enable = "neon,frintts"']] - FnCall: [unstable, ['feature = "stdarch_neon_ftts"', 'issue = "117227"']] - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [frint32x]]}]] - safety: - unsafe: [neon] + safety: safe types: - float64x1_t compose: @@ -9940,8 +9544,7 @@ intrinsics: - FnCall: [target_feature, ['enable = "neon,frintts"']] - FnCall: [unstable, ['feature = "stdarch_neon_ftts"', 'issue = "117227"']] - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [frint32z]]}]] - safety: - unsafe: [neon] + safety: safe types: - float32x2_t - float32x4_t @@ -9961,8 +9564,7 @@ intrinsics: - FnCall: [target_feature, ['enable = "neon,frintts"']] - FnCall: [unstable, ['feature = "stdarch_neon_ftts"', 'issue = "117227"']] - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [frint32z]]}]] - safety: - unsafe: [neon] + safety: safe types: - float64x1_t compose: @@ -9986,8 +9588,7 @@ intrinsics: - FnCall: [target_feature, ['enable = "neon,frintts"']] - FnCall: [unstable, ['feature = "stdarch_neon_ftts"', 'issue = "117227"']] - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [frint64x]]}]] - safety: - unsafe: [neon] + safety: safe types: - float32x2_t - float32x4_t @@ -10007,8 +9608,7 @@ intrinsics: - FnCall: [target_feature, ['enable = "neon,frintts"']] - FnCall: [unstable, ['feature = "stdarch_neon_ftts"', 'issue = "117227"']] - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [frint64x]]}]] - safety: - unsafe: [neon] + safety: safe types: - float64x1_t compose: @@ -10032,8 +9632,7 @@ intrinsics: - FnCall: [target_feature, ['enable = "neon,frintts"']] - FnCall: [unstable, ['feature = "stdarch_neon_ftts"', 'issue = "117227"']] - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [frint64z]]}]] - safety: - unsafe: [neon] + safety: safe types: - float32x2_t - float32x4_t @@ -10053,8 +9652,7 @@ intrinsics: - FnCall: [target_feature, ['enable = "neon,frintts"']] - FnCall: [unstable, ['feature = "stdarch_neon_ftts"', 'issue = "117227"']] - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [frint64z]]}]] - safety: - unsafe: [neon] + safety: safe types: - float64x1_t compose: @@ -10077,8 +9675,7 @@ intrinsics: attr: - *neon-stable - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [trn1]]}]] - safety: - unsafe: [neon] + safety: safe types: - [int8x8_t, '[0, 8, 2, 10, 4, 12, 6, 14]'] - [int8x16_t, '[0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30]'] @@ -10107,8 +9704,7 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [trn1]]}]] - safety: - unsafe: [neon] + safety: safe types: - [float16x4_t, '[0, 4, 2, 6]'] - [float16x8_t, '[0, 8, 2, 10, 4, 12, 6, 14]'] @@ -10122,8 +9718,7 @@ intrinsics: attr: - *neon-stable - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [zip1]]}]] - safety: - unsafe: [neon] + safety: safe types: - [int32x2_t, '[0, 2]'] - [int64x2_t, '[0, 2]'] @@ -10142,8 +9737,7 @@ intrinsics: attr: - *neon-stable - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [trn2]]}]] - safety: - unsafe: [neon] + safety: safe types: - [int8x8_t, '[1, 9, 3, 11, 5, 13, 7, 15]'] - [int8x16_t, '[1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31]'] @@ -10171,8 +9765,7 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [trn2]]}]] - safety: - unsafe: [neon] + safety: safe types: - [float16x4_t, '[1, 5, 3, 7]'] - [float16x8_t, '[1, 9, 3, 11, 5, 13, 7, 15]'] @@ -10186,8 +9779,7 @@ intrinsics: attr: - *neon-stable - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [zip2]]}]] - safety: - unsafe: [neon] + safety: safe types: - [int32x2_t, '[1, 3]'] - [int64x2_t, '[1, 3]'] @@ -10206,8 +9798,7 @@ intrinsics: attr: - *neon-stable - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [zip2]]}]] - safety: - unsafe: [neon] + safety: safe types: - [int8x8_t, '[4, 12, 5, 13, 6, 14, 7, 15]'] - [int8x16_t, '[8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31]'] @@ -10242,8 +9833,7 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [zip2]]}]] - safety: - unsafe: [neon] + safety: safe types: - [float16x4_t, '[2, 6, 3, 7]'] - [float16x8_t, '[4, 12, 5, 13, 6, 14, 7, 15]'] @@ -10257,8 +9847,7 @@ intrinsics: attr: - *neon-stable - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [zip1]]}]] - safety: - unsafe: [neon] + safety: safe types: - [int8x8_t, '[0, 8, 1, 9, 2, 10, 3, 11]'] - [int8x16_t, '[0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23]'] @@ -10294,8 +9883,7 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [zip1]]}]] - safety: - unsafe: [neon] + safety: safe types: - [float16x4_t, '[0, 4, 1, 5]'] - [float16x8_t, '[0, 8, 1, 9, 2, 10, 3, 11]'] @@ -10309,8 +9897,7 @@ intrinsics: attr: - *neon-stable - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [zip1]]}]] - safety: - unsafe: [neon] + safety: safe types: - [int32x2_t, '[0, 2]'] - [int64x2_t, '[0, 2]'] @@ -10329,8 +9916,7 @@ intrinsics: attr: - *neon-stable - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [uzp1]]}]] - safety: - unsafe: [neon] + safety: safe types: - [int8x8_t, '[0, 2, 4, 6, 8, 10, 12, 14]'] - [int8x16_t, '[0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30]'] @@ -10358,8 +9944,7 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [uzp1]]}]] - safety: - unsafe: [neon] + safety: safe types: - [float16x4_t, '[0, 2, 4, 6]'] - [float16x8_t, '[0, 2, 4, 6, 8, 10, 12, 14]'] @@ -10373,8 +9958,7 @@ intrinsics: attr: - *neon-stable - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [zip2]]}]] - safety: - unsafe: [neon] + safety: safe types: - [int32x2_t, '[1, 3]'] - [int64x2_t, '[1, 3]'] @@ -10393,8 +9977,7 @@ intrinsics: attr: - *neon-stable - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [uzp2]]}]] - safety: - unsafe: [neon] + safety: safe types: - [int8x8_t, '[1, 3, 5, 7, 9, 11, 13, 15]'] - [int8x16_t, '[1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31]'] @@ -10426,8 +10009,7 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [uzp2]]}]] - safety: - unsafe: [neon] + safety: safe types: - [float16x4_t, '[1, 3, 5, 7]'] - [float16x8_t, '[1, 3, 5, 7, 9, 11, 13, 15]'] @@ -10445,8 +10027,7 @@ intrinsics: attr: - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [uabal]]}]] - safety: - unsafe: [neon] + safety: safe types: - [uint16x8_t, uint8x16_t, uint8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]', '[8, 9, 10, 11, 12, 13, 14, 15]'] - [uint32x4_t, uint16x8_t, uint16x4_t, '[4, 5, 6, 7]', '[4, 5, 6, 7]'] @@ -10473,8 +10054,7 @@ intrinsics: attr: - *neon-stable - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [sabal]]}]] - safety: - unsafe: [neon] + safety: safe types: - [int16x8_t, int8x16_t, int8x16_t, '[8, 9, 10, 11, 12, 13, 14, 15]', int8x8_t, uint8x8_t] - [int32x4_t, int16x8_t, int16x8_t, '[4, 5, 6, 7]', int16x4_t, uint16x4_t] @@ -10523,8 +10103,7 @@ intrinsics: attr: - *neon-stable - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [sqabs]]}]] - safety: - unsafe: [neon] + safety: safe types: - int64x1_t - int64x2_t @@ -10545,8 +10124,7 @@ intrinsics: - *neon-stable - FnCall: [rustc_legacy_const_generics, ['2']] - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [sli, 'N = 2']]}]] - safety: - unsafe: [neon] + safety: safe types: - i64 - u64 @@ -10575,8 +10153,7 @@ intrinsics: - *neon-stable - FnCall: [rustc_legacy_const_generics, ['2']] - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [sri, 'N = 2']]}]] - safety: - unsafe: [neon] + safety: safe types: - i64 - u64 @@ -10602,8 +10179,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmaxnmp]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - float32x2_t - float64x2_t @@ -10696,8 +10272,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['3']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const LANE: i32'] - safety: - unsafe: [neon] + safety: safe types: - [float32x2_t, float32x2_t, '1', '_lane_f32'] - [float32x2_t, float32x4_t, '2', '_laneq_f32'] @@ -10723,8 +10298,7 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 static_defs: ['const LANE: i32'] - safety: - unsafe: [neon] + safety: safe types: - [float16x4_t, float16x4_t, '2', '_lane_f16'] - [float16x4_t, float16x8_t, '3', '_laneq_f16'] @@ -10750,8 +10324,7 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 static_defs: ['const LANE: i32'] - safety: - unsafe: [neon] + safety: safe types: - [float16x4_t, float16x4_t, '2', '_lane_f16'] - [float16x4_t, float16x8_t, '3', '_laneq_f16'] @@ -10774,8 +10347,7 @@ intrinsics: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmsub]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - ["f16", "h_f16"] compose: @@ -10791,8 +10363,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['3']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const LANE: i32'] - safety: - unsafe: [neon] + safety: safe types: - float64x1_t compose: @@ -10812,8 +10383,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['3']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const LANE: i32'] - safety: - unsafe: [neon] + safety: safe types: - [float64x1_t, float64x2_t] compose: @@ -10833,8 +10403,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['3']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const LANE: i32'] - safety: - unsafe: [neon] + safety: safe types: - [float64x2_t, float64x1_t] compose: @@ -10854,8 +10423,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['3']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const LANE: i32'] - safety: - unsafe: [neon] + safety: safe types: - ["f32", float32x2_t, "s_lane_f32", '1'] - ["f32", float32x4_t, "s_laneq_f32", '2'] @@ -10869,7 +10437,7 @@ intrinsics: arch: aarch64,arm64ec - FnCall: [static_assert_uimm_bits!, ['LANE', "{type[3]}"]] - Let: [c, "{type[0]}", {FnCall: [simd_extract!, [c, 'LANE as u32']]}] - - FnCall: ["_vfma{type[2]}", [b, c, a]] + - FnCall: ["_vfma{type[2]}", [b, c, a], [], true] - name: "vfmad_lane_f64" doc: "Floating-point fused multiply-add to accumulator" @@ -10880,8 +10448,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['3']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const LANE: i32'] - safety: - unsafe: [neon] + safety: safe types: - ["f64", float64x1_t] compose: @@ -10904,8 +10471,7 @@ intrinsics: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmadd]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - ["f16", "h_f16"] compose: @@ -10914,7 +10480,7 @@ intrinsics: links: - link: "llvm.fma.{type[0]}" arch: aarch64,arm64ec - - FnCall: ["_vfma{type[1]}", [b, c, a]] + - FnCall: ["_vfma{type[1]}", [b, c, a], [], true] - name: "vfmah_lane{type[2]}" @@ -10927,8 +10493,7 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 static_defs: ['const LANE: i32'] - safety: - unsafe: [neon] + safety: safe types: - ["f16", float16x4_t, '_f16', '2'] - ["f16", float16x8_t, 'q_f16', '3'] @@ -10947,8 +10512,7 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 static_defs: ['const LANE: i32'] - safety: - unsafe: [neon] + safety: safe types: - ["f16", float16x4_t, '_f16', '2'] - ["f16", float16x8_t, 'q_f16', '3'] @@ -10964,8 +10528,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmsub]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - float64x1_t compose: @@ -10979,8 +10542,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmls]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - float64x2_t compose: @@ -10994,8 +10556,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmul]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - float64x1_t - float64x2_t @@ -11011,8 +10572,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['3']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const LANE: i32'] - safety: - unsafe: [neon] + safety: safe types: - [float32x2_t, float32x2_t, '1', _lane_f32] - [float32x2_t, float32x4_t, '2', _laneq_f32] @@ -11032,8 +10592,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['3']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const LANE: i32'] - safety: - unsafe: [neon] + safety: safe types: - float64x1_t compose: @@ -11049,8 +10608,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['3']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const LANE: i32'] - safety: - unsafe: [neon] + safety: safe types: - [float64x1_t, float64x2_t] compose: @@ -11066,8 +10624,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['3']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const LANE: i32'] - safety: - unsafe: [neon] + safety: safe types: - [float64x2_t, float64x1_t] compose: @@ -11083,8 +10640,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['3']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const LANE: i32'] - safety: - unsafe: [neon] + safety: safe types: - ["f32", float32x2_t, "s_lane_f32"] - ["f32", float32x4_t, "s_laneq_f32"] @@ -11101,8 +10657,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmeq]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [float32x2_t, uint32x2_t, 'f32x2', 'f32x2::new(0.0, 0.0)'] - [float32x4_t, uint32x4_t, 'f32x4', 'f32x4::new(0.0, 0.0, 0.0, 0.0)'] @@ -11120,8 +10675,7 @@ intrinsics: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmeq]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - [float16x4_t, uint16x4_t, 'f16x4', 'f16x4::new(0.0, 0.0, 0.0, 0.0)'] - [float16x8_t, uint16x8_t, 'f16x8', 'f16x8::new(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0)'] @@ -11136,8 +10690,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmp]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - ["f32", "u32", "s_f32"] - ["f64", "u64", "d_f64"] @@ -11157,8 +10710,7 @@ intrinsics: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmp]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - ["f16", "u16", "h_f16"] compose: @@ -11176,8 +10728,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmp]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - ["i64", "u64", "s64"] - ["u64", "u64", "u64"] @@ -11195,8 +10746,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmeq]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [int8x8_t, uint8x8_t, i8x8, 'i8x8::new(0, 0, 0, 0, 0, 0, 0, 0)'] - [int8x16_t, uint8x16_t, i8x16, 'i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)'] @@ -11224,8 +10774,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmeq]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [uint8x8_t, uint8x8_t, u8x8, 'u8x8::new(0, 0, 0, 0, 0, 0, 0, 0)'] - [uint8x16_t, uint8x16_t, u8x16, 'u8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)'] @@ -11249,8 +10798,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmhs]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - uint64x1_t - uint64x2_t @@ -11264,8 +10812,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmp]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - ["s_f32", "f32", "u32"] - ["d_f64", "f64", "u64"] @@ -11287,8 +10834,7 @@ intrinsics: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmp]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - ["h_f16", "f16", "u16"] compose: @@ -11307,8 +10853,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmge]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [float64x1_t, uint64x1_t] - [float64x2_t, uint64x2_t] @@ -11322,8 +10867,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmp]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - ["d_s64", "i64", "u64", s64] - ["d_u64", "u64", "u64", u64] @@ -11342,8 +10886,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmhi]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - uint64x1_t - uint64x2_t @@ -11357,8 +10900,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmp]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - ["s64", "i64", "u64"] - ["u64", "u64", "u64"] @@ -11377,8 +10919,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmtst]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [uint64x1_t, u64x1, 'u64x1::new(0)'] - [uint64x2_t, u64x2, 'u64x2::new(0, 0)'] @@ -11394,8 +10935,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmge]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [float32x2_t, uint32x2_t, f32x2, 'f32x2::new(0.0, 0.0)'] - [float32x4_t, uint32x4_t, f32x4, 'f32x4::new(0.0, 0.0, 0.0, 0.0)'] @@ -11415,8 +10955,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmp]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - ["s_f32", "f32", "u32"] - ["d_f64", "f64", "u64"] @@ -11437,8 +10976,7 @@ intrinsics: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmp]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - ["h_f16", "f16", "u16"] compose: @@ -11456,8 +10994,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmp]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - ["i64", "u64"] compose: @@ -11472,8 +11009,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmp]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - ["i64", "u64", 's64'] - ["u64", "u64", 'u64'] @@ -11492,8 +11028,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmgt]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [int8x8_t, uint8x8_t, i8x8, 'i8x8::new(0, 0, 0, 0, 0, 0, 0, 0)'] - [int8x16_t, uint8x16_t, i8x16, 'i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)'] @@ -11517,8 +11052,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmp]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - ["i64", "u64"] compose: @@ -11535,8 +11069,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmgt]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [float32x2_t, uint32x2_t, f32x2, 'f32x2::new(0.0, 0.0)'] - [float32x4_t, uint32x4_t, f32x4, 'f32x4::new(0.0, 0.0, 0.0, 0.0)'] @@ -11553,8 +11086,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmp]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - ["s_f32", "f32", "u32"] - ["d_f64", "f64", "u64"] @@ -11574,8 +11106,7 @@ intrinsics: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmp]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - ["h_f16", "f16", "u16"] compose: @@ -11593,8 +11124,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtzu]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [float64x1_t, uint64x1_t] - [float64x2_t, uint64x2_t] @@ -11612,8 +11142,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmul]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [float64x1_t, "f64"] - [float64x2_t, "f64"] @@ -11632,8 +11161,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['2']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const LANE: i32'] - safety: - unsafe: [neon] + safety: safe types: - float64x1_t compose: @@ -11654,8 +11182,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['2']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const LANE: i32'] - safety: - unsafe: [neon] + safety: safe types: - [float64x2_t, float64x1_t] compose: @@ -11674,8 +11201,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['2']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const LANE: i32'] - safety: - unsafe: [neon] + safety: safe types: - ["f64", float64x1_t] compose: @@ -11692,8 +11218,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['2']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const LANE: i32'] - safety: - unsafe: [neon] + safety: safe types: - [float64x1_t, float64x2_t] compose: @@ -11714,8 +11239,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['2']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const LANE: i32'] - safety: - unsafe: [neon] + safety: safe types: - [float64x2_t, float64x2_t, float64x2_t] compose: @@ -11737,8 +11261,7 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 static_defs: ['const LANE: i32'] - safety: - unsafe: [neon] + safety: safe types: - [float16x4_t, float16x8_t, '_lane', "[LANE as u32, LANE as u32, LANE as u32, LANE as u32]"] - [float16x8_t, float16x8_t, 'q_lane', "[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]"] @@ -11758,8 +11281,7 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 assert_instr: [nop] - safety: - unsafe: [neon] + safety: safe types: - [f16, 'h'] compose: @@ -11775,8 +11297,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['2']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const LANE: i32'] - safety: - unsafe: [neon] + safety: safe types: - ["f32", float32x2_t, "s_lane_f32", '1'] - ["f32", float32x4_t, "s_laneq_f32", '2'] @@ -11797,8 +11318,7 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 static_defs: ['const LANE: i32'] - safety: - unsafe: [neon] + safety: safe types: - ["f16", float16x4_t, "h_lane_f16", '2'] - ["f16", float16x8_t, "h_laneq_f16", '3'] @@ -11817,8 +11337,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['2']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - "i64" compose: @@ -11833,8 +11352,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [smlsl2]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [int32x4_t, int16x8_t, "i16"] - [int64x2_t, int32x4_t, "i32"] @@ -11848,8 +11366,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [umlsl2]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [uint32x4_t, uint16x8_t, "u16"] - [uint64x2_t, uint32x4_t, "u32"] @@ -11865,8 +11382,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['3']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const LANE: i32'] - safety: - unsafe: [neon] + safety: safe types: - [int32x4_t, int16x8_t, int16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - [int32x4_t, int16x8_t, int16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] @@ -11889,8 +11405,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['3']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const LANE: i32'] - safety: - unsafe: [neon] + safety: safe types: - [uint32x4_t, uint16x8_t, uint16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - [uint32x4_t, uint16x8_t, uint16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] @@ -11911,8 +11426,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmgt]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [float64x1_t, uint64x1_t] - [float64x2_t, uint64x2_t] @@ -11926,8 +11440,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmp]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - ["f32", "u32", 's_f32'] - ["f64", "u64", 'd_f64'] @@ -11949,8 +11462,7 @@ intrinsics: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmp]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - ["f16", "u16", 'h_f16'] compose: @@ -11969,8 +11481,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [uabdl]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [uint8x16_t, uint16x8_t, uint8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]'] - [uint16x8_t, uint32x4_t, uint16x4_t, '[4, 5, 6, 7]'] @@ -11987,8 +11498,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmsub]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [float64x1_t, "f64"] compose: @@ -12005,8 +11515,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmls]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [float64x2_t, "f64"] compose: @@ -12025,8 +11534,7 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 assert_instr: [fmls] - safety: - unsafe: [neon] + safety: safe types: - [float16x4_t, f16] - [float16x8_t, f16] @@ -12047,8 +11555,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fminnmp]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - ['s_f32', float32x2_t, "f32"] - ['qd_f64', float64x2_t, "f64"] @@ -12066,8 +11573,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmaxnmp]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - ['s_f32', float32x2_t, "f32"] - ['qd_f64', float64x2_t, "f64"] @@ -12085,8 +11591,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmp]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - ["s64", "i64", "u64"] - ["u64", "u64", "u64"] @@ -12107,8 +11612,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['2']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const LANE: i32'] - safety: - unsafe: [neon] + safety: safe types: - [int16x4_t, int16x4_t, '2'] - [int16x8_t, int16x4_t, '2'] @@ -12130,8 +11634,7 @@ intrinsics: attr: - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [sqabs]]}]] - safety: - unsafe: [neon] + safety: safe types: - ["i8", "s8", 'b_s8'] - ["i16", "s16", 'h_s16'] @@ -12148,8 +11651,7 @@ intrinsics: attr: - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [sqabs]]}]] - safety: - unsafe: [neon] + safety: safe types: - ["i32", "s_s32"] - ["i64", "d_s64"] @@ -12167,8 +11669,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [smull2]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [int16x8_t, "i16", int32x4_t] - [int32x4_t, "i32", int64x2_t] @@ -12185,8 +11686,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [umull2]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [uint16x8_t, "u16", uint32x4_t] - [uint32x4_t, "u32", uint64x2_t] @@ -12205,8 +11705,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['2']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const LANE: i32'] - safety: - unsafe: [neon] + safety: safe types: - [int16x8_t, int16x4_t, int32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - [int16x8_t, int16x8_t, int32x4_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] @@ -12228,8 +11727,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['2']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const LANE: i32'] - safety: - unsafe: [neon] + safety: safe types: - [uint16x8_t, uint16x4_t, uint32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - [uint16x8_t, uint16x8_t, uint32x4_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] @@ -12249,8 +11747,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [frsqrte]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - float64x1_t - float64x2_t @@ -12268,8 +11765,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [frsqrte]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - ["s_f32", "f32"] - ["d_f64", "f64"] @@ -12290,8 +11786,7 @@ intrinsics: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [frsqrte]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - ["h_f16", "f16"] compose: @@ -12309,8 +11804,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fminnmp]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - float32x2_t - float64x2_t @@ -12331,8 +11825,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['1']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [b_n_s8, i8, u8, '3', s8] - [h_n_s16, i16, u16, '4', s16] @@ -12354,8 +11847,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtau]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [float32x2_t, uint32x2_t] - [float32x4_t, uint32x4_t] @@ -12377,8 +11869,7 @@ intrinsics: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtau]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - [float16x4_t, uint16x4_t] - [float16x8_t, uint16x8_t] @@ -12397,8 +11888,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtzs]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [float64x1_t, int64x1_t] - [float64x2_t, int64x2_t] @@ -12417,8 +11907,7 @@ intrinsics: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtms]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - ["f16", "i32", 'h'] - ["f16", "i64", 'h'] @@ -12438,8 +11927,7 @@ intrinsics: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtms]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - ["f16", "i16", 'h', 'i32'] compose: @@ -12454,8 +11942,7 @@ intrinsics: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtmu]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - ["f16", "u32", 'h'] - ["f16", "u64", 'h'] @@ -12475,8 +11962,7 @@ intrinsics: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtmu]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - ["f16", "u16", 'h', 'u32'] compose: @@ -12489,8 +11975,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [smlal2]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [int32x4_t, int16x8_t, "i16"] - [int64x2_t, int32x4_t, "i32"] @@ -12508,8 +11993,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [umlal2]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [uint32x4_t, uint16x8_t, "u16"] - [uint64x2_t, uint32x4_t, "u32"] @@ -12529,8 +12013,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['3']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const LANE: i32'] - safety: - unsafe: [neon] + safety: safe types: - [int32x4_t, int16x8_t, int16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - [int32x4_t, int16x8_t, int16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] @@ -12549,8 +12032,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['3']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const LANE: i32'] - safety: - unsafe: [neon] + safety: safe types: - [uint32x4_t, uint16x8_t, uint16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - [uint32x4_t, uint16x8_t, uint16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] @@ -12569,8 +12051,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['2']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - "u64" compose: @@ -12585,8 +12066,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmhs]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - uint64x1_t - uint64x2_t @@ -12656,8 +12136,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [int8x8_t, int8x8x4_t] compose: @@ -12679,8 +12158,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [uint8x8_t, uint8x8x4_t, uint8x8_t] - [poly8x8_t, poly8x8x4_t, uint8x8_t] @@ -12705,10 +12183,9 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - - [int8x8_t, 'int8x8_t', 'transmute(b)'] + - [int8x8_t, 'int8x8_t', 'unsafe {{ transmute(b) }}'] - [uint8x8_t, 'uint8x8_t', 'b'] - [poly8x8_t, 'uint8x8_t', 'b'] compose: @@ -12717,7 +12194,7 @@ intrinsics: - - FnCall: - 'vcombine{neon_type[0].no}' - - a - - 'crate::mem::zeroed()' + - 'unsafe {{ crate::mem::zeroed() }}' - Identifier: ['{type[2]}', Symbol] - name: "vtbl2{neon_type[1].noq}" @@ -12727,8 +12204,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [int8x8x2_t, 'int8x8_t'] compose: @@ -12749,8 +12225,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [uint8x8x2_t, 'uint8x8_t', 'uint8x8_t'] - [poly8x8x2_t, 'uint8x8_t', 'poly8x8_t'] @@ -12774,8 +12249,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [int8x8x3_t, 'int8x8_t', 'int8x16x2'] compose: @@ -12784,7 +12258,7 @@ intrinsics: - FnCall: - '{type[2]}_t' - - FnCall: ['vcombine{neon_type[1].no}', ['a.0', 'a.1']] - - FnCall: ['vcombine{neon_type[1].no}', ['a.2', 'crate::mem::zeroed()']] + - FnCall: ['vcombine{neon_type[1].no}', ['a.2', 'unsafe {{ crate::mem::zeroed() }}']] - FnCall: - transmute - - FnCall: @@ -12800,8 +12274,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [uint8x8x3_t, 'uint8x8_t', 'uint8x16x2', 'uint8x8_t'] - [poly8x8x3_t, 'uint8x8_t', 'poly8x16x2', 'poly8x8_t'] @@ -12812,7 +12285,7 @@ intrinsics: - FnCall: - '{type[2]}_t' - - FnCall: ['vcombine{neon_type[3].no}', ['a.0', 'a.1']] - - FnCall: ['vcombine{neon_type[3].no}', ['a.2', 'crate::mem::zeroed()']] + - FnCall: ['vcombine{neon_type[3].no}', ['a.2', 'unsafe {{ crate::mem::zeroed() }}']] - FnCall: - transmute - - FnCall: @@ -12828,8 +12301,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [int8x8x4_t, 'int8x8_t', 'int8x16x2'] compose: @@ -12854,8 +12326,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [uint8x8x4_t, 'uint8x8_t', 'uint8x16x2', 'uint8x8_t'] - [poly8x8x4_t, 'uint8x8_t', 'poly8x16x2', 'poly8x8_t'] @@ -12882,8 +12353,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [int8x8_t, int8x16_t, uint8x8_t, vqtbx1] - [int8x16_t, int8x16_t, uint8x16_t, vqtbx1q] @@ -12897,8 +12367,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [uint8x8_t, "uint8x16_t", uint8x8_t, "vqtbx1", "_u8"] - [poly8x8_t, "poly8x16_t", uint8x8_t, "vqtbx1", "_p8"] @@ -12923,8 +12392,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [int8x8_t, "int8x8_t", "transmute(c)", "i8x8::splat(8)", "int8x8"] - [uint8x8_t, "uint8x8_t", "c", "u8x8::splat(8)", "uint8x8"] @@ -12954,8 +12422,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [int8x8_t, 'int8x8x2_t'] compose: @@ -12974,8 +12441,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [uint8x8_t, 'uint8x8x2_t', uint8x8_t] - [poly8x8_t, 'poly8x8x2_t', uint8x8_t] @@ -12997,8 +12463,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [int8x8_t, 'int8x8x3_t', 'int8x16x2', 'i8x8::splat(24)', 'int8x8'] compose: @@ -13007,7 +12472,7 @@ intrinsics: - FnCall: - '{type[2]}_t' - - FnCall: ['vcombine{neon_type[0].no}', ['b.0', 'b.1']] - - FnCall: ['vcombine{neon_type[0].no}', ['b.2', 'crate::mem::zeroed()']] + - FnCall: ['vcombine{neon_type[0].no}', ['b.2', 'unsafe {{ crate::mem::zeroed() }}']] - FnCall: - transmute - - FnCall: @@ -13033,8 +12498,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [uint8x8_t, 'uint8x8x3_t', 'uint8x16x2', 'u8x8::splat(24)', 'uint8x8'] - [poly8x8_t, 'poly8x8x3_t', 'poly8x16x2', 'u8x8::splat(24)', 'poly8x8'] @@ -13045,7 +12509,7 @@ intrinsics: - FnCall: - '{type[2]}_t' - - FnCall: ['vcombine{neon_type[0].no}', ['b.0', 'b.1']] - - FnCall: ['vcombine{neon_type[0].no}', ['b.2', 'crate::mem::zeroed()']] + - FnCall: ['vcombine{neon_type[0].no}', ['b.2', 'unsafe {{ crate::mem::zeroed() }}']] - FnCall: - transmute - - FnCall: @@ -13071,8 +12535,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - ['int8x16_t', uint8x8_t, 'vqtbl1', 'int8x8_t'] - ['int8x16_t', uint8x16_t, 'vqtbl1q', 'int8x16_t'] @@ -13086,8 +12549,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - ['uint8x16_t', uint8x8_t, 'vqtbl1', 'uint8x8_t'] - ['poly8x16_t', uint8x8_t, 'vqtbl1', 'poly8x8_t'] @@ -13111,8 +12573,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - ['int8x16x2_t', uint8x8_t, 'vqtbl2', 'int8x8_t'] - ['int8x16x2_t', uint8x16_t, 'vqtbl2q', 'int8x16_t'] @@ -13126,8 +12587,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - ['uint8x16x2_t', uint8x8_t, 'vqtbl2', 'uint8x8_t'] - ['uint8x16x2_t', uint8x16_t, 'vqtbl2q', 'uint8x16_t'] @@ -13149,8 +12609,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [int8x8_t, 'int8x16x2_t', uint8x8_t, 'vqtbx2'] - [int8x16_t, 'int8x16x2_t', uint8x16_t, 'vqtbx2q'] @@ -13164,8 +12623,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [uint8x8_t, 'uint8x16x2_t', uint8x8_t, 'vqtbx2'] - [uint8x16_t, 'uint8x16x2_t', uint8x16_t, 'vqtbx2q'] @@ -13188,8 +12646,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - ['int8x8_t', 'int8x16x3_t', uint8x8_t, 'vqtbl3'] - ['int8x16_t', 'int8x16x3_t', uint8x16_t, 'vqtbl3q'] @@ -13203,8 +12660,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - ['uint8x8_t', 'uint8x16x3_t', uint8x8_t, 'vqtbl3'] - ['uint8x16_t','uint8x16x3_t', uint8x16_t, 'vqtbl3q'] @@ -13227,8 +12683,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [int8x8_t, 'int8x16x3_t', uint8x8_t, 'vqtbx3'] - [int8x16_t, 'int8x16x3_t', uint8x16_t, 'vqtbx3q'] @@ -13242,8 +12697,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [uint8x8_t, 'uint8x16x3_t', uint8x8_t, 'vqtbx3'] - [uint8x16_t, 'uint8x16x3_t', uint8x16_t, 'vqtbx3q'] @@ -13267,8 +12721,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - ['int8x16x4_t', uint8x8_t, 'vqtbl4', 'int8x8_t'] - ['int8x16x4_t', uint8x16_t, 'vqtbl4q', 'int8x16_t'] @@ -13282,8 +12735,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - ['uint8x16x4_t', uint8x8_t, 'vqtbl4', 'uint8x8_t'] - ['uint8x16x4_t', uint8x16_t, 'vqtbl4q', 'uint8x16_t'] @@ -13307,8 +12759,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [int8x8_t, 'int8x16x4_t', uint8x8_t, 'vqtbx4'] - [int8x16_t, 'int8x16x4_t', uint8x16_t, 'vqtbx4q'] @@ -13322,8 +12773,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [uint8x8_t, 'uint8x16x4_t', uint8x8_t, 'vqtbx4'] - [uint8x16_t, 'uint8x16x4_t', uint8x16_t, 'vqtbx4q'] @@ -13349,8 +12799,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - ["vqtbl1", "int8x16_t", "uint8x8_t", "int8x8_t"] - ["vqtbl1q", "int8x16_t", "uint8x16_t", "int8x16_t"] @@ -13369,8 +12818,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - ["vqtbl2", "int8x16_t", "uint8x8_t", "int8x8_t"] - ["vqtbl2q", "int8x16_t", "uint8x16_t", "int8x16_t"] @@ -13389,8 +12837,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - ["vqtbl3", int8x16_t, uint8x8_t, int8x8_t] - ["vqtbl3q", int8x16_t, uint8x16_t, int8x16_t] @@ -13409,8 +12856,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - ["vqtbl4", int8x16_t, uint8x8_t, int8x8_t] - ["vqtbl4q", int8x16_t, uint8x16_t, int8x16_t] @@ -13429,8 +12875,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [vqtbx1, "int8x8_t", "int8x16_t", "uint8x8_t"] - [vqtbx1q, "int8x16_t", "int8x16_t", "uint8x16_t"] @@ -13449,8 +12894,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [vqtbx2, "int8x8_t", "int8x16_t", "uint8x8_t"] - [vqtbx2q, "int8x16_t", "int8x16_t", "uint8x16_t"] @@ -13469,8 +12913,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [vqtbx3, "int8x8_t", "int8x16_t", "uint8x8_t"] - [vqtbx3q, "int8x16_t", "int8x16_t", "uint8x16_t"] @@ -13489,8 +12932,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] - safety: - unsafe: [neon] + safety: safe types: - [vqtbx4, "int8x8_t", "int8x16_t", "uint8x8_t"] - [vqtbx4q, "int8x16_t", "int8x16_t", "uint8x16_t"] @@ -13644,8 +13086,7 @@ intrinsics: - *target-not-arm - FnCall: [cfg_attr, [test, { FnCall: [assert_instr, ["crc32x"]] }]] - *aarch64-crc-stable - safety: - unsafe: [neon] + safety: safe types: - [u32, u64] compose: @@ -13667,8 +13108,7 @@ intrinsics: - *target-not-arm - FnCall: [cfg_attr, [test, { FnCall: [assert_instr, ["crc32cx"]] }]] - *aarch64-crc-stable - safety: - unsafe: [neon] + safety: safe types: - [u32, u64] compose: @@ -13688,8 +13128,7 @@ intrinsics: attr: - *neon-stable assert_instr: [abs] - safety: - unsafe: [neon] + safety: safe types: - ['vabsd_s64', i64, i64] - ['vabs_s64', int64x1_t, v1i64] @@ -13708,8 +13147,7 @@ intrinsics: attr: - *neon-stable assert_instr: [suqadd] - safety: - unsafe: [neon] + safety: safe types: - [int8x8_t, uint8x8_t] - [int8x16_t, uint8x16_t] @@ -13733,8 +13171,7 @@ intrinsics: attr: - *neon-stable assert_instr: [usqadd] - safety: - unsafe: [neon] + safety: safe types: - [uint8x8_t, int8x8_t] - [uint8x16_t, int8x16_t] @@ -13758,8 +13195,7 @@ intrinsics: attr: - *neon-stable assert_instr: [addp] - safety: - unsafe: [neon] + safety: safe types: - int8x16_t - int16x8_t @@ -13779,8 +13215,7 @@ intrinsics: attr: - *neon-stable assert_instr: [addp] - safety: - unsafe: [neon] + safety: safe types: - [uint8x16_t, int8x16_t] - [uint16x8_t, int16x8_t] @@ -13801,8 +13236,7 @@ intrinsics: attr: - *neon-stable assert_instr: [addp] - safety: - unsafe: [neon] + safety: safe types: - [int64x2_t, i64] compose: @@ -13819,8 +13253,7 @@ intrinsics: attr: - *neon-stable assert_instr: [addp] - safety: - unsafe: [neon] + safety: safe types: - [uint64x2_t, u64] compose: @@ -13833,8 +13266,7 @@ intrinsics: attr: - *neon-stable assert_instr: [addv] - safety: - unsafe: [neon] + safety: safe types: - [int8x8_t, i8, i32] - [int16x4_t, i16, i32] @@ -13855,8 +13287,7 @@ intrinsics: attr: - *neon-stable assert_instr: [addp] - safety: - unsafe: [neon] + safety: safe types: - [int32x2_t, i32] compose: @@ -13873,8 +13304,7 @@ intrinsics: attr: - *neon-stable assert_instr: [addp] - safety: - unsafe: [neon] + safety: safe types: - [int64x2_t, i64] compose: @@ -13891,8 +13321,7 @@ intrinsics: attr: - *neon-stable assert_instr: [addv] - safety: - unsafe: [neon] + safety: safe types: - [uint8x8_t, u8, i32] - [uint16x4_t, u16, i32] @@ -13913,8 +13342,7 @@ intrinsics: attr: - *neon-stable assert_instr: [addp] - safety: - unsafe: [neon] + safety: safe types: - [uint32x2_t, u32, i32] compose: @@ -13931,8 +13359,7 @@ intrinsics: attr: - *neon-stable assert_instr: [addp] - safety: - unsafe: [neon] + safety: safe types: - [uint64x2_t, u64, i64] compose: @@ -13949,8 +13376,7 @@ intrinsics: attr: - *neon-stable assert_instr: [saddlv] - safety: - unsafe: [neon] + safety: safe types: - [int8x8_t, i16] - [int8x16_t, i16] @@ -13961,7 +13387,7 @@ intrinsics: links: - link: "llvm.aarch64.neon.saddlv.i32.{neon_type[0]}" arch: aarch64,arm64ec - - Identifier: ["_vaddlv{neon_type[0].no}(a) as i16", Symbol] + - Identifier: ["unsafe {{ _vaddlv{neon_type[0].no}(a) as i16 }}", Symbol] - name: "vaddlv{neon_type[0].no}" doc: "Unsigned Add Long across Vector" @@ -13970,8 +13396,7 @@ intrinsics: attr: - *neon-stable assert_instr: [uaddlv] - safety: - unsafe: [neon] + safety: safe types: - [uint8x8_t, u16] - [uint8x16_t, u16] @@ -13982,7 +13407,7 @@ intrinsics: links: - link: "llvm.aarch64.neon.uaddlv.i32.{neon_type[0]}" arch: aarch64,arm64ec - - Identifier: ["_vaddlv{neon_type[0].no}(a) as u16", Symbol] + - Identifier: ["unsafe {{ _vaddlv{neon_type[0].no}(a) as u16 }}", Symbol] - name: "vmaxv{neon_type[0].no}" doc: "Horizontal vector max." @@ -13991,8 +13416,7 @@ intrinsics: attr: - *neon-stable assert_instr: ['{type[2]}'] - safety: - unsafe: [neon] + safety: safe types: - [int8x8_t, i8, 'smaxv'] - [int16x4_t, i16, 'smaxv'] @@ -14014,8 +13438,7 @@ intrinsics: attr: - *neon-stable assert_instr: ['{type[2]}'] - safety: - unsafe: [neon] + safety: safe types: - [uint8x8_t, u8, 'umaxv'] - [uint16x4_t, u16, 'umaxv'] @@ -14037,8 +13460,7 @@ intrinsics: attr: - *neon-stable assert_instr: ['{type[2]}'] - safety: - unsafe: [neon] + safety: safe types: - [float32x2_t, f32, 'fmaxp'] - [float32x4_t, f32, 'fmaxv'] @@ -14057,8 +13479,7 @@ intrinsics: attr: - *neon-stable assert_instr: ['{type[2]}'] - safety: - unsafe: [neon] + safety: safe types: - [int8x8_t, i8, 'sminv'] - [int16x4_t, i16, 'sminv'] @@ -14080,8 +13501,7 @@ intrinsics: attr: - *neon-stable assert_instr: ['{type[2]}'] - safety: - unsafe: [neon] + safety: safe types: - [uint8x8_t, u8, 'uminv'] - [uint16x4_t, u16, 'uminv'] @@ -14103,8 +13523,7 @@ intrinsics: attr: - *neon-stable assert_instr: ['{type[2]}'] - safety: - unsafe: [neon] + safety: safe types: - [float32x2_t, f32, 'fminp'] - [float32x4_t, f32, 'fminv'] @@ -14123,8 +13542,7 @@ intrinsics: attr: - *neon-stable assert_instr: ['sminp'] - safety: - unsafe: [neon] + safety: safe types: - int8x16_t - int16x8_t @@ -14143,8 +13561,7 @@ intrinsics: attr: - *neon-stable assert_instr: ['uminp'] - safety: - unsafe: [neon] + safety: safe types: - uint8x16_t - uint16x8_t @@ -14163,8 +13580,7 @@ intrinsics: attr: - *neon-stable assert_instr: ['fminp'] - safety: - unsafe: [neon] + safety: safe types: - float32x4_t - float64x2_t @@ -14182,8 +13598,7 @@ intrinsics: attr: - *neon-stable assert_instr: ['smaxp'] - safety: - unsafe: [neon] + safety: safe types: - int8x16_t - int16x8_t @@ -14202,8 +13617,7 @@ intrinsics: attr: - *neon-stable assert_instr: ['umaxp'] - safety: - unsafe: [neon] + safety: safe types: - uint8x16_t - uint16x8_t @@ -14222,8 +13636,7 @@ intrinsics: attr: - *neon-stable assert_instr: ['fmaxp'] - safety: - unsafe: [neon] + safety: safe types: - float32x4_t - float64x2_t @@ -14243,8 +13656,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['2']] - *neon-stable static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [int8x8_t, 'static_assert_uimm_bits!', 'N, 3'] - [int8x16_t, 'static_assert_uimm_bits!', 'N, 3'] @@ -14265,7 +13677,7 @@ intrinsics: links: - link: "llvm.aarch64.neon.vsli.{neon_type[0]}" arch: aarch64,arm64ec - - FnCall: ["_vsli{neon_type[0].N}", [a, b, N]] + - FnCall: ["_vsli{neon_type[0].N}", [a, b, N], [], true] - name: "vsli{neon_type[0].N}" doc: "Shift Left and Insert (immediate)" @@ -14277,8 +13689,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['2']] - *neon-stable static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [uint8x8_t, int8x8_t, 'static_assert_uimm_bits!', 'N, 3', "neon"] - [uint8x16_t, int8x16_t, 'static_assert_uimm_bits!', 'N, 3', "neon"] @@ -14316,8 +13727,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['2']] - *neon-stable static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [int8x8_t, 'N >= 1 && N <= 8'] - [int8x16_t, 'N >= 1 && N <= 8'] @@ -14338,7 +13748,7 @@ intrinsics: links: - link: "llvm.aarch64.neon.vsri.{neon_type[0]}" arch: aarch64,arm64ec - - FnCall: ["_vsri{neon_type[0].N}", [a, b, N]] + - FnCall: ["_vsri{neon_type[0].N}", [a, b, N], [], true] - name: "vsri{neon_type[0].N}" doc: "Shift Right and Insert (immediate)" @@ -14350,8 +13760,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['2']] - *neon-stable static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [uint8x8_t, int8x8_t, 'N >= 1 && N <= 8', "neon"] - [uint8x16_t, int8x16_t, 'N >= 1 && N <= 8', "neon"] @@ -14389,8 +13798,7 @@ intrinsics: - *enable-fhm - *neon-unstable-f16 assert_instr: [fmlal2] - safety: - unsafe: [neon] + safety: safe types: - [float32x2_t, float16x4_t, '_high_'] - [float32x4_t, float16x8_t, 'q_high_'] @@ -14413,8 +13821,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['3']] - *neon-unstable-f16 static_defs: ['const LANE: i32'] - safety: - unsafe: [neon] + safety: safe types: - [float32x2_t, float16x4_t, float16x4_t, '_lane_high_', '_high_', '2'] - [float32x2_t, float16x4_t, float16x8_t, '_laneq_high_', '_high_', '3'] @@ -14438,8 +13845,7 @@ intrinsics: - *enable-fhm - *neon-unstable-f16 assert_instr: [fmlal] - safety: - unsafe: [neon] + safety: safe types: - [float32x2_t, float16x4_t, '_low_'] - [float32x4_t, float16x8_t, 'q_low_'] @@ -14462,8 +13868,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['3']] - *neon-unstable-f16 static_defs: ['const LANE: i32'] - safety: - unsafe: [neon] + safety: safe types: - [float32x2_t, float16x4_t, float16x4_t, '_lane_low_', '_low_', '2'] - [float32x2_t, float16x4_t, float16x8_t, '_laneq_low_', '_low_', '3'] @@ -14487,8 +13892,7 @@ intrinsics: - *enable-fhm - *neon-unstable-f16 assert_instr: [fmlsl2] - safety: - unsafe: [neon] + safety: safe types: - [float32x2_t, float16x4_t, '_high_'] - [float32x4_t, float16x8_t, 'q_high_'] @@ -14510,8 +13914,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['3']] - *neon-unstable-f16 static_defs: ['const LANE: i32'] - safety: - unsafe: [neon] + safety: safe types: - [float32x2_t, float16x4_t, float16x4_t, '_lane_high_', '_high_', '2'] - [float32x2_t, float16x4_t, float16x8_t, '_laneq_high_', '_high_', '3'] @@ -14535,8 +13938,7 @@ intrinsics: - *enable-fhm - *neon-unstable-f16 assert_instr: [fmlsl] - safety: - unsafe: [neon] + safety: safe types: - [float32x2_t, float16x4_t, '_low_'] - [float32x4_t, float16x8_t, 'q_low_'] @@ -14558,8 +13960,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['3']] - *neon-unstable-f16 static_defs: ['const LANE: i32'] - safety: - unsafe: [neon] + safety: safe types: - [float32x2_t, float16x4_t, float16x4_t, '_lane_low_', '_low_', '2'] - [float32x2_t, float16x4_t, float16x8_t, '_laneq_low_', '_low_', '3'] diff --git a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml index b125ae9a96..b9be94642d 100644 --- a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml +++ b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml @@ -99,8 +99,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [and]]}]] - *neon-stable-not-arm - *neon-unstable-is-arm - safety: - unsafe: [neon] + safety: safe types: - int8x8_t - int8x16_t @@ -134,8 +133,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [orr]]}]] - *neon-stable-not-arm - *neon-unstable-is-arm - safety: - unsafe: [neon] + safety: safe types: - int8x8_t - int8x16_t @@ -169,8 +167,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [eor]]}]] - *neon-stable-not-arm - *neon-unstable-is-arm - safety: - unsafe: [neon] + safety: safe types: - int8x8_t - int8x16_t @@ -204,8 +201,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [sabd]]}]] - *neon-stable-not-arm - *neon-unstable-is-arm - safety: - unsafe: [neon] + safety: safe types: - int8x8_t - int8x16_t @@ -232,8 +228,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [uabd]]}]] - *neon-stable-not-arm - *neon-unstable-is-arm - safety: - unsafe: [neon] + safety: safe types: - uint8x8_t - uint8x16_t @@ -260,8 +255,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [fabd]]}]] - *neon-stable-not-arm - *neon-unstable-is-arm - safety: - unsafe: [neon] + safety: safe types: - float32x2_t - float32x4_t @@ -284,8 +278,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [fabd]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - float16x4_t - float16x8_t @@ -346,8 +339,7 @@ intrinsics: - unstable - - 'feature = "stdarch_arm_neon_intrinsics"' - 'issue = "111800"' - safety: - unsafe: [neon] + safety: safe types: - [int8x8_t, int16x8_t, uint8x8_t] - [int16x4_t, int32x4_t, uint16x4_t] @@ -376,8 +368,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [cmeq]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - [uint8x8_t, uint8x8_t, ".i8"] - [uint8x16_t, uint8x16_t, ".i8"] @@ -406,8 +397,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [fcmeq]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - [float32x2_t, uint32x2_t] - [float32x4_t, uint32x4_t] @@ -425,8 +415,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [fcmeq]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - [float16x4_t, uint16x4_t] - [float16x8_t, uint16x8_t] @@ -443,8 +432,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [cmtst]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - [int8x8_t, uint8x8_t, i8x8, 'i8x8::new(0, 0, 0, 0, 0, 0, 0, 0)'] - [int8x16_t, uint8x16_t, i8x16, 'i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)'] @@ -471,8 +459,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [fabs]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - float32x2_t - float32x4_t @@ -489,8 +476,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [fabs]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - float16x4_t - float16x8_t @@ -507,8 +493,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [fabs]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - ['h_f16', 'f16'] compose: @@ -529,8 +514,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [cmgt]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - [int8x8_t, uint8x8_t, "s8"] - [int8x16_t, uint8x16_t, "s8"] @@ -551,8 +535,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [cmhi]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - uint8x8_t - uint8x16_t @@ -573,8 +556,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [fcmgt]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - [float32x2_t, uint32x2_t] - [float32x4_t, uint32x4_t] @@ -592,8 +574,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [fcmgt]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - [float16x4_t, uint16x4_t] - [float16x8_t, uint16x8_t] @@ -611,8 +592,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [fcmgt]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - [float16x4_t, uint16x4_t, f16x4, 'f16x4::new(0.0, 0.0, 0.0, 0.0)'] - [float16x8_t, uint16x8_t, f16x8, 'f16x8::new(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0)'] @@ -630,8 +610,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [cmgt]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - [int8x8_t, uint8x8_t] - [int8x16_t, uint8x16_t] @@ -652,8 +631,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [cmge]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - [int8x8_t, uint8x8_t] - [int8x16_t, uint8x16_t] @@ -674,8 +652,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [fcmge]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - [float32x2_t, uint32x2_t] - [float32x4_t, uint32x4_t] @@ -693,8 +670,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [fcmge]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - [float16x4_t, uint16x4_t] - [float16x8_t, uint16x8_t] @@ -711,8 +687,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [fcmle]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - [float16x4_t, uint16x4_t, f16x4, 'f16x4::new(0.0, 0.0, 0.0, 0.0)'] - [float16x8_t, uint16x8_t, f16x8, 'f16x8::new(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0)'] @@ -733,8 +708,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [cmge]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - [int8x8_t, uint8x8_t] - [int8x16_t, uint8x16_t] @@ -755,8 +729,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [cls]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - int8x8_t - int8x16_t @@ -783,8 +756,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [cls]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - [uint8x8_t, int8x8_t] - [uint8x16_t, int8x16_t] @@ -807,8 +779,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [clz]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - [uint8x8_t, int8x8_t] - [uint8x16_t, int8x16_t] @@ -829,8 +800,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [clz]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - [int8x8_t, '.i8'] - [int8x16_t, '.i8'] @@ -857,8 +827,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [clz]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - [uint32x2_t, '.i32', int32x2_t] - [uint32x4_t, '.i32', int32x4_t] @@ -881,8 +850,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [facgt]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - [float32x2_t, uint32x2_t] - [float32x4_t, uint32x4_t] @@ -906,8 +874,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [facgt]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - [float16x4_t, uint16x4_t] - [float16x8_t, uint16x8_t] @@ -930,8 +897,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [facge]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - [float32x2_t, uint32x2_t] - [float32x4_t, uint32x4_t] @@ -954,8 +920,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [facge]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - [float16x4_t, uint16x4_t] - [float16x8_t, uint16x8_t] @@ -978,8 +943,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [facgt]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - [float32x2_t, uint32x2_t] - [float32x4_t, uint32x4_t] @@ -996,8 +960,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [facgt]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - [float16x4_t, uint16x4_t] - [float16x8_t, uint16x8_t] @@ -1014,8 +977,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [facge]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - [float32x2_t, uint32x2_t] - [float32x4_t, uint32x4_t] @@ -1033,8 +995,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [facge]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - [float16x4_t, uint16x4_t] - [float16x8_t, uint16x8_t] @@ -1051,8 +1012,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [scvtf]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - [int32x2_t, float32x2_t] - [int32x4_t, float32x4_t] @@ -1069,8 +1029,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [scvtf]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - [int16x4_t, float16x4_t] - [int16x8_t, float16x8_t] @@ -1087,8 +1046,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [ucvtf]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - [uint32x2_t, float32x2_t] - [uint32x4_t, float32x4_t] @@ -1105,8 +1063,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [ucvtf]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - [uint16x4_t, float16x4_t] - [uint16x8_t, float16x8_t] @@ -1124,8 +1081,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['1']] - FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [uint32x2_t, float32x2_t] - [uint32x4_t, float32x4_t] @@ -1139,7 +1095,7 @@ intrinsics: links: - link: "llvm.arm.neon.vcvtfxu2fp.{neon_type[1]}.{neon_type[0]}" arch: arm - - FnCall: ["_vcvt{neon_type[1].N}_{neon_type[0]}", ["a", N]] + - FnCall: ["_vcvt{neon_type[1].N}_{neon_type[0]}", ["a", N], [], true] - name: "vcvt{neon_type[1].N}_{neon_type[0]}" doc: "Fixed-point convert to floating-point" @@ -1151,8 +1107,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['1']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [uint32x2_t, float32x2_t] - [uint32x4_t, float32x4_t] @@ -1166,7 +1121,7 @@ intrinsics: links: - link: "llvm.aarch64.neon.vcvtfxu2fp.{neon_type[1]}.{neon_type[0]}" arch: aarch64,arm64ec - - FnCall: ["_vcvt{neon_type[1].N}_{neon_type[0]}", ["a", N]] + - FnCall: ["_vcvt{neon_type[1].N}_{neon_type[0]}", ["a", N], [], true] - name: "vcvt{neon_type[1].N}_{neon_type[0]}" doc: "Fixed-point convert to floating-point" @@ -1180,8 +1135,7 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [uint16x4_t, float16x4_t] - [uint16x8_t, float16x8_t] @@ -1197,7 +1151,7 @@ intrinsics: arch: arm - link: "llvm.aarch64.neon.vcvtfxu2fp.{neon_type[1]}.{neon_type[0]}" arch: aarch64,arm64ec - - FnCall: ["_vcvt{neon_type[1].N}_{neon_type[0]}", ["a", N]] + - FnCall: ["_vcvt{neon_type[1].N}_{neon_type[0]}", ["a", N], [], true] - name: "vcvt{neon_type[1].N}_{neon_type[0]}" @@ -1212,8 +1166,7 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [float16x4_t, int16x4_t] - [float16x8_t, int16x8_t] @@ -1229,7 +1182,7 @@ intrinsics: arch: arm - link: "llvm.aarch64.neon.vcvtfp2fxs.{neon_type[1]}.{neon_type[0]}" arch: aarch64,arm64ec - - FnCall: ["_vcvt{neon_type[1].N}_{neon_type[0]}", [a, N]] + - FnCall: ["_vcvt{neon_type[1].N}_{neon_type[0]}", [a, N], [], true] - name: "vcvt{neon_type[1].N}_{neon_type[0]}" @@ -1244,8 +1197,7 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [float16x4_t, uint16x4_t] - [float16x8_t, uint16x8_t] @@ -1261,7 +1213,7 @@ intrinsics: arch: arm - link: "llvm.aarch64.neon.vcvtfp2fxu.{neon_type[1]}.{neon_type[0]}" arch: aarch64,arm64ec - - FnCall: ["_vcvt{neon_type[1].N}_{neon_type[0]}", ["a", N]] + - FnCall: ["_vcvt{neon_type[1].N}_{neon_type[0]}", ["a", N], [], true] - name: "vcvt{neon_type[1].N}_{neon_type[0]}" doc: "Fixed-point convert to floating-point" @@ -1274,8 +1226,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['1']] - FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [int32x2_t, float32x2_t] - [int32x4_t, float32x4_t] @@ -1289,7 +1240,7 @@ intrinsics: links: - link: "llvm.arm.neon.vcvtfxs2fp.{neon_type[1]}.{neon_type[0]}" arch: arm - - FnCall: ["_vcvt{neon_type[1].N}_{neon_type[0]}", [a, N]] + - FnCall: ["_vcvt{neon_type[1].N}_{neon_type[0]}", [a, N], [], true] - name: "vcvt{neon_type[1].N}_{neon_type[0]}" @@ -1304,8 +1255,7 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [int16x4_t, float16x4_t] - [int16x8_t, float16x8_t] @@ -1321,7 +1271,7 @@ intrinsics: arch: arm - link: "llvm.aarch64.neon.vcvtfxs2fp.{neon_type[1]}.{neon_type[0]}" arch: aarch64,arm64ec - - FnCall: ["_vcvt{neon_type[1].N}_{neon_type[0]}", [a, N]] + - FnCall: ["_vcvt{neon_type[1].N}_{neon_type[0]}", [a, N], [], true] - name: "vcvt{neon_type[1].N}_{neon_type[0]}" doc: "Fixed-point convert to floating-point" @@ -1333,8 +1283,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['1']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [int32x2_t, float32x2_t] - [int32x4_t, float32x4_t] @@ -1348,7 +1297,7 @@ intrinsics: links: - link: "llvm.aarch64.neon.vcvtfxs2fp.{neon_type[1]}.{neon_type[0]}" arch: aarch64,arm64ec - - FnCall: ["_vcvt{neon_type[1].N}_{neon_type[0]}", [a, N]] + - FnCall: ["_vcvt{neon_type[1].N}_{neon_type[0]}", [a, N], [], true] - name: "vcvt{type[2]}" doc: "Floating-point convert to fixed-point, rounding toward zero" @@ -1361,8 +1310,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['1']] - FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [float32x2_t, int32x2_t, _n_s32_f32] - [float32x4_t, int32x4_t, q_n_s32_f32] @@ -1374,7 +1322,7 @@ intrinsics: links: - link: "llvm.arm.neon.vcvtfp2fxs.{neon_type[1]}.{neon_type[0]}" arch: arm - - FnCall: ["_vcvt{type[2]}", [a, N]] + - FnCall: ["_vcvt{type[2]}", [a, N], [], true] - name: "vcvt{type[2]}" doc: "Floating-point convert to fixed-point, rounding toward zero" @@ -1387,8 +1335,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['1']] - FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [float32x2_t, uint32x2_t, _n_u32_f32] - [float32x4_t, uint32x4_t, q_n_u32_f32] @@ -1400,7 +1347,7 @@ intrinsics: links: - link: "llvm.arm.neon.vcvtfp2fxu.{neon_type[1]}.{neon_type[0]}" arch: arm - - FnCall: ["_vcvt{type[2]}", [a, N]] + - FnCall: ["_vcvt{type[2]}", [a, N], [], true] - name: "vcvt{type[2]}" doc: "Floating-point convert to fixed-point, rounding toward zero" @@ -1412,8 +1359,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['1']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [float32x2_t, int32x2_t, _n_s32_f32] - [float32x4_t, int32x4_t, q_n_s32_f32] @@ -1425,7 +1371,7 @@ intrinsics: links: - link: "llvm.aarch64.neon.vcvtfp2fxs.{neon_type[1]}.{neon_type[0]}" arch: aarch64,arm64ec - - FnCall: ["_vcvt{type[2]}", [a, N]] + - FnCall: ["_vcvt{type[2]}", [a, N], [], true] - name: "vcvt{type[2]}" doc: "Floating-point convert to fixed-point, rounding toward zero" @@ -1437,8 +1383,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['1']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [float32x2_t, uint32x2_t, _n_u32_f32] - [float32x4_t, uint32x4_t, q_n_u32_f32] @@ -1452,7 +1397,7 @@ intrinsics: links: - link: "llvm.aarch64.neon.vcvtfp2fxu.{neon_type[1]}.{neon_type[0]}" arch: aarch64,arm64ec - - FnCall: ["_vcvt{type[2]}", [a, N]] + - FnCall: ["_vcvt{type[2]}", [a, N], [], true] - name: "vdup{type[0]}" doc: "Set all vector lanes to the same value" @@ -1466,8 +1411,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [_lane_s8, int8x8_t, int8x8_t, '3', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]'] - [q_lane_s8, int8x8_t, int8x16_t, '3', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]'] @@ -1491,8 +1435,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [q_laneq_s8, int8x16_t, int8x16_t, '4', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]'] - [_laneq_s8, int8x16_t, int8x8_t, '4', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]'] @@ -1516,8 +1459,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [_lane_s16, int16x4_t, int16x4_t, '2', '[N as u32, N as u32, N as u32, N as u32]'] - [q_lane_s16, int16x4_t, int16x8_t, '2', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]'] @@ -1541,8 +1483,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [q_laneq_s16, int16x8_t, int16x8_t, '3', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]'] - [_laneq_s16, int16x8_t, int16x4_t, '3', '[N as u32, N as u32, N as u32, N as u32]'] @@ -1567,8 +1508,7 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [q_laneq_f16, float16x8_t, float16x8_t, '3', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]'] - [_laneq_f16, float16x8_t, float16x4_t, '3', '[N as u32, N as u32, N as u32, N as u32]'] @@ -1586,8 +1526,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [dup]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - [float16x4_t, f16, 'float16x4', '_n_'] - [float16x8_t, f16, 'float16x8', 'q_n_'] @@ -1606,8 +1545,7 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [_lane_f16, float16x4_t, float16x4_t, '2', '[N as u32, N as u32, N as u32, N as u32]'] - [q_lane_f16, float16x4_t, float16x8_t, '2', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]'] @@ -1628,8 +1566,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [_lane_s32, int32x2_t, int32x2_t, '1', '[N as u32, N as u32]'] - [q_lane_s32, int32x2_t, int32x4_t, '1', '[N as u32, N as u32, N as u32, N as u32]'] @@ -1653,8 +1590,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [q_laneq_s32, int32x4_t, int32x4_t, '2', '[N as u32, N as u32, N as u32, N as u32]'] - [_laneq_s32, int32x4_t, int32x2_t, '2', '[N as u32, N as u32]'] @@ -1678,8 +1614,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [q_laneq_s64, int64x2_t, '1', '[N as u32, N as u32]'] - [q_laneq_u64, uint64x2_t, '1', '[N as u32, N as u32]'] @@ -1699,8 +1634,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [q_lane_s64, int64x1_t, int64x2_t] - [q_lane_u64, uint64x1_t, uint64x2_t] @@ -1720,8 +1654,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [_lane_s64, int64x1_t] - [_lane_u64, uint64x1_t] @@ -1741,8 +1674,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [_laneq_s64, int64x2_t, int64x1_t, '::'] - [_laneq_u64, uint64x2_t, uint64x1_t, '::'] @@ -1764,15 +1696,14 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - - [int8x8_t, ' static_assert_uimm_bits!(N, 3);', 'match N & 0b111 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), _ => unreachable_unchecked(), }'] - - [int16x8_t, ' static_assert_uimm_bits!(N, 3);', 'match N & 0b111 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), _ => unreachable_unchecked(), }'] - - [uint8x8_t, ' static_assert_uimm_bits!(N, 3);', 'match N & 0b111 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), _ => unreachable_unchecked(), }'] - - [uint16x8_t, ' static_assert_uimm_bits!(N, 3);', 'match N & 0b111 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), _ => unreachable_unchecked(), }'] - - [poly8x8_t, ' static_assert_uimm_bits!(N, 3);', 'match N & 0b111 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), _ => unreachable_unchecked(), }'] - - [poly16x8_t, ' static_assert_uimm_bits!(N, 3);', 'match N & 0b111 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), _ => unreachable_unchecked(), }'] + - [int8x8_t, ' static_assert_uimm_bits!(N, 3);', 'unsafe { match N & 0b111 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), _ => unreachable_unchecked(), } }'] + - [int16x8_t, ' static_assert_uimm_bits!(N, 3);', 'unsafe { match N & 0b111 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), _ => unreachable_unchecked(), } }'] + - [uint8x8_t, ' static_assert_uimm_bits!(N, 3);', 'unsafe { match N & 0b111 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), _ => unreachable_unchecked(), } }'] + - [uint16x8_t, ' static_assert_uimm_bits!(N, 3);', 'unsafe { match N & 0b111 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), _ => unreachable_unchecked(), } }'] + - [poly8x8_t, ' static_assert_uimm_bits!(N, 3);', 'unsafe { match N & 0b111 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), _ => unreachable_unchecked(), } }'] + - [poly16x8_t, ' static_assert_uimm_bits!(N, 3);', 'unsafe { match N & 0b111 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), _ => unreachable_unchecked(), } }'] compose: - Identifier: ["{type[1]}", Symbol] - Identifier: ["{type[2]}", Symbol] @@ -1789,12 +1720,11 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - - [int8x16_t, ' static_assert_uimm_bits!(N, 4);', 'match N & 0b1111 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18]), 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19]), 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20]), 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21]), 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22]), 8 => simd_shuffle!(a, b, [8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23]), 9 => simd_shuffle!(a, b, [9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24]), 10 => simd_shuffle!(a, b, [10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25]), 11 => simd_shuffle!(a, b, [11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26]), 12 => simd_shuffle!(a, b, [12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27]), 13 => simd_shuffle!(a, b, [13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28]), 14 => simd_shuffle!(a, b, [14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29]), 15 => simd_shuffle!(a, b, [15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30]), _ => unreachable_unchecked(), }'] - - [uint8x16_t, ' static_assert_uimm_bits!(N, 4);', 'match N & 0b1111 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18]), 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19]), 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20]), 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21]), 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22]), 8 => simd_shuffle!(a, b, [8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23]), 9 => simd_shuffle!(a, b, [9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24]), 10 => simd_shuffle!(a, b, [10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25]), 11 => simd_shuffle!(a, b, [11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26]), 12 => simd_shuffle!(a, b, [12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27]), 13 => simd_shuffle!(a, b, [13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28]), 14 => simd_shuffle!(a, b, [14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29]), 15 => simd_shuffle!(a, b, [15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30]), _ => unreachable_unchecked(), }'] - - [poly8x16_t, ' static_assert_uimm_bits!(N, 4);', 'match N & 0b1111 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18]), 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19]), 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20]), 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21]), 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22]), 8 => simd_shuffle!(a, b, [8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23]), 9 => simd_shuffle!(a, b, [9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24]), 10 => simd_shuffle!(a, b, [10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25]), 11 => simd_shuffle!(a, b, [11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26]), 12 => simd_shuffle!(a, b, [12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27]), 13 => simd_shuffle!(a, b, [13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28]), 14 => simd_shuffle!(a, b, [14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29]), 15 => simd_shuffle!(a, b, [15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30]), _ => unreachable_unchecked(), }'] + - [int8x16_t, ' static_assert_uimm_bits!(N, 4);', 'unsafe { match N & 0b1111 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18]), 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19]), 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20]), 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21]), 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22]), 8 => simd_shuffle!(a, b, [8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23]), 9 => simd_shuffle!(a, b, [9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24]), 10 => simd_shuffle!(a, b, [10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25]), 11 => simd_shuffle!(a, b, [11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26]), 12 => simd_shuffle!(a, b, [12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27]), 13 => simd_shuffle!(a, b, [13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28]), 14 => simd_shuffle!(a, b, [14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29]), 15 => simd_shuffle!(a, b, [15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30]), _ => unreachable_unchecked(), } }'] + - [uint8x16_t, ' static_assert_uimm_bits!(N, 4);', 'unsafe { match N & 0b1111 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18]), 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19]), 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20]), 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21]), 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22]), 8 => simd_shuffle!(a, b, [8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23]), 9 => simd_shuffle!(a, b, [9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24]), 10 => simd_shuffle!(a, b, [10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25]), 11 => simd_shuffle!(a, b, [11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26]), 12 => simd_shuffle!(a, b, [12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27]), 13 => simd_shuffle!(a, b, [13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28]), 14 => simd_shuffle!(a, b, [14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29]), 15 => simd_shuffle!(a, b, [15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30]), _ => unreachable_unchecked(), } }'] + - [poly8x16_t, ' static_assert_uimm_bits!(N, 4);', 'unsafe { match N & 0b1111 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18]), 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19]), 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20]), 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21]), 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22]), 8 => simd_shuffle!(a, b, [8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23]), 9 => simd_shuffle!(a, b, [9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24]), 10 => simd_shuffle!(a, b, [10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25]), 11 => simd_shuffle!(a, b, [11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26]), 12 => simd_shuffle!(a, b, [12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27]), 13 => simd_shuffle!(a, b, [13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28]), 14 => simd_shuffle!(a, b, [14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29]), 15 => simd_shuffle!(a, b, [15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30]), _ => unreachable_unchecked(), } }'] compose: - Identifier: ["{type[1]}", Symbol] - Identifier: ["{type[2]}", Symbol] @@ -1811,15 +1741,14 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - - [int16x4_t, 'static_assert_uimm_bits!(N, 2);', 'match N & 0b11 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), _ => unreachable_unchecked(), }'] - - [int32x4_t, ' static_assert_uimm_bits!(N, 2);', 'match N & 0b11 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), _ => unreachable_unchecked(), }'] - - [uint16x4_t, ' static_assert_uimm_bits!(N, 2);', 'match N & 0b11 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), _ => unreachable_unchecked(), }'] - - [uint32x4_t, ' static_assert_uimm_bits!(N, 2);', 'match N & 0b11 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), _ => unreachable_unchecked(), }'] - - [poly16x4_t, ' static_assert_uimm_bits!(N, 2);', 'match N & 0b11 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), _ => unreachable_unchecked(), }'] - - [float32x4_t, ' static_assert_uimm_bits!(N, 2);', 'match N & 0b11 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), _ => unreachable_unchecked(), }'] + - [int16x4_t, 'static_assert_uimm_bits!(N, 2);', 'unsafe { match N & 0b11 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), _ => unreachable_unchecked(), } }'] + - [int32x4_t, ' static_assert_uimm_bits!(N, 2);', 'unsafe { match N & 0b11 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), _ => unreachable_unchecked(), } }'] + - [uint16x4_t, ' static_assert_uimm_bits!(N, 2);', 'unsafe { match N & 0b11 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), _ => unreachable_unchecked(), } }'] + - [uint32x4_t, ' static_assert_uimm_bits!(N, 2);', 'unsafe { match N & 0b11 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), _ => unreachable_unchecked(), } }'] + - [poly16x4_t, ' static_assert_uimm_bits!(N, 2);', 'unsafe { match N & 0b11 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), _ => unreachable_unchecked(), } }'] + - [float32x4_t, ' static_assert_uimm_bits!(N, 2);', 'unsafe { match N & 0b11 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), _ => unreachable_unchecked(), } }'] compose: - Identifier: ["{type[1]}", Symbol] - Identifier: ["{type[2]}", Symbol] @@ -1837,10 +1766,9 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - - [float16x4_t, ' static_assert_uimm_bits!(N, 2); match N & 0b11 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), _ => unreachable_unchecked(), }'] + - [float16x4_t, ' static_assert_uimm_bits!(N, 2); unsafe { match N & 0b11 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), _ => unreachable_unchecked(), } }'] compose: - Identifier: ["{type[1]}", Symbol] @@ -1856,10 +1784,9 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - - [float16x8_t, ' static_assert_uimm_bits!(N, 3); match N & 0b111 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), _ => unreachable_unchecked(), }'] + - [float16x8_t, ' static_assert_uimm_bits!(N, 3); unsafe { match N & 0b111 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), _ => unreachable_unchecked(), } }'] compose: - Identifier: ["{type[1]}", Symbol] @@ -1877,12 +1804,11 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - - [int32x2_t, ' static_assert_uimm_bits!(N, 1);', 'match N & 0b1 { 0 => simd_shuffle!(a, b, [0, 1]), 1 => simd_shuffle!(a, b, [1, 2]), _ => unreachable_unchecked(), }'] - - [uint32x2_t, ' static_assert_uimm_bits!(N, 1);', 'match N & 0b1 { 0 => simd_shuffle!(a, b, [0, 1]), 1 => simd_shuffle!(a, b, [1, 2]), _ => unreachable_unchecked(), }'] - - [float32x2_t, ' static_assert_uimm_bits!(N, 1);', 'match N & 0b1 { 0 => simd_shuffle!(a, b, [0, 1]), 1 => simd_shuffle!(a, b, [1, 2]), _ => unreachable_unchecked(), }'] + - [int32x2_t, ' static_assert_uimm_bits!(N, 1);', 'unsafe { match N & 0b1 { 0 => simd_shuffle!(a, b, [0, 1]), 1 => simd_shuffle!(a, b, [1, 2]), _ => unreachable_unchecked(), } }'] + - [uint32x2_t, ' static_assert_uimm_bits!(N, 1);', 'unsafe { match N & 0b1 { 0 => simd_shuffle!(a, b, [0, 1]), 1 => simd_shuffle!(a, b, [1, 2]), _ => unreachable_unchecked(), } }'] + - [float32x2_t, ' static_assert_uimm_bits!(N, 1);', 'unsafe { match N & 0b1 { 0 => simd_shuffle!(a, b, [0, 1]), 1 => simd_shuffle!(a, b, [1, 2]), _ => unreachable_unchecked(), } }'] compose: - Identifier: ["{type[1]}", Symbol] - Identifier: ["{type[2]}", Symbol] @@ -1899,11 +1825,10 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - - [int64x2_t, 'static_assert_uimm_bits!(N, 1);', 'match N & 0b1 { 0 => simd_shuffle!(a, b, [0, 1]), 1 => simd_shuffle!(a, b, [1, 2]), _ => unreachable_unchecked(), }'] - - [uint64x2_t, 'static_assert_uimm_bits!(N, 1);', 'match N & 0b1 { 0 => simd_shuffle!(a, b, [0, 1]), 1 => simd_shuffle!(a, b, [1, 2]), _ => unreachable_unchecked(), }'] + - [int64x2_t, 'static_assert_uimm_bits!(N, 1);', 'unsafe { match N & 0b1 { 0 => simd_shuffle!(a, b, [0, 1]), 1 => simd_shuffle!(a, b, [1, 2]), _ => unreachable_unchecked(), } }'] + - [uint64x2_t, 'static_assert_uimm_bits!(N, 1);', 'unsafe { match N & 0b1 { 0 => simd_shuffle!(a, b, [0, 1]), 1 => simd_shuffle!(a, b, [1, 2]), _ => unreachable_unchecked(), } }'] compose: - Identifier: ["{type[1]}", Symbol] - Identifier: ["{type[2]}", Symbol] @@ -1918,8 +1843,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [mla]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - [int8x8_t, ".i8"] - [int8x16_t, ".i8"] @@ -1946,8 +1870,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [fmul]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - float32x2_t - float32x4_t @@ -1964,8 +1887,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [smlal]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - [int16x8_t, int8x8_t, "s8"] - [int32x4_t, int16x4_t, "s16"] @@ -1983,8 +1905,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [smlal]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - [int32x4_t, int16x4_t, "i16", int32x4_t, 's16'] - [int64x2_t, int32x2_t, "i32", int64x2_t, 's32'] @@ -2005,8 +1926,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [umlal]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - [uint32x4_t, uint16x4_t, "u16", uint32x4_t] - [uint64x2_t, uint32x2_t, "u32", uint64x2_t] @@ -2029,8 +1949,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] static_defs: ['const LANE: i32'] - safety: - unsafe: [neon] + safety: safe types: - [int32x4_t, int16x4_t, int16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - [int32x4_t, int16x4_t, int16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] @@ -2056,8 +1975,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] static_defs: ['const LANE: i32'] - safety: - unsafe: [neon] + safety: safe types: - [uint32x4_t, uint16x4_t, uint16x4_t, uint32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - [uint32x4_t, uint16x4_t, uint16x8_t, uint32x4_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] @@ -2081,8 +1999,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [umlal]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - [uint16x8_t, uint8x8_t] - [uint32x4_t, uint16x4_t] @@ -2103,8 +2020,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [mls]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - [int8x8_t, '.i8'] - [int8x16_t, '.i8'] @@ -2134,8 +2050,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [smlsl]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - [int16x8_t, int8x8_t] - [int32x4_t, int16x4_t] @@ -2153,8 +2068,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [smlsl]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - [int32x4_t, int16x4_t, "i16"] - [int64x2_t, int32x2_t, "i32"] @@ -2171,8 +2085,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [umlsl]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - [uint32x4_t, uint16x4_t, "u16"] - [uint64x2_t, uint32x2_t, "u32"] @@ -2191,8 +2104,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] static_defs: ['const LANE: i32'] - safety: - unsafe: [neon] + safety: safe types: - [int32x4_t, int16x4_t, int16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - [int32x4_t, int16x4_t, int16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] @@ -2216,8 +2128,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] static_defs: ['const LANE: i32'] - safety: - unsafe: [neon] + safety: safe types: - [int64x2_t, int32x2_t, int32x2_t, '[LANE as u32, LANE as u32]', '1'] - [int64x2_t, int32x2_t, int32x4_t, '[LANE as u32, LANE as u32]', '2'] @@ -2241,8 +2152,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] static_defs: ['const LANE: i32'] - safety: - unsafe: [neon] + safety: safe types: - [uint32x4_t, uint16x4_t, uint16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - [uint32x4_t, uint16x4_t, uint16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] @@ -2266,8 +2176,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [umlsl]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - [uint16x8_t, uint8x8_t] - [uint32x4_t, uint16x4_t] @@ -2285,8 +2194,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [neg]]}]] - *neon-stable-not-arm - *neon-unstable-is-arm - safety: - unsafe: [neon] + safety: safe types: - [int8x8_t, 's8'] - [int8x16_t, 's8'] @@ -2307,8 +2215,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [fneg]]}]] - *neon-stable-not-arm - *neon-unstable-is-arm - safety: - unsafe: [neon] + safety: safe types: - [float32x2_t, 'f32'] - [float32x4_t, 'f32'] @@ -2325,8 +2232,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [fneg]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - [float16x4_t, 'f16'] - [float16x8_t, 'f16'] @@ -2343,8 +2249,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [sqneg]]}]] - *neon-stable-not-arm - *neon-unstable-is-arm - safety: - unsafe: [neon] + safety: safe types: - [int8x8_t, 's8', 'i8'] - [int8x16_t, 's8', 'i8'] @@ -2371,8 +2276,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [uqsub]]}]] - *neon-stable-not-arm - *neon-unstable-is-arm - safety: - unsafe: [neon] + safety: safe types: - [uint8x8_t, u8, i8] - [uint8x16_t, u8, i8] @@ -2401,8 +2305,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [sqsub]]}]] - *neon-stable-not-arm - *neon-unstable-is-arm - safety: - unsafe: [neon] + safety: safe types: - [int8x8_t, s8, i8] - [int8x16_t, s8, i8] @@ -2469,8 +2372,7 @@ intrinsics: - unstable - - 'feature = "stdarch_arm_neon_intrinsics"' - 'issue = "111800"' - safety: - unsafe: [neon] + safety: safe types: - uint8x8_t - uint8x16_t @@ -2535,8 +2437,7 @@ intrinsics: - unstable - - 'feature = "stdarch_arm_neon_intrinsics"' - 'issue = "111800"' - safety: - unsafe: [neon] + safety: safe types: - int8x8_t - int8x16_t @@ -2563,8 +2464,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [srhadd]]}]] - *neon-stable-not-arm - *neon-unstable-is-arm - safety: - unsafe: [neon] + safety: safe types: - int8x8_t - int8x16_t @@ -2591,8 +2491,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [urhadd]]}]] - *neon-stable-not-arm - *neon-unstable-is-arm - safety: - unsafe: [neon] + safety: safe types: - uint8x8_t - uint8x16_t @@ -2619,8 +2518,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [frintn]]}]] - *neon-stable-not-arm - *neon-unstable-is-arm - safety: - unsafe: [neon] + safety: safe types: - float32x2_t - float32x4_t @@ -2643,8 +2541,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [frintn]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - float16x4_t - float16x8_t @@ -2667,8 +2564,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [uqadd]]}]] - *neon-stable-not-arm - *neon-unstable-is-arm - safety: - unsafe: [neon] + safety: safe types: - uint8x8_t - uint8x16_t @@ -2697,8 +2593,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [sqadd]]}]] - *neon-stable-not-arm - *neon-unstable-is-arm - safety: - unsafe: [neon] + safety: safe types: - int8x8_t - int8x16_t @@ -4061,10 +3956,10 @@ intrinsics: - *enable-v7 - *neon-unstable assert_instr: [nop] - types: - - ['*const i64', int64x1x3_t, i64] safety: unsafe: [neon] + types: + - ['*const i64', int64x1x3_t, i64] compose: - LLVMLink: name: 'vld3{neon_type[1].nox}' @@ -6359,8 +6254,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [usdot]]}]] - *neon-unstable-i8mm - *neon-unstable-is-arm - safety: - unsafe: [neon] + safety: safe types: - [int32x2_t, uint8x8_t, int8x8_t] - [int32x4_t, uint8x16_t, int8x16_t] @@ -6386,8 +6280,7 @@ intrinsics: - *neon-unstable-i8mm - *neon-unstable-is-arm static_defs: ["const LANE: i32"] - safety: - unsafe: [neon] + safety: safe types: - ['_lane_s32', int32x2_t, uint8x8_t, '[LANE as u32, LANE as u32]'] - ['q_lane_s32', int32x4_t, uint8x16_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] @@ -6416,8 +6309,7 @@ intrinsics: - *neon-unstable-i8mm - *neon-unstable-is-arm static_defs: ["const LANE: i32"] - safety: - unsafe: [neon] + safety: safe types: - [int32x2_t, int8x8_t, uint8x8_t, '[LANE as u32, LANE as u32]', uint32x2_t] - [int32x4_t, int8x16_t, uint8x8_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]', uint32x4_t] @@ -6443,8 +6335,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [mul]]}]] - *neon-stable-not-arm - *neon-unstable-is-arm - safety: - unsafe: [neon] + safety: safe types: - ['.i8', int8x8_t] - ['.i8', int8x16_t] @@ -6471,8 +6362,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [fmul]]}]] - *neon-stable-not-arm - *neon-unstable-is-arm - safety: - unsafe: [neon] + safety: safe types: - [f32, float32x2_t] - [f32, float32x4_t] @@ -6490,8 +6380,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [fmul]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - [f16, float16x4_t] - [f16, float16x8_t] @@ -6511,8 +6400,7 @@ intrinsics: - *neon-stable-not-arm - *neon-unstable-is-arm static_defs: ["const LANE: i32"] - safety: - unsafe: [neon] + safety: safe types: - [int16x4_t, int16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - [int16x8_t, int16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] @@ -6542,8 +6430,7 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 static_defs: ["const LANE: i32"] - safety: - unsafe: [neon] + safety: safe types: - [float16x4_t, float16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - [float16x8_t, float16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] @@ -6567,8 +6454,7 @@ intrinsics: - *neon-stable-not-arm - *neon-unstable-is-arm static_defs: ["const LANE: i32"] - safety: - unsafe: [neon] + safety: safe types: - [int16x4_t, int16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - [int16x8_t, int16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] @@ -6595,8 +6481,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [smull]]}]] - *neon-stable-not-arm - *neon-unstable-is-arm - safety: - unsafe: [neon] + safety: safe types: - ["s8", int8x8_t, int16x8_t] - ["s16", int16x4_t, int32x4_t] @@ -6620,8 +6505,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [umull]]}]] - *neon-stable-not-arm - *neon-unstable-is-arm - safety: - unsafe: [neon] + safety: safe types: - ["u8", uint8x8_t, uint16x8_t] - ["u16", uint16x4_t, uint32x4_t] @@ -6645,8 +6529,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [pmull]]}]] - *neon-stable-not-arm - *neon-unstable-is-arm - safety: - unsafe: [neon] + safety: safe types: - ["p8", poly8x8_t, poly16x8_t] compose: @@ -6668,8 +6551,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [smull]]}]] - *neon-stable-not-arm - *neon-unstable-is-arm - safety: - unsafe: [neon] + safety: safe types: - [int16x4_t, "i16", int32x4_t] - [int32x2_t, "i32", int64x2_t] @@ -6691,8 +6573,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [umull]]}]] - *neon-stable-not-arm - *neon-unstable-is-arm - safety: - unsafe: [neon] + safety: safe types: - [uint16x4_t, "u16", uint32x4_t] - [uint32x2_t, "u32", uint64x2_t] @@ -6747,8 +6628,7 @@ intrinsics: - unstable - - 'feature = "stdarch_arm_neon_intrinsics"' - 'issue = "111800"' - safety: - unsafe: [neon] + safety: safe types: - float32x2_t - float32x4_t @@ -6760,7 +6640,7 @@ intrinsics: arch: aarch64 - link: "llvm.fma.{neon_type}" arch: arm - - FnCall: ["_vfma{neon_type.no}", [b, c, a]] + - FnCall: ["_vfma{neon_type.no}", [b, c, a], [], true] - name: "vfma{neon_type.no}" @@ -6773,8 +6653,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [fmla]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - float16x4_t - float16x8_t @@ -6786,7 +6665,7 @@ intrinsics: arch: aarch64 - link: "llvm.fma.{neon_type}" arch: arm - - FnCall: ["_vfma{neon_type.no}", [b, c, a]] + - FnCall: ["_vfma{neon_type.no}", [b, c, a], [], true] - name: "vfma{neon_type[0].N}" @@ -6832,8 +6711,7 @@ intrinsics: - unstable - - 'feature = "stdarch_arm_neon_intrinsics"' - 'issue = "111800"' - safety: - unsafe: [neon] + safety: safe types: - [float32x2_t, f32] - [float32x4_t, f32] @@ -6856,8 +6734,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [sub]]}]] - *neon-stable-not-arm - *neon-unstable-is-arm - safety: - unsafe: [neon] + safety: safe types: - ['.i8', int8x8_t] - ['.i8', int8x16_t] @@ -6888,8 +6765,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [fsub]]}]] - *neon-stable-not-arm - *neon-unstable-is-arm - safety: - unsafe: [neon] + safety: safe types: - ['f32', float32x2_t] - ['f32', float32x4_t] @@ -6907,8 +6783,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [fsub]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - ['f16', float16x4_t] - ['f16', float16x8_t] @@ -6926,8 +6801,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [fadd]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - float16x4_t - float16x8_t @@ -6947,8 +6821,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [fadd]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - ['h_f16', 'f16'] compose: @@ -7002,8 +6875,7 @@ intrinsics: - unstable - - 'feature = "stdarch_arm_neon_intrinsics"' - 'issue = "111800"' - safety: - unsafe: [neon] + safety: safe types: - poly8x8_t - poly16x4_t @@ -7065,8 +6937,7 @@ intrinsics: - unstable - - 'feature = "stdarch_arm_neon_intrinsics"' - 'issue = "111800"' - safety: - unsafe: [neon] + safety: safe types: - p128 compose: @@ -7084,8 +6955,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [subhn]]}]] - *neon-stable-not-arm - *neon-unstable-is-arm - safety: - unsafe: [neon] + safety: safe types: - [int16x8_t, int8x8_t, 'i16x8', 'i16x8::new(8, 8, 8, 8, 8, 8, 8, 8)'] - [int32x4_t, int16x4_t, 'i32x4', 'i32x4::new(16, 16, 16, 16)'] @@ -7112,8 +6982,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [subhn2]]}]] - *neon-stable-not-arm - *neon-unstable-is-arm - safety: - unsafe: [neon] + safety: safe types: - [int8x8_t, int16x8_t, int8x16_t, '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]'] - [int16x4_t, int32x4_t, int16x8_t, '[0, 1, 2, 3, 4, 5, 6, 7]'] @@ -7138,8 +7007,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [uhsub]]}]] - *neon-stable-not-arm - *neon-unstable-is-arm - safety: - unsafe: [neon] + safety: safe types: - ['u8', uint8x8_t] - ['u8', uint8x16_t] @@ -7166,8 +7034,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [shsub]]}]] - *neon-stable-not-arm - *neon-unstable-is-arm - safety: - unsafe: [neon] + safety: safe types: - ['s8', int8x8_t] - ['s8', int8x16_t] @@ -7194,8 +7061,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ssubw]]}]] - *neon-stable-not-arm - *neon-unstable-is-arm - safety: - unsafe: [neon] + safety: safe types: - [int16x8_t, int8x8_t] - [int32x4_t, int16x4_t] @@ -7216,8 +7082,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [usubw]]}]] - *neon-stable-not-arm - *neon-unstable-is-arm - safety: - unsafe: [neon] + safety: safe types: - [uint16x8_t, uint8x8_t] - [uint32x4_t, uint16x4_t] @@ -7238,8 +7103,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ssubl]]}]] - *neon-stable-not-arm - *neon-unstable-is-arm - safety: - unsafe: [neon] + safety: safe types: - [int8x8_t, int16x8_t] - [int16x4_t, int32x4_t] @@ -7265,8 +7129,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [usubl]]}]] - *neon-stable-not-arm - *neon-unstable-is-arm - safety: - unsafe: [neon] + safety: safe types: - [uint8x8_t, uint16x8_t] - [uint16x4_t, uint32x4_t] @@ -7293,8 +7156,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [sdot]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [unstable, ['feature = "stdarch_neon_dotprod"', 'issue = "117224"']]}]] - *neon-unstable-is-arm - safety: - unsafe: [neon] + safety: safe types: - [int32x2_t, int8x8_t] - [int32x4_t, int8x16_t] @@ -7318,8 +7180,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [udot]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [unstable, ['feature = "stdarch_neon_dotprod"', 'issue = "117224"']]}]] - *neon-unstable-is-arm - safety: - unsafe: [neon] + safety: safe types: - [uint32x2_t, uint8x8_t] - [uint32x4_t, uint8x16_t] @@ -7345,8 +7206,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['3']] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [unstable, ['feature = "stdarch_neon_dotprod"', 'issue = "117224"']]}]] - *neon-unstable-is-arm - safety: - unsafe: [neon] + safety: safe types: - [int32x2_t, int8x8_t, int8x8_t, int32x2_t, '[LANE as u32, LANE as u32]'] - [int32x4_t, int8x16_t, int8x8_t, int32x2_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] @@ -7379,8 +7239,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['3']] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [unstable, ['feature = "stdarch_neon_dotprod"', 'issue = "117224"']]}]] - *neon-unstable-is-arm - safety: - unsafe: [neon] + safety: safe types: - [uint32x2_t, uint8x8_t, uint8x8_t, uint32x2_t, '[LANE as u32, LANE as u32]'] - [uint32x4_t, uint8x16_t, uint8x8_t, uint32x2_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] @@ -7410,8 +7269,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [smax]]}]] - *neon-stable-not-arm - *neon-unstable-is-arm - safety: - unsafe: [neon] + safety: safe types: - int8x8_t - int8x16_t @@ -7438,8 +7296,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [umax]]}]] - *neon-stable-not-arm - *neon-unstable-is-arm - safety: - unsafe: [neon] + safety: safe types: - uint8x8_t - uint8x16_t @@ -7466,8 +7323,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [fmax]]}]] - *neon-stable-not-arm - *neon-unstable-is-arm - safety: - unsafe: [neon] + safety: safe types: - float32x2_t - float32x4_t @@ -7491,8 +7347,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [fmax]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - float16x4_t - float16x8_t @@ -7516,8 +7371,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [fmaxnm]]}]] - *neon-stable-not-arm - *neon-unstable-is-arm - safety: - unsafe: [neon] + safety: safe types: - float32x2_t - float32x4_t @@ -7541,8 +7395,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [fmaxnm]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - float16x4_t - float16x8_t @@ -7566,8 +7419,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [fminnm]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - float16x4_t - float16x8_t @@ -7591,8 +7443,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [smin]]}]] - *neon-stable-not-arm - *neon-unstable-is-arm - safety: - unsafe: [neon] + safety: safe types: - int8x8_t - int8x16_t @@ -7619,8 +7470,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [umin]]}]] - *neon-stable-not-arm - *neon-unstable-is-arm - safety: - unsafe: [neon] + safety: safe types: - uint8x8_t - uint8x16_t @@ -7647,8 +7497,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [fmin]]}]] - *neon-stable-not-arm - *neon-unstable-is-arm - safety: - unsafe: [neon] + safety: safe types: - float32x2_t - float32x4_t @@ -7672,8 +7521,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [fmin]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - float16x4_t - float16x8_t @@ -7698,8 +7546,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [fminnm]]}]] - *neon-stable-not-arm - *neon-unstable-is-arm - safety: - unsafe: [neon] + safety: safe types: - float32x2_t - float32x4_t @@ -7722,8 +7569,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [faddp]]}]] - *neon-stable-not-arm - *neon-unstable-is-arm - safety: - unsafe: [neon] + safety: safe types: - float32x2_t compose: @@ -7745,8 +7591,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [faddp]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - float16x4_t compose: @@ -7769,8 +7614,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [sqdmull]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - [int16x4_t, int32x4_t] - [int32x2_t, int64x2_t] @@ -7793,8 +7637,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [sqdmull]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - [int16x4_t, "i16", int32x4_t] - [int32x2_t, "i32", int64x2_t] @@ -7813,8 +7656,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [int16x4_t, int16x4_t, int32x4_t, '[N as u32, N as u32, N as u32, N as u32]'] compose: @@ -7834,8 +7676,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [int32x2_t, int32x2_t, int64x2_t, '[N as u32, N as u32]'] compose: @@ -7853,8 +7694,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [sqdmlal]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - [int32x4_t, int16x4_t, int16x4_t, int32x4_t] - [int64x2_t, int32x2_t, int32x2_t, int64x2_t] @@ -7871,8 +7711,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [sqdmlal]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - [int32x4_t, int16x4_t, "i16", int32x4_t] - [int64x2_t, int32x2_t, "i32", int64x2_t] @@ -7891,8 +7730,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [int32x4_t, int16x4_t, int16x4_t, int32x4_t] compose: @@ -7911,8 +7749,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [int64x2_t, int32x2_t, int32x2_t, int64x2_t] compose: @@ -7929,8 +7766,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [sqdmlsl]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - [int32x4_t, int16x4_t, int16x4_t, int32x4_t] - [int64x2_t, int32x2_t, int32x2_t, int64x2_t] @@ -7947,8 +7783,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [sqdmlsl]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - [int32x4_t, int16x4_t, "i16", int32x4_t, '_n_s16'] - [int64x2_t, int32x2_t, "i32", int64x2_t, '_n_s32'] @@ -7967,8 +7802,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [int32x4_t, int16x4_t, int16x4_t, int32x4_t] compose: @@ -7987,8 +7821,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [int64x2_t, int32x2_t, int32x2_t, int64x2_t] compose: @@ -8005,8 +7838,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [sqdmulh]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - [int16x4_t, int16x4_t, int16x4_t] - [int16x8_t, int16x8_t, int16x8_t] @@ -8031,8 +7863,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [sqdmulh]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - [int16x4_t, "i16", int16x4_t, '_n_s16'] - [int32x2_t, "i32", int32x2_t, '_n_s32'] @@ -8052,8 +7883,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [sqxtn]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - [int16x8_t, int8x8_t] - [int32x4_t, int16x4_t] @@ -8077,8 +7907,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [sqxtun]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - [int16x8_t, uint8x8_t] - [int32x4_t, uint16x4_t] @@ -8102,8 +7931,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [sqrdmulh]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - [int16x4_t, int16x4_t, int16x4_t] - [int16x8_t, int16x8_t, int16x8_t] @@ -8128,8 +7956,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [sqrshl]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - int8x8_t - int8x16_t @@ -8158,8 +7985,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [uqrshl]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - [uint8x8_t, int8x8_t] - [uint8x16_t, int8x16_t] @@ -8189,8 +8015,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['1']] - FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [int16x8_t, int8x8_t, 'N >= 1 && N <= 8', 'const { int16x8_t([-N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16]) }'] - [int32x4_t, int16x4_t, 'N >= 1 && N <= 16', 'const { int32x4_t([-N as i32, -N as i32, -N as i32, -N as i32]) }'] @@ -8205,7 +8030,7 @@ intrinsics: links: - link: "llvm.arm.neon.vqrshiftns.{neon_type[1]}" arch: arm - - FnCall: ["_vqrshrn_n{neon_type[0].noq}", [a, '{type[3]}']] + - FnCall: ["_vqrshrn_n{neon_type[0].noq}", [a, '{type[3]}'], [], true] - name: "vqrshrn_n{neon_type[0].noq}" doc: "Signed saturating rounded shift right narrow" @@ -8217,8 +8042,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['1']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [int16x8_t, int8x8_t, 'N >= 1 && N <= 8'] - [int32x4_t, int16x4_t, 'N >= 1 && N <= 16'] @@ -8233,7 +8057,7 @@ intrinsics: links: - link: "llvm.aarch64.neon.sqrshrn.{neon_type[1]}" arch: aarch64,arm64ec - - FnCall: ["_vqrshrn_n{neon_type[0].noq}", [a, N]] + - FnCall: ["_vqrshrn_n{neon_type[0].noq}", [a, N], [], true] - name: "vqrshrun_n{neon_type[0].noq}" doc: "Signed saturating rounded shift right unsigned narrow" @@ -8246,8 +8070,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['1']] - FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [int16x8_t, uint8x8_t, 'N >= 1 && N <= 8', 'const { int16x8_t([-N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16]) }'] - [int32x4_t, uint16x4_t, 'N >= 1 && N <= 16', 'const { int32x4_t([-N as i32, -N as i32, -N as i32, -N as i32]) }'] @@ -8266,6 +8089,8 @@ intrinsics: - "_vqrshrun_n{neon_type[0].noq}" - - a - "{type[3]}" + - [] + - true - name: "vqrshrun_n{neon_type[0].noq}" doc: "Signed saturating rounded shift right unsigned narrow" @@ -8277,8 +8102,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['1']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [int16x8_t, uint8x8_t, 'N >= 1 && N <= 8'] - [int32x4_t, uint16x4_t, 'N >= 1 && N <= 16'] @@ -8293,7 +8117,7 @@ intrinsics: links: - link: "llvm.aarch64.neon.sqrshrun.{neon_type[1]}" arch: aarch64,arm64ec - - FnCall: ["_vqrshrun_n{neon_type[0].noq}", [a, N]] + - FnCall: ["_vqrshrun_n{neon_type[0].noq}", [a, N], [], true] - name: "vqshl{neon_type.no}" doc: "Signed saturating shift left" @@ -8305,8 +8129,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [sqshl]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - int8x8_t - int8x16_t @@ -8337,8 +8160,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [int8x8_t, '3'] - [int8x16_t, '3'] @@ -8365,8 +8187,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [uqshl]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - [uint8x8_t, int8x8_t] - [uint8x16_t, int8x16_t] @@ -8397,8 +8218,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [uint8x8_t, '3', int8x8_t] - [uint8x16_t, '3', int8x16_t] @@ -8426,8 +8246,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['1']] - FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [int16x8_t, int8x8_t, 'N >= 1 && N <= 8', 'const { int16x8_t([-N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16]) }'] - [int32x4_t, int16x4_t, 'N >= 1 && N <= 16', 'const { int32x4_t([-N as i32, -N as i32, -N as i32, -N as i32]) }'] @@ -8442,7 +8261,7 @@ intrinsics: links: - link: "llvm.arm.neon.vqshiftns.{neon_type[1]}" arch: arm - - FnCall: ["_vqshrn_n{neon_type[0].noq}", [a, "{type[3]}"]] + - FnCall: ["_vqshrn_n{neon_type[0].noq}", [a, "{type[3]}"], [], true] - name: "vqshrn_n{neon_type[0].noq}" doc: "Signed saturating shift right narrow" @@ -8454,8 +8273,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['1']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [int16x8_t, int8x8_t, 'N >= 1 && N <= 8'] - [int32x4_t, int16x4_t, 'N >= 1 && N <= 16'] @@ -8470,7 +8288,7 @@ intrinsics: links: - link: "llvm.aarch64.neon.sqshrn.{neon_type[1]}" arch: aarch64,arm64ec - - FnCall: ["_vqshrn_n{neon_type[0].noq}", [a, N]] + - FnCall: ["_vqshrn_n{neon_type[0].noq}", [a, N], [], true] - name: "vqshrn_n_{neon_type[0]}" doc: "Unsigned saturating shift right narrow" @@ -8483,8 +8301,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['1']] - FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [uint16x8_t, uint8x8_t, 'N >= 1 && N <= 8', 'const { uint16x8_t([-N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16]) }'] - [uint32x4_t, uint16x4_t, 'N >= 1 && N <= 16', 'const { uint32x4_t([-N as u32, -N as u32, -N as u32, -N as u32]) }'] @@ -8499,7 +8316,7 @@ intrinsics: links: - link: "llvm.arm.neon.vqshiftnu.{neon_type[1]}" arch: arm - - FnCall: ["_vqshrn_n_{neon_type[0]}", ["a", "{type[3]}"]] + - FnCall: ["_vqshrn_n_{neon_type[0]}", ["a", "{type[3]}"], [], true] - name: "vqshrn_n_{neon_type[0]}" doc: "Unsigned saturating shift right narrow" @@ -8511,8 +8328,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['1']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [uint16x8_t, uint8x8_t, 'N >= 1 && N <= 8'] - [uint32x4_t, uint16x4_t, 'N >= 1 && N <= 16'] @@ -8527,7 +8343,7 @@ intrinsics: links: - link: "llvm.aarch64.neon.uqshrn.{neon_type[1]}" arch: aarch64,arm64ec - - FnCall: ["_vqshrn_n_{neon_type[0]}", ["a", N]] + - FnCall: ["_vqshrn_n_{neon_type[0]}", ["a", N], [], true] - name: "vqshrun_n_{neon_type[0]}" doc: "Signed saturating shift right unsigned narrow" @@ -8540,8 +8356,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['1']] - FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [int16x8_t, uint8x8_t, 'N >= 1 && N <= 8', 'const { int16x8_t([-N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16]) }'] - [int32x4_t, uint16x4_t, 'N >= 1 && N <= 16', 'const { int32x4_t([-N as i32, -N as i32, -N as i32, -N as i32]) }'] @@ -8556,7 +8371,7 @@ intrinsics: links: - link: "llvm.arm.neon.vqshiftnsu.{neon_type[1]}" arch: arm - - FnCall: ["_vqshrun_n_{neon_type[0]}", [a, "{type[3]}"]] + - FnCall: ["_vqshrun_n_{neon_type[0]}", [a, "{type[3]}"], [], true] - name: "vqshrun_n_{neon_type[0]}" doc: "Signed saturating shift right unsigned narrow" @@ -8568,8 +8383,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['1']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [int16x8_t, uint8x8_t, 'N >= 1 && N <= 8'] - [int32x4_t, uint16x4_t, 'N >= 1 && N <= 16'] @@ -8584,7 +8398,7 @@ intrinsics: links: - link: "llvm.aarch64.neon.sqshrun.{neon_type[1]}" arch: aarch64,arm64ec - - FnCall: ["_vqshrun_n_{neon_type[0]}", [a, N]] + - FnCall: ["_vqshrun_n_{neon_type[0]}", [a, N], [], true] - name: "vrsqrts{neon_type.no}" doc: "Floating-point reciprocal square root step" @@ -8596,8 +8410,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [frsqrts]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - float32x2_t - float32x4_t @@ -8621,8 +8434,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [vrsqrts]]}]] - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [frsqrts]]}]] - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - float16x4_t - float16x8_t @@ -8646,8 +8458,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [frecpe]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - float32x2_t - float32x4_t @@ -8671,8 +8482,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [frecpe]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - float16x4_t - float16x8_t @@ -8696,8 +8506,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [frecps]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - float32x2_t - float32x4_t @@ -8721,8 +8530,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [frecps]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - float16x4_t - float16x8_t @@ -8747,8 +8555,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [nop]]}]] - *neon-stable-not-arm - *neon-unstable-is-arm - safety: - unsafe: [neon] + safety: safe types: - [poly64x1_t, int32x2_t] - [poly64x1_t, uint32x2_t] @@ -8817,8 +8624,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [nop]]}]] - *neon-stable-not-arm - *neon-unstable-is-arm - safety: - unsafe: [neon] + safety: safe types: - [uint8x8_t, int8x8_t] - [poly8x8_t, int8x8_t] @@ -9056,8 +8862,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [nop]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: # non-q - [float32x2_t, float16x4_t] @@ -9119,8 +8924,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [nop]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - [poly64x1_t, float16x4_t] - [float16x4_t, poly64x1_t] @@ -9142,8 +8946,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [rev64]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - [float16x4_t, "[3, 2, 1, 0]"] - [float16x8_t, "[3, 2, 1, 0, 7, 6, 5, 4]"] @@ -9160,8 +8963,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [srshl]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - int8x8_t - int8x16_t @@ -9190,8 +8992,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [urshl]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - [uint8x8_t, int8x8_t] - [uint8x16_t, int8x16_t] @@ -9222,8 +9023,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [int8x8_t, 'N >= 1 && N <= 8'] - [int8x16_t, 'N >= 1 && N <= 8'] @@ -9252,8 +9052,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [uint8x8_t, int8x8_t, 'N >= 1 && N <= 8'] - [uint8x16_t, int8x16_t, 'N >= 1 && N <= 8'] @@ -9281,8 +9080,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['1']] - FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [int16x8_t, int8x8_t, 'N >= 1 && N <= 8', 'const { int16x8_t([-N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16]) }'] - [int32x4_t, int16x4_t, 'N >= 1 && N <= 16', 'const { int32x4_t([-N as i32, -N as i32, -N as i32, -N as i32]) }'] @@ -9297,7 +9095,7 @@ intrinsics: links: - link: "llvm.arm.neon.vrshiftn.{neon_type[1]}" arch: arm - - FnCall: ["_vrshrn_n_{neon_type[0]}", [a, "{type[3]}"]] + - FnCall: ["_vrshrn_n_{neon_type[0]}", [a, "{type[3]}"], [], true] - name: "vrshrn_n_{neon_type[0]}" doc: "Rounding shift right narrow" @@ -9309,8 +9107,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['1']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [int16x8_t, int8x8_t, 'N >= 1 && N <= 8'] - [int32x4_t, int16x4_t, 'N >= 1 && N <= 16'] @@ -9325,7 +9122,7 @@ intrinsics: links: - link: "llvm.aarch64.neon.rshrn.{neon_type[1]}" arch: aarch64,arm64ec - - FnCall: ["_vrshrn_n_{neon_type[0]}", [a, N]] + - FnCall: ["_vrshrn_n_{neon_type[0]}", [a, N], [], true] - name: "vrshrn_n_{neon_type[0]}" doc: "Rounding shift right narrow" @@ -9339,8 +9136,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [uint16x8_t, uint8x8_t, 'N >= 1 && N <= 8', s16] - [uint32x4_t, uint16x4_t, 'N >= 1 && N <= 16', s32] @@ -9365,8 +9161,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [int8x8_t, 'N >= 1 && N <= 8'] - [int8x16_t, 'N >= 1 && N <= 8'] @@ -9393,8 +9188,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [rsubhn]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - [int16x8_t, int16x8_t, int8x8_t] - [int32x4_t, int32x4_t, int16x4_t] @@ -9418,8 +9212,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [rsubhn]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - [uint16x8_t, uint16x8_t, uint8x8_t, s16] - [uint32x4_t, uint32x4_t, uint16x4_t, s32] @@ -9442,8 +9235,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [nop]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - ["u64", int8x8_t] - ["u64", int16x4_t] @@ -9469,8 +9261,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [nop]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - ["u64", float16x4_t] compose: @@ -9487,8 +9278,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [nop]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - ["u64", poly64x1_t] compose: @@ -9506,8 +9296,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] static_defs: ['const LANE: i32'] - safety: - unsafe: [neon] + safety: safe types: - ["i8", int8x8_t, '3'] - ["i16", int16x4_t, '2'] @@ -9546,8 +9335,7 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 static_defs: ['const LANE: i32'] - safety: - unsafe: [neon] + safety: safe types: - ["f16", float16x4_t, '2'] - ["f16", float16x8_t, '3'] @@ -9568,8 +9356,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] static_defs: ['const LANE: i32'] - safety: - unsafe: [neon] + safety: safe types: - ["i64", int64x1_t, int64x1_t] - ["u64", uint64x1_t, uint64x1_t] @@ -9590,8 +9377,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] static_defs: ['const LANE: i32'] - safety: - unsafe: [neon] + safety: safe types: - ["p64", poly64x1_t, poly64x1_t] compose: @@ -9611,8 +9397,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] static_defs: ['const LANE: i32'] - safety: - unsafe: [neon] + safety: safe types: - ["p64", poly64x2_t, poly64x2_t] compose: @@ -9629,8 +9414,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [sshl]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - int8x8_t - int8x16_t @@ -9659,8 +9443,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [ushl]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - [uint8x8_t, int8x8_t] - [uint8x16_t, int8x16_t] @@ -9691,8 +9474,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [int8x8_t, int16x8_t, 'N >= 0 && N <= 8'] compose: @@ -9714,8 +9496,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [int16x4_t, int32x4_t] compose: @@ -9737,8 +9518,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [int32x2_t, int64x2_t] compose: @@ -9760,8 +9540,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [uint8x8_t, uint16x8_t] compose: @@ -9783,8 +9562,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [uint16x4_t, uint32x4_t] compose: @@ -9806,8 +9584,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [uint32x2_t, uint64x2_t] compose: @@ -9829,8 +9606,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [int8x8_t, 'N >= 1 && N <= 8', 'let n: i32 = if N == 8 { 7 }', 'else { N };'] - [int8x16_t, 'N >= 1 && N <= 8', 'let n: i32 = if N == 8 { 7 }', 'else { N };'] @@ -9860,8 +9636,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [uint8x8_t, 'N >= 1 && N <= 8', 'let n: i32 = if N == 8 { return vdup_n_u8(0); }', 'else { N };'] - [uint8x16_t, 'N >= 1 && N <= 8', 'let n: i32 = if N == 8 { return vdupq_n_u8(0); }', 'else { N };'] @@ -9891,8 +9666,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [int16x8_t, int8x8_t, '.i16', 'N >= 1 && N <= 8'] - [uint16x8_t, uint8x8_t, '.i16', 'N >= 1 && N <= 8'] @@ -9921,8 +9695,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [int8x8_t, 'N >= 1 && N <= 8'] - [int8x16_t, 'N >= 1 && N <= 8'] @@ -9949,8 +9722,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [trn]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - [int8x8_t, int8x8x2_t, '[0, 8, 2, 10, 4, 12, 6, 14]', '[1, 9, 3, 11, 5, 13, 7, 15]'] - [int16x4_t, int16x4x2_t, '[0, 4, 2, 6]', '[1, 5, 3, 7]'] @@ -9991,8 +9763,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [trn]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - [float16x4_t, float16x4x2_t, '[0, 4, 2, 6]', '[1, 5, 3, 7]'] - [float16x8_t, float16x8x2_t, '[0, 8, 2, 10, 4, 12, 6, 14]', '[1, 9, 3, 11, 5, 13, 7, 15]'] @@ -10020,8 +9791,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [zip]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - [int32x2_t, int32x2x2_t, '[0, 2]', '[1, 3]'] - [uint32x2_t, uint32x2x2_t, '[0, 2]', '[1, 3]'] @@ -10049,8 +9819,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [zip]]}]] - *neon-stable-not-arm - *neon-unstable-is-arm - safety: - unsafe: [neon] + safety: safe types: - [int8x16_t, int8x16x2_t, '[0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23]', '[8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31]'] - [int16x8_t, int16x8x2_t, '[0, 8, 1, 9, 2, 10, 3, 11]', '[4, 12, 5, 13, 6, 14, 7, 15]'] @@ -10084,8 +9853,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [zip]]}]] - *neon-stable-not-arm - *neon-unstable-is-arm - safety: - unsafe: [neon] + safety: safe types: - [int32x2_t, int32x2x2_t, '[0, 2]', '[1, 3]'] - [uint32x2_t, uint32x2x2_t, '[0, 2]', '[1, 3]'] @@ -10113,8 +9881,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [zip]]}]] - *neon-stable-not-arm - *neon-unstable-is-arm - safety: - unsafe: [neon] + safety: safe types: - [int8x8_t, int8x8x2_t, '[0, 8, 1, 9, 2, 10, 3, 11]', '[4, 12, 5, 13, 6, 14, 7, 15]'] - [int16x4_t, int16x4x2_t, '[0, 4, 1, 5]', '[2, 6, 3, 7]'] @@ -10146,8 +9913,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [zip]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - [float16x4_t, float16x4x2_t, '[0, 4, 1, 5]', '[2, 6, 3, 7]'] - [float16x8_t, float16x8x2_t, '[0, 8, 1, 9, 2, 10, 3, 11]', '[4, 12, 5, 13, 6, 14, 7, 15]'] @@ -10174,8 +9940,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [uzp]]}]] - *neon-stable-not-arm - *neon-unstable-is-arm - safety: - unsafe: [neon] + safety: safe types: - [int8x8_t, int8x8x2_t, '[0, 2, 4, 6, 8, 10, 12, 14]', '[1, 3, 5, 7, 9, 11, 13, 15]'] - [int16x4_t, int16x4x2_t, '[0, 2, 4, 6]', '[1, 3, 5, 7]'] @@ -10216,8 +9981,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [uzp]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - [float16x4_t, float16x4x2_t, '[0, 2, 4, 6]', '[1, 3, 5, 7]'] - [float16x8_t, float16x8x2_t, '[0, 2, 4, 6, 8, 10, 12, 14]', '[1, 3, 5, 7, 9, 11, 13, 15]'] @@ -10245,8 +10009,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [zip]]}]] - *neon-stable-not-arm - *neon-unstable-is-arm - safety: - unsafe: [neon] + safety: safe types: - [float32x2_t, float32x2x2_t, '[0, 2]', '[1, 3]'] - [int32x2_t, int32x2x2_t, '[0, 2]', '[1, 3]'] @@ -10274,8 +10037,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [uabal]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - [uint16x8_t, uint8x8_t, "u8"] - [uint32x4_t, uint16x4_t, "u16"] @@ -10294,8 +10056,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [sabal]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - [int16x8_t, int8x8_t, uint8x8_t] - [int32x4_t, int16x4_t, uint16x4_t] @@ -10315,8 +10076,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [sqabs]]}]] - *neon-stable-not-arm - *neon-unstable-is-arm - safety: - unsafe: [neon] + safety: safe types: - int8x8_t - int8x16_t @@ -10697,8 +10457,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [fmls]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - float32x2_t - float32x4_t @@ -10716,8 +10475,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [pmul]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - [poly8x8_t, int8x8_t] - [poly8x16_t, int8x16_t] @@ -10740,8 +10498,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [fmul]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - float32x2_t - float32x4_t @@ -10758,8 +10515,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [cmhs]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - uint8x8_t - uint8x16_t @@ -10780,8 +10536,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [fcmge]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - [float32x2_t, uint32x2_t] - [float32x4_t, uint32x4_t] @@ -10798,8 +10553,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [fcmge]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - [float16x4_t, uint16x4_t] - [float16x8_t, uint16x8_t] @@ -10817,8 +10571,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [fcmge]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - [float16x4_t, uint16x4_t, f16x4, 'f16x4::new(0.0, 0.0, 0.0, 0.0)'] - [float16x8_t, uint16x8_t, f16x8, 'f16x8::new(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0)'] @@ -10839,8 +10592,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [cmhi]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - uint8x8_t - uint8x16_t @@ -10861,8 +10613,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [cmtst]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - [uint8x8_t, u8x8, 'u8x8::new(0, 0, 0, 0, 0, 0, 0, 0)'] - [uint8x16_t, u8x16, 'u8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)'] @@ -10887,8 +10638,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [int8x8_t, '3'] - [int8x16_t, '3'] @@ -10925,8 +10675,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [uint8x8_t, '8'] - [uint8x16_t, '8'] @@ -10955,8 +10704,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [uint8x8_t, '8'] - [uint8x16_t, '8'] @@ -10984,8 +10732,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['1']] - FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [uint16x8_t, uint8x8_t, '8', 'const { uint16x8_t([-N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16]) }'] - [uint32x4_t, uint16x4_t, '16', 'const { uint32x4_t([-N as u32, -N as u32, -N as u32, -N as u32]) }'] @@ -11000,7 +10747,7 @@ intrinsics: links: - link: "llvm.arm.neon.vqrshiftnu.{neon_type[1]}" arch: arm - - FnCall: ["_vqrshrn_n{neon_type[0].noq}", ["a", "{type[3]}"]] + - FnCall: ["_vqrshrn_n{neon_type[0].noq}", ["a", "{type[3]}"], [], true] - name: "vqrshrn_n_{neon_type[0]}" doc: "Unsigned signed saturating rounded shift right narrow" @@ -11012,8 +10759,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['1']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [uint16x8_t, uint8x8_t, '8'] - [uint32x4_t, uint16x4_t, '16'] @@ -11028,7 +10774,7 @@ intrinsics: links: - link: "llvm.aarch64.neon.uqrshrn.{neon_type[1]}" arch: aarch64,arm64ec - - FnCall: ["_vqrshrn_n_{neon_type[0]}", ["a", N]] + - FnCall: ["_vqrshrn_n_{neon_type[0]}", ["a", N], [], true] - name: "vcvt{neon_type[1].no}_{neon_type[0]}" doc: "Floating-point convert to unsigned fixed-point, rounding toward zero" @@ -11040,8 +10786,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [fcvtzu]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - [float32x2_t, uint32x2_t] - [float32x4_t, uint32x4_t] @@ -11065,8 +10810,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [fcvtzu]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - [float16x4_t, uint16x4_t] - [float16x8_t, uint16x8_t] @@ -11085,8 +10829,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [fcvtn]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - [float32x4_t, float16x4_t] compose: @@ -11102,8 +10845,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [fcvtl]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - [float16x4_t, float32x4_t] compose: @@ -11119,8 +10861,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [mla]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - [int16x4_t, "i16", int16x4_t] - [int16x8_t, "i16", int16x8_t] @@ -11143,8 +10884,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [mla]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - [int32x2_t, "i32", int32x2_t] - [int32x4_t, "i32", int32x4_t] @@ -11167,8 +10907,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [fmul]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - [float32x2_t, "f32", float32x2_t] - [float32x4_t, "f32", float32x4_t] @@ -11187,8 +10926,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] static_defs: ['const LANE: i32'] - safety: - unsafe: [neon] + safety: safe types: - [_lane_s16, int16x4_t, int16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - [_laneq_s16, int16x4_t, int16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] @@ -11218,8 +10956,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] static_defs: ['const LANE: i32'] - safety: - unsafe: [neon] + safety: safe types: - [_lane_s32, int32x2_t, int32x2_t, '1', '[LANE as u32, LANE as u32]'] - [_laneq_s32, int32x2_t, int32x4_t, '2', '[LANE as u32, LANE as u32]'] @@ -11249,8 +10986,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] static_defs: ['const LANE: i32'] - safety: - unsafe: [neon] + safety: safe types: - [_lane_f32, float32x2_t, float32x2_t, '1', '[LANE as u32, LANE as u32]'] - [_laneq_f32, float32x2_t, float32x4_t, '2', '[LANE as u32, LANE as u32]'] @@ -11274,8 +11010,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [mls]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - [int16x4_t, "i16", int16x4_t] - [int16x8_t, "i16", int16x8_t] @@ -11298,8 +11033,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [mls]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - [int32x2_t, "i32", int32x2_t] - [int32x4_t, "i32", int32x4_t] @@ -11322,8 +11056,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [fmul]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - [float32x2_t, "f32", float32x2_t] - [float32x4_t, "f32", float32x4_t] @@ -11342,8 +11075,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] static_defs: ['const LANE: i32'] - safety: - unsafe: [neon] + safety: safe types: - [_lane_s16, int16x4_t, int16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - [_laneq_s16, int16x4_t, int16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] @@ -11373,8 +11105,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] static_defs: ['const LANE: i32'] - safety: - unsafe: [neon] + safety: safe types: - [_lane_s32, int32x2_t, int32x2_t, '1', '[LANE as u32, LANE as u32]'] - [_laneq_s32, int32x2_t, int32x4_t, '2', '[LANE as u32, LANE as u32]'] @@ -11404,8 +11135,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] static_defs: ['const LANE: i32'] - safety: - unsafe: [neon] + safety: safe types: - [_lane_f32, float32x2_t, float32x2_t, '1', '[LANE as u32, LANE as u32]'] - [_laneq_f32, float32x2_t, float32x4_t, '2', '[LANE as u32, LANE as u32]'] @@ -11429,8 +11159,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [mul]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - [int16x4_t, "i16"] - [int16x8_t, "i16"] @@ -11456,8 +11185,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [fmul]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - [float32x2_t, "f32"] - [float32x4_t, "f32"] @@ -11478,8 +11206,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [fmul]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - [float16x4_t, "f16"] - [float16x8_t, "f16"] @@ -11502,8 +11229,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] static_defs: ['const LANE: i32'] - safety: - unsafe: [neon] + safety: safe types: - [float32x2_t, float32x2_t, '_lane_f32', '1', '[LANE as u32, LANE as u32]'] - [float32x2_t, float32x4_t, '_laneq_f32', '2', '[LANE as u32, LANE as u32]'] @@ -11528,8 +11254,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] static_defs: ['const LANE: i32'] - safety: - unsafe: [neon] + safety: safe types: - [_lane_s16, int16x4_t, int16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - [_laneq_s16, int16x4_t, int16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] @@ -11554,8 +11279,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [sqrdmulh]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - [int16x4_t, "i16"] - [int16x8_t, "i16"] @@ -11577,8 +11301,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [fcmgt]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - [float32x2_t, uint32x2_t] - [float32x4_t, uint32x4_t] @@ -11595,8 +11318,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [fcmgt]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - [float16x4_t, uint16x4_t] - [float16x8_t, uint16x8_t] @@ -11614,8 +11336,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [fcmlt]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - [float16x4_t, uint16x4_t, f16x4, 'f16x4::new(0.0, 0.0, 0.0, 0.0)'] - [float16x8_t, uint16x8_t, f16x8, 'f16x8::new(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0)'] @@ -11636,8 +11357,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [uabdl]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - [uint8x8_t, uint16x8_t] - [uint16x4_t, uint32x4_t] @@ -11657,8 +11377,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] static_defs: ['const LANE: i32'] - safety: - unsafe: [neon] + safety: safe types: - [int16x4_t, int16x4_t, int32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - [int16x4_t, int16x8_t, int32x4_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] @@ -11683,8 +11402,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] static_defs: ['const LANE: i32'] - safety: - unsafe: [neon] + safety: safe types: - [uint16x4_t, uint16x4_t, uint32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] - [uint16x4_t, uint16x8_t, uint32x4_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] @@ -11707,8 +11425,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [fmls]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - [float32x2_t, "f32"] - [float32x4_t, "f32"] @@ -11731,8 +11448,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [fmls]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - float16x4_t - float16x8_t @@ -11752,8 +11468,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] static_defs: ['const LANE: i32'] - safety: - unsafe: [neon] + safety: safe types: - [int16x8_t, int16x8_t, '3'] - [int16x4_t, int16x8_t, '3'] @@ -11778,8 +11493,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [urecpe]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - uint32x2_t - uint32x4_t @@ -11802,8 +11516,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [ursqrte]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - uint32x2_t - uint32x4_t @@ -11826,8 +11539,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [frsqrte]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - float32x2_t - float32x4_t @@ -11851,8 +11563,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [vrsqrte]]}]] - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [frsqrte]]}]] - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - float16x4_t - float16x8_t @@ -11877,8 +11588,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['1']] - FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [int8x8_t, uint8x8_t, '3', 'const { int8x8_t([N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8]) }'] - [int16x4_t, uint16x4_t, '4', 'const { int16x4_t([N as i16, N as i16, N as i16, N as i16]) }'] @@ -11898,7 +11608,7 @@ intrinsics: links: - link: "llvm.arm.neon.vqshiftsu.{neon_type[0]}" arch: arm - - FnCall: ["_vqshlu{neon_type[0].N}", [a, "{type[3]}"]] + - FnCall: ["_vqshlu{neon_type[0].N}", [a, "{type[3]}"], [], true] - name: "vqshlu{neon_type[0].N}" doc: "Signed saturating shift left unsigned" @@ -11910,8 +11620,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ['1']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const N: i32'] - safety: - unsafe: [neon] + safety: safe types: - [int8x8_t, uint8x8_t, '3', 'const { int8x8_t([N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8]) }'] - [int16x4_t, uint16x4_t, '4', 'const { int16x4_t([N as i16, N as i16, N as i16, N as i16]) }'] @@ -11931,7 +11640,7 @@ intrinsics: links: - link: "llvm.aarch64.neon.sqshlu.{neon_type[0]}" arch: aarch64,arm64ec - - FnCall: ["_vqshlu{neon_type[0].N}", [a, "{type[3]}"]] + - FnCall: ["_vqshlu{neon_type[0].N}", [a, "{type[3]}"], [], true] - name: "vcvt{neon_type[1].no}_{neon_type[0]}" doc: "Floating-point convert to signed fixed-point, rounding toward zero" @@ -11943,8 +11652,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [fcvtzs]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - [float32x2_t, int32x2_t] - [float32x4_t, int32x4_t] @@ -11968,8 +11676,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [fcvtzs]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - [float16x4_t, int16x4_t] - [float16x8_t, int16x8_t] @@ -11988,8 +11695,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [uqxtn]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - [uint16x8_t, uint8x8_t] - [uint32x4_t, uint16x4_t] @@ -12013,8 +11719,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [cmhs]]}]] - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] - safety: - unsafe: [neon] + safety: safe types: - uint8x8_t - uint8x16_t @@ -12347,8 +12052,7 @@ intrinsics: - *target-is-arm - *neon-unstable assert_instr: [vtbx] - safety: - unsafe: [neon] + safety: safe types: - "int8x8_t" compose: @@ -12367,8 +12071,7 @@ intrinsics: - *target-is-arm - *neon-unstable assert_instr: [vtbx] - safety: - unsafe: [neon] + safety: safe types: - int8x8_t compose: @@ -12383,8 +12086,7 @@ intrinsics: - *target-is-arm - *neon-unstable assert_instr: [vtbx] - safety: - unsafe: [neon] + safety: safe types: - uint8x8_t - poly8x8_t @@ -12407,8 +12109,7 @@ intrinsics: - *target-is-arm - *neon-unstable assert_instr: [vtbx] - safety: - unsafe: [neon] + safety: safe types: - "int8x8_t" compose: @@ -12427,8 +12128,7 @@ intrinsics: - *target-is-arm - *neon-unstable assert_instr: [vtbx] - safety: - unsafe: [neon] + safety: safe types: - [int8x8_t, int8x8x2_t] compose: @@ -12443,8 +12143,7 @@ intrinsics: - *target-is-arm - *neon-unstable assert_instr: [vtbx] - safety: - unsafe: [neon] + safety: safe types: - [uint8x8_t, uint8x8x2_t, uint8x8_t] - [poly8x8_t, poly8x8x2_t, uint8x8_t] @@ -12468,8 +12167,7 @@ intrinsics: - *target-is-arm - *neon-unstable assert_instr: [vtbx] - safety: - unsafe: [neon] + safety: safe types: - "int8x8_t" compose: @@ -12488,8 +12186,7 @@ intrinsics: - *target-is-arm - *neon-unstable assert_instr: [vtbx] - safety: - unsafe: [neon] + safety: safe types: - [int8x8_t, int8x8x3_t] compose: @@ -12504,8 +12201,7 @@ intrinsics: - *target-is-arm - *neon-unstable assert_instr: [vtbx] - safety: - unsafe: [neon] + safety: safe types: - [uint8x8_t, uint8x8x3_t, uint8x8_t] - [poly8x8_t, poly8x8x3_t, uint8x8_t] @@ -12530,8 +12226,7 @@ intrinsics: - *target-is-arm - *neon-unstable assert_instr: [vtbx] - safety: - unsafe: [neon] + safety: safe types: - "int8x8_t" compose: @@ -12550,8 +12245,7 @@ intrinsics: - *target-is-arm - *neon-unstable assert_instr: [vtbx] - safety: - unsafe: [neon] + safety: safe types: - ["uint8x8_t", "uint8x8x4_t", "uint8x8_t"] - ["poly8x8_t", "poly8x8x4_t", "uint8x8_t"] @@ -12576,8 +12270,7 @@ intrinsics: - *target-is-arm - *neon-unstable assert_instr: [vtbx] - safety: - unsafe: [neon] + safety: safe types: - ["int8x8_t", "int8x8x4_t"] big_endian_inverse: true @@ -12802,8 +12495,7 @@ intrinsics: - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [nop]]}]] - *neon-stable-not-arm - *neon-unstable-is-arm - safety: - unsafe: [neon] + safety: safe types: - [float32x2_t, float32x4_t, '[0, 1, 2, 3]'] - [poly8x8_t, poly8x16_t, '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]'] @@ -12830,8 +12522,7 @@ intrinsics: - FnCall: [cfg_attr, [test, { FnCall: [assert_instr, [aese]] }]] - *neon-unstable-is-arm - FnCall: [cfg_attr, [*not-arm, { FnCall: [stable, ['feature = "aarch64_neon_crypto_intrinsics"', 'since = "1.72.0"']] }]] - safety: - unsafe: [neon] + safety: safe types: - uint8x16_t compose: @@ -12853,8 +12544,7 @@ intrinsics: - FnCall: [cfg_attr, [test, { FnCall: [assert_instr, [aesd]] }]] - *neon-unstable-is-arm - FnCall: [cfg_attr, [*not-arm, { FnCall: [stable, ['feature = "aarch64_neon_crypto_intrinsics"', 'since = "1.72.0"']] }]] - safety: - unsafe: [neon] + safety: safe types: - uint8x16_t compose: @@ -12876,8 +12566,7 @@ intrinsics: - FnCall: [cfg_attr, [test, { FnCall: [assert_instr, ["{type[1]}"]] }]] - *neon-unstable-is-arm - FnCall: [cfg_attr, [*not-arm, { FnCall: [stable, ['feature = "aarch64_neon_crypto_intrinsics"', 'since = "1.72.0"']] }]] - safety: - unsafe: [neon] + safety: safe types: - [uint8x16_t, "aesmc"] compose: @@ -12899,8 +12588,7 @@ intrinsics: - FnCall: [cfg_attr, [test, { FnCall: [assert_instr, ["{type[1]}"]] }]] - *neon-unstable-is-arm - FnCall: [cfg_attr, [*not-arm, { FnCall: [stable, ['feature = "aarch64_neon_crypto_intrinsics"', 'since = "1.72.0"']] }]] - safety: - unsafe: [neon] + safety: safe types: - [uint8x16_t, "aesimc"] compose: @@ -12922,8 +12610,7 @@ intrinsics: - FnCall: [cfg_attr, [test, { FnCall: [assert_instr, ["{type[1]}"]] }]] - *neon-unstable-is-arm - FnCall: [cfg_attr, [*not-arm, { FnCall: [stable, ['feature = "aarch64_neon_crypto_intrinsics"', 'since = "1.72.0"']] }]] - safety: - unsafe: [neon] + safety: safe types: - [u32, "sha1h"] compose: @@ -12945,8 +12632,7 @@ intrinsics: - FnCall: [cfg_attr, [test, { FnCall: [assert_instr, ["{type[1]}"]] }]] - *neon-unstable-is-arm - FnCall: [cfg_attr, [*not-arm, { FnCall: [stable, ['feature = "aarch64_neon_crypto_intrinsics"', 'since = "1.72.0"']] }]] - safety: - unsafe: [neon] + safety: safe types: - [u32, "sha1c", "uint32x4_t"] compose: @@ -12968,8 +12654,7 @@ intrinsics: - FnCall: [cfg_attr, [test, { FnCall: [assert_instr, ["{type[1]}"]] }]] - *neon-unstable-is-arm - FnCall: [cfg_attr, [*not-arm, { FnCall: [stable, ['feature = "aarch64_neon_crypto_intrinsics"', 'since = "1.72.0"']] }]] - safety: - unsafe: [neon] + safety: safe types: - [u32, "sha1m", "uint32x4_t"] compose: @@ -12991,8 +12676,7 @@ intrinsics: - FnCall: [cfg_attr, [test, { FnCall: [assert_instr, ["{type[1]}"]] }]] - *neon-unstable-is-arm - FnCall: [cfg_attr, [*not-arm, { FnCall: [stable, ['feature = "aarch64_neon_crypto_intrinsics"', 'since = "1.72.0"']] }]] - safety: - unsafe: [neon] + safety: safe types: - [u32, "sha1p", "uint32x4_t"] compose: @@ -13014,8 +12698,7 @@ intrinsics: - FnCall: [cfg_attr, [test, { FnCall: [assert_instr, ["{type[1]}"]] }]] - *neon-unstable-is-arm - FnCall: [cfg_attr, [*not-arm, { FnCall: [stable, ['feature = "aarch64_neon_crypto_intrinsics"', 'since = "1.72.0"']] }]] - safety: - unsafe: [neon] + safety: safe types: - [uint32x4_t, "sha1su0"] compose: @@ -13037,8 +12720,7 @@ intrinsics: - FnCall: [cfg_attr, [test, { FnCall: [assert_instr, ["{type[1]}"]] }]] - *neon-unstable-is-arm - FnCall: [cfg_attr, [*not-arm, { FnCall: [stable, ['feature = "aarch64_neon_crypto_intrinsics"', 'since = "1.72.0"']] }]] - safety: - unsafe: [neon] + safety: safe types: - [uint32x4_t, "sha1su1"] compose: @@ -13060,8 +12742,7 @@ intrinsics: - FnCall: [cfg_attr, [test, { FnCall: [assert_instr, ["{type[1]}"]] }]] - *neon-unstable-is-arm - FnCall: [cfg_attr, [*not-arm, { FnCall: [stable, ['feature = "aarch64_neon_crypto_intrinsics"', 'since = "1.72.0"']] }]] - safety: - unsafe: [neon] + safety: safe types: - [uint32x4_t, "sha256h"] compose: @@ -13083,8 +12764,7 @@ intrinsics: - FnCall: [cfg_attr, [test, { FnCall: [assert_instr, ["{type[1]}"]] }]] - *neon-unstable-is-arm - FnCall: [cfg_attr, [*not-arm, { FnCall: [stable, ['feature = "aarch64_neon_crypto_intrinsics"', 'since = "1.72.0"']] }]] - safety: - unsafe: [neon] + safety: safe types: - [uint32x4_t, "sha256h2"] compose: @@ -13106,8 +12786,7 @@ intrinsics: - FnCall: [cfg_attr, [test, { FnCall: [assert_instr, ["{type[1]}"]] }]] - *neon-unstable-is-arm - FnCall: [cfg_attr, [*not-arm, { FnCall: [stable, ['feature = "aarch64_neon_crypto_intrinsics"', 'since = "1.72.0"']] }]] - safety: - unsafe: [neon] + safety: safe types: - [uint32x4_t, "sha256su0"] compose: @@ -13129,8 +12808,7 @@ intrinsics: - FnCall: [cfg_attr, [test, { FnCall: [assert_instr, ["{type[1]}"]] }]] - *neon-unstable-is-arm - FnCall: [cfg_attr, [*not-arm, { FnCall: [stable, ['feature = "aarch64_neon_crypto_intrinsics"', 'since = "1.72.0"']] }]] - safety: - unsafe: [neon] + safety: safe types: - [uint32x4_t, "sha256su1"] compose: @@ -13152,8 +12830,7 @@ intrinsics: - FnCall: [cfg_attr, [test, { FnCall: [assert_instr, ["crc32b"]] }]] - *arm-crc-unstable - *aarch64-crc-stable - safety: - unsafe: [neon] + safety: safe types: - [u32, u8] compose: @@ -13167,7 +12844,7 @@ intrinsics: arch: aarch64,arm64ec - link: "llvm.arm.crc32b" arch: arm - - FnCall: ["___crc32b", ["crc", "data as u32"]] + - FnCall: ["___crc32b", ["crc", "data as u32"], [], true] - name: "__crc32h" doc: "CRC32 single round checksum for bytes (16 bits)." @@ -13179,8 +12856,7 @@ intrinsics: - FnCall: [cfg_attr, [test, { FnCall: [assert_instr, ["crc32h"]] }]] - *arm-crc-unstable - *aarch64-crc-stable - safety: - unsafe: [neon] + safety: safe types: - [u32, u16] compose: @@ -13194,7 +12870,7 @@ intrinsics: arch: aarch64,arm64ec - link: "llvm.arm.crc32h" arch: arm - - FnCall: ["___crc32h", ["crc", "data as u32"]] + - FnCall: ["___crc32h", ["crc", "data as u32"], [], true] - name: "__crc32w" doc: "CRC32 single round checksum for bytes (32 bits)." @@ -13206,8 +12882,7 @@ intrinsics: - FnCall: [cfg_attr, [test, { FnCall: [assert_instr, ["crc32w"]] }]] - *arm-crc-unstable - *aarch64-crc-stable - safety: - unsafe: [neon] + safety: safe types: - u32 compose: @@ -13229,8 +12904,7 @@ intrinsics: - FnCall: [cfg_attr, [test, { FnCall: [assert_instr, ["crc32cb"]] }]] - *arm-crc-unstable - *aarch64-crc-stable - safety: - unsafe: [neon] + safety: safe types: - [u32, u8] compose: @@ -13244,7 +12918,7 @@ intrinsics: arch: aarch64,arm64ec - link: "llvm.arm.crc32cb" arch: arm - - FnCall: ["___crc32cb", ["crc", "data as u32"]] + - FnCall: ["___crc32cb", ["crc", "data as u32"], [], true] - name: "__crc32ch" doc: "CRC32-C single round checksum for bytes (16 bits)." @@ -13256,8 +12930,7 @@ intrinsics: - FnCall: [cfg_attr, [test, { FnCall: [assert_instr, ["crc32ch"]] }]] - *arm-crc-unstable - *aarch64-crc-stable - safety: - unsafe: [neon] + safety: safe types: - [u32, u16] compose: @@ -13271,7 +12944,7 @@ intrinsics: arch: aarch64,arm64ec - link: "llvm.arm.crc32ch" arch: arm - - FnCall: ["___crc32ch", ["crc", "data as u32"]] + - FnCall: ["___crc32ch", ["crc", "data as u32"], [], true] - name: "__crc32cw" doc: "CRC32-C single round checksum for bytes (32 bits)." @@ -13283,8 +12956,7 @@ intrinsics: - FnCall: [cfg_attr, [test, { FnCall: [assert_instr, ["crc32cw"]] }]] - *arm-crc-unstable - *aarch64-crc-stable - safety: - unsafe: [neon] + safety: safe types: - u32 compose: @@ -13305,8 +12977,7 @@ intrinsics: - FnCall: [cfg, ['target_arch = "arm"']] - FnCall: [cfg_attr, [test, { FnCall: [assert_instr, ["crc32w"]] }]] - *arm-crc-unstable - safety: - unsafe: [neon] + safety: safe types: - [u32, u64] compose: @@ -13315,7 +12986,7 @@ intrinsics: # in the correct instructions being generated - Let: [b, u32, '(data & 0xFFFFFFFF) as u32'] - Let: [c, u32, '(data >> 32) as u32'] - - 'unsafe extern "unadjusted" {{ #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32w")] fn ___crc32w(crc: u32, data: u32) -> u32;}} ___crc32w(___crc32w(crc, b), c)' + - 'unsafe extern "unadjusted" {{ #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32w")] fn ___crc32w(crc: u32, data: u32) -> u32;}} unsafe {{ ___crc32w(___crc32w(crc, b), c) }}' - name: "__crc32cd" doc: "CRC32-C single round checksum for quad words (64 bits)." @@ -13326,14 +12997,13 @@ intrinsics: - FnCall: [cfg, ['target_arch = "arm"']] - FnCall: [cfg_attr, [test, { FnCall: [assert_instr, ["crc32cw"]] }]] - *arm-crc-unstable - safety: - unsafe: [neon] + safety: safe types: - [u32, u64] compose: - Let: [b, u32, '(data & 0xFFFFFFFF) as u32'] - Let: [c, u32, '(data >> 32) as u32'] - - 'unsafe extern "unadjusted" {{ #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32cw")] fn ___crc32cw(crc: u32, data: u32) -> u32;}} ___crc32cw(___crc32cw(crc, b), c)' + - 'unsafe extern "unadjusted" {{ #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32cw")] fn ___crc32cw(crc: u32, data: u32) -> u32;}} unsafe {{ ___crc32cw(___crc32cw(crc, b), c) }}' - name: "vabs{neon_type.no}" doc: "Absolute value (wrapping)." @@ -13345,8 +13015,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [abs]]}]] - *neon-stable-not-arm - *neon-unstable-is-arm - safety: - unsafe: [neon] + safety: safe types: - int8x8_t - int16x4_t @@ -13373,8 +13042,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [sminp]]}]] - *neon-stable-not-arm - *neon-unstable-is-arm - safety: - unsafe: [neon] + safety: safe types: - int8x8_t - int16x4_t @@ -13398,8 +13066,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [uminp]]}]] - *neon-stable-not-arm - *neon-unstable-is-arm - safety: - unsafe: [neon] + safety: safe types: - uint8x8_t - uint16x4_t @@ -13423,8 +13090,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [fminp]]}]] - *neon-stable-not-arm - *neon-unstable-is-arm - safety: - unsafe: [neon] + safety: safe types: - float32x2_t compose: @@ -13446,8 +13112,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [smaxp]]}]] - *neon-stable-not-arm - *neon-unstable-is-arm - safety: - unsafe: [neon] + safety: safe types: - int8x8_t - int16x4_t @@ -13471,8 +13136,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [umaxp]]}]] - *neon-stable-not-arm - *neon-unstable-is-arm - safety: - unsafe: [neon] + safety: safe types: - uint8x8_t - uint16x4_t @@ -13496,8 +13160,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [fmaxp]]}]] - *neon-stable-not-arm - *neon-unstable-is-arm - safety: - unsafe: [neon] + safety: safe types: - float32x2_t compose: @@ -13519,8 +13182,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [raddhn]]}]] - *neon-stable-not-arm - *neon-unstable-is-arm - safety: - unsafe: [neon] + safety: safe types: - [int16x8_t, int8x8_t, 'vraddhn.i16'] - [int32x4_t, int16x4_t, 'vraddhn.i32'] @@ -13544,8 +13206,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [raddhn]]}]] - *neon-stable-not-arm - *neon-unstable-is-arm - safety: - unsafe: [neon] + safety: safe types: - [uint16x8_t, uint8x8_t, 'vraddhn.i16', int16x8_t] - [uint32x4_t, uint16x4_t, 'vraddhn.i32', int32x4_t] @@ -13568,8 +13229,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [raddhn2]]}]] - *neon-stable-not-arm - *neon-unstable-is-arm - safety: - unsafe: [neon] + safety: safe types: - [uint8x8_t , uint16x8_t, uint8x16_t, 'vraddhn.i16', int16x8_t, '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]'] - [uint16x4_t, uint32x4_t, uint16x8_t, 'vraddhn.i32', int32x4_t, '[0, 1, 2, 3, 4, 5, 6, 7]'] @@ -13596,8 +13256,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [raddhn2]]}]] - *neon-stable-not-arm - *neon-unstable-is-arm - safety: - unsafe: [neon] + safety: safe types: - [int8x8_t , int16x8_t, int8x16_t, 'vraddhn.i16', '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]'] - [int16x4_t, int32x4_t, int16x8_t, 'vraddhn.i32', '[0, 1, 2, 3, 4, 5, 6, 7]'] @@ -13621,8 +13280,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [addp]]}]] - *neon-stable-not-arm - *neon-unstable-is-arm - safety: - unsafe: [neon] + safety: safe types: - int8x8_t - int16x4_t @@ -13646,8 +13304,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [addp]]}]] - *neon-stable-not-arm - *neon-unstable-is-arm - safety: - unsafe: [neon] + safety: safe types: - [uint8x8_t, int8x8_t] - [uint16x4_t, int16x4_t] @@ -13666,8 +13323,7 @@ intrinsics: doc: "Signed Add and Accumulate Long Pairwise." arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] return_type: "{neon_type[0]}" - safety: - unsafe: [neon] + safety: safe attr: - *neon-v7 - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['{type[2]}']]}]] @@ -13692,8 +13348,7 @@ intrinsics: doc: "Signed Add and Accumulate Long Pairwise." arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] return_type: "{neon_type[0]}" - safety: - unsafe: [neon] + safety: safe attr: - *neon-v7 - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['{type[2]}']]}]] @@ -13716,8 +13371,7 @@ intrinsics: doc: "Signed Add and Accumulate Long Pairwise." arguments: ["a: {neon_type[0]}"] return_type: "{neon_type[1]}" - safety: - unsafe: [neon] + safety: safe attr: - *neon-v7 - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['{type[2]}']]}]] @@ -13744,8 +13398,7 @@ intrinsics: doc: "Unsigned Add and Accumulate Long Pairwise." arguments: ["a: {neon_type[0]}"] return_type: "{neon_type[1]}" - safety: - unsafe: [neon] + safety: safe attr: - *neon-v7 - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['{type[2]}']]}]] @@ -13772,8 +13425,7 @@ intrinsics: doc: "Signed Add and Accumulate Long Pairwise." arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] return_type: "{neon_type[0]}" - safety: - unsafe: [neon] + safety: safe attr: - *neon-v7 - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['"{type[2]}"']]}]] @@ -13781,12 +13433,12 @@ intrinsics: - *neon-stable-not-arm - *neon-unstable-is-arm types: - - [int16x4_t, int8x8_t, 'vpadal.s8', 'let x: int16x4_t; #[cfg(target_arch = "arm")] { x = priv_vpadal_s8(a, b); } #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))] { x = simd_add(vpaddl_s8(b), a);}'] - - [int32x2_t, int16x4_t, 'vpadal.s16', 'let x: int32x2_t; #[cfg(target_arch = "arm")] { x = priv_vpadal_s16(a, b); } #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))] { x = simd_add(vpaddl_s16(b), a);}'] - - [int64x1_t, int32x2_t, 'vpadal.s32', 'let x: int64x1_t; #[cfg(target_arch = "arm")] { x = priv_vpadal_s32(a, b); } #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))] { x = simd_add(vpaddl_s32(b), a);}'] - - [int16x8_t, int8x16_t, 'vpadal.s8', 'let x: int16x8_t; #[cfg(target_arch = "arm")] { x = priv_vpadalq_s8(a, b); } #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))] { x = simd_add(vpaddlq_s8(b), a);}'] - - [int32x4_t, int16x8_t, 'vpadal.s16', 'let x: int32x4_t; #[cfg(target_arch = "arm")] { x = priv_vpadalq_s16(a, b); } #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))] { x = simd_add(vpaddlq_s16(b), a);}'] - - [int64x2_t, int32x4_t, 'vpadal.s32', 'let x: int64x2_t; #[cfg(target_arch = "arm")] { x = priv_vpadalq_s32(a, b); } #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))] { x = simd_add(vpaddlq_s32(b), a);}'] + - [int16x4_t, int8x8_t, 'vpadal.s8', 'let x: int16x4_t; #[cfg(target_arch = "arm")] { x = priv_vpadal_s8(a, b); } #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))] unsafe { x = simd_add(vpaddl_s8(b), a);}'] + - [int32x2_t, int16x4_t, 'vpadal.s16', 'let x: int32x2_t; #[cfg(target_arch = "arm")] { x = priv_vpadal_s16(a, b); } #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))] unsafe { x = simd_add(vpaddl_s16(b), a);}'] + - [int64x1_t, int32x2_t, 'vpadal.s32', 'let x: int64x1_t; #[cfg(target_arch = "arm")] { x = priv_vpadal_s32(a, b); } #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))] unsafe { x = simd_add(vpaddl_s32(b), a);}'] + - [int16x8_t, int8x16_t, 'vpadal.s8', 'let x: int16x8_t; #[cfg(target_arch = "arm")] { x = priv_vpadalq_s8(a, b); } #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))] unsafe { x = simd_add(vpaddlq_s8(b), a);}'] + - [int32x4_t, int16x8_t, 'vpadal.s16', 'let x: int32x4_t; #[cfg(target_arch = "arm")] { x = priv_vpadalq_s16(a, b); } #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))] unsafe { x = simd_add(vpaddlq_s16(b), a);}'] + - [int64x2_t, int32x4_t, 'vpadal.s32', 'let x: int64x2_t; #[cfg(target_arch = "arm")] { x = priv_vpadalq_s32(a, b); } #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))] unsafe { x = simd_add(vpaddlq_s32(b), a);}'] compose: - Identifier: ['{type[3]}', Symbol] - Identifier: [x, Symbol] @@ -13795,8 +13447,7 @@ intrinsics: doc: "Unsigned Add and Accumulate Long Pairwise." arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] return_type: "{neon_type[0]}" - safety: - unsafe: [neon] + safety: safe attr: - *neon-v7 - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['"{type[2]}"']]}]] @@ -13804,12 +13455,12 @@ intrinsics: - *neon-stable-not-arm - *neon-unstable-is-arm types: - - [uint16x4_t, uint8x8_t, 'vpadal.u8', 'let x: uint16x4_t; #[cfg(target_arch = "arm")] { x = priv_vpadal_u8(a, b); } #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))] { x = simd_add(vpaddl_u8(b), a);}'] - - [uint32x2_t, uint16x4_t, 'vpadal.u16', 'let x: uint32x2_t; #[cfg(target_arch = "arm")] { x = priv_vpadal_u16(a, b); } #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))] { x = simd_add(vpaddl_u16(b), a);}'] - - [uint64x1_t, uint32x2_t, 'vpadal.u32', 'let x: uint64x1_t; #[cfg(target_arch = "arm")] { x = priv_vpadal_u32(a, b); } #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))] { x = simd_add(vpaddl_u32(b), a);}'] - - [uint16x8_t, uint8x16_t, 'vpadal.u8', 'let x: uint16x8_t; #[cfg(target_arch = "arm")] { x = priv_vpadalq_u8(a, b); } #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))] { x = simd_add(vpaddlq_u8(b), a);}'] - - [uint32x4_t, uint16x8_t, 'vpadal.u16', 'let x: uint32x4_t; #[cfg(target_arch = "arm")] { x = priv_vpadalq_u16(a, b); } #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))] { x = simd_add(vpaddlq_u16(b), a);}'] - - [uint64x2_t, uint32x4_t, 'vpadal.u32', 'let x: uint64x2_t; #[cfg(target_arch = "arm")] { x = priv_vpadalq_u32(a, b); } #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))] { x = simd_add(vpaddlq_u32(b), a);}'] + - [uint16x4_t, uint8x8_t, 'vpadal.u8', 'let x: uint16x4_t; #[cfg(target_arch = "arm")] { x = priv_vpadal_u8(a, b); } #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))] unsafe { x = simd_add(vpaddl_u8(b), a);}'] + - [uint32x2_t, uint16x4_t, 'vpadal.u16', 'let x: uint32x2_t; #[cfg(target_arch = "arm")] { x = priv_vpadal_u16(a, b); } #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))] unsafe { x = simd_add(vpaddl_u16(b), a);}'] + - [uint64x1_t, uint32x2_t, 'vpadal.u32', 'let x: uint64x1_t; #[cfg(target_arch = "arm")] { x = priv_vpadal_u32(a, b); } #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))] unsafe { x = simd_add(vpaddl_u32(b), a);}'] + - [uint16x8_t, uint8x16_t, 'vpadal.u8', 'let x: uint16x8_t; #[cfg(target_arch = "arm")] { x = priv_vpadalq_u8(a, b); } #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))] unsafe { x = simd_add(vpaddlq_u8(b), a);}'] + - [uint32x4_t, uint16x8_t, 'vpadal.u16', 'let x: uint32x4_t; #[cfg(target_arch = "arm")] { x = priv_vpadalq_u16(a, b); } #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))] unsafe { x = simd_add(vpaddlq_u16(b), a);}'] + - [uint64x2_t, uint32x4_t, 'vpadal.u32', 'let x: uint64x2_t; #[cfg(target_arch = "arm")] { x = priv_vpadalq_u32(a, b); } #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))] unsafe { x = simd_add(vpaddlq_u32(b), a);}'] compose: - Identifier: ['{type[3]}', Symbol] - Identifier: [x, Symbol] @@ -13818,8 +13469,7 @@ intrinsics: doc: "Population count per byte." arguments: ["a: {neon_type}"] return_type: "{neon_type}" - safety: - unsafe: [neon] + safety: safe attr: - *neon-v7 - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vcnt]]}]] @@ -13842,8 +13492,7 @@ intrinsics: doc: "Population count per byte." arguments: ["a: {neon_type[0]}"] return_type: "{neon_type[0]}" - safety: - unsafe: [neon] + safety: safe attr: - *neon-v7 - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vcnt]]}]] @@ -13868,8 +13517,7 @@ intrinsics: doc: "8-bit integer matrix multiply-accumulate" arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[1]}"] return_type: "{neon_type[0]}" - safety: - unsafe: [neon] + safety: safe attr: - *neon-i8mm - *neon-v8 @@ -13892,8 +13540,7 @@ intrinsics: doc: "8-bit integer matrix multiply-accumulate" arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[1]}"] return_type: "{neon_type[0]}" - safety: - unsafe: [neon] + safety: safe attr: - *neon-i8mm - *neon-v8 @@ -13916,8 +13563,7 @@ intrinsics: doc: "Unsigned and signed 8-bit integer matrix multiply-accumulate" arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"] return_type: "{neon_type[0]}" - safety: - unsafe: [neon] + safety: safe attr: - *neon-i8mm - *neon-v8 @@ -13941,8 +13587,7 @@ intrinsics: doc: "Table look-up" arguments: ["a: {neon_type}", "b: {neon_type}"] return_type: "{neon_type}" - safety: - unsafe: [neon] + safety: safe attr: - *target-is-arm - *neon-v7 @@ -13961,8 +13606,7 @@ intrinsics: doc: "Table look-up" arguments: ["a: {neon_type}", "b: {neon_type}"] return_type: "{neon_type}" - safety: - unsafe: [neon] + safety: safe attr: - *target-is-arm - *neon-v7 @@ -13977,8 +13621,7 @@ intrinsics: doc: "Table look-up" arguments: ["a: {neon_type[0]}", "b: uint8x8_t"] return_type: "{neon_type[1]}" - safety: - unsafe: [neon] + safety: safe attr: - *target-is-arm - *neon-v7 @@ -14000,8 +13643,7 @@ intrinsics: doc: "Table look-up" arguments: ["a: {neon_type}", "b: {neon_type}", "c: {neon_type}"] return_type: "{neon_type}" - safety: - unsafe: [neon] + safety: safe attr: - *target-is-arm - *neon-v7 @@ -14020,8 +13662,7 @@ intrinsics: doc: "Table look-up" arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] return_type: "{neon_type[1]}" - safety: - unsafe: [neon] + safety: safe attr: - *target-is-arm - *neon-v7 @@ -14036,8 +13677,7 @@ intrinsics: doc: "Table look-up" arguments: ["a: {neon_type[0]}", "b: uint8x8_t"] return_type: "{neon_type[1]}" - safety: - unsafe: [neon] + safety: safe attr: - *target-is-arm - *neon-v7 @@ -14060,8 +13700,7 @@ intrinsics: doc: "Table look-up" arguments: ["a: {neon_type}", "b: {neon_type}", "c: {neon_type}", "d: {neon_type}"] return_type: "{neon_type}" - safety: - unsafe: [neon] + safety: safe attr: - *target-is-arm - *neon-v7 @@ -14080,8 +13719,7 @@ intrinsics: doc: "Table look-up" arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] return_type: "{neon_type[1]}" - safety: - unsafe: [neon] + safety: safe attr: - *target-is-arm - *neon-v7 @@ -14096,8 +13734,7 @@ intrinsics: doc: "Table look-up" arguments: ["a: {neon_type[0]}", "b: uint8x8_t"] return_type: "{neon_type[1]}" - safety: - unsafe: [neon] + safety: safe attr: - *target-is-arm - *neon-v7 @@ -14121,8 +13758,7 @@ intrinsics: doc: "Table look-up" arguments: ["a: {neon_type}", "b: {neon_type}", "c: {neon_type}", "d: {neon_type}", "e: {neon_type}"] return_type: "{neon_type}" - safety: - unsafe: [neon] + safety: safe attr: - *target-is-arm - *neon-v7 @@ -14141,8 +13777,7 @@ intrinsics: doc: "Table look-up" arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] return_type: "{neon_type[1]}" - safety: - unsafe: [neon] + safety: safe attr: - *target-is-arm - *neon-v7 @@ -14157,8 +13792,7 @@ intrinsics: doc: "Table look-up" arguments: ["a: {neon_type[0]}", "b: uint8x8_t"] return_type: "{neon_type[1]}" - safety: - unsafe: [neon] + safety: safe attr: - *target-is-arm - *neon-v7 @@ -14299,8 +13933,7 @@ intrinsics: doc: "Shift Right and Insert (immediate)" arguments: ["a: {neon_type[1]}", "b: {neon_type[1]}", "c: {neon_type[1]}"] return_type: "{neon_type[1]}" - safety: - unsafe: [neon] + safety: safe attr: #- *target-is-arm #- *neon-v7 @@ -14325,8 +13958,7 @@ intrinsics: doc: "Shift Right and Insert (immediate)" arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] return_type: "{neon_type[0]}" - safety: - unsafe: [neon] + safety: safe attr: - *target-is-arm - FnCall: [target_feature, ['enable = "{type[1]}"']] @@ -14371,8 +14003,7 @@ intrinsics: - *neon-unstable - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['"vsri.{type[1]}"', 'N = 1']]}]] - FnCall: [rustc_legacy_const_generics, ['2']] - safety: - unsafe: [neon] + safety: safe types: - [int8x8_t, '8', '1 <= N && N <= 8', 'v8i8', 'int8x8_t::splat', '-N as i8'] - [int8x16_t, '8', '1 <= N && N <= 8', 'v16i8', 'int8x16_t::splat', '-N as i8'] @@ -14394,8 +14025,7 @@ intrinsics: doc: "Shift Left and Insert (immediate)" arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] return_type: "{neon_type[0]}" - safety: - unsafe: [neon] + safety: safe attr: - *target-is-arm - FnCall: [target_feature, ['enable = "{type[1]}"']] @@ -14433,8 +14063,7 @@ intrinsics: doc: "Shift Left and Insert (immediate)" arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] return_type: "{neon_type[0]}" - safety: - unsafe: [neon] + safety: safe attr: - *target-is-arm - FnCall: [target_feature, ['enable = "neon,v7"']] @@ -14468,8 +14097,7 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 assert_instr: [nop] - safety: - unsafe: [neon] + safety: safe types: - [float16x4_t, float16x8_t] compose: @@ -14484,8 +14112,7 @@ intrinsics: - *neon-fp16 - *neon-unstable-f16 assert_instr: [nop] - safety: - unsafe: [neon] + safety: safe types: - [float16x4_t, float16x8_t, 'low', "[0, 1, 2, 3]"] - [float16x4_t, float16x8_t, 'high', "[4, 5, 6, 7]"] @@ -14504,8 +14131,7 @@ intrinsics: - FnCall: [rustc_legacy_const_generics, ["1"]] - *neon-unstable-f16 static_defs: ['const LANE: i32'] - safety: - unsafe: [neon] + safety: safe types: - [float16x4_t, f16, '_lane_f16', '2'] - [float16x8_t, f16, 'q_lane_f16', '3'] @@ -14523,8 +14149,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [dup]]}]] - *neon-fp16 - *neon-unstable-f16 - safety: - unsafe: [neon] + safety: safe types: - [float16x4_t, f16] - [float16x8_t, f16] diff --git a/crates/stdarch-gen-arm/src/expression.rs b/crates/stdarch-gen-arm/src/expression.rs index 55957a6d6b..b1db251a14 100644 --- a/crates/stdarch-gen-arm/src/expression.rs +++ b/crates/stdarch-gen-arm/src/expression.rs @@ -42,11 +42,18 @@ pub struct FnCall( /// Function turbofish arguments #[serde(default)] pub Vec, + /// Function requires unsafe wrapper + #[serde(default)] + pub bool, ); impl FnCall { pub fn new_expression(fn_ptr: Expression, arguments: Vec) -> Expression { - FnCall(Box::new(fn_ptr), arguments, Vec::new()).into() + FnCall(Box::new(fn_ptr), arguments, Vec::new(), false).into() + } + + pub fn new_unsafe_expression(fn_ptr: Expression, arguments: Vec) -> Expression { + FnCall(Box::new(fn_ptr), arguments, Vec::new(), true).into() } pub fn is_llvm_link_call(&self, llvm_link_name: &String) -> bool { @@ -84,7 +91,7 @@ impl FnCall { impl ToTokens for FnCall { fn to_tokens(&self, tokens: &mut TokenStream) { - let FnCall(fn_ptr, arguments, turbofish) = self; + let FnCall(fn_ptr, arguments, turbofish, _requires_unsafe_wrapper) = self; fn_ptr.to_tokens(tokens); @@ -301,7 +308,7 @@ impl Expression { } Self::CastAs(exp, _ty) => exp.requires_unsafe_wrapper(ctx_fn), // Functions and macros can be unsafe, but can also contain other expressions. - Self::FnCall(FnCall(fn_exp, args, turbo_args)) => { + Self::FnCall(FnCall(fn_exp, args, turbo_args, requires_unsafe_wrapper)) => { let fn_name = fn_exp.to_string(); fn_exp.requires_unsafe_wrapper(ctx_fn) || fn_name.starts_with("_sv") @@ -311,6 +318,7 @@ impl Expression { || turbo_args .iter() .any(|exp| exp.requires_unsafe_wrapper(ctx_fn)) + || *requires_unsafe_wrapper } Self::MethodCall(exp, fn_name, args) => match fn_name.as_str() { // `as_signed` and `as_unsigned` are unsafe because they're trait methods with diff --git a/crates/stdarch-gen-arm/src/intrinsic.rs b/crates/stdarch-gen-arm/src/intrinsic.rs index fc8f4343b5..822bf74ef0 100644 --- a/crates/stdarch-gen-arm/src/intrinsic.rs +++ b/crates/stdarch-gen-arm/src/intrinsic.rs @@ -598,7 +598,10 @@ impl LLVMLink { }) .try_collect()?; - Ok(FnCall::new_expression(link_sig.fn_name().into(), call_args)) + Ok(FnCall::new_unsafe_expression( + link_sig.fn_name().into(), + call_args, + )) } /// Given a FnCall, apply all the predicate and unsigned conversions as required. @@ -1251,7 +1254,7 @@ impl Intrinsic { .iter() .map(|sd| sd.try_into()) .try_collect()?; - let mut call: Expression = FnCall(Box::new(name), args, statics).into(); + let mut call: Expression = FnCall(Box::new(name), args, statics, false).into(); call.build(self, ctx)?; Ok(vec![call]) } @@ -1320,7 +1323,7 @@ impl Intrinsic { .iter() .map(|sd| sd.try_into()) .try_collect()?; - let mut call: Expression = FnCall(Box::new(name), args, statics).into(); + let mut call: Expression = FnCall(Box::new(name), args, statics, false).into(); call.build(self, ctx)?; Ok(vec![call]) } @@ -1413,7 +1416,7 @@ impl Intrinsic { .iter() .map(|sd| sd.try_into()) .try_collect()?; - let mut call: Expression = FnCall(Box::new(name), args, statics).into(); + let mut call: Expression = FnCall(Box::new(name), args, statics, false).into(); call.build(self, ctx)?; variant.compose = vec![call]; @@ -1665,7 +1668,13 @@ impl Intrinsic { .return_type .as_ref() .and_then(|t| t.wildcard()); - let call = FnCall(Box::new(target_signature.fn_name().into()), args, turbofish).into(); + let call = FnCall( + Box::new(target_signature.fn_name().into()), + args, + turbofish, + false, + ) + .into(); self.compose = vec![convert_if_required( ret_wildcard,