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CPU_FPGA.syr
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Release 14.7 - xst P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
-->
Parameter TMPDIR set to xst/projnav.tmp
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.02 secs
-->
Parameter xsthdpdir set to xst
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.02 secs
-->
Reading design: CPU_FPGA.prj
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) Design Hierarchy Analysis
4) HDL Analysis
5) HDL Synthesis
5.1) HDL Synthesis Report
6) Advanced HDL Synthesis
6.1) Advanced HDL Synthesis Report
7) Low Level Synthesis
8) Partition Report
9) Final Report
9.1) Device utilization summary
9.2) Partition Resource Summary
9.3) TIMING REPORT
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : "CPU_FPGA.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "CPU_FPGA"
Output Format : NGC
Target Device : xc3s400-4-pq208
---- Source Options
Top Module Name : CPU_FPGA
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : LUT
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Mux Style : Auto
Decoder Extraction : YES
Priority Encoder Extraction : Yes
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES
ROM Style : Auto
Mux Extraction : Yes
Resource Sharing : YES
Asynchronous To Synchronous : NO
Multiplier Style : Auto
Automatic Register Balancing : No
---- Target Options
Add IO Buffers : YES
Global Maximum Fanout : 100000
Add Generic Clock Buffer(BUFG) : 8
Register Duplication : YES
Slice Packing : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Yes
Use Synchronous Set : Yes
Use Synchronous Reset : Yes
Pack IO Registers into IOBs : Auto
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Keep Hierarchy : No
Netlist Hierarchy : As_Optimized
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : Maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
Verilog 2001 : YES
Auto BRAM Packing : NO
Slice Utilization Ratio Delta : 5
---- Other Options
Cores Search Directories : {"ipcore_dir" }
=========================================================================
=========================================================================
* HDL Compilation *
=========================================================================
Compiling verilog file "XOR_32bit.v" in library work
Compiling verilog file "SHIFTER.v" in library work
Module <XOR_32bit> compiled
Compiling verilog file "MUX_4to1.v" in library work
Module <SHIFTER> compiled
Compiling verilog file "MUX_2to1.v" in library work
Module <MUX_4to1> compiled
Compiling verilog file "DIFF_32bit.v" in library work
Module <MUX_2to1> compiled
Compiling verilog file "AND_32bit.v" in library work
Module <DIFF_32bit> compiled
Compiling verilog file "ADDR_32bit.v" in library work
Module <AND_32bit> compiled
Compiling verilog file "SIGN_EXTND.v" in library work
Module <ADDR_32bit> compiled
Compiling verilog file "RegFile.v" in library work
Module <SIGN_EXTND> compiled
Compiling verilog file "MUX_10to1.v" in library work
Module <RegFile> compiled
Compiling verilog file "JumpDecider.v" in library work
Module <MUX_10to1> compiled
Compiling verilog file "ipcore_dir/READ_WRITE_MEM.v" in library work
Module <JumpDecider> compiled
Compiling verilog file "ipcore_dir/READ_ONLY_MEM.v" in library work
Module <READ_WRITE_MEM> compiled
Compiling verilog file "control.v" in library work
Module <READ_ONLY_MEM> compiled
Compiling verilog file "BranchDecider.v" in library work
Module <control> compiled
Compiling verilog file "ALU_32bit.v" in library work
Module <BranchDecider> compiled
Compiling verilog file "CPU_FPGA.v" in library work
Module <ALU_32bit> compiled
Module <CPU_FPGA> compiled
No errors in compilation
Analysis of file <"CPU_FPGA.prj"> succeeded.
=========================================================================
* Design Hierarchy Analysis *
=========================================================================
Analyzing hierarchy for module <CPU_FPGA> in library <work>.
Analyzing hierarchy for module <control> in library <work>.
Analyzing hierarchy for module <Register> in library <work> with parameters.
WIDTH = "00000000000000000000000000100000"
Analyzing hierarchy for module <MUX_2to1> in library <work> with parameters.
WIDTH = "00000000000000000000000000001100"
Analyzing hierarchy for module <MUX_4to1> in library <work> with parameters.
WIDTH = "00000000000000000000000000000101"
Analyzing hierarchy for module <RegFile> in library <work>.
Analyzing hierarchy for module <SIGN_EXTND> in library <work> with parameters.
INPUT_WIDTH = "00000000000000000000000000010000"
Analyzing hierarchy for module <SIGN_EXTND> in library <work> with parameters.
INPUT_WIDTH = "00000000000000000000000000010101"
Analyzing hierarchy for module <MUX_2to1> in library <work> with parameters.
WIDTH = "00000000000000000000000000100000"
Analyzing hierarchy for module <MUX_2to1> in library <work> with parameters.
WIDTH = "00000000000000000000000000000101"
Analyzing hierarchy for module <ALU_32bit> in library <work>.
Analyzing hierarchy for module <Register> in library <work> with parameters.
WIDTH = "00000000000000000000000000000001"
Analyzing hierarchy for module <BranchDecider> in library <work>.
Analyzing hierarchy for module <JumpDecider> in library <work>.
Analyzing hierarchy for module <ADDR_32bit> in library <work>.
Analyzing hierarchy for module <MUX_4to1> in library <work> with parameters.
WIDTH = "00000000000000000000000000100000"
Analyzing hierarchy for module <MUX_10to1> in library <work> with parameters.
WIDTH = "00000000000000000000000000100000"
Analyzing hierarchy for module <MUX_2to1> in library <work> with parameters.
WIDTH = "00000000000000000000000000100000"
Analyzing hierarchy for module <AND_32bit> in library <work>.
Analyzing hierarchy for module <XOR_32bit> in library <work>.
Analyzing hierarchy for module <DIFF_32bit> in library <work>.
Analyzing hierarchy for module <MUX_2to1> in library <work> with parameters.
WIDTH = "00000000000000000000000000100000"
Analyzing hierarchy for module <SHIFTER> in library <work>.
Analyzing hierarchy for module <MUX_4to1> in library <work> with parameters.
WIDTH = "00000000000000000000000000000001"
=========================================================================
* HDL Analysis *
=========================================================================
Analyzing top module <CPU_FPGA>.
WARNING:Xst:2211 - "ipcore_dir/READ_ONLY_MEM.v" line 71: Instantiating black box module <READ_ONLY_MEM>.
WARNING:Xst:2211 - "ipcore_dir/READ_WRITE_MEM.v" line 140: Instantiating black box module <READ_WRITE_MEM>.
Module <CPU_FPGA> is correct for synthesis.
Analyzing module <control> in library <work>.
Module <control> is correct for synthesis.
Analyzing module <Register.1> in library <work>.
WIDTH = 32'sb00000000000000000000000000100000
Module <Register.1> is correct for synthesis.
Analyzing module <MUX_2to1.1> in library <work>.
WIDTH = 32'sb00000000000000000000000000001100
Module <MUX_2to1.1> is correct for synthesis.
Analyzing module <MUX_4to1.1> in library <work>.
WIDTH = 32'sb00000000000000000000000000000101
Module <MUX_4to1.1> is correct for synthesis.
Analyzing module <RegFile> in library <work>.
Module <RegFile> is correct for synthesis.
Analyzing module <SIGN_EXTND.1> in library <work>.
INPUT_WIDTH = 32'sb00000000000000000000000000010000
Module <SIGN_EXTND.1> is correct for synthesis.
Analyzing module <SIGN_EXTND.2> in library <work>.
INPUT_WIDTH = 32'sb00000000000000000000000000010101
Module <SIGN_EXTND.2> is correct for synthesis.
Analyzing module <MUX_2to1.2> in library <work>.
WIDTH = 32'sb00000000000000000000000000100000
Module <MUX_2to1.2> is correct for synthesis.
Analyzing module <MUX_2to1.3> in library <work>.
WIDTH = 32'sb00000000000000000000000000000101
Module <MUX_2to1.3> is correct for synthesis.
Analyzing module <ALU_32bit> in library <work>.
Module <ALU_32bit> is correct for synthesis.
Analyzing module <AND_32bit> in library <work>.
Module <AND_32bit> is correct for synthesis.
Analyzing module <XOR_32bit> in library <work>.
Module <XOR_32bit> is correct for synthesis.
Analyzing module <DIFF_32bit> in library <work>.
Module <DIFF_32bit> is correct for synthesis.
Analyzing module <SHIFTER> in library <work>.
Module <SHIFTER> is correct for synthesis.
Analyzing module <Register.2> in library <work>.
WIDTH = 32'sb00000000000000000000000000000001
Module <Register.2> is correct for synthesis.
Analyzing module <BranchDecider> in library <work>.
Module <BranchDecider> is correct for synthesis.
Analyzing module <MUX_4to1.3> in library <work>.
WIDTH = 32'sb00000000000000000000000000000001
Module <MUX_4to1.3> is correct for synthesis.
Analyzing module <JumpDecider> in library <work>.
Module <JumpDecider> is correct for synthesis.
Analyzing module <ADDR_32bit> in library <work>.
Module <ADDR_32bit> is correct for synthesis.
Analyzing module <MUX_4to1.2> in library <work>.
WIDTH = 32'sb00000000000000000000000000100000
Module <MUX_4to1.2> is correct for synthesis.
Analyzing module <MUX_10to1> in library <work>.
WIDTH = 32'sb00000000000000000000000000100000
Module <MUX_10to1> is correct for synthesis.
=========================================================================
* HDL Synthesis *
=========================================================================
Performing bidirectional port resolution...
Synthesizing Unit <control>.
Related source file is "control.v".
Unit <control> synthesized.
Synthesizing Unit <Register_1>.
Related source file is "Register.v".
Found 32-bit register for signal <Q>.
Summary:
inferred 32 D-type flip-flop(s).
Unit <Register_1> synthesized.
Synthesizing Unit <MUX_2to1_1>.
Related source file is "MUX_2to1.v".
Unit <MUX_2to1_1> synthesized.
Synthesizing Unit <MUX_4to1_1>.
Related source file is "MUX_4to1.v".
Unit <MUX_4to1_1> synthesized.
Synthesizing Unit <RegFile>.
Related source file is "RegFile.v".
Found 32-bit 32-to-1 multiplexer for signal <rsOut>.
Found 32-bit 32-to-1 multiplexer for signal <rtOut>.
Found 1024-bit register for signal <Registers>.
INFO:Xst:738 - HDL ADVISOR - 1024 flip-flops were inferred for signal <Registers>. You may be trying to describe a RAM in a way that is incompatible with block and distributed RAM resources available on Xilinx devices, or with a specific template that is not supported. Please review the Xilinx resources documentation and the XST user manual for coding guidelines. Taking advantage of RAM resources will lead to improved device usage and reduced synthesis time.
Summary:
inferred 1024 D-type flip-flop(s).
inferred 64 Multiplexer(s).
Unit <RegFile> synthesized.
Synthesizing Unit <SIGN_EXTND_1>.
Related source file is "SIGN_EXTND.v".
Unit <SIGN_EXTND_1> synthesized.
Synthesizing Unit <SIGN_EXTND_2>.
Related source file is "SIGN_EXTND.v".
Unit <SIGN_EXTND_2> synthesized.
Synthesizing Unit <MUX_2to1_2>.
Related source file is "MUX_2to1.v".
Unit <MUX_2to1_2> synthesized.
Synthesizing Unit <MUX_2to1_3>.
Related source file is "MUX_2to1.v".
Unit <MUX_2to1_3> synthesized.
Synthesizing Unit <Register_2>.
Related source file is "Register.v".
Found 1-bit register for signal <Q<0>>.
Summary:
inferred 1 D-type flip-flop(s).
Unit <Register_2> synthesized.
Synthesizing Unit <ADDR_32bit>.
Related source file is "ADDR_32bit.v".
Found 32-bit adder carry in/out for signal <AUX_34$addsub0000>.
Summary:
inferred 1 Adder/Subtractor(s).
Unit <ADDR_32bit> synthesized.
Synthesizing Unit <MUX_4to1_2>.
Related source file is "MUX_4to1.v".
Found 32-bit 4-to-1 multiplexer for signal <out>.
Summary:
inferred 32 Multiplexer(s).
Unit <MUX_4to1_2> synthesized.
Synthesizing Unit <MUX_10to1>.
Related source file is "MUX_10to1.v".
Unit <MUX_10to1> synthesized.
Synthesizing Unit <AND_32bit>.
Related source file is "AND_32bit.v".
Unit <AND_32bit> synthesized.
Synthesizing Unit <XOR_32bit>.
Related source file is "XOR_32bit.v".
Found 32-bit xor2 for signal <XORout>.
Unit <XOR_32bit> synthesized.
Synthesizing Unit <DIFF_32bit>.
Related source file is "DIFF_32bit.v".
Found 1-bit xor2 for signal <DIFFout_31$xor0000> created at line 31.
Found 1-bit xor2 for signal <old_check_10$xor0000> created at line 31.
Found 1-bit xor2 for signal <old_check_11$xor0000> created at line 31.
Found 1-bit xor2 for signal <old_check_12$xor0000> created at line 31.
Found 1-bit xor2 for signal <old_check_13$xor0000> created at line 31.
Found 1-bit xor2 for signal <old_check_14$xor0000> created at line 31.
Found 1-bit xor2 for signal <old_check_15$xor0000> created at line 31.
Found 1-bit xor2 for signal <old_check_16$xor0000> created at line 31.
Found 1-bit xor2 for signal <old_check_17$xor0000> created at line 31.
Found 1-bit xor2 for signal <old_check_18$xor0000> created at line 31.
Found 1-bit xor2 for signal <old_check_19$xor0000> created at line 31.
Found 1-bit xor2 for signal <old_check_20$xor0000> created at line 31.
Found 1-bit xor2 for signal <old_check_21$xor0000> created at line 31.
Found 1-bit xor2 for signal <old_check_22$xor0000> created at line 31.
Found 1-bit xor2 for signal <old_check_23$xor0000> created at line 31.
Found 1-bit xor2 for signal <old_check_24$xor0000> created at line 31.
Found 1-bit xor2 for signal <old_check_25$xor0000> created at line 31.
Found 1-bit xor2 for signal <old_check_26$xor0000> created at line 31.
Found 1-bit xor2 for signal <old_check_27$xor0000> created at line 31.
Found 1-bit xor2 for signal <old_check_28$xor0000> created at line 31.
Found 1-bit xor2 for signal <old_check_29$xor0000> created at line 31.
Found 1-bit xor2 for signal <old_check_3$xor0000> created at line 31.
Found 1-bit xor2 for signal <old_check_30$xor0000> created at line 31.
Found 1-bit xor2 for signal <old_check_31$xor0000> created at line 31.
Found 1-bit xor2 for signal <old_check_32$xor0000> created at line 31.
Found 1-bit xor2 for signal <old_check_33$xor0000> created at line 31.
Found 1-bit xor2 for signal <old_check_4$xor0000> created at line 31.
Found 1-bit xor2 for signal <old_check_5$xor0000> created at line 31.
Found 1-bit xor2 for signal <old_check_6$xor0000> created at line 31.
Found 1-bit xor2 for signal <old_check_7$xor0000> created at line 31.
Found 1-bit xor2 for signal <old_check_8$xor0000> created at line 31.
Found 1-bit xor2 for signal <old_check_9$xor0000> created at line 31.
Summary:
inferred 960 Multiplexer(s).
Unit <DIFF_32bit> synthesized.
Synthesizing Unit <SHIFTER>.
Related source file is "SHIFTER.v".
Found 32-bit shifter logical left for signal <SHIFTERout$shift0000> created at line 46.
Found 32-bit shifter logical right for signal <SHIFTERout$shift0001> created at line 48.
Found 32-bit shifter arithmetic right for signal <SHIFTERout$shift0002> created at line 49.
Summary:
inferred 3 Combinational logic shifter(s).
Unit <SHIFTER> synthesized.
Synthesizing Unit <MUX_4to1_3>.
Related source file is "MUX_4to1.v".
Unit <MUX_4to1_3> synthesized.
Synthesizing Unit <ALU_32bit>.
Related source file is "ALU_32bit.v".
WARNING:Xst:647 - Input <ShifterInputSel> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Unit <ALU_32bit> synthesized.
Synthesizing Unit <BranchDecider>.
Related source file is "BranchDecider.v".
Unit <BranchDecider> synthesized.
Synthesizing Unit <JumpDecider>.
Related source file is "JumpDecider.v".
Unit <JumpDecider> synthesized.
Synthesizing Unit <CPU_FPGA>.
Related source file is "CPU_FPGA.v".
WARNING:Xst:646 - Signal <MemRead> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
Unit <CPU_FPGA> synthesized.
=========================================================================
HDL Synthesis Report
Macro Statistics
# Adders/Subtractors : 3
32-bit adder carry in/out : 3
# Registers : 34
1-bit register : 1
32-bit register : 33
# Multiplexers : 34
32-bit 32-to-1 multiplexer : 2
32-bit 4-to-1 multiplexer : 32
# Logic shifters : 3
32-bit shifter arithmetic right : 1
32-bit shifter logical left : 1
32-bit shifter logical right : 1
# Xors : 33
1-bit xor2 : 32
32-bit xor2 : 1
=========================================================================
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
Reading core <ipcore_dir/READ_ONLY_MEM.ngc>.
Reading core <ipcore_dir/READ_WRITE_MEM.ngc>.
Loading core <READ_ONLY_MEM> for timing and area information for instance <I_CACHE>.
Loading core <READ_WRITE_MEM> for timing and area information for instance <DATA_MEM>.
=========================================================================
Advanced HDL Synthesis Report
Macro Statistics
# Adders/Subtractors : 3
32-bit adder carry in/out : 3
# Registers : 1057
Flip-Flops : 1057
# Multiplexers : 96
1-bit 32-to-1 multiplexer : 64
32-bit 4-to-1 multiplexer : 32
# Logic shifters : 3
32-bit shifter arithmetic right : 1
32-bit shifter logical left : 1
32-bit shifter logical right : 1
# Xors : 33
1-bit xor2 : 32
32-bit xor2 : 1
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
WARNING:Xst:1989 - Unit <CPU_FPGA>: instances <IMM_SE_16>, <OFFSET_SIGN_EXTEND> of unit <SIGN_EXTND_1> are equivalent, second instance is removed
INFO:Xst:1901 - Instance U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/s3_init.ram/dpram.dp4x4.ram in unit U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/s3_init.ram/dpram.dp4x4.ram of type RAMB16_S4_S4 has been replaced by RAMB16
INFO:Xst:1901 - Instance U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/s3_init.ram/dpram.dp4x4.ram in unit U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/s3_init.ram/dpram.dp4x4.ram of type RAMB16_S4_S4 has been replaced by RAMB16
INFO:Xst:1901 - Instance U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s3_init.ram/dpram.dp4x4.ram in unit U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/s3_init.ram/dpram.dp4x4.ram of type RAMB16_S4_S4 has been replaced by RAMB16
INFO:Xst:1901 - Instance U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/s3_init.ram/dpram.dp4x4.ram in unit U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/s3_init.ram/dpram.dp4x4.ram of type RAMB16_S4_S4 has been replaced by RAMB16
INFO:Xst:1901 - Instance U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s3_init.ram/dpram.dp4x4.ram in unit U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s3_init.ram/dpram.dp4x4.ram of type RAMB16_S4_S4 has been replaced by RAMB16
INFO:Xst:1901 - Instance U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s3_init.ram/dpram.dp4x4.ram in unit U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s3_init.ram/dpram.dp4x4.ram of type RAMB16_S4_S4 has been replaced by RAMB16
INFO:Xst:1901 - Instance U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s3_init.ram/dpram.dp4x4.ram in unit U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s3_init.ram/dpram.dp4x4.ram of type RAMB16_S4_S4 has been replaced by RAMB16
INFO:Xst:1901 - Instance U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/dpram.dp4x4.ram in unit U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/dpram.dp4x4.ram of type RAMB16_S4_S4 has been replaced by RAMB16
INFO:Xst:1901 - Instance U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/dpram.dp18x18.ram in unit U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/dpram.dp18x18.ram of type RAMB16_S18_S18 has been replaced by RAMB16
INFO:Xst:1901 - Instance U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s3_init.ram/dpram.dp18x18.ram in unit U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s3_init.ram/dpram.dp18x18.ram of type RAMB16_S18_S18 has been replaced by RAMB16
Optimizing unit <CPU_FPGA> ...
Optimizing unit <Register_1> ...
Optimizing unit <RegFile> ...
Optimizing unit <SHIFTER> ...
Optimizing unit <ALU_32bit> ...
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block CPU_FPGA, actual ratio is 43.
Final Macro Processing ...
=========================================================================
Final Register Report
Macro Statistics
# Registers : 1057
Flip-Flops : 1057
=========================================================================
=========================================================================
* Partition Report *
=========================================================================
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : CPU_FPGA.ngr
Top Level Output File Name : CPU_FPGA
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : No
Design Statistics
# IOs : 38
Cell Usage :
# BELS : 3709
# GND : 13
# INV : 2
# LUT1 : 31
# LUT2 : 148
# LUT3 : 1313
# LUT3_D : 42
# LUT3_L : 9
# LUT4 : 757
# LUT4_D : 39
# LUT4_L : 24
# MUXCY : 102
# MUXF5 : 683
# MUXF6 : 256
# MUXF7 : 128
# MUXF8 : 64
# VCC : 2
# XORCY : 96
# FlipFlops/Latches : 1057
# FDC : 33
# FDCE : 1024
# RAMS : 10
# RAMB16 : 10
# Clock Buffers : 1
# BUFGP : 1
# IO Buffers : 37
# IBUF : 5
# OBUF : 32
=========================================================================
Device utilization summary:
---------------------------
Selected Device : 3s400pq208-4
Number of Slices: 1553 out of 3584 43%
Number of Slice Flip Flops: 1057 out of 7168 14%
Number of 4 input LUTs: 2365 out of 7168 32%
Number of IOs: 38
Number of bonded IOBs: 38 out of 141 26%
Number of BRAMs: 10 out of 16 62%
Number of GCLKs: 1 out of 8 12%
---------------------------
Partition Resource Summary:
---------------------------
No Partitions were found in this design.
---------------------------
=========================================================================
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
-----------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+
clk | BUFGP | 1067 |
I_CACHE/N1 | NONE(I_CACHE/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/s3_init.ram/dpram.dp4x4.ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/s3_init.ram/dpram.dp4x4.ram) | 8 |
DATA_MEM/N1 | NONE(DATA_MEM/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/dpram.dp18x18.ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/dpram.dp18x18.ram)| 2 |
-----------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
Asynchronous Control Signals Information:
----------------------------------------
-----------------------------------+------------------------+-------+
Control Signal | Buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
rst | IBUF | 1057 |
-----------------------------------+------------------------+-------+
Timing Summary:
---------------
Speed Grade: -4
Minimum period: 46.184ns (Maximum Frequency: 21.653MHz)
Minimum input arrival time before clock: 7.678ns
Maximum output required time after clock: 11.887ns
Maximum combinational path delay: 15.102ns
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
Clock period: 46.184ns (frequency: 21.653MHz)
Total number of paths / destination ports: 332582470 / 1205
-------------------------------------------------------------------------
Delay: 23.092ns (Levels of Logic = 19)
Source: REG_FILE/Registers_0_13 (FF)
Destination: DATA_MEM/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/dpram.dp18x18.ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/dpram.dp18x18.ram (RAM)
Source Clock: clk rising
Destination Clock: clk falling
Data Path: REG_FILE/Registers_0_13 to DATA_MEM/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/dpram.dp18x18.ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/dpram.dp18x18.ram
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDCE:C->Q 3 0.720 1.102 REG_FILE/Registers_0_13 (REG_FILE/Registers_0_13)
LUT3:I1->O 1 0.551 0.000 REG_FILE/mux4_10 (REG_FILE/mux4_10)
MUXF5:I0->O 1 0.360 0.000 REG_FILE/mux4_8_f5 (REG_FILE/mux4_8_f5)
MUXF6:I0->O 1 0.342 0.000 REG_FILE/mux4_6_f6 (REG_FILE/mux4_6_f6)
MUXF7:I0->O 1 0.342 0.000 REG_FILE/mux4_4_f7 (REG_FILE/mux4_4_f7)
MUXF8:I0->O 7 0.342 1.261 REG_FILE/mux4_2_f8 (READ_REG1<13>)
LUT2:I1->O 4 0.551 0.943 ALUsrcA_SELECTOR_MUX/out<13>1 (ALUSrcA<13>)
LUT4:I3->O 1 0.551 1.140 ALUmain/DIFF_ALU/Mmux__old_check_181_SW0 (N100)
LUT4_D:I0->O 3 0.551 0.975 ALUmain/DIFF_ALU/Mmux__old_check_121_SW2 (N168)
LUT4_D:I2->O 3 0.551 0.933 ALUmain/DIFF_ALU/Mmux__old_check_181 (ALUmain/DIFF_ALU/old_check_19_cmp_eq0001)
LUT4:I3->O 1 0.551 0.827 ALUmain/DIFF_ALU/DIFFout_18_mux00001 (ALUmain/DIFFoutALU<18>)
LUT4_L:I3->LO 1 0.551 0.168 ALUmain/PrimaryOutputMUX/Mmux_out_49 (ALUmain/PrimaryOutputMUX/Mmux_out_49)
LUT3:I2->O 7 0.551 1.261 ALUmain/ShifterInputMUX/out<18>1 (ALUmain/ShifterInput<18>)
LUT3:I1->O 1 0.551 0.000 ALUmain/SHIFTER_ALU/SHIFTERout<10>401_F (N307)
MUXF5:I0->O 2 0.360 0.877 ALUmain/SHIFTER_ALU/SHIFTERout<10>401 (ALUmain/SHIFTER_ALU/SHIFTERout<10>_bdd77)
MUXF5:S->O 4 0.621 0.943 ALUmain/SHIFTER_ALU/SHIFTERout<14>121 (ALUmain/SHIFTER_ALU/SHIFTERout<14>_bdd21)
LUT4:I3->O 1 0.551 0.869 REG_WRITE_DATA_SELECTOR_MUX/Mmux_out2094 (ALUmain/SHIFTER_ALU/SHIFTERout<2>178)
LUT4:I2->O 1 0.551 0.827 ALUmain/SHIFTER_ALU/SHIFTERout<2>1130 (ALUmain/SHIFTER_ALU/SHIFTERout<2>1130)
LUT4:I3->O 4 0.551 0.917 ALUmain/SHIFTER_ALU/SHIFTERout<2>1174 (ALU_RES<2>)
begin scope: 'DATA_MEM'
begin scope: 'U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/dpram.dp18x18.ram'
RAMB16:ADDRA6 0.350 U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/dpram.dp18x18.ram
----------------------------------------
Total 23.092ns (10.049ns logic, 13.043ns route)
(43.5% logic, 56.5% route)
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
Total number of paths / destination ports: 96 / 96
-------------------------------------------------------------------------
Offset: 7.678ns (Levels of Logic = 3)
Source: rst (PAD)
Destination: I_CACHE/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/s3_init.ram/dpram.dp4x4.ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/s3_init.ram/dpram.dp4x4.ram (RAM)
Destination Clock: clk rising
Data Path: rst to I_CACHE/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/s3_init.ram/dpram.dp4x4.ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/s3_init.ram/dpram.dp4x4.ram
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 1069 0.821 4.873 rst_IBUF (rst_IBUF)
LUT2:I0->O 8 0.551 1.083 I_CACHE_ADDR_SELECTOR_MUX/out<9>1 (I_CACHE_ADDR_IN<9>)
begin scope: 'I_CACHE'
begin scope: 'U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/s3_init.ram/dpram.dp4x4.ram'
RAMB16:ADDRA11 0.350 U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/s3_init.ram/dpram.dp4x4.ram
----------------------------------------
Total 7.678ns (1.722ns logic, 5.956ns route)
(22.4% logic, 77.6% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
Total number of paths / destination ports: 320 / 32
-------------------------------------------------------------------------
Offset: 11.887ns (Levels of Logic = 4)
Source: REG_FILE/Registers_9_31 (FF)
Destination: CPU_OUTPUT<31> (PAD)
Source Clock: clk rising
Data Path: REG_FILE/Registers_9_31 to CPU_OUTPUT<31>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDCE:C->Q 3 0.720 1.102 REG_FILE/Registers_9_31 (REG_FILE/Registers_9_31)
LUT4:I1->O 1 0.551 1.140 OUTPUT_SELECTOR_MUX/out<31>37 (OUTPUT_SELECTOR_MUX/out<31>37)
LUT2:I0->O 1 0.551 0.827 OUTPUT_SELECTOR_MUX/out<31>43 (OUTPUT_SELECTOR_MUX/out<31>43)
LUT4:I3->O 1 0.551 0.801 OUTPUT_SELECTOR_MUX/out<31>52 (CPU_OUTPUT_31_OBUF)
OBUF:I->O 5.644 CPU_OUTPUT_31_OBUF (CPU_OUTPUT<31>)
----------------------------------------
Total 11.887ns (8.017ns logic, 3.870ns route)
(67.4% logic, 32.6% route)
=========================================================================
Timing constraint: Default path analysis
Total number of paths / destination ports: 1280 / 32
-------------------------------------------------------------------------
Delay: 15.102ns (Levels of Logic = 6)
Source: output_sel<2> (PAD)
Destination: CPU_OUTPUT<31> (PAD)
Data Path: output_sel<2> to CPU_OUTPUT<31>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 10 0.821 1.473 output_sel_2_IBUF (output_sel_2_IBUF)
LUT4:I0->O 32 0.551 2.192 OUTPUT_SELECTOR_MUX/out_cmp_eq00091 (OUTPUT_SELECTOR_MUX/out_cmp_eq0009)
LUT4:I0->O 1 0.551 1.140 OUTPUT_SELECTOR_MUX/out<9>37 (OUTPUT_SELECTOR_MUX/out<9>37)
LUT2:I0->O 1 0.551 0.827 OUTPUT_SELECTOR_MUX/out<9>43 (OUTPUT_SELECTOR_MUX/out<9>43)
LUT4:I3->O 1 0.551 0.801 OUTPUT_SELECTOR_MUX/out<9>52 (CPU_OUTPUT_9_OBUF)
OBUF:I->O 5.644 CPU_OUTPUT_9_OBUF (CPU_OUTPUT<9>)
----------------------------------------
Total 15.102ns (8.669ns logic, 6.433ns route)
(57.4% logic, 42.6% route)
=========================================================================
Total REAL time to Xst completion: 17.00 secs
Total CPU time to Xst completion: 17.47 secs
-->
Total memory usage is 564528 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 5 ( 0 filtered)
Number of infos : 12 ( 0 filtered)