CPU_FPGA.bld

Release 14.7 ngdbuild P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.

Command Line: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/ngdbuild -intstyle
ise -dd _ngo -sd ipcore_dir -nt timestamp -i -p xc3s400-pq208-4 CPU_FPGA.ngc
CPU_FPGA.ngd

Reading NGO file "/home/rounak/Documents/SEM_5/COA/verilog/Verilog Demo/ISE
Project/KGP_miniRISC/CPU_FPGA.ngc" ...
Loading design module "ipcore_dir/READ_ONLY_MEM.ngc"...
Loading design module "ipcore_dir/READ_WRITE_MEM.ngc"...
Gathering constraint information from source properties...
Done.

Resolving constraint associations...
Checking Constraint Associations...
Done...

Checking expanded design ...

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 390428 kilobytes

Writing NGD file "CPU_FPGA.ngd" ...
Total REAL time to NGDBUILD completion:  1 sec
Total CPU time to NGDBUILD completion:   1 sec

Writing NGDBUILD log file "CPU_FPGA.bld"...