From 31a378b11779d097e4cfffc8ec4bcf4d3ba82aaf Mon Sep 17 00:00:00 2001 From: Beeman Strong <97133824+bcstrongx@users.noreply.github.com> Date: Mon, 16 Dec 2024 13:43:47 -0800 Subject: [PATCH] Delete event_files/rvv_spec.json Signed-off-by: Beeman Strong <97133824+bcstrongx@users.noreply.github.com> --- event_files/rvv_spec.json | 92 --------------------------------------- 1 file changed, 92 deletions(-) delete mode 100644 event_files/rvv_spec.json diff --git a/event_files/rvv_spec.json b/event_files/rvv_spec.json deleted file mode 100644 index c771c66..0000000 --- a/event_files/rvv_spec.json +++ /dev/null @@ -1,92 +0,0 @@ -[ - { - "EventName": "INST.RVV.SPEC", - "EventCode": "0x0", - "BriefDescription": "Number of RVV instructions executed", - "PublicDescription": "Number of RVV instructions executed" - }, - { - "EventName": "INST.RVV.INT.SPEC", - "EventCode": "0x0", - "BriefDescription": "Number of integer RVV instructions executed", - "PublicDescription": "Number of integer RVV instructions executed" - }, - { - "EventName": "INST.RVV.FP.SPEC", - "EventCode": "0x0", - "BriefDescription": "Number of floating point RVV instructions executed", - "PublicDescription": "Number of floating point RVV instructions executed" - }, - { - "EventName": "RVV.ELEMENT.UNMASKED.INT8.SPEC", - "EventCode": "0x0", - "BriefDescription": "Number of 8-bit integer element operation executed", - "PublicDescription": "Number of 8-bit integer element operation executed. For example, if we have SEW=8, LMUL=1, VLEN=128 and doing vector integer arith instruction - it should increment the RVV.ELEMENT.UNMASKED.INT8 counter by 16. Masked-out elements should not increment the counter - so in the previous example if half of the lanes are masked the RVV.ELEMENT.UNMASKED.INT8 will be incremented by 8. For multiply-add instructions each element operation should increment counter by 2 to account for both multiplication and addition." - }, - { - "EventName": "RVV.ELEMENT.INT8.SPEC", - "EventCode": "0x0", - "BriefDescription": "Number of 8-bit integer element operation executed not taking into account masking", - "PublicDescription": "Number of 8-bit integer element operation executed. For example, if we have SEW=8, LMUL=1, VLEN=128 and doing vector integer arith instruction - it should increment the RVV.ELEMENT.INT8 counter by 16. Mask should not be taken into account - so in the previous example if half of the lanes are masked the RVV.ELEMENT.INT8 will still be incremented by 16. For multiply-add instructions each element operation should increment counter by 2 to account for both multiplication and addition." - }, - { - "EventName": "RVV.ELEMENT.UNMASKED.INT16.SPEC", - "EventCode": "0x0", - "BriefDescription": "Number of 16-bit integer element operation executed", - "PublicDescription": "Number of 16-bit integer element operation executed. For example, if we have SEW=16, LMUL=1, VLEN=128 and doing vector integer arith instruction - it should increment the RVV.ELEMENT.UNMASKED.INT16 counter by 8. Masked-out elements should not increment the counter - so in the previous example half of the lanes are masked the RVV.ELEMENT.UNMASKED.INT16 counter will be incremented by 4. For multiply-add instructions each element operation should increment counter by 2 to account for both multiplication and addition." - }, - { - "EventName": "RVV.ELEMENT.INT16.SPEC", - "EventCode": "0x0", - "BriefDescription": "Number of 16-bit integer element operation executed not taking into account masking", - "PublicDescription": "Number of 16-bit integer element operation executed. For example, if we have SEW=16, LMUL=1, VLEN=128 and doing vector integer arith instruction - it should increment the RVV.ELEMENT.INT16 counter by 8. Mask should not be taken into account - so in the previous example if half of the lanes are masked the RVV.ELEMENT.INT16 counter will still be incremented by 8. For multiply-add instructions each element operation should increment counter by 2 to account for both multiplication and addition." - }, - { - "EventName": "RVV.ELEMENT.UNMASKED.INT32.SPEC", - "EventCode": "0x0", - "BriefDescription": "Number of 32-bit integer element operation executed", - "PublicDescription": "Number of 32-bit integer element operation executed. For example, if we have SEW=32, LMUL=1, VLEN=128 and doing vector integer arith instruction - it should increment the RVV.ELEMENT.UNMASKED.INT16 counter by 4. Masked-out elements should not increment the counter - so in the previous example if half of the lanes are masked the RVV.ELEMENT.UNMASKED.INT32 counter will be incremented by 2. For multiply-add instructions each element operation should increment counter by 2 to account for both multiplication and addition." - }, - { - "EventName": "RVV.ELEMENT.INT32.SPEC", - "EventCode": "0x0", - "BriefDescription": "Number of 32-bit integer element operation executed not taking into account masking", - "PublicDescription": "Number of 32-bit integer element operation executed. For example, if we have SEW=32, LMUL=1, VLEN=128 and doing vector integer arith instruction - it should increment the RVV.ELEMENT.INT16 counter by 4. Mask should not be taken into account - so in the previous example if half of the lanes are masked the RVV.ELEMENT.INT32 counter will still be incremented by 4. For multiply-add instructions each element operation should increment counter by 2 to account for both multiplication and addition." - }, - { - "EventName": "RVV.ELEMENT.UNMASKED.INT64.SPEC", - "EventCode": "0x0", - "BriefDescription": "Number of 64-bit integer element operation executed", - "PublicDescription": "Number of 64-bit integer element operation executed. For example, if we have SEW=64, LMUL=1, VLEN=128 and doing vector integer arith instruction - it should increment the RVV.ELEMENT.UNMASKED.INT64 counter by 2. Masked-out elements should not increment the counter - so in the previous example half of the lanes are masked the RVV.ELEMENT.UNMASKED.INT64 counter will be incremented by 1. For multiply-add instructions each element operation should increment counter by 2 to account for both multiplication and addition." - }, - { - "EventName": "RVV.ELEMENT.INT64.SPEC", - "EventCode": "0x0", - "BriefDescription": "Number of 64-bit integer element operation executed not taking into account masking", - "PublicDescription": "Number of 64-bit integer element operation executed. For example, if we have SEW=64, LMUL=1, VLEN=128 and doing vector integer arith instruction - it should increment the RVV.ELEMENT.INT64 counter by 2. Mask should not be taken into account - so in the previous example if half of the lanes are masked the RVV.ELEMENT.INT64 counter will still be incremented by 2. For multiply-add instructions each element operation should increment counter by 2 to account for both multiplication and addition." - }, - { - "EventName": "RVV.ELEMENT.UNMASKED.FP_SINGLE.SPEC", - "EventCode": "0x0", - "BriefDescription": "Number of single-precision floating point element operation executed", - "PublicDescription": "Number of single-precision floating point element operation executed. For example, if we have SEW=32, LMUL=1, VLEN=128 and doing vector FP arith instruction - it should increment the RVV.ELEMENT.UNMASKED.FP_SINGLE counter by 4. Masked-out elements should not increment the counter - so in the previous example if half of the lanes are masked the RVV.ELEMENT.UNMASKED.FP_SINGLE counter will be incremented by 2. For multiply-add instructions each element operation should increment counter by 2 to account for both multiplication and addition." - }, - { - "EventName": "RVV.ELEMENT.FP_SINGLE.SPEC", - "EventCode": "0x0", - "BriefDescription": "Number of single-precision floating point element operation executed not taking into account masking", - "PublicDescription": "Number of single-precision floating point element operation executed. For example, if we have SEW=32, LMUL=1, VLEN=128 and doing vector FP arith instruction - it should increment the RVV.ELEMENT.FP_SINGLE counter by 4. Mask should not be taken into account - so in the previous example if half of the lanes are masked the RVV.ELEMENT.FP_SINGLE counter will still be incremented by 4. For multiply-add instructions each element operation should increment counter by 2 to account for both multiplication and addition." - }, - { - "EventName": "RVV.ELEMENT.UNMASKED.FP_DOUBLE.SPEC", - "EventCode": "0x0", - "BriefDescription": "Number of double-precision floating point element operation executed", - "PublicDescription": "Number of double-precision floating point element operation executed. For example, if we have SEW=64, LMUL=1, VLEN=128 and doing vector FP arith instruction - it should increment the RVV.ELEMENT.UNMASKED.FP_DOUBLE counter by 2. Masked-out elements should not increment the counter - so in the previous example if half of the lanes are masked the RVV.ELEMENT.UNMASKED.FP_DOUBLE counter will be incremented by 1. For multiply-add instructions each element operation should increment counter by 2 to account for both multiplication and addition." - }, - { - "EventName": "RVV.ELEMENT.FP_DOUBLE.SPEC", - "EventCode": "0x0", - "BriefDescription": "Number of double-precision floating point element operation executed not taking into account masking", - "PublicDescription": "Number of double-precision floating point element operation executed. For example, if we have SEW=64, LMUL=1, VLEN=128 and doing vector FP arith instruction - it should increment the RVV.ELEMENT.FP_DOUBLE counter by 2. Mask should not be taken into account - so in the previous example if half of the lanes are masked the RVV.ELEMENT.FP_DOUBLE counter will still be incremented by 2. For multiply-add instructions each element operation should increment counter by 2 to account for both multiplication and addition." - } -]