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Add events and metrics in the form of perf JSON files
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@bcstrongx
bcstrongx authored Sep 26, 2024
2 parents a54b7e4 + 858f63d commit 0f04ac0
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2 changes: 1 addition & 1 deletion Makefile
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Expand Up @@ -19,7 +19,7 @@ DOCKER_RUN := docker run --rm -v ${PWD}:/build -w /build \
riscvintl/riscv-docs-base-container-image:latest

HEADER_SOURCE := header.adoc
PDF_RESULT := spec-sample.pdf
PDF_RESULT := riscv-perf-events-latest.pdf

ASCIIDOCTOR_PDF := asciidoctor-pdf
OPTIONS := --trace \
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26 changes: 26 additions & 0 deletions adoc_event_tables/cache_retired.adoc
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.CACHE group events
[width="100%",cols="30%,70%",options="header",]
|===
|Name |Description
|CACHE.L1D.LOAD.ACCESS.RET |Retired load instruction which accessed L1D cache
|CACHE.L1D.LOAD.MISS.RET |Retired load instruction which missed L1D cache
|CACHE.L1D.LOAD.HIT.RET |Retired load instruction which hit L1D cache
|CACHE.L1D.LOAD.MERGE.RET |Retired load instruction which hit L1D cache with data not yet in cache but was already requested by preceding miss
|CACHE.L1D.STORE.ACCESS.RET |Retired store instruction which accessed L1D cache
|CACHE.L1D.STORE.MISS.RET |Retired store instruction which missed L1D cache
|CACHE.L1D.STORE.HIT.RET |Retired store instruction which hit L1D cache
|CACHE.L1D.STORE.MERGE.RET |Retired store instruction which hit L1D cache with data not yet in cache but was already requested by preceding miss
|CACHE.L1I.MISS.RET |Retired instruction with L1 Instruction cache miss on fetching
|CACHE.L2.LOAD.ACCESS.RET |Retired load instruction which got data from L2 or from some next level in memory hierarchy - L3 cache, local mmemory, remote cache, remote memory, etc.
|CACHE.L2.LOAD.MISS.RET |Retired load instruction which got data from some next level (relative to L2) in memory hierarchy - L3 cache, local mmemory, remote cache, remote memory, etc.
|CACHE.L2.LOAD.HIT.RET |Retired load instruction which got data from L2 cache
|CACHE.L2.LOAD.MERGE.RET |Retired load instruction which hit L2 cache with data not yet in cache but was already requested by preceding miss
|CACHE.L3.LOAD.ACCESS.RET |Retired load instruction which got data from L3 cache or from some next level in memory hierarchy - local mmemory, remote cache, remote memory, etc.
|CACHE.L3.LOAD.MISS.RET |Retired load instruction which got data from some next level (relative to L3) in memory hierarchy - local mmemory, remote cache, remote memory, etc.
|CACHE.L3.LOAD.HIT.RET |Retired load instruction which got data from L3 cache
|CACHE.L3.LOAD.MERGE.RET |Retired load instruction which hit L3 cache with data not yet in cache but was already requested by preceding miss
|CACHE.LOAD.LOCAL_MEMORY.RET |Retired load instruction which got data from local memory.
|CACHE.LOAD.REMOTE_MEMORY.RET |Retired load instruction which got data from remote memory (memory attached to remote socket).
|CACHE.LOAD.REMOTE_CACHE.RET |Retired load instruction which got data from remote cache (cache on remote socket).
|===

16 changes: 16 additions & 0 deletions adoc_event_tables/cache_retired_metrics.adoc
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.CACHE group metrics
[width="100%",cols="25%,40%,35%",options="header",]
|===
|Name |Description |Formula
|CACHE.L1D.LOAD.RET.MPKI |The rate of retired L1 data load cache misses per kilo instructions retired |CACHE.L1D.LOAD.MISS.RET / INST.RET * 1000
|CACHE.L1D.LOAD.MISS.RET.RATE |The ratio of retired L1D cache load misses to the total number of retired L1D load accesses |CACHE.L1D.LOAD.MISS.RET / CACHE.L1D.LOAD.ACCESS.RET
|CACHE.L1D.LOAD.MERGE.RET.PKI |The rate of retired L1 data load cache misses which merged with previous cache miss per kilo instructions retired |CACHE.L1D.LOAD.MERGE.RET / INST.RET * 1000
|CACHE.L1I.RET.MPKI |The rate of retired instructions with L1 instruction cache misses per kilo instructions retired |CACHE.L1I.MISS.RET / INST.RET * 1000
|CACHE.L1D.STORE.RET.MPKI |The rate of retired L1 data store cache misses per kilo instructions retired |CACHE.L1D.STORE.MISS.RET / INST.RET * 1000
|CACHE.L1D.STORE.MISS.RET.RATE |The ratio of retired L1D cache store misses to the total number of retired L1D store accesses |CACHE.L1D.STORE.MISS.RET / CACHE.L1D.STORE.ACCESS.RET
|CACHE.L2.LOAD.RET.MPKI |The rate of retired L2 data load cache misses per kilo instructions retired |CACHE.L2.LOAD.MISS.RET / INST.RET * 1000
|CACHE.L2.LOAD.MISS.RET.RATE |The ratio of retired L2 cache load misses to the total number of retired L2 load accesses |CACHE.L2.LOAD.MISS.RET / CACHE.L2.LOAD.ACCESS.RET
|CACHE.L3.LOAD.RET.MPKI |The rate of retired L3 data load cache misses per kilo instructions retired |CACHE.L3.LOAD.MISS.RET / INST.RET * 1000
|CACHE.L3.LOAD.MISS.RET.RATE |The ratio of retired L3 cache load misses to the total number of retired L3 load accesses |CACHE.L3.LOAD.MISS.RET / CACHE.L3.LOAD.ACCESS.RET
|===

59 changes: 59 additions & 0 deletions adoc_event_tables/cache_spec.adoc
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.CACHE group events
[width="100%",cols="30%,70%",options="header",]
|===
|Name |Description
|CACHE.L1D.LOAD.ACCESS.SPEC |L1D cache accesses for load instructions. Speculatively executed instructions are also taken into account.
|CACHE.L1D.LOAD.MISS.SPEC |L1D cache misses for load instructions. Speculatively executed instructions are also taken into account.
|CACHE.L1D.LOAD.HIT.SPEC |L1D cache hits for load instructions. Speculatively executed instructions are also taken into account.
|CACHE.L1D.LOAD.MERGE.SPEC |L1D cache hits for load instructions where data is not yet in cache but was already requested by preceding miss. Speculatively executed instructions are also taken into account.
|CACHE.L1D.LOAD.MISS_OUTSTANDING.CYCLES |Cycles while at least one load L1 data cache miss in progress.
|CACHE.L1D.STORE.ACCESS.SPEC |L1D cache accesses for store instructions. Speculatively executed instructions are also taken into account.
|CACHE.L1D.STORE.MISS.SPEC |L1D cache misses for store instructions. Speculatively executed instructions are also taken into account.
|CACHE.L1D.STORE.HIT.SPEC |L1D cache hits for store instructions. Speculatively executed instructions are also taken into account.
|CACHE.L1D.STORE.MERGE.SPEC |L1D cache hits for store instructions where data is not yet in cache but was already requested by preceding miss. Speculatively executed instructions are also taken into account.
|CACHE.L1D.PREF.ISSUED |Prefetcher requests issued by L1D to next level cache.
|CACHE.L1D.PREF.UNUSED |Number of cachelines brought into L1D by prefetcher and evicted without being accessed even once.
|CACHE.L1D.WB |Writebacks from L1D to next level cache or memory.
|CACHE.L1I.ACCESS.SPEC |L1I cache accesses.
|CACHE.L1I.MISS.SPEC |L1I cache misses.
|CACHE.L1I.HIT.SPEC |L1I cache hits.
|CACHE.L1I.MERGE.SPEC |L1I cache hits data is not yet in cache but was already requested by preceding miss.
|CACHE.L1I.MISS_OUTSTANDING.CYCLES |Cycles with L1 Instruction cache miss in progress.
|CACHE.L2.LOAD.ACCESS.SPEC |L2 cache accesses initiated by load instructions. Speculatively executed instructions are also taken into account.
|CACHE.L2.LOAD.MISS.SPEC |L2 cache misses initiated by load instructions. Speculatively executed instructions are also taken into account.
|CACHE.L2.LOAD.HIT.SPEC |L2 cache hits initiated by load instructions. Speculatively executed instructions are also taken into account.
|CACHE.L2.LOAD.MERGE.SPEC |L2 cache hits initiated by load instructions where data is not yet in cache but was already requested by preceding miss. Speculatively executed instructions are also taken into account.
|CACHE.L2.LOAD.MISS_OUTSTANDING.CYCLES |Cycles while at least one load L2 cache miss in progress.
|CACHE.L2.STORE.ACCESS.SPEC |L2 cache accesses initiated by store instructions. Speculatively executed instructions are also taken into account.
|CACHE.L2.STORE.MISS.SPEC |L2 cache misses initiated by store instructions. Speculatively executed instructions are also taken into account.
|CACHE.L2.STORE.HIT.SPEC |L2 cache hits initiated by store instructions. Speculatively executed instructions are also taken into account.
|CACHE.L2.STORE.MERGE.SPEC |L2 cache hits initiated by store instructions where data is not yet in cache but was already requested by preceding miss. Speculatively executed instructions are also taken into account.
|CACHE.L2.STORE.HIT.RFO.SPEC |L2 cache hits for store instructions with the purpose to get exclusive ownership. Speculatively executed instructions are also taken into account.
|CACHE.L2.PREF.ISSUED |Prefetcher requests issued by L2 to next level cache or memory.
|CACHE.L2.PREF.ACCESS |L2 cache accesses caused by prefetcher.
|CACHE.L2.PREF.HIT |L2 cache hits caused by prefetcher.
|CACHE.L2.PREF.MISS |L2 cache misses caused by prefetcher.
|CACHE.L2.PREF.MERGE |L2 cache hits caused by prefetcher where data is not yet in cache but was already requested by preceding miss.
|CACHE.L2.PREF.UNUSED |Number of cachelines brought into L2 by prefetcher and evicted without being accessed even once.
|CACHE.L2.WB |Writebacks to next level cache or memory.
|CACHE.SNOOP.LOCAL_REQ_REMOTE_HITM.SPEC |Private cache misses where data was found in another core cache in modified state. This event can be used to accout for contested accesses cases where several cores read/write the same cachelines.
|CACHE.SNOOP.REMOTE_REQ_LOCAL_HITM |Snoop requests which found cacheline in the core cache in modified state. This event can be used to accout for contested accesses cases where several cores read/write the same cachelines.
|CACHE.L3.LOAD.ACCESS.SPEC |L3 cache accesses for load instructions. Speculatively executed instructions are also taken into account.
|CACHE.L3.LOAD.MISS.SPEC |L3 cache misses for load instructions. Speculatively executed instructions are also taken into account.
|CACHE.L3.LOAD.HIT.SPEC |L3 cache hits for load instructions. Speculatively executed instructions are also taken into account.
|CACHE.L3.LOAD.MERGE.SPEC |L3 cache hits for load instructions where data is not yet in cache but was already requested by preceding miss. Speculatively executed instructions are also taken into account.
|CACHE.L3.LOAD.MISS_OUTSTANDING.CYCLES.SPEC |Cycles while at least one load L3 cache miss in progress.
|CACHE.L3.STORE.ACCESS.SPEC |L3 cache accesses for store instructions. Speculatively executed instructions are also taken into account.
|CACHE.L3.STORE.MISS.SPEC |L3 cache misses for store instructions. Speculatively executed instructions are also taken into account.
|CACHE.L3.STORE.HIT.SPEC |L3 cache hits for store instructions. Speculatively executed instructions are also taken into account.
|CACHE.L3.STORE.MERGE.SPEC |L3 cache hits for store instructions where data is not yet in cache but was already requested by preceding miss. Speculatively executed instructions are also taken into account.
|CACHE.L3.STORE.HIT.RFO.SPEC |L3 cache hits for store instructions with the purpose to get exclusive ownership. Speculatively executed instructions are also taken into account.
|CACHE.L3.PREF.ISSUED |Prefetcher requests issued by L3 to next level cache or memory.
|CACHE.L3.PREF.ACCESS |L3 cache accesses caused by prefetcher.
|CACHE.L3.PREF.HIT |L3 cache hits caused by prefetcher.
|CACHE.L3.PREF.MISS |L3 cache misses caused by prefetcher.
|CACHE.L3.PREF.MERGE |L3 cache hits caused by prefetcher where data is not yet in cache but was already requested by preceding miss.
|CACHE.L3.PREF.UNUSED |Number of cachelines brought into L3 by prefetcher and evicted without being accessed even once.
|CACHE.L3.WB |Writebacks to next level cache or memory.
|===

32 changes: 32 additions & 0 deletions adoc_event_tables/cache_spec_metrics.adoc
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.CACHE group metrics
[width="100%",cols="25%,40%,35%",options="header",]
|===
|Name |Description |Formula
|CACHE.L1D.LOAD.SPEC.MPKI |The rate of speculative L1 data cache misses caused by data loads per kilo instructions retired |CACHE.L1D.LOAD.MISS.SPEC / INST.RET * 1000
|CACHE.L1D.LOAD.MISS.SPEC.RATE |The ratio of speculative L1D cache misses to the total number of L1D accesses caused by data loads |CACHE.L1D.LOAD.MISS.SPEC / CACHE.L1D.LOAD.ACCESS.SPEC
|CACHE.L1D.LOAD.MERGE.SPEC.PKI |The rate of speculative L1 data cache accesses which merged with previous cache miss per kilo instructions retired |CACHE.L1D.LOAD.MERGE.SPEC / INST.RET * 1000
|CACHE.L1D.STORE.SPEC.MPKI |The rate of speculative L1 data cache misses caused by data stores per kilo instructions retired |CACHE.L1D.STORE.MISS.SPEC / INST.RET * 1000
|CACHE.L1D.STORE.MISS.SPEC.RATE |The ratio of speculative L1D cache misses to the total number of L1D accesses caused by data stores |CACHE.L1D.STORE.MISS.SPEC / CACHE.L1D.STORE.ACCESS.SPEC
|CACHE.L1D.PREF.ISSUED.PKI |The rate of prefetcher requests issued by L1D to next level cache per kilo instructions retired |CACHE.L1D.PREF.ISSUED / INST.RET * 1000
|CACHE.L1D.PREF.UNUSED.RATE |The ratio of unused cachelines brought into L1D by prefetcher to the total number of prefetcher requests issued by L1D |CACHE.L1D.PREF.UNUSED / CACHE.L1D.PREF.ISSUED
|CACHE.L1I.SPEC.MPKI |The rate of L1 instruction cache misses per kilo instructions retired |CACHE.L1I.MISS.SPEC / INST.RET * 1000
|CACHE.L1I.MISS.SPEC.RATE |The ratio of L1 instruction cache misses to the total number of L1I accesses |CACHE.L1I.MISS.SPEC / CACHE.L1I.ACCESS.SPEC
|CACHE.L1I.MERGE.SPEC.PKI |The rate of L1 instruction cache accesses which merged with previous cache miss per kilo instructions retired |CACHE.L1I.MERGE.SPEC / INST.RET * 1000
|CACHE.L1I.MISS.IMPACT |The approximate ratio of cycles lost due to L1I misses |CACHE.L1I.MISS_OUTSTANDING.CYCLES / CYCLES.HART
|CACHE.L2.LOAD.SPEC.MPKI |The rate of speculative L2 cache misses caused by data loads per kilo instructions retired |CACHE.L2.LOAD.MISS.SPEC / INST.RET * 1000
|CACHE.L2.LOAD.MISS.SPEC.RATE |The ratio of speculative L2 cache misses to the total number of L2 accesses caused by data loads |CACHE.L2.LOAD.MISS.SPEC / CACHE.L2.LOAD.ACCESS.SPEC
|CACHE.L2.STORE.SPEC.MPKI |The rate of speculative L2 cache misses caused by data stores per kilo instructions retired |CACHE.L2.STORE.MISS.SPEC / INST.RET * 1000
|CACHE.L2.STORE.MISS.SPEC.RATE |The ratio of speculative L2 cache misses to the total number of L2 accesses caused by data stores |CACHE.L2.STORE.MISS.SPEC / CACHE.L2.STORE.ACCESS.SPEC
|CACHE.L2.STORE.HIT.RFO.SPEC.PKI |The rate of L2 cache hits for store instructions with the purpose to get exclusive ownership per kilo instructions retired |CACHE.L2.STORE.HIT.RFO.SPEC / INST.RET * 1000
|CACHE.L2.PREF.ISSUED.PKI |The rate of prefetcher requests issued by L2 to next level cache per kilo instructions retired |CACHE.L2.PREF.ISSUED / INST.RET * 1000
|CACHE.L2.PREF.MPKI |The rate of L2 cache misses caused by prefetcher per kilo instructions retired |CACHE.L2.PREF.MISS / INST.RET * 1000
|CACHE.L2.PREF.UNUSED.RATE |The ratio of unused cachelines brought into L2 by prefetcher to the total number of prefetcher requests issued by L2 |CACHE.L2.PREF.UNUSED / CACHE.L2.PF.ISSUED
|CACHE.L3.LOAD.SPEC.MPKI |The rate of speculative L3 cache misses caused by data loads per kilo instructions retired |CACHE.L3.LOAD.MISS.SPEC / INST.RET * 1000
|CACHE.L3.LOAD.MISS.SPEC.RATE |The ratio of speculative L3 cache misses to the total number of L3 accesses caused by data loads |CACHE.L3.LOAD.MISS.SPEC / CACHE.L3.LOAD.ACCESS.SPEC
|CACHE.L3.STORE.SPEC.MPKI |The rate of speculative L3 cache misses caused by data stores per kilo instructions retired |CACHE.L3.STORE.MISS.SPEC / INST.RET * 1000
|CACHE.L3.STORE.MISS.SPEC.RATE |The ratio of speculative L3 cache misses to the total number of L3 accesses caused by data stores |CACHE.L3.STORE.MISS.SPEC / CACHE.L3.STORE.ACCESS.SPEC
|CACHE.L3.PREF.ISSUED.PKI |The rate of prefetcher requests issued by L3 to next level cache per kilo instructions retired |CACHE.L3.PREF.ISSUED / INST.RET * 1000
|CACHE.L3.PREF.MPKI |The rate of L3 cache misses caused by prefetcher per kilo instructions retired |CACHE.L3.PREF.MISS / INST.RET * 1000
|CACHE.L3.PREF.UNUSED.RATE |The ratio of unused cachelines brought into L3 by prefetcher to the total number of prefetcher requests issued by L3 |CACHE.L3.PREF.UNUSED / CACHE.L3.PREF.ISSUED
|===

7 changes: 7 additions & 0 deletions adoc_event_tables/general.adoc
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.GEN group events
[width="100%",cols="30%,70%",options="header",]
|===
|Name |Description
|CYCLES.HART |Cycles when the hart is not in halt state. The cycles are counted with real (potentially variable) frequency the hart is working at
|===

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