From 5182d9fe2987aa44f7b3e067b98ce917fa67468b Mon Sep 17 00:00:00 2001
From: Tom Aird <thomas.aird@codasip.com>
Date: Fri, 14 Feb 2025 15:03:59 +0000
Subject: [PATCH] Minor wording fix for mtvecc vectored check

---
 src/riscv-integration.adoc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/riscv-integration.adoc b/src/riscv-integration.adoc
index 8e7965e8..ad05cf2a 100644
--- a/src/riscv-integration.adoc
+++ b/src/riscv-integration.adoc
@@ -513,7 +513,7 @@ either check fails.
 
 Additionally, when MODE=Vectored the capability has its tag bit cleared if the
 capability address + 4 x HICAUSE is not within the <<section_cap_representable_check>>.
-HICAUSE is the largest exception cause value that the implementation can write
+HICAUSE is the largest interrupt cause value that the implementation can write
 to <<mcause>> or <<scause>>/<<vscause>> when an interrupt is taken.
 
 NOTE: When MODE=Vectored, it is only required that address + 4 x HICAUSE is