From ae6e8bd5bdc01e9c37a457c9a496cbc854a670c5 Mon Sep 17 00:00:00 2001 From: Anup Patel Date: Fri, 8 Nov 2024 10:54:28 +0530 Subject: [PATCH] Add non-normative text about how semihosting sequence was chosen Based on public review feedback, add non-normative text about how semihosting instruction sequence was chosen. Signed-off-by: Anup Patel --- src/bibliography.bib | 5 +++++ src/binary-interface.adoc | 9 +++++++++ 2 files changed, 14 insertions(+) diff --git a/src/bibliography.bib b/src/bibliography.bib index 490439c..1b23382 100644 --- a/src/bibliography.bib +++ b/src/bibliography.bib @@ -3,3 +3,8 @@ @electronic{ARMSemihostingRef url = {https://github.com/ARM-software/abi-aa/releases/download/2023Q3/semihosting.pdf}, year = {2023} } +@electronic{RISCVUnprivRef, + title = {The RISC-V Instruction Set Manual Volume I: Unprivileged Architecture}, + url = {https://github.com/riscv/riscv-isa-manual/releases}, + year = {2024} +} diff --git a/src/binary-interface.adoc b/src/binary-interface.adoc index 1fac05c..3f857f6 100644 --- a/src/binary-interface.adoc +++ b/src/binary-interface.adoc @@ -27,6 +27,15 @@ enabled for the semihosting caller then the semihosting instruction sequence and data passed via memory must be paged in else the behavior of the semihosting call is UNSPECIFIED. +NOTE: The `SLLI`, `EBREAK`, and `SRAI` instructions are part of the ratified +RV32E, RV32I, RV64E and RV64I (aka Base Integer Instruction Set) specifications +cite:[RISCVUnprivRef] hence these instructions are present on almost all RISC-V +platforms. + +NOTE: The `SLLI` and `SRAI` instruction based NOPs which serve as semihosting +marker have been randomly selected from the Base Integer Instruction Set since +these are designated for custom use and unlikely to appear in real life code. + === Semihosting Parameters The type of semihosting operation and its parameters are specified using