add Quality of Service (QoS) Identifiers extension

iommu_ref_model/libiommu/include/iommu_data_structures.h

@@ -144,7 +144,21 @@ typedef union {
         // `Bare`.
         uint64_t reserved0:12;
         uint64_t PSCID:20;
-        uint64_t reserved1:32;
+        uint64_t reserved1:8;
+        // The RCID and MCID fields are added by the QoS ID extension. If
+        // capabilities.QOSID is 0, these bits are reserved and must be set to 0.
+        // IOMMU-initiated requests for accessing the following data structures
+        // use the value configured in the RCID and MCID fields of DC.ta.
+        // - Process directory table (PDT)
+        // - Second-stage page table
+        // - First-stage page table
+        // - MSI page table
+        // - Memory-resident interrupt file (MRIF)
+        // The RCID and MCID configured in DC.ta are provided to the IO bridge on
+        // successful address translations. The IO bridge should associate these QoS IDs
+        // with device-initiated requests.
+        uint64_t rcid:12;
+        uint64_t mcid:12;
     };
     uint64_t raw;
 } ta_t;

iommu_ref_model/libiommu/include/iommu_ref_api.h

@@ -5,9 +5,14 @@
 #ifndef __IOMMU_REF_API_H__
 #define __IOMMU_REF_API_H__
 
-extern uint8_t read_memory(uint64_t addr, uint8_t size, char *data);
-extern uint8_t read_memory_for_AMO(uint64_t address, uint8_t size, char *data);
-extern uint8_t write_memory(char *data, uint64_t address, uint32_t size);
+extern uint8_t read_memory(uint64_t addr, uint8_t size, char *data,
+                           uint32_t rcid, uint32_t mcid);
+extern uint8_t read_memory_for_AMO(uint64_t address, uint8_t size, char *data,
+                                   uint32_t rcid, uint32_t mcid);
+extern uint8_t write_memory(char *data, uint64_t address, uint32_t size,
+                            uint32_t rcid, uint32_t mcid);
+extern uint8_t read_memory_test(uint64_t addr, uint8_t size, char *data);
+extern uint8_t write_memory_test(char *data, uint64_t address, uint32_t size);
 
 extern uint64_t read_register(uint16_t offset, uint8_t num_bytes);
 extern void write_register(uint16_t offset, uint8_t num_bytes, uint64_t data);

iommu_ref_model/libiommu/include/iommu_registers.h

@@ -74,7 +74,8 @@ typedef union {
         uint64_t pd8     : 1;      // One level PDT with 8-bit process_id supported.
         uint64_t pd17    : 1;      // Two level PDT with 17-bit process_id supported.
         uint64_t pd20    : 1;      // Three level PDT with 20-bit process_id supported.
-        uint64_t rsvd3   : 15;     // Reserved for standard use
+        uint64_t qosid   : 1;      // Associating QoS IDs with requests is supported.
+        uint64_t rsvd3   : 14;     // Reserved for standard use
         uint64_t custom  : 8;      // _Designated for custom use_
     };
     uint64_t raw;
@@ -580,6 +581,26 @@ typedef struct {
     uint32_t msi_data;
     msi_vec_ctrl_t msi_vec_ctrl;
 } msi_cfg_tbl_t;
+
+// IOMMU-initiated requests for accessing the following data structures use
+// the value programmed in the RCID and MCID fields of the iommu_qosid register.
+//  - Device directory table (DDT)
+//  - Fault queue (FQ)
+//  - Command queue (CQ)
+//  - Page-request queue (PQ)
+//  - IOMMU-initiated MSI (Message-signaled interrupts)
+// When ddtp.iommu_mode == Bare, all device-originated requests are associated
+// with the QoS IDs configured in the iommu_qosid register.
+typedef union {
+    struct {
+        uint32_t rcid:12;              // RCID for IOMMU-initiated requests.
+        uint32_t rsvd1:4;
+        uint32_t mcid:12;              // MCID for IOMMU-initiated requests.
+        uint32_t rsvd2:4;
+    };
+    uint32_t raw;
+} iommu_qosid_t;
+
 // The IOMMU provides a memory-mapped programming interface. The memory-mapped
 // registers of each IOMMU are located within a naturally aligned 4-KiB region
 // (a page) of physical address space.
@@ -613,9 +634,10 @@ typedef union {                        // |Ofst|Name            |Size|Descriptio
         tr_req_iova_t  tr_req_iova;    // |600 |`tr_req_iova`   |8   |Translation-request IOVA
         tr_req_ctrl_t  tr_req_ctrl;    // |608 |`tr_req_ctrl`   |8   |Translation-request control
         tr_response_t  tr_response;    // |616 |`tr_response`   |8   |Translation-request response
-        uint8_t        reserved0[58];  // |624 |Reserved        |82  |Reserved for future use (`WPRI`)
-        uint8_t        custom1[78];    // |682 |_custom_        |78  |Designated for custom use (`WARL`)_
-        icvec_t        icvec;          // |760 |`icvec`         |4   |Interrupt cause to vector register
+        iommu_qosid_t  iommu_qosid;    // |624 |`iommu_qosid`   |4   |IOMMU QoS ID
+        uint8_t        reserved0[60];  // |628 |Reserved        |60  |Reserved for future use (`WPRI`)
+        uint8_t        custom1[72];    // |682 |_custom_        |72  |Designated for custom use (`WARL`)_
+        icvec_t        icvec;          // |760 |`icvec`         |8   |Interrupt cause to vector register
         msi_cfg_tbl_t  msi_cfg_tbl[16];// |768 |`msi_cfg_tbl`   |256 |MSI Configuration Table
         uint8_t        reserved1[3072];// |1024|Reserved        |3072|Reserved for future use (`WPRI`)
     };
@@ -712,8 +734,9 @@ typedef union {                        // |Ofst|Name            |Size|Descriptio
 #define TR_REQ_IOVA_OFFSET   600
 #define TR_REQ_CTRL_OFFSET   608
 #define TR_RESPONSE_OFFSET   616
-#define RESERVED_OFFSET      624
-#define CUSTOM_OFFSET        682
+#define IOMMU_QOSID_OFFSET   624
+#define RESERVED_OFFSET      628
+#define CUSTOM_OFFSET        688
 #define ICVEC_OFFSET         760
 
 #define MSI_ADDR_0_OFFSET      768 + 0 * 16 + 0
@@ -795,6 +818,7 @@ extern uint64_t g_sv57_bare_pg_sz;
 extern uint64_t g_sv48_bare_pg_sz;
 extern uint64_t g_sv39_bare_pg_sz;
 extern uint64_t g_sv32_bare_pg_sz;
+extern uint32_t g_iommu_qosid_mask;
 
 extern void process_commands(void);
 #endif //_IOMMU_REGS_H_

iommu_ref_model/libiommu/include/iommu_translate.h

@@ -98,21 +98,22 @@ two_stage_address_translation(
     iosatp_t iosatp, uint8_t priv, uint8_t SUM, uint8_t SADE,
     uint8_t GV, uint32_t GSCID, iohgatp_t iohgatp, uint8_t GADE, uint8_t SXL,
     uint32_t *cause, uint64_t *iotval2, uint64_t *pa,
-    uint64_t *page_sz, pte_t *vs_pte);
+    uint64_t *page_sz, pte_t *vs_pte, uint32_t rcid, uint32_t mcid);
 
 extern uint8_t
 second_stage_address_translation(
     uint64_t gpa, uint8_t check_access_perms, uint32_t DID,
     uint8_t is_read, uint8_t is_write, uint8_t is_exec, uint8_t is_implicit,
     uint8_t PV, uint32_t PID, uint8_t PSCV, uint32_t PSCID,
     uint8_t GV, uint32_t GSCID, iohgatp_t iohgatp, uint8_t GADE, uint8_t SADE, uint8_t SXL,
-    uint64_t *pa, uint64_t *gst_page_sz, gpte_t *gpte);
+    uint64_t *pa, uint64_t *gst_page_sz, gpte_t *gpte, uint32_t rcid, uint32_t mcid);
 
 extern uint8_t
 msi_address_translation(
     uint64_t gpa, uint8_t is_exec, device_context_t *DC,
     uint8_t *is_msi, uint8_t *is_mrif, uint32_t *mrif_nid, uint64_t *dest_mrif_addr,
     uint32_t *cause, uint64_t *iotval2, uint64_t *pa,
-    uint64_t *page_sz, gpte_t *g_pte, uint8_t check_access_perms );
+    uint64_t *page_sz, gpte_t *g_pte, uint8_t check_access_perms, uint32_t rcid,
+    uint32_t mcid);
 
 #endif // __IOMMU_TRANSLATE_H__

iommu_ref_model/libiommu/src/iommu_ats.c

@@ -277,7 +277,9 @@ handle_page_request(
     prec.reserved0= 0;
     prec.reserved1= 0;
     prec_addr = ((pqb * PAGESIZE) | (pqt * PQ_ENTRY_SZ));
-    status = write_memory((char *)&prec, prec_addr, 16);
+    status = write_memory((char *)&prec, prec_addr, 16,
+                          g_reg_file.iommu_qosid.rcid,
+                          g_reg_file.iommu_qosid.mcid);
     if ( (status & ACCESS_FAULT) || (status & DATA_CORRUPTION) ) {
         g_reg_file.pqcsr.pqmf = 1;
         generate_interrupt(PAGE_QUEUE);

iommu_ref_model/libiommu/src/iommu_command_queue.c

@@ -64,7 +64,8 @@ process_commands(
         return;
 
     a = g_reg_file.cqb.ppn * PAGESIZE | (g_reg_file.cqh.index * CQ_ENTRY_SZ);
-    status = read_memory(a, CQ_ENTRY_SZ, (char *)&command);
+    status = read_memory(a, CQ_ENTRY_SZ, (char *)&command,
+                         g_reg_file.iommu_qosid.rcid, g_reg_file.iommu_qosid.mcid);
     if ( status != 0 ) {
         // If command-queue access leads to a memory fault then the
         // command-queue-memory-fault bit is set to 1 and the command
@@ -487,7 +488,8 @@ do_iofence_c(
     // If AV=1, the IOMMU writes DATA to memory at a 4-byte aligned address ADDR[63:2] * 4 as
     // a 4-byte store.
     if ( AV == 1 ) {
-        status = write_memory((char *)&DATA, ADDR, 4);
+        status = write_memory((char *)&DATA, ADDR, 4, g_reg_file.iommu_qosid.rcid,
+                              g_reg_file.iommu_qosid.mcid);
         if ( status != 0 ) {
             if ( g_reg_file.cqcsr.cqmf == 0 ) {
                 g_reg_file.cqcsr.cqmf = 1;

iommu_ref_model/libiommu/src/iommu_device_context.c

@@ -108,7 +108,9 @@ locate_device_context(
     // 3. Let `ddte` be value of eight bytes at address `a + DDI[i] x 8`. If accessing
     //    `ddte` violates a PMA or PMP check, then stop and report "DDT entry load
     //     access fault" (cause = 257).
-    status = read_memory((a + (DDI[i] * 8)), 8, (char *)&ddte.raw);
+    status = read_memory((a + (DDI[i] * 8)), 8, (char *)&ddte.raw,
+                         g_reg_file.iommu_qosid.rcid,
+                         g_reg_file.iommu_qosid.mcid);
     if ( status & ACCESS_FAULT ) {
         *cause = 257;     // DDT entry load access fault
         return 1;
@@ -153,7 +155,9 @@ locate_device_context(
     //    (cause = 268). This fault is detected if the IOMMU supports the RAS capability
     //    (`capabilities.RAS == 1`).
     DC_SIZE = ( g_reg_file.capabilities.msi_flat == 1 ) ? EXT_FORMAT_DC_SIZE : BASE_FORMAT_DC_SIZE;
-    status = read_memory((a + (DDI[0] * DC_SIZE)), DC_SIZE, (char *)DC);
+    status = read_memory((a + (DDI[0] * DC_SIZE)), DC_SIZE, (char *)DC,
+                         g_reg_file.iommu_qosid.rcid,
+                         g_reg_file.iommu_qosid.mcid);
     if ( status & ACCESS_FAULT ) {
         *cause = 257;     // DDT entry load access fault
         return 1;
@@ -184,6 +188,8 @@ do_device_context_configuration_checks(
     // misconfigured" (cause = 259).
 
     // 1. If any bits or encoding that are reserved for future standard use are set.
+    //    The RCID and MCID fields are added by the QoS ID extension. If capabilities.QOSID
+    //    is 0, these bits are reserved and must be set to 0.
     if ( ((g_reg_file.capabilities.msi_flat == 1) && (DC->reserved != 0)) ||
          ((g_reg_file.capabilities.msi_flat == 1) && (DC->msiptp.reserved != 0)) ||
          ((g_reg_file.capabilities.msi_flat == 1) && (DC->msi_addr_mask.reserved != 0)) ||
@@ -193,7 +199,8 @@ do_device_context_configuration_checks(
          (DC->fsc.pdtp.reserved != 0 && DC->tc.PDTV == 1) ||
          (DC->fsc.iosatp.reserved != 0 && DC->tc.PDTV == 0) ||
          (DC->ta.reserved0 != 0) ||
-         (DC->ta.reserved1 != 0) ) {
+         (DC->ta.reserved1 != 0) ||
+         (g_reg_file.capabilities.qosid == 0 && (DC->ta.rcid != 0 || DC->ta.mcid != 0)) ) {
         return 1;
     }
     // 2. `capabilities.ATS` is 0 and `DC.tc.EN_ATS`, or `DC.tc.EN_PRI`,
@@ -331,6 +338,7 @@ do_device_context_configuration_checks(
     if ( (g_reg_file.fctl.gxl == 1) && (DC->tc.SXL != 1) ) {
         return 1;
     }
+
     if ( (g_reg_file.fctl.gxl == 0) && (g_gxl_writeable == 0) && (DC->tc.SXL != 0) ) {
         return 1;
     }

iommu_ref_model/libiommu/src/iommu_faults.c

@@ -138,7 +138,8 @@ report_fault(uint16_t cause, uint64_t iotval, uint64_t iotval2, uint8_t TTYP, ui
     // from 0 to 1 or when a new fault record is produced in the fault-queue, fault
     // interrupt pending (fip) bit is set in the fqcsr.
     frec_addr = ((fqb * PAGESIZE) | (fqt * FQ_ENTRY_SZ));
-    status = write_memory((char *)&frec, frec_addr, 32);
+    status = write_memory((char *)&frec, frec_addr, 32,
+                          g_reg_file.iommu_qosid.rcid, g_reg_file.iommu_qosid.mcid);
     if ( (status & ACCESS_FAULT) || (status & DATA_CORRUPTION) ) {
         g_reg_file.fqcsr.fqmf = 1;
     } else {

iommu_ref_model/libiommu/src/iommu_interrupt.c

@@ -10,7 +10,8 @@ static void
 do_msi(
     uint32_t msi_data, uint64_t msi_addr) {
     uint8_t  status;
-    status = write_memory((char *)&msi_data, msi_addr, 4);
+    status = write_memory((char *)&msi_data, msi_addr, 4,
+                          g_reg_file.iommu_qosid.rcid, g_reg_file.iommu_qosid.mcid);
     if ( status & ACCESS_FAULT ) {
         // If an access fault is detected on a MSI write using msi_addr_x,
         // then the IOMMU reports a "IOMMU MSI write access fault" (cause 273) fault,

iommu_ref_model/libiommu/src/iommu_msi_trans.c

@@ -21,7 +21,8 @@ msi_address_translation(
     uint64_t gpa, uint8_t is_exec, device_context_t *DC,
     uint8_t *is_msi, uint8_t *is_mrif, uint32_t *mrif_nid, uint64_t *dest_mrif_addr,
     uint32_t *cause, uint64_t *iotval2, uint64_t *pa,
-    uint64_t *page_sz, gpte_t *g_pte, uint8_t check_access_perms ) {
+    uint64_t *page_sz, gpte_t *g_pte, uint8_t check_access_perms,
+    uint32_t rcid, uint32_t mcid) {
 
     uint64_t A, m, I;
     uint8_t status;
@@ -67,7 +68,7 @@ msi_address_translation(
     // 7. Let `msipte` be the value of sixteen bytes at address `(m | (I x 16))`. If
     //    accessing `msipte` violates a PMA or PMP check, then stop and report
     //    "MSI PTE load access fault" (cause = 261).
-    status = read_memory((m + (I * 16)), 16, (char *)&msipte.raw);
+    status = read_memory((m + (I * 16)), 16, (char *)&msipte.raw, rcid, mcid);
     if ( status & ACCESS_FAULT ) {
         *cause = 261;     // MSI PTE load access fault
         return 1;

iommu_ref_model/libiommu/src/iommu_process_context.c

@@ -87,7 +87,8 @@ locate_process_context(
                            is_exec, is_implicit, 1, process_id, 0, 0,
                            ((DC->iohgatp.MODE == IOHGATP_Bare) ? 0 : 1),
                            DC->iohgatp.GSCID, DC->iohgatp, DC->tc.GADE, DC->tc.SADE,
-                           DC->tc.SXL, &a, &gst_page_sz, &g_pte) ) ) {
+                           DC->tc.SXL, &a, &gst_page_sz, &g_pte, DC->ta.rcid,
+                           DC->ta.mcid) ) ) {
         if ( gst_fault == GST_PAGE_FAULT ) {
             *cause = 21;            // Read guest page fault
             *iotval2 = (a & ~0x3);
@@ -113,7 +114,7 @@ locate_process_context(
     // 4. Let `pdte` be value of eight bytes at address `a + PDI[i] x 8`. If
     //    accessing `pdte` violates a PMA or PMP check, then stop and report
     //    "PDT entry load access fault" (cause = 265).
-    status = read_memory(a, 8, (char *)&pdte.raw);
+    status = read_memory(a, 8, (char *)&pdte.raw, DC->ta.rcid, DC->ta.mcid);
     if ( status & ACCESS_FAULT ) {
         *cause = 265;     // PDT entry load access fault
         return 1;
@@ -153,7 +154,7 @@ locate_process_context(
     //    fault" (cause = 265).If `PC` access detects a data corruption
     //    (a.k.a. poisoned data), then stop and report "PDT data corruption"
     //    (cause = 269).
-    status = read_memory(a, 16, (char *)PC);
+    status = read_memory(a, 16, (char *)PC, DC->ta.rcid, DC->ta.mcid);
     if ( status & ACCESS_FAULT ) {
         *cause = 265;     // PDT entry load access fault
         return 1;

iommu_ref_model/libiommu/src/iommu_reg.c

@@ -25,6 +25,7 @@ uint64_t g_sv57_bare_pg_sz;
 uint64_t g_sv48_bare_pg_sz;
 uint64_t g_sv39_bare_pg_sz;
 uint64_t g_sv32_bare_pg_sz;
+uint32_t g_iommu_qosid_mask;
 
 uint8_t
 is_access_valid(
@@ -726,6 +727,13 @@ write_register(
                 }
             }
             break;
+        case IOMMU_QOSID_OFFSET:
+            // This register is read-only zero if qosid extension is not
+            // supported. The RCID and MCID fields of the register are WARL
+            if ( g_reg_file.capabilities.qosid == 1 ) {
+                g_reg_file.iommu_qosid.raw = data4 & g_iommu_qosid_mask;
+            }
+            break;
         case ICVEC_OFFSET:
             // The performance-monitoring-interrupt-vector
             // (`pmiv`) is the vector number assigned to the
@@ -978,6 +986,7 @@ reset_iommu(uint8_t num_hpm, uint8_t hpmctr_bits, uint16_t eventID_limit,
     for ( i = RESERVED_OFFSET; i < ICVEC_OFFSET; i++ ) {
         g_offset_to_size[i] = 1;
     }
+    g_offset_to_size[IOMMU_QOSID_OFFSET] = 4;
     g_offset_to_size[ICVEC_OFFSET] = 8;
     g_offset_to_size[ICVEC_OFFSET + 4] = 8;
     for ( i = 0; i < 256; i += 16) {

iommu_ref_model/libiommu/src/iommu_second_stage_trans.c

@@ -10,7 +10,8 @@ second_stage_address_translation(
     uint8_t is_read, uint8_t is_write, uint8_t is_exec, uint8_t is_implicit,
     uint8_t PV, uint32_t PID, uint8_t PSCV, uint32_t PSCID,
     uint8_t GV, uint32_t GSCID, iohgatp_t iohgatp, uint8_t GADE, uint8_t SADE,
-    uint8_t SXL, uint64_t *pa, uint64_t *gst_page_sz, gpte_t *gpte) {
+    uint8_t SXL, uint64_t *pa, uint64_t *gst_page_sz, gpte_t *gpte,
+    uint32_t rcid, uint32_t mcid) {
 
     uint16_t vpn[5];
     uint16_t ppn[5];
@@ -117,7 +118,8 @@ second_stage_address_translation(
     //    then an access fault occurs
     if ( a & ~pa_mask ) return GST_ACCESS_FAULT;
     gpte->raw = 0;
-    status = read_memory((a | (vpn[i] * PTESIZE)), PTESIZE, (char *)&gpte->raw);
+    status = read_memory((a | (vpn[i] * PTESIZE)), PTESIZE, (char *)&gpte->raw,
+                         rcid, mcid);
     if ( status & ACCESS_FAULT ) return GST_ACCESS_FAULT;
     if ( status & DATA_CORRUPTION) return GST_DATA_CORRUPTION;
 
@@ -283,7 +285,8 @@ second_stage_address_translation(
     // Count G stage page walks
     count_events(PV, PID, PSCV, PSCID, DID, GV, GSCID, G_PT_WALKS);
     amo_gpte.raw = 0;
-    status = read_memory_for_AMO((a + (vpn[i] * PTESIZE)), PTESIZE, (char *)&amo_gpte.raw);
+    status = read_memory_for_AMO((a + (vpn[i] * PTESIZE)), PTESIZE,
+                                 (char *)&amo_gpte.raw, rcid, mcid);
 
     if ( status & ACCESS_FAULT ) return GST_ACCESS_FAULT;
     if ( status & DATA_CORRUPTION) return GST_DATA_CORRUPTION;
@@ -299,7 +302,8 @@ second_stage_address_translation(
         if ( (is_write == 1 || is_implicit == 1) && (amo_gpte.W == 1) ) amo_gpte.D = 1;
     }
 
-    status = write_memory((char *)&amo_gpte.raw, (a + (vpn[i] * PTESIZE)), PTESIZE);
+    status = write_memory((char *)&amo_gpte.raw, (a + (vpn[i] * PTESIZE)),
+                          PTESIZE, rcid, mcid);
 
     if ( status & ACCESS_FAULT ) return GST_ACCESS_FAULT;
     if ( status & DATA_CORRUPTION) return GST_DATA_CORRUPTION;

iommu_ref_model/libiommu/src/iommu_translate.c

@@ -291,7 +291,8 @@ iommu_translate_iova(
     if ( two_stage_address_translation(req->tr.iova, check_access_perms, DID, is_read, is_write, is_exec,
                                         PV, PID, PSCV, PSCID, iosatp, priv, SUM, DC.tc.SADE,
                                         GV, GSCID, iohgatp, DC.tc.GADE, DC.tc.SXL,
-                                        &cause, &iotval2, &gpa, &page_sz, &vs_pte) )
+                                        &cause, &iotval2, &gpa, &page_sz,
+                                        &vs_pte, DC.ta.rcid, DC.ta.mcid) )
         goto stop_and_report_fault;
 
     // 18. If MSI address translations using MSI page tables is enabled
@@ -301,7 +302,8 @@ iommu_translate_iova(
     //     If a fault is detected by the MSI address translation process then stop and
     //     report the fault else the process continues at step 20.
     if ( msi_address_translation(gpa, is_exec, &DC, &is_msi, &is_mrif, &mrif_nid, &dest_mrif_addr,
-                                 &cause, &iotval2, &pa, &gst_page_sz, &g_pte, check_access_perms) )
+                                 &cause, &iotval2, &pa, &gst_page_sz, &g_pte,
+                                 check_access_perms, DC.ta.rcid, DC.ta.mcid) )
         goto stop_and_report_fault;
 
     // Chapter 5: If the IOVA is determined to be that of a virtual interrupt file
@@ -321,7 +323,8 @@ iommu_translate_iova(
     is_implicit = 0;
     if ( (gst_fault = second_stage_address_translation(gpa, check_access_perms, DID,
                           is_read, is_write, is_exec, is_implicit, PV, PID, PSCV, PSCID, GV, GSCID,
-                          iohgatp, DC.tc.GADE, DC.tc.SADE, DC.tc.SXL, &pa, &gst_page_sz, &g_pte) ) ) {
+                          iohgatp, DC.tc.GADE, DC.tc.SADE, DC.tc.SXL, &pa, &gst_page_sz, &g_pte,
+                          DC.ta.rcid, DC.ta.mcid) ) ) {
         if ( gst_fault == GST_PAGE_FAULT ) goto guest_page_fault;
         if ( gst_fault == GST_ACCESS_FAULT ) goto access_fault;
         goto data_corruption;