diff --git a/iommu_ref_model/libiommu/include/iommu_data_structures.h b/iommu_ref_model/libiommu/include/iommu_data_structures.h index acf4cb3f..4af1e9c3 100644 --- a/iommu_ref_model/libiommu/include/iommu_data_structures.h +++ b/iommu_ref_model/libiommu/include/iommu_data_structures.h @@ -144,7 +144,21 @@ typedef union { // `Bare`. uint64_t reserved0:12; uint64_t PSCID:20; - uint64_t reserved1:32; + uint64_t reserved1:8; + // The RCID and MCID fields are added by the QoS ID extension. If + // capabilities.QOSID is 0, these bits are reserved and must be set to 0. + // IOMMU-initiated requests for accessing the following data structures + // use the value configured in the RCID and MCID fields of DC.ta. + // - Process directory table (PDT) + // - Second-stage page table + // - First-stage page table + // - MSI page table + // - Memory-resident interrupt file (MRIF) + // The RCID and MCID configured in DC.ta are provided to the IO bridge on + // successful address translations. The IO bridge should associate these QoS IDs + // with device-initiated requests. + uint64_t rcid:12; + uint64_t mcid:12; }; uint64_t raw; } ta_t; diff --git a/iommu_ref_model/libiommu/include/iommu_ref_api.h b/iommu_ref_model/libiommu/include/iommu_ref_api.h index 62f4d2ea..fab666f5 100644 --- a/iommu_ref_model/libiommu/include/iommu_ref_api.h +++ b/iommu_ref_model/libiommu/include/iommu_ref_api.h @@ -5,9 +5,14 @@ #ifndef __IOMMU_REF_API_H__ #define __IOMMU_REF_API_H__ -extern uint8_t read_memory(uint64_t addr, uint8_t size, char *data); -extern uint8_t read_memory_for_AMO(uint64_t address, uint8_t size, char *data); -extern uint8_t write_memory(char *data, uint64_t address, uint32_t size); +extern uint8_t read_memory(uint64_t addr, uint8_t size, char *data, + uint32_t rcid, uint32_t mcid); +extern uint8_t read_memory_for_AMO(uint64_t address, uint8_t size, char *data, + uint32_t rcid, uint32_t mcid); +extern uint8_t write_memory(char *data, uint64_t address, uint32_t size, + uint32_t rcid, uint32_t mcid); +extern uint8_t read_memory_test(uint64_t addr, uint8_t size, char *data); +extern uint8_t write_memory_test(char *data, uint64_t address, uint32_t size); extern uint64_t read_register(uint16_t offset, uint8_t num_bytes); extern void write_register(uint16_t offset, uint8_t num_bytes, uint64_t data); diff --git a/iommu_ref_model/libiommu/include/iommu_registers.h b/iommu_ref_model/libiommu/include/iommu_registers.h index 45739cee..b0ebf5d3 100644 --- a/iommu_ref_model/libiommu/include/iommu_registers.h +++ b/iommu_ref_model/libiommu/include/iommu_registers.h @@ -74,7 +74,8 @@ typedef union { uint64_t pd8 : 1; // One level PDT with 8-bit process_id supported. uint64_t pd17 : 1; // Two level PDT with 17-bit process_id supported. uint64_t pd20 : 1; // Three level PDT with 20-bit process_id supported. - uint64_t rsvd3 : 15; // Reserved for standard use + uint64_t qosid : 1; // Associating QoS IDs with requests is supported. + uint64_t rsvd3 : 14; // Reserved for standard use uint64_t custom : 8; // _Designated for custom use_ }; uint64_t raw; @@ -580,6 +581,26 @@ typedef struct { uint32_t msi_data; msi_vec_ctrl_t msi_vec_ctrl; } msi_cfg_tbl_t; + +// IOMMU-initiated requests for accessing the following data structures use +// the value programmed in the RCID and MCID fields of the iommu_qosid register. +// - Device directory table (DDT) +// - Fault queue (FQ) +// - Command queue (CQ) +// - Page-request queue (PQ) +// - IOMMU-initiated MSI (Message-signaled interrupts) +// When ddtp.iommu_mode == Bare, all device-originated requests are associated +// with the QoS IDs configured in the iommu_qosid register. +typedef union { + struct { + uint32_t rcid:12; // RCID for IOMMU-initiated requests. + uint32_t rsvd1:4; + uint32_t mcid:12; // MCID for IOMMU-initiated requests. + uint32_t rsvd2:4; + }; + uint32_t raw; +} iommu_qosid_t; + // The IOMMU provides a memory-mapped programming interface. The memory-mapped // registers of each IOMMU are located within a naturally aligned 4-KiB region // (a page) of physical address space. @@ -613,9 +634,10 @@ typedef union { // |Ofst|Name |Size|Descriptio tr_req_iova_t tr_req_iova; // |600 |`tr_req_iova` |8 |Translation-request IOVA tr_req_ctrl_t tr_req_ctrl; // |608 |`tr_req_ctrl` |8 |Translation-request control tr_response_t tr_response; // |616 |`tr_response` |8 |Translation-request response - uint8_t reserved0[58]; // |624 |Reserved |82 |Reserved for future use (`WPRI`) - uint8_t custom1[78]; // |682 |_custom_ |78 |Designated for custom use (`WARL`)_ - icvec_t icvec; // |760 |`icvec` |4 |Interrupt cause to vector register + iommu_qosid_t iommu_qosid; // |624 |`iommu_qosid` |4 |IOMMU QoS ID + uint8_t reserved0[60]; // |628 |Reserved |60 |Reserved for future use (`WPRI`) + uint8_t custom1[72]; // |682 |_custom_ |72 |Designated for custom use (`WARL`)_ + icvec_t icvec; // |760 |`icvec` |8 |Interrupt cause to vector register msi_cfg_tbl_t msi_cfg_tbl[16];// |768 |`msi_cfg_tbl` |256 |MSI Configuration Table uint8_t reserved1[3072];// |1024|Reserved |3072|Reserved for future use (`WPRI`) }; @@ -712,8 +734,9 @@ typedef union { // |Ofst|Name |Size|Descriptio #define TR_REQ_IOVA_OFFSET 600 #define TR_REQ_CTRL_OFFSET 608 #define TR_RESPONSE_OFFSET 616 -#define RESERVED_OFFSET 624 -#define CUSTOM_OFFSET 682 +#define IOMMU_QOSID_OFFSET 624 +#define RESERVED_OFFSET 628 +#define CUSTOM_OFFSET 688 #define ICVEC_OFFSET 760 #define MSI_ADDR_0_OFFSET 768 + 0 * 16 + 0 @@ -795,6 +818,7 @@ extern uint64_t g_sv57_bare_pg_sz; extern uint64_t g_sv48_bare_pg_sz; extern uint64_t g_sv39_bare_pg_sz; extern uint64_t g_sv32_bare_pg_sz; +extern uint32_t g_iommu_qosid_mask; extern void process_commands(void); #endif //_IOMMU_REGS_H_ diff --git a/iommu_ref_model/libiommu/include/iommu_translate.h b/iommu_ref_model/libiommu/include/iommu_translate.h index d0c36e30..13d0a816 100644 --- a/iommu_ref_model/libiommu/include/iommu_translate.h +++ b/iommu_ref_model/libiommu/include/iommu_translate.h @@ -98,7 +98,7 @@ two_stage_address_translation( iosatp_t iosatp, uint8_t priv, uint8_t SUM, uint8_t SADE, uint8_t GV, uint32_t GSCID, iohgatp_t iohgatp, uint8_t GADE, uint8_t SXL, uint32_t *cause, uint64_t *iotval2, uint64_t *pa, - uint64_t *page_sz, pte_t *vs_pte); + uint64_t *page_sz, pte_t *vs_pte, uint32_t rcid, uint32_t mcid); extern uint8_t second_stage_address_translation( @@ -106,13 +106,14 @@ second_stage_address_translation( uint8_t is_read, uint8_t is_write, uint8_t is_exec, uint8_t is_implicit, uint8_t PV, uint32_t PID, uint8_t PSCV, uint32_t PSCID, uint8_t GV, uint32_t GSCID, iohgatp_t iohgatp, uint8_t GADE, uint8_t SADE, uint8_t SXL, - uint64_t *pa, uint64_t *gst_page_sz, gpte_t *gpte); + uint64_t *pa, uint64_t *gst_page_sz, gpte_t *gpte, uint32_t rcid, uint32_t mcid); extern uint8_t msi_address_translation( uint64_t gpa, uint8_t is_exec, device_context_t *DC, uint8_t *is_msi, uint8_t *is_mrif, uint32_t *mrif_nid, uint64_t *dest_mrif_addr, uint32_t *cause, uint64_t *iotval2, uint64_t *pa, - uint64_t *page_sz, gpte_t *g_pte, uint8_t check_access_perms ); + uint64_t *page_sz, gpte_t *g_pte, uint8_t check_access_perms, uint32_t rcid, + uint32_t mcid); #endif // __IOMMU_TRANSLATE_H__ diff --git a/iommu_ref_model/libiommu/src/iommu_ats.c b/iommu_ref_model/libiommu/src/iommu_ats.c index eee9d099..76429208 100644 --- a/iommu_ref_model/libiommu/src/iommu_ats.c +++ b/iommu_ref_model/libiommu/src/iommu_ats.c @@ -277,7 +277,9 @@ handle_page_request( prec.reserved0= 0; prec.reserved1= 0; prec_addr = ((pqb * PAGESIZE) | (pqt * PQ_ENTRY_SZ)); - status = write_memory((char *)&prec, prec_addr, 16); + status = write_memory((char *)&prec, prec_addr, 16, + g_reg_file.iommu_qosid.rcid, + g_reg_file.iommu_qosid.mcid); if ( (status & ACCESS_FAULT) || (status & DATA_CORRUPTION) ) { g_reg_file.pqcsr.pqmf = 1; generate_interrupt(PAGE_QUEUE); diff --git a/iommu_ref_model/libiommu/src/iommu_command_queue.c b/iommu_ref_model/libiommu/src/iommu_command_queue.c index 8bcb4152..cb54d43a 100644 --- a/iommu_ref_model/libiommu/src/iommu_command_queue.c +++ b/iommu_ref_model/libiommu/src/iommu_command_queue.c @@ -64,7 +64,8 @@ process_commands( return; a = g_reg_file.cqb.ppn * PAGESIZE | (g_reg_file.cqh.index * CQ_ENTRY_SZ); - status = read_memory(a, CQ_ENTRY_SZ, (char *)&command); + status = read_memory(a, CQ_ENTRY_SZ, (char *)&command, + g_reg_file.iommu_qosid.rcid, g_reg_file.iommu_qosid.mcid); if ( status != 0 ) { // If command-queue access leads to a memory fault then the // command-queue-memory-fault bit is set to 1 and the command @@ -487,7 +488,8 @@ do_iofence_c( // If AV=1, the IOMMU writes DATA to memory at a 4-byte aligned address ADDR[63:2] * 4 as // a 4-byte store. if ( AV == 1 ) { - status = write_memory((char *)&DATA, ADDR, 4); + status = write_memory((char *)&DATA, ADDR, 4, g_reg_file.iommu_qosid.rcid, + g_reg_file.iommu_qosid.mcid); if ( status != 0 ) { if ( g_reg_file.cqcsr.cqmf == 0 ) { g_reg_file.cqcsr.cqmf = 1; diff --git a/iommu_ref_model/libiommu/src/iommu_device_context.c b/iommu_ref_model/libiommu/src/iommu_device_context.c index 782dadc7..fffe79a6 100644 --- a/iommu_ref_model/libiommu/src/iommu_device_context.c +++ b/iommu_ref_model/libiommu/src/iommu_device_context.c @@ -108,7 +108,9 @@ locate_device_context( // 3. Let `ddte` be value of eight bytes at address `a + DDI[i] x 8`. If accessing // `ddte` violates a PMA or PMP check, then stop and report "DDT entry load // access fault" (cause = 257). - status = read_memory((a + (DDI[i] * 8)), 8, (char *)&ddte.raw); + status = read_memory((a + (DDI[i] * 8)), 8, (char *)&ddte.raw, + g_reg_file.iommu_qosid.rcid, + g_reg_file.iommu_qosid.mcid); if ( status & ACCESS_FAULT ) { *cause = 257; // DDT entry load access fault return 1; @@ -153,7 +155,9 @@ locate_device_context( // (cause = 268). This fault is detected if the IOMMU supports the RAS capability // (`capabilities.RAS == 1`). DC_SIZE = ( g_reg_file.capabilities.msi_flat == 1 ) ? EXT_FORMAT_DC_SIZE : BASE_FORMAT_DC_SIZE; - status = read_memory((a + (DDI[0] * DC_SIZE)), DC_SIZE, (char *)DC); + status = read_memory((a + (DDI[0] * DC_SIZE)), DC_SIZE, (char *)DC, + g_reg_file.iommu_qosid.rcid, + g_reg_file.iommu_qosid.mcid); if ( status & ACCESS_FAULT ) { *cause = 257; // DDT entry load access fault return 1; @@ -184,6 +188,8 @@ do_device_context_configuration_checks( // misconfigured" (cause = 259). // 1. If any bits or encoding that are reserved for future standard use are set. + // The RCID and MCID fields are added by the QoS ID extension. If capabilities.QOSID + // is 0, these bits are reserved and must be set to 0. if ( ((g_reg_file.capabilities.msi_flat == 1) && (DC->reserved != 0)) || ((g_reg_file.capabilities.msi_flat == 1) && (DC->msiptp.reserved != 0)) || ((g_reg_file.capabilities.msi_flat == 1) && (DC->msi_addr_mask.reserved != 0)) || @@ -193,7 +199,8 @@ do_device_context_configuration_checks( (DC->fsc.pdtp.reserved != 0 && DC->tc.PDTV == 1) || (DC->fsc.iosatp.reserved != 0 && DC->tc.PDTV == 0) || (DC->ta.reserved0 != 0) || - (DC->ta.reserved1 != 0) ) { + (DC->ta.reserved1 != 0) || + (g_reg_file.capabilities.qosid == 0 && (DC->ta.rcid != 0 || DC->ta.mcid != 0)) ) { return 1; } // 2. `capabilities.ATS` is 0 and `DC.tc.EN_ATS`, or `DC.tc.EN_PRI`, @@ -331,6 +338,7 @@ do_device_context_configuration_checks( if ( (g_reg_file.fctl.gxl == 1) && (DC->tc.SXL != 1) ) { return 1; } + if ( (g_reg_file.fctl.gxl == 0) && (g_gxl_writeable == 0) && (DC->tc.SXL != 0) ) { return 1; } diff --git a/iommu_ref_model/libiommu/src/iommu_faults.c b/iommu_ref_model/libiommu/src/iommu_faults.c index 5e833898..02d57440 100644 --- a/iommu_ref_model/libiommu/src/iommu_faults.c +++ b/iommu_ref_model/libiommu/src/iommu_faults.c @@ -138,7 +138,8 @@ report_fault(uint16_t cause, uint64_t iotval, uint64_t iotval2, uint8_t TTYP, ui // from 0 to 1 or when a new fault record is produced in the fault-queue, fault // interrupt pending (fip) bit is set in the fqcsr. frec_addr = ((fqb * PAGESIZE) | (fqt * FQ_ENTRY_SZ)); - status = write_memory((char *)&frec, frec_addr, 32); + status = write_memory((char *)&frec, frec_addr, 32, + g_reg_file.iommu_qosid.rcid, g_reg_file.iommu_qosid.mcid); if ( (status & ACCESS_FAULT) || (status & DATA_CORRUPTION) ) { g_reg_file.fqcsr.fqmf = 1; } else { diff --git a/iommu_ref_model/libiommu/src/iommu_interrupt.c b/iommu_ref_model/libiommu/src/iommu_interrupt.c index 73115e50..df8d0785 100644 --- a/iommu_ref_model/libiommu/src/iommu_interrupt.c +++ b/iommu_ref_model/libiommu/src/iommu_interrupt.c @@ -10,7 +10,8 @@ static void do_msi( uint32_t msi_data, uint64_t msi_addr) { uint8_t status; - status = write_memory((char *)&msi_data, msi_addr, 4); + status = write_memory((char *)&msi_data, msi_addr, 4, + g_reg_file.iommu_qosid.rcid, g_reg_file.iommu_qosid.mcid); if ( status & ACCESS_FAULT ) { // If an access fault is detected on a MSI write using msi_addr_x, // then the IOMMU reports a "IOMMU MSI write access fault" (cause 273) fault, diff --git a/iommu_ref_model/libiommu/src/iommu_msi_trans.c b/iommu_ref_model/libiommu/src/iommu_msi_trans.c index 5ed0a260..29589193 100644 --- a/iommu_ref_model/libiommu/src/iommu_msi_trans.c +++ b/iommu_ref_model/libiommu/src/iommu_msi_trans.c @@ -21,7 +21,8 @@ msi_address_translation( uint64_t gpa, uint8_t is_exec, device_context_t *DC, uint8_t *is_msi, uint8_t *is_mrif, uint32_t *mrif_nid, uint64_t *dest_mrif_addr, uint32_t *cause, uint64_t *iotval2, uint64_t *pa, - uint64_t *page_sz, gpte_t *g_pte, uint8_t check_access_perms ) { + uint64_t *page_sz, gpte_t *g_pte, uint8_t check_access_perms, + uint32_t rcid, uint32_t mcid) { uint64_t A, m, I; uint8_t status; @@ -67,7 +68,7 @@ msi_address_translation( // 7. Let `msipte` be the value of sixteen bytes at address `(m | (I x 16))`. If // accessing `msipte` violates a PMA or PMP check, then stop and report // "MSI PTE load access fault" (cause = 261). - status = read_memory((m + (I * 16)), 16, (char *)&msipte.raw); + status = read_memory((m + (I * 16)), 16, (char *)&msipte.raw, rcid, mcid); if ( status & ACCESS_FAULT ) { *cause = 261; // MSI PTE load access fault return 1; diff --git a/iommu_ref_model/libiommu/src/iommu_process_context.c b/iommu_ref_model/libiommu/src/iommu_process_context.c index 646692db..11a84958 100644 --- a/iommu_ref_model/libiommu/src/iommu_process_context.c +++ b/iommu_ref_model/libiommu/src/iommu_process_context.c @@ -87,7 +87,8 @@ locate_process_context( is_exec, is_implicit, 1, process_id, 0, 0, ((DC->iohgatp.MODE == IOHGATP_Bare) ? 0 : 1), DC->iohgatp.GSCID, DC->iohgatp, DC->tc.GADE, DC->tc.SADE, - DC->tc.SXL, &a, &gst_page_sz, &g_pte) ) ) { + DC->tc.SXL, &a, &gst_page_sz, &g_pte, DC->ta.rcid, + DC->ta.mcid) ) ) { if ( gst_fault == GST_PAGE_FAULT ) { *cause = 21; // Read guest page fault *iotval2 = (a & ~0x3); @@ -113,7 +114,7 @@ locate_process_context( // 4. Let `pdte` be value of eight bytes at address `a + PDI[i] x 8`. If // accessing `pdte` violates a PMA or PMP check, then stop and report // "PDT entry load access fault" (cause = 265). - status = read_memory(a, 8, (char *)&pdte.raw); + status = read_memory(a, 8, (char *)&pdte.raw, DC->ta.rcid, DC->ta.mcid); if ( status & ACCESS_FAULT ) { *cause = 265; // PDT entry load access fault return 1; @@ -153,7 +154,7 @@ locate_process_context( // fault" (cause = 265).If `PC` access detects a data corruption // (a.k.a. poisoned data), then stop and report "PDT data corruption" // (cause = 269). - status = read_memory(a, 16, (char *)PC); + status = read_memory(a, 16, (char *)PC, DC->ta.rcid, DC->ta.mcid); if ( status & ACCESS_FAULT ) { *cause = 265; // PDT entry load access fault return 1; diff --git a/iommu_ref_model/libiommu/src/iommu_reg.c b/iommu_ref_model/libiommu/src/iommu_reg.c index 43e2f5f5..fe07a80a 100644 --- a/iommu_ref_model/libiommu/src/iommu_reg.c +++ b/iommu_ref_model/libiommu/src/iommu_reg.c @@ -25,6 +25,7 @@ uint64_t g_sv57_bare_pg_sz; uint64_t g_sv48_bare_pg_sz; uint64_t g_sv39_bare_pg_sz; uint64_t g_sv32_bare_pg_sz; +uint32_t g_iommu_qosid_mask; uint8_t is_access_valid( @@ -726,6 +727,13 @@ write_register( } } break; + case IOMMU_QOSID_OFFSET: + // This register is read-only zero if qosid extension is not + // supported. The RCID and MCID fields of the register are WARL + if ( g_reg_file.capabilities.qosid == 1 ) { + g_reg_file.iommu_qosid.raw = data4 & g_iommu_qosid_mask; + } + break; case ICVEC_OFFSET: // The performance-monitoring-interrupt-vector // (`pmiv`) is the vector number assigned to the @@ -978,6 +986,7 @@ reset_iommu(uint8_t num_hpm, uint8_t hpmctr_bits, uint16_t eventID_limit, for ( i = RESERVED_OFFSET; i < ICVEC_OFFSET; i++ ) { g_offset_to_size[i] = 1; } + g_offset_to_size[IOMMU_QOSID_OFFSET] = 4; g_offset_to_size[ICVEC_OFFSET] = 8; g_offset_to_size[ICVEC_OFFSET + 4] = 8; for ( i = 0; i < 256; i += 16) { diff --git a/iommu_ref_model/libiommu/src/iommu_second_stage_trans.c b/iommu_ref_model/libiommu/src/iommu_second_stage_trans.c index d4b3f0b2..a2866978 100644 --- a/iommu_ref_model/libiommu/src/iommu_second_stage_trans.c +++ b/iommu_ref_model/libiommu/src/iommu_second_stage_trans.c @@ -10,7 +10,8 @@ second_stage_address_translation( uint8_t is_read, uint8_t is_write, uint8_t is_exec, uint8_t is_implicit, uint8_t PV, uint32_t PID, uint8_t PSCV, uint32_t PSCID, uint8_t GV, uint32_t GSCID, iohgatp_t iohgatp, uint8_t GADE, uint8_t SADE, - uint8_t SXL, uint64_t *pa, uint64_t *gst_page_sz, gpte_t *gpte) { + uint8_t SXL, uint64_t *pa, uint64_t *gst_page_sz, gpte_t *gpte, + uint32_t rcid, uint32_t mcid) { uint16_t vpn[5]; uint16_t ppn[5]; @@ -117,7 +118,8 @@ second_stage_address_translation( // then an access fault occurs if ( a & ~pa_mask ) return GST_ACCESS_FAULT; gpte->raw = 0; - status = read_memory((a | (vpn[i] * PTESIZE)), PTESIZE, (char *)&gpte->raw); + status = read_memory((a | (vpn[i] * PTESIZE)), PTESIZE, (char *)&gpte->raw, + rcid, mcid); if ( status & ACCESS_FAULT ) return GST_ACCESS_FAULT; if ( status & DATA_CORRUPTION) return GST_DATA_CORRUPTION; @@ -283,7 +285,8 @@ second_stage_address_translation( // Count G stage page walks count_events(PV, PID, PSCV, PSCID, DID, GV, GSCID, G_PT_WALKS); amo_gpte.raw = 0; - status = read_memory_for_AMO((a + (vpn[i] * PTESIZE)), PTESIZE, (char *)&amo_gpte.raw); + status = read_memory_for_AMO((a + (vpn[i] * PTESIZE)), PTESIZE, + (char *)&amo_gpte.raw, rcid, mcid); if ( status & ACCESS_FAULT ) return GST_ACCESS_FAULT; if ( status & DATA_CORRUPTION) return GST_DATA_CORRUPTION; @@ -299,7 +302,8 @@ second_stage_address_translation( if ( (is_write == 1 || is_implicit == 1) && (amo_gpte.W == 1) ) amo_gpte.D = 1; } - status = write_memory((char *)&amo_gpte.raw, (a + (vpn[i] * PTESIZE)), PTESIZE); + status = write_memory((char *)&amo_gpte.raw, (a + (vpn[i] * PTESIZE)), + PTESIZE, rcid, mcid); if ( status & ACCESS_FAULT ) return GST_ACCESS_FAULT; if ( status & DATA_CORRUPTION) return GST_DATA_CORRUPTION; diff --git a/iommu_ref_model/libiommu/src/iommu_translate.c b/iommu_ref_model/libiommu/src/iommu_translate.c index fbfe050c..7d52c6e1 100644 --- a/iommu_ref_model/libiommu/src/iommu_translate.c +++ b/iommu_ref_model/libiommu/src/iommu_translate.c @@ -291,7 +291,8 @@ iommu_translate_iova( if ( two_stage_address_translation(req->tr.iova, check_access_perms, DID, is_read, is_write, is_exec, PV, PID, PSCV, PSCID, iosatp, priv, SUM, DC.tc.SADE, GV, GSCID, iohgatp, DC.tc.GADE, DC.tc.SXL, - &cause, &iotval2, &gpa, &page_sz, &vs_pte) ) + &cause, &iotval2, &gpa, &page_sz, + &vs_pte, DC.ta.rcid, DC.ta.mcid) ) goto stop_and_report_fault; // 18. If MSI address translations using MSI page tables is enabled @@ -301,7 +302,8 @@ iommu_translate_iova( // If a fault is detected by the MSI address translation process then stop and // report the fault else the process continues at step 20. if ( msi_address_translation(gpa, is_exec, &DC, &is_msi, &is_mrif, &mrif_nid, &dest_mrif_addr, - &cause, &iotval2, &pa, &gst_page_sz, &g_pte, check_access_perms) ) + &cause, &iotval2, &pa, &gst_page_sz, &g_pte, + check_access_perms, DC.ta.rcid, DC.ta.mcid) ) goto stop_and_report_fault; // Chapter 5: If the IOVA is determined to be that of a virtual interrupt file @@ -321,7 +323,8 @@ iommu_translate_iova( is_implicit = 0; if ( (gst_fault = second_stage_address_translation(gpa, check_access_perms, DID, is_read, is_write, is_exec, is_implicit, PV, PID, PSCV, PSCID, GV, GSCID, - iohgatp, DC.tc.GADE, DC.tc.SADE, DC.tc.SXL, &pa, &gst_page_sz, &g_pte) ) ) { + iohgatp, DC.tc.GADE, DC.tc.SADE, DC.tc.SXL, &pa, &gst_page_sz, &g_pte, + DC.ta.rcid, DC.ta.mcid) ) ) { if ( gst_fault == GST_PAGE_FAULT ) goto guest_page_fault; if ( gst_fault == GST_ACCESS_FAULT ) goto access_fault; goto data_corruption; diff --git a/iommu_ref_model/libiommu/src/iommu_two_stage_trans.c b/iommu_ref_model/libiommu/src/iommu_two_stage_trans.c index 4f7eb5e5..30312a22 100644 --- a/iommu_ref_model/libiommu/src/iommu_two_stage_trans.c +++ b/iommu_ref_model/libiommu/src/iommu_two_stage_trans.c @@ -13,7 +13,7 @@ two_stage_address_translation( iosatp_t iosatp, uint8_t priv, uint8_t SUM, uint8_t SADE, uint8_t GV, uint32_t GSCID, iohgatp_t iohgatp, uint8_t GADE, uint8_t SXL, uint32_t *cause, uint64_t *iotval2, uint64_t *pa, - uint64_t *page_sz, pte_t *pte) { + uint64_t *page_sz, pte_t *pte, uint32_t rcid, uint32_t mcid) { uint16_t vpn[5]; uint16_t ppn[5]; @@ -126,7 +126,7 @@ two_stage_address_translation( is_implicit = 1; if ( ( gst_fault = second_stage_address_translation(a, 1, DID, 1, 0, 0, is_implicit, PV, PID, PSCV, PSCID, GV, GSCID, iohgatp, GADE, SADE, SXL, - &a, &gst_page_sz, &gpte) ) ) { + &a, &gst_page_sz, &gpte, rcid, mcid) ) ) { if ( gst_fault == GST_PAGE_FAULT ) goto guest_page_fault; if ( gst_fault == GST_ACCESS_FAULT ) goto access_fault; goto data_corruption; @@ -139,7 +139,7 @@ two_stage_address_translation( // Count S/VS stage page walks count_events(PV, PID, PSCV, PSCID, DID, GV, GSCID, S_VS_PT_WALKS); pte->raw = 0; - status = read_memory(a, PTESIZE, (char *)&pte->raw); + status = read_memory(a, PTESIZE, (char *)&pte->raw, rcid, mcid); if ( status & ACCESS_FAULT ) goto access_fault; if ( status & DATA_CORRUPTION) goto data_corruption; @@ -314,7 +314,7 @@ two_stage_address_translation( // Count S/VS stage page walks count_events(PV, PID, PSCV, PSCID, DID, GV, GSCID, S_VS_PT_WALKS); amo_pte.raw = 0; - status = read_memory_for_AMO(a, PTESIZE, (char *)&amo_pte.raw); + status = read_memory_for_AMO(a, PTESIZE, (char *)&amo_pte.raw, rcid, mcid); if ( status & ACCESS_FAULT ) goto access_fault; if ( status & DATA_CORRUPTION) goto data_corruption; @@ -330,7 +330,7 @@ two_stage_address_translation( if ( (is_write == 1) && (amo_pte.W == 1) ) amo_pte.D = 1; } - status = write_memory((char *)&amo_pte.raw, a, PTESIZE); + status = write_memory((char *)&amo_pte.raw, a, PTESIZE, rcid, mcid); if ( status & ACCESS_FAULT ) goto access_fault; if ( status & DATA_CORRUPTION) goto data_corruption; diff --git a/iommu_ref_model/libtables/src/build_ddt.c b/iommu_ref_model/libtables/src/build_ddt.c index 824a5cdd..6d8f3356 100644 --- a/iommu_ref_model/libtables/src/build_ddt.c +++ b/iommu_ref_model/libtables/src/build_ddt.c @@ -34,15 +34,15 @@ add_dev_context( i = LEVELS - 1; while ( i > 0 ) { ddte.raw = 0; - if ( read_memory((a + (DDI[i] * 8)), 8, (char *)&ddte.raw) ) return -1; + if ( read_memory_test((a + (DDI[i] * 8)), 8, (char *)&ddte.raw) ) return -1; if ( ddte.V == 0 ) { ddte.V = 1; ddte.PPN = get_free_ppn(1); - if ( write_memory((char *)&ddte.raw, (a + (DDI[i] * 8)), 8) ) return -1; + if ( write_memory_test((char *)&ddte.raw, (a + (DDI[i] * 8)), 8) ) return -1; } i = i - 1; a = ddte.PPN * PAGESIZE; } - if ( write_memory((char *)DC, (a + (DDI[0] * DC_SIZE)), DC_SIZE) ) return -1; + if ( write_memory_test((char *)DC, (a + (DDI[0] * DC_SIZE)), DC_SIZE) ) return -1; return (a + (DDI[0] * DC_SIZE)); } diff --git a/iommu_ref_model/libtables/src/build_g_stage_pt.c b/iommu_ref_model/libtables/src/build_g_stage_pt.c index c231eae3..61b07dd4 100644 --- a/iommu_ref_model/libtables/src/build_g_stage_pt.c +++ b/iommu_ref_model/libtables/src/build_g_stage_pt.c @@ -45,16 +45,16 @@ add_g_stage_pte ( a = iohgatp.PPN * PAGESIZE; while ( i > add_level ) { nl_gpte.raw = 0; - if ( read_memory((a | (vpn[i] * PTESIZE)), PTESIZE, (char *)&nl_gpte.raw) ) return -1; + if ( read_memory_test((a | (vpn[i] * PTESIZE)), PTESIZE, (char *)&nl_gpte.raw) ) return -1; if ( nl_gpte.V == 0 ) { nl_gpte.V = 1; nl_gpte.PPN = get_free_ppn(1); - if ( write_memory((char *)&nl_gpte.raw, (a | (vpn[i] * PTESIZE)), PTESIZE) ) return -1; + if ( write_memory_test((char *)&nl_gpte.raw, (a | (vpn[i] * PTESIZE)), PTESIZE) ) return -1; } i = i - 1; if ( i < 0 ) return -1; a = nl_gpte.PPN * PAGESIZE; } - if ( write_memory((char *)&gpte.raw, (a | (vpn[i] * PTESIZE)), PTESIZE) ) return -1; + if ( write_memory_test((char *)&gpte.raw, (a | (vpn[i] * PTESIZE)), PTESIZE) ) return -1; return (a | (vpn[i] * PTESIZE)); } diff --git a/iommu_ref_model/libtables/src/build_pdt.c b/iommu_ref_model/libtables/src/build_pdt.c index 3afe87fd..503102e8 100644 --- a/iommu_ref_model/libtables/src/build_pdt.c +++ b/iommu_ref_model/libtables/src/build_pdt.c @@ -26,7 +26,7 @@ add_process_context( while ( i > 0 ) { if ( translate_gpa(DC->iohgatp, a, &a) == -1 ) return -1; pdte.raw = 0; - if ( read_memory((a + (PDI[i] * 8)), 8, (char *)&pdte.raw) ) return -1; + if ( read_memory_test((a + (PDI[i] * 8)), 8, (char *)&pdte.raw) ) return -1; if ( pdte.V == 0 ) { pdte.V = 1; pdte.reserved0 = pdte.reserved1 = 0; @@ -51,12 +51,12 @@ add_process_context( } else { pdte.PPN = get_free_ppn(1); } - if ( write_memory((char *)&pdte.raw, (a + (PDI[i] * 8)), 8) ) return -1; + if ( write_memory_test((char *)&pdte.raw, (a + (PDI[i] * 8)), 8) ) return -1; } i = i - 1; a = pdte.PPN * PAGESIZE; } if ( translate_gpa(DC->iohgatp, a, &a) == -1 ) return -1; - if ( write_memory((char *)PC, (a + (PDI[0] * 16)), 16) ) return -1; + if ( write_memory_test((char *)PC, (a + (PDI[0] * 16)), 16) ) return -1; return (a + (PDI[0] * 16)); } diff --git a/iommu_ref_model/libtables/src/build_s_stage_pt.c b/iommu_ref_model/libtables/src/build_s_stage_pt.c index f4894133..b979448c 100644 --- a/iommu_ref_model/libtables/src/build_s_stage_pt.c +++ b/iommu_ref_model/libtables/src/build_s_stage_pt.c @@ -45,16 +45,16 @@ add_s_stage_pte ( a = satp.PPN * PAGESIZE; while ( i > add_level ) { nl_pte.raw = 0; - if ( read_memory((a | (vpn[i] * PTESIZE)), PTESIZE, (char *)&nl_pte.raw)) return -1; + if ( read_memory_test((a | (vpn[i] * PTESIZE)), PTESIZE, (char *)&nl_pte.raw)) return -1; if ( nl_pte.V == 0 ) { nl_pte.V = 1; nl_pte.PPN = get_free_ppn(1); - if ( write_memory((char *)&nl_pte.raw, (a | (vpn[i] * PTESIZE)), PTESIZE) ) return -1; + if ( write_memory_test((char *)&nl_pte.raw, (a | (vpn[i] * PTESIZE)), PTESIZE) ) return -1; } i = i - 1; if ( i < 0 ) return -1; a = nl_pte.PPN * PAGESIZE; } - if ( write_memory((char *)&pte.raw, (a | (vpn[i] * PTESIZE)), PTESIZE) ) return -1; + if ( write_memory_test((char *)&pte.raw, (a | (vpn[i] * PTESIZE)), PTESIZE) ) return -1; return (a | (vpn[i] * PTESIZE)); } diff --git a/iommu_ref_model/libtables/src/build_vs_stage_pt.c b/iommu_ref_model/libtables/src/build_vs_stage_pt.c index 4aa9bc67..149b5bd7 100644 --- a/iommu_ref_model/libtables/src/build_vs_stage_pt.c +++ b/iommu_ref_model/libtables/src/build_vs_stage_pt.c @@ -47,7 +47,7 @@ add_vs_stage_pte ( while ( i > add_level ) { if ( translate_gpa(iohgatp, a, &a) == -1) return -1; nl_pte.raw = 0; - if ( read_memory((a | (vpn[i] * PTESIZE)), PTESIZE, (char *)&nl_pte.raw)) return -1; + if ( read_memory_test((a | (vpn[i] * PTESIZE)), PTESIZE, (char *)&nl_pte.raw)) return -1; if ( nl_pte.V == 0 ) { gpte_t gpte; @@ -68,13 +68,13 @@ add_vs_stage_pte ( if ( add_g_stage_pte(iohgatp, (PAGESIZE * nl_pte.PPN), gpte, 0) == -1) return -1; - if ( write_memory((char *)&nl_pte.raw, (a | (vpn[i] * PTESIZE)), PTESIZE) ) return -1; + if ( write_memory_test((char *)&nl_pte.raw, (a | (vpn[i] * PTESIZE)), PTESIZE) ) return -1; } i = i - 1; if ( i < 0 ) return 1; a = nl_pte.PPN * PAGESIZE; } if ( translate_gpa(iohgatp, a, &a) == -1) return -1; - if ( write_memory((char *)&pte.raw, (a | (vpn[i] * PTESIZE)), PTESIZE) ) return -1; + if ( write_memory_test((char *)&pte.raw, (a | (vpn[i] * PTESIZE)), PTESIZE) ) return -1; return (a | (vpn[i] * PTESIZE)); } diff --git a/iommu_ref_model/libtables/src/translate_gpa.c b/iommu_ref_model/libtables/src/translate_gpa.c index 9c765c60..fe7fcb54 100644 --- a/iommu_ref_model/libtables/src/translate_gpa.c +++ b/iommu_ref_model/libtables/src/translate_gpa.c @@ -53,7 +53,7 @@ translate_gpa ( a = iohgatp.PPN * PAGESIZE; while ( 1 ) { nl_gpte.raw = 0; - if ( read_memory((a | (vpn[i] * PTESIZE)), PTESIZE, (char *)&nl_gpte.raw) ) return -1; + if ( read_memory_test((a | (vpn[i] * PTESIZE)), PTESIZE, (char *)&nl_gpte.raw) ) return -1; if ( nl_gpte.V == 0 ) return -1; if ( nl_gpte.R != 0 || nl_gpte.X != 0 ) { *spa = nl_gpte.PPN; diff --git a/iommu_ref_model/test/tbapi.c b/iommu_ref_model/test/tbapi.c index 3e935795..2da19870 100644 --- a/iommu_ref_model/test/tbapi.c +++ b/iommu_ref_model/test/tbapi.c @@ -11,28 +11,38 @@ uint8_t read_memory( - uint64_t addr, uint8_t size, char *data){ + uint64_t addr, uint8_t size, char *data, uint32_t rcid, uint32_t mcid){ if ( addr == access_viol_addr ) return ACCESS_FAULT; if ( addr == data_corruption_addr ) return DATA_CORRUPTION; memcpy(data, &memory[addr], size); return 0; } - uint8_t -read_memory_for_AMO( +read_memory_test( uint64_t addr, uint8_t size, char *data) { + return read_memory(addr, size, data, 0, 0); +} +uint8_t +read_memory_for_AMO( + uint64_t addr, uint8_t size, char *data, uint32_t rcid, uint32_t mcid) { // Same for now - return read_memory(addr, size, data); + return read_memory(addr, size, data, rcid, mcid); } uint8_t write_memory( - char *data, uint64_t addr, uint32_t size) { + char *data, uint64_t addr, uint32_t size, uint32_t rcid, uint32_t mcid) { if ( addr == access_viol_addr ) return ACCESS_FAULT; if ( addr == data_corruption_addr ) return DATA_CORRUPTION; memcpy(&memory[addr], data, size); return 0; } +uint8_t +write_memory_test( + char *data, uint64_t addr, uint32_t size) { + return write_memory(data, addr, size, 0, 0); +} + void iommu_to_hb_do_global_observability_sync( diff --git a/iommu_ref_model/test/test_app.c b/iommu_ref_model/test/test_app.c index 825fdd77..8600ebbd 100644 --- a/iommu_ref_model/test/test_app.c +++ b/iommu_ref_model/test/test_app.c @@ -301,7 +301,7 @@ main(void) { // make DDTE invalid ddtp.raw = read_register(DDTP_OFFSET, 8); ddte.raw = 0; - write_memory((char *)&ddte, (ddtp.ppn * PAGESIZE) | (get_bits(23, 15, 0x012345) * 8), 8); + write_memory_test((char *)&ddte, (ddtp.ppn * PAGESIZE) | (get_bits(23, 15, 0x012345) * 8), 8); FOR_ALL_TRANSACTION_TYPES(at, pid_valid, exec_req, priv_req, no_write, { if ( at == ADDR_TYPE_PCIE_ATS_TRANSLATION_REQUEST ) { send_translation_request(0x012345, pid_valid, 0x99, no_write, exec_req, @@ -339,7 +339,7 @@ main(void) { ddte.reserved0 |= no_write; ddte.reserved1 |= ~no_write; ddte.V = 1; - write_memory((char *)&ddte, (ddtp.ppn * PAGESIZE) | (get_bits(23, 15, 0x012345) * 8), 8); + write_memory_test((char *)&ddte, (ddtp.ppn * PAGESIZE) | (get_bits(23, 15, 0x012345) * 8), 8); if ( at == ADDR_TYPE_PCIE_ATS_TRANSLATION_REQUEST ) { send_translation_request(0x012345, pid_valid, 0x99, no_write, exec_req, priv_req, 0, at, 0xdeadbeef, 16, READ, &req, &rsp); @@ -351,7 +351,7 @@ main(void) { } }); ddte.raw = 0; - write_memory((char *)&ddte, (ddtp.ppn * PAGESIZE) | (get_bits(23, 15, 0x012345) * 8), 8); + write_memory_test((char *)&ddte, (ddtp.ppn * PAGESIZE) | (get_bits(23, 15, 0x012345) * 8), 8); END_TEST(); @@ -367,7 +367,7 @@ main(void) { write_register(ICVEC_OFFSET, 8, 0x0000000000000050); temp = get_free_ppn(1) * PAGESIZE; j = 0; - write_memory((char *)&j, temp, 4); + write_memory_test((char *)&j, temp, 4); write_register(MSI_ADDR_5_OFFSET, 8, temp); write_register(MSI_DATA_5_OFFSET, 4, 0xDEADBEEF); write_register(MSI_VEC_CTRL_5_OFFSET, 4, 0); @@ -388,10 +388,10 @@ main(void) { } ipsr.raw = read_register(IPSR_OFFSET, 4); fail_if( ( ipsr.fip == 0 ) ); - read_memory(temp, 4, (char *)&j); + read_memory_test(temp, 4, (char *)&j); fail_if( ( j != 0xDEADBEEF ) ); j = 0; - write_memory((char *)&j, temp, 4); + write_memory_test((char *)&j, temp, 4); // Clear IPSR ipsr.raw = read_register(IPSR_OFFSET, 4); fail_if( ( ipsr.fip != 1 ) ); @@ -414,10 +414,10 @@ main(void) { fail_if( ( fqcsr.fqof == 0 ) ); // Overflow should have triggered a MSI - read_memory(temp, 4, (char *)&j); + read_memory_test(temp, 4, (char *)&j); fail_if( ( j != 0xDEADBEEF ) ); j = 0; - write_memory((char *)&j, temp, 4); + write_memory_test((char *)&j, temp, 4); ipsr.raw = read_register(IPSR_OFFSET, 4); fail_if( ( ipsr.fip != 1 ) ); // Clear IPSR @@ -425,10 +425,10 @@ main(void) { // Should retrigger since fqof is still set ipsr.raw = read_register(IPSR_OFFSET, 4); fail_if( ( ipsr.fip != 1 ) ); - read_memory(temp, 4, (char *)&j); + read_memory_test(temp, 4, (char *)&j); fail_if( ( j != 0xDEADBEEF ) ); j = 0; - write_memory((char *)&j, temp, 4); + write_memory_test((char *)&j, temp, 4); // Overflow should remain send_translation_request(0x012345, pid_valid, 0x99, no_write, exec_req, @@ -516,7 +516,7 @@ main(void) { fail_if( ( ipsr.fip != 1 ) ); fqh.raw = read_register(FQH_OFFSET, 4); fqb.raw = read_register(FQB_OFFSET, 8); - read_memory(((fqb.ppn * PAGESIZE) | ((fqh.index + 1) * 32)), 32, (char *)&fault_rec); + read_memory_test(((fqb.ppn * PAGESIZE) | ((fqh.index + 1) * 32)), 32, (char *)&fault_rec); fail_if( ( fault_rec.TTYP != 0 ) ); fail_if( ( fault_rec.iotval != temp ) ); fail_if( ( fault_rec.CAUSE != 273 ) ); @@ -542,9 +542,9 @@ main(void) { (void)(DC_addr); // make DC invalid - read_memory(DC_addr, 64, (char *)&DC); + read_memory_test(DC_addr, 64, (char *)&DC); DC.tc.V = 0; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); FOR_ALL_TRANSACTION_TYPES(at, pid_valid, exec_req, priv_req, no_write, { if ( at == ADDR_TYPE_PCIE_ATS_TRANSLATION_REQUEST ) { send_translation_request(0x012345, pid_valid, 0x99, no_write, exec_req, @@ -557,29 +557,29 @@ main(void) { } }); DC.tc.V = 1; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); END_TEST(); START_TEST("Device context misconfigured"); - read_memory(DC_addr, 64, (char *)&DC); + read_memory_test(DC_addr, 64, (char *)&DC); at = ADDR_TYPE_UNTRANSLATED; pid_valid = no_write = exec_req = priv_req = 0; DC.reserved = 1; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); send_translation_request(0x012345, pid_valid, 0x99, no_write, exec_req, priv_req, 0, at, 0xdeadbeef, 16, (no_write ^ 1), &req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 259, 0) < 0 ) ); DC.reserved = 0; DC.tc.reserved0 = 1; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); send_translation_request(0x012345, pid_valid, 0x99, no_write, exec_req, priv_req, 0, at, 0xdeadbeef, 16, (no_write ^ 1), &req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 259, 0) < 0 ) ); DC.tc.reserved0 = 0; DC.tc.reserved1 = 1; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); send_translation_request(0x012345, pid_valid, 0x99, no_write, exec_req, priv_req, 0, at, 0xdeadbeef, 16, (no_write ^ 1), &req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 259, 0) < 0 ) ); @@ -587,7 +587,7 @@ main(void) { DC.tc.reserved0 = 1; DC.tc.reserved1 = 1; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); send_translation_request(0x012345, pid_valid, 0x99, no_write, exec_req, priv_req, 0, at, 0xdeadbeef, 16, (no_write ^ 1), &req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 259, 0) < 0 ) ); @@ -595,195 +595,195 @@ main(void) { DC.tc.reserved1 = 0; DC.ta.reserved0 = 1; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); send_translation_request(0x012345, pid_valid, 0x99, no_write, exec_req, priv_req, 0, at, 0xdeadbeef, 16, (no_write ^ 1), &req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 259, 0) < 0 ) ); DC.ta.reserved0 = 0; DC.ta.reserved1 = 1; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); send_translation_request(0x012345, pid_valid, 0x99, no_write, exec_req, priv_req, 0, at, 0xdeadbeef, 16, (no_write ^ 1), &req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 259, 0) < 0 ) ); DC.ta.reserved1 = 0; DC.fsc.iosatp.reserved = 1; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); send_translation_request(0x012345, pid_valid, 0x99, no_write, exec_req, priv_req, 0, at, 0xdeadbeef, 16, (no_write ^ 1), &req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 259, 0) < 0 ) ); DC.fsc.iosatp.reserved = 0; DC.msiptp.reserved = 1; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); send_translation_request(0x012345, pid_valid, 0x99, no_write, exec_req, priv_req, 0, at, 0xdeadbeef, 16, (no_write ^ 1), &req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 259, 0) < 0 ) ); DC.msiptp.reserved = 0; DC.msi_addr_mask.reserved = 1; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); send_translation_request(0x012345, pid_valid, 0x99, no_write, exec_req, priv_req, 0, at, 0xdeadbeef, 16, (no_write ^ 1), &req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 259, 0) < 0 ) ); DC.msi_addr_mask.reserved = 0; DC.msi_addr_pattern.reserved = 1; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); send_translation_request(0x012345, pid_valid, 0x99, no_write, exec_req, priv_req, 0, at, 0xdeadbeef, 16, (no_write ^ 1), &req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 259, 0) < 0 ) ); DC.msi_addr_pattern.reserved = 0; g_reg_file.fctl.gxl = 1; DC.iohgatp.MODE = IOHGATP_Sv32x4; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); send_translation_request(0x012345, pid_valid, 0x99, no_write, exec_req, priv_req, 0, at, 0xdeadbeef, 16, (no_write ^ 1), &req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 259, 0) < 0 ) ); g_reg_file.fctl.gxl = 0; DC.iohgatp.MODE = IOHGATP_Sv48x4; DC.iohgatp.MODE = IOHGATP_Sv57x4 + 1; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); send_translation_request(0x012345, pid_valid, 0x99, no_write, exec_req, priv_req, 0, at, 0xdeadbeef, 16, (no_write ^ 1), &req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 259, 0) < 0 ) ); DC.iohgatp.MODE = IOHGATP_Sv48x4; g_reg_file.fctl.gxl = 1; DC.fsc.iosatp.MODE = IOSATP_Sv32; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); send_translation_request(0x012345, pid_valid, 0x99, no_write, exec_req, priv_req, 0, at, 0xdeadbeef, 16, (no_write ^ 1), &req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 259, 0) < 0 ) ); g_reg_file.fctl.gxl = 0; DC.fsc.iosatp.MODE = IOSATP_Bare; DC.fsc.iosatp.MODE = IOSATP_Sv57 + 1; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); send_translation_request(0x012345, pid_valid, 0x99, no_write, exec_req, priv_req, 0, at, 0xdeadbeef, 16, (no_write ^ 1), &req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 259, 0) < 0 ) ); DC.fsc.iosatp.MODE = IOSATP_Bare; DC.msiptp.MODE = MSIPTP_Flat + 1; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); send_translation_request(0x012345, pid_valid, 0x99, no_write, exec_req, priv_req, 0, at, 0xdeadbeef, 16, (no_write ^ 1), &req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 259, 0) < 0 ) ); DC.msiptp.MODE = MSIPTP_Off; DC.tc.T2GPA = 1; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); send_translation_request(0x012345, pid_valid, 0x99, no_write, exec_req, priv_req, 0, at, 0xdeadbeef, 16, (no_write ^ 1), &req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 259, 0) < 0 ) ); DC.tc.T2GPA = 0; DC.tc.EN_PRI = 1; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); send_translation_request(0x012345, pid_valid, 0x99, no_write, exec_req, priv_req, 0, at, 0xdeadbeef, 16, (no_write ^ 1), &req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 259, 0) < 0 ) ); DC.tc.EN_PRI = 0; DC.tc.PRPR = 1; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); send_translation_request(0x012345, pid_valid, 0x99, no_write, exec_req, priv_req, 0, at, 0xdeadbeef, 16, (no_write ^ 1), &req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 259, 0) < 0 ) ); DC.tc.PRPR = 0; DC.tc.PDTV = 1; DC.fsc.pdtp.MODE = PD20 + 1; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); send_translation_request(0x012345, pid_valid, 0x99, no_write, exec_req, priv_req, 0, at, 0xdeadbeef, 16, (no_write ^ 1), &req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 259, 0) < 0 ) ); DC.fsc.pdtp.MODE = PDTP_Bare; DC.fsc.pdtp.reserved = 1; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); send_translation_request(0x012345, pid_valid, 0x99, no_write, exec_req, priv_req, 0, at, 0xdeadbeef, 16, (no_write ^ 1), &req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 259, 0) < 0 ) ); DC.fsc.pdtp.reserved = 0; DC.tc.PDTV = 0; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); DC.iohgatp.PPN |= 1; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); send_translation_request(0x012345, pid_valid, 0x99, no_write, exec_req, priv_req, 0, at, 0xdeadbeef, 16, (no_write ^ 1), &req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 259, 0) < 0 ) ); DC.iohgatp.PPN |= 2; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); send_translation_request(0x012345, pid_valid, 0x99, no_write, exec_req, priv_req, 0, at, 0xdeadbeef, 16, (no_write ^ 1), &req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 259, 0) < 0 ) ); DC.iohgatp.PPN &= ~0x3; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); g_reg_file.capabilities.amo_hwad = 0; DC.tc.SADE = 1; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); send_translation_request(0x012345, pid_valid, 0x99, no_write, exec_req, priv_req, 0, at, 0xdeadbeef, 16, (no_write ^ 1), &req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 259, 0) < 0 ) ); DC.tc.SADE = 0; DC.tc.GADE = 1; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); send_translation_request(0x012345, pid_valid, 0x99, no_write, exec_req, priv_req, 0, at, 0xdeadbeef, 16, (no_write ^ 1), &req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 259, 0) < 0 ) ); DC.tc.SADE = 1; DC.tc.GADE = 1; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); send_translation_request(0x012345, pid_valid, 0x99, no_write, exec_req, priv_req, 0, at, 0xdeadbeef, 16, (no_write ^ 1), &req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 259, 0) < 0 ) ); DC.tc.SADE = 0; DC.tc.GADE = 0; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); g_reg_file.capabilities.amo_hwad = 1; g_reg_file.capabilities.ats = 0; DC.tc.EN_ATS = 1; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); send_translation_request(0x012345, pid_valid, 0x99, no_write, exec_req, priv_req, 0, at, 0xdeadbeef, 16, (no_write ^ 1), &req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 259, 0) < 0 ) ); DC.tc.EN_ATS = 0; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); DC.tc.EN_PRI = 1; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); send_translation_request(0x012345, pid_valid, 0x99, no_write, exec_req, priv_req, 0, at, 0xdeadbeef, 16, (no_write ^ 1), &req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 259, 0) < 0 ) ); DC.tc.EN_PRI = 0; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); DC.tc.PRPR = 1; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); send_translation_request(0x012345, pid_valid, 0x99, no_write, exec_req, priv_req, 0, at, 0xdeadbeef, 16, (no_write ^ 1), &req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 259, 0) < 0 ) ); DC.tc.PRPR = 0; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); g_reg_file.capabilities.ats = 1; g_reg_file.capabilities.t2gpa = 0; DC.tc.T2GPA = 1; DC.tc.EN_ATS = 1; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); send_translation_request(0x012345, pid_valid, 0x99, no_write, exec_req, priv_req, 0, at, 0xdeadbeef, 16, (no_write ^ 1), &req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 259, 0) < 0 ) ); DC.tc.T2GPA = 0; DC.tc.EN_ATS = 0; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); g_reg_file.capabilities.t2gpa = 1; DC.tc.T2GPA = 1; DC.tc.EN_ATS = 1; temp = DC.iohgatp.MODE; DC.iohgatp.MODE = IOHGATP_Bare; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); send_translation_request(0x012345, pid_valid, 0x99, no_write, exec_req, priv_req, 0, at, 0xdeadbeef, 16, (no_write ^ 1), &req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 259, 0) < 0 ) ); DC.tc.T2GPA = 0; DC.tc.EN_ATS = 0; DC.iohgatp.MODE = temp; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); DC.tc.PDTV = 1; @@ -791,7 +791,7 @@ main(void) { g_reg_file.capabilities.pd20 = 0; DC.fsc.pdtp.MODE = PD20; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); send_translation_request(0x012345, pid_valid, 0x99, no_write, exec_req, priv_req, 0, at, 0xdeadbeef, 16, (no_write ^ 1), &req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 259, 0) < 0 ) ); @@ -799,7 +799,7 @@ main(void) { g_reg_file.capabilities.pd17 = 0; DC.fsc.pdtp.MODE = PD17; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); send_translation_request(0x012345, pid_valid, 0x99, no_write, exec_req, priv_req, 0, at, 0xdeadbeef, 16, (no_write ^ 1), &req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 259, 0) < 0 ) ); @@ -807,61 +807,61 @@ main(void) { g_reg_file.capabilities.pd8 = 0; DC.fsc.pdtp.MODE = PD8; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); send_translation_request(0x012345, pid_valid, 0x99, no_write, exec_req, priv_req, 0, at, 0xdeadbeef, 16, (no_write ^ 1), &req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 259, 0) < 0 ) ); g_reg_file.capabilities.pd8 = 1; DC.tc.PDTV = 0; DC.fsc.pdtp.MODE = temp; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); DC.tc.SXL = 1; temp = DC.fsc.iosatp.MODE; DC.fsc.iosatp.MODE = IOSATP_Sv48; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); send_translation_request(0x012345, pid_valid, 0x99, no_write, exec_req, priv_req, 0, at, 0xdeadbeef, 16, (no_write ^ 1), &req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 259, 0) < 0 ) ); DC.tc.SXL = 0; DC.fsc.iosatp.MODE = temp; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); temp = DC.fsc.iosatp.MODE; g_reg_file.capabilities.Sv39 = 0; DC.fsc.iosatp.MODE = IOSATP_Sv39; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); send_translation_request(0x012345, pid_valid, 0x99, no_write, exec_req, priv_req, 0, at, 0xdeadbeef, 16, (no_write ^ 1), &req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 259, 0) < 0 ) ); - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); g_reg_file.capabilities.Sv39 = 1; g_reg_file.capabilities.Sv48 = 0; DC.fsc.iosatp.MODE = IOSATP_Sv48; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); send_translation_request(0x012345, pid_valid, 0x99, no_write, exec_req, priv_req, 0, at, 0xdeadbeef, 16, (no_write ^ 1), &req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 259, 0) < 0 ) ); - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); g_reg_file.capabilities.Sv48 = 1; g_reg_file.capabilities.Sv57 = 0; DC.fsc.iosatp.MODE = IOSATP_Sv57; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); send_translation_request(0x012345, pid_valid, 0x99, no_write, exec_req, priv_req, 0, at, 0xdeadbeef, 16, (no_write ^ 1), &req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 259, 0) < 0 ) ); - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); g_reg_file.capabilities.Sv57 = 1; DC.tc.SXL = 1; DC.fsc.iosatp.MODE = IOSATP_Sv32; g_reg_file.capabilities.Sv32 = 0; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); send_translation_request(0x012345, pid_valid, 0x99, no_write, exec_req, priv_req, 0, at, 0xdeadbeef, 16, (no_write ^ 1), &req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 259, 0) < 0 ) ); @@ -869,34 +869,34 @@ main(void) { DC.tc.SXL = 0; DC.fsc.iosatp.MODE = temp; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); DC.tc.DPE = 1; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); send_translation_request(0x012345, pid_valid, 0x99, no_write, exec_req, priv_req, 0, at, 0xdeadbeef, 16, (no_write ^ 1), &req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 259, 0) < 0 ) ); DC.tc.DPE = 0; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); g_reg_file.fctl.gxl = 1; temp = DC.iohgatp.MODE; DC.iohgatp.MODE = IOHGATP_Sv39x4; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); send_translation_request(0x012345, pid_valid, 0x99, no_write, exec_req, priv_req, 0, at, 0xdeadbeef, 16, (no_write ^ 1), &req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 259, 0) < 0 ) ); DC.iohgatp.MODE = IOHGATP_Sv32x4; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); g_reg_file.capabilities.Sv32x4 = 0; send_translation_request(0x012345, pid_valid, 0x99, no_write, exec_req, priv_req, 0, at, 0xdeadbeef, 16, (no_write ^ 1), &req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 259, 0) < 0 ) ); DC.iohgatp.MODE = temp; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); g_reg_file.capabilities.Sv32x4 = 1; g_reg_file.fctl.gxl = 0; @@ -904,37 +904,37 @@ main(void) { temp = DC.iohgatp.MODE; g_reg_file.capabilities.Sv39x4 = 0; DC.iohgatp.MODE = IOHGATP_Sv39x4; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); send_translation_request(0x012345, pid_valid, 0x99, no_write, exec_req, priv_req, 0, at, 0xdeadbeef, 16, (no_write ^ 1), &req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 259, 0) < 0 ) ); - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); g_reg_file.capabilities.Sv39x4 = 1; g_reg_file.capabilities.Sv48x4 = 0; DC.iohgatp.MODE = IOHGATP_Sv48x4; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); send_translation_request(0x012345, pid_valid, 0x99, no_write, exec_req, priv_req, 0, at, 0xdeadbeef, 16, (no_write ^ 1), &req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 259, 0) < 0 ) ); - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); g_reg_file.capabilities.Sv48x4 = 1; g_reg_file.capabilities.Sv57x4 = 0; DC.iohgatp.MODE = IOHGATP_Sv57x4; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); send_translation_request(0x012345, pid_valid, 0x99, no_write, exec_req, priv_req, 0, at, 0xdeadbeef, 16, (no_write ^ 1), &req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 259, 0) < 0 ) ); DC.iohgatp.MODE = temp; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); g_reg_file.capabilities.Sv57x4 = 1; g_reg_file.capabilities.end = 0; g_reg_file.fctl.be = 0; DC.tc.SBE = 1; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); send_translation_request(0x012345, pid_valid, 0x99, no_write, exec_req, priv_req, 0, at, 0xdeadbeef, 16, (no_write ^ 1), &req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 259, 0) < 0 ) ); @@ -942,29 +942,29 @@ main(void) { g_reg_file.capabilities.end = 0; g_reg_file.fctl.be = 0; DC.tc.SBE = 0; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); g_reg_file.fctl.gxl = 1; temp = DC.iohgatp.MODE; DC.iohgatp.MODE = IOHGATP_Sv32x4; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); send_translation_request(0x012345, pid_valid, 0x99, no_write, exec_req, priv_req, 0, at, 0xdeadbeef, 16, (no_write ^ 1), &req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 259, 0) < 0 ) ); g_reg_file.fctl.gxl = 0; DC.iohgatp.MODE = temp; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); DC.tc.SXL = 1; temp = DC.fsc.iosatp.MODE; DC.fsc.iosatp.MODE = IOSATP_Sv32; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); send_translation_request(0x012345, pid_valid, 0x99, no_write, exec_req, priv_req, 0, at, 0xdeadbeef, 16, (no_write ^ 1), &req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 259, 0) < 0 ) ); DC.fsc.iosatp.MODE = temp; DC.tc.SXL = 0; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); g_reg_file.fctl.be = 1; g_reg_file.capabilities.end = 1; @@ -1032,7 +1032,7 @@ main(void) { fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 23, 0xdeadbeec) < 0 ) ); // Update memory to mark invalid DC.tc.V = 0; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); // Cached copy should apply send_translation_request(0x012345, pid_valid, 0x99, no_write, exec_req, priv_req, 0, at, 0xdeadbeef, 16, (no_write ^1), &req, &rsp); @@ -1045,7 +1045,7 @@ main(void) { fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 258, 0) < 0 ) ); DC.tc.V = 1; DC.tc.EN_ATS = 1; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); END_TEST(); START_TEST("IOFENCE"); @@ -1054,11 +1054,11 @@ main(void) { for ( PW = 0; PW < 2; PW++ ) { for ( AV = 0; AV < 2; AV++ ) { iofence_data = 0x1234567812345678; - write_memory((char *)&iofence_data, (iofence_PPN * PAGESIZE), 8); + write_memory_test((char *)&iofence_data, (iofence_PPN * PAGESIZE), 8); pr_go_requested = 0; pw_go_requested = 0; iofence(IOFENCE_C, PR, PW, AV, 0, (iofence_PPN * PAGESIZE), 0xDEADBEEF); - read_memory((iofence_PPN * PAGESIZE), 8, (char *)&iofence_data); + read_memory_test((iofence_PPN * PAGESIZE), 8, (char *)&iofence_data); fail_if( ( AV == 1 && iofence_data != 0x12345678DEADBEEF ) ); fail_if( ( AV == 0 && iofence_data != 0x1234567812345678 ) ); fail_if( ( PR != pr_go_requested ) ); @@ -1070,57 +1070,57 @@ main(void) { iofence_data = 0x1234567812345678; pr_go_requested = 0; pw_go_requested = 0; - write_memory((char *)&iofence_data, (iofence_PPN * PAGESIZE), 8); + write_memory_test((char *)&iofence_data, (iofence_PPN * PAGESIZE), 8); iofence(IOFENCE_C+1, 1, 0, 1, 0, (iofence_PPN * PAGESIZE), 0xDEADBEEF); cqcsr.raw = read_register(CQCSR_OFFSET, 4); fail_if( ( cqcsr.cmd_ill != 1 ) ); - read_memory((iofence_PPN * PAGESIZE), 8, (char *)&iofence_data); + read_memory_test((iofence_PPN * PAGESIZE), 8, (char *)&iofence_data); fail_if( ( iofence_data != 0x1234567812345678 ) ); fail_if( ( 0 != pr_go_requested ) ); // Queue another - since illegal is set, head should not move iofence(IOFENCE_C, 1, 0, 1, 0, (iofence_PPN * PAGESIZE), 0xDEADBEEF); fail_if( ( (read_register(CQH_OFFSET, 4) + 2) != read_register(CQT_OFFSET, 4) ) ); - read_memory((iofence_PPN * PAGESIZE), 8, (char *)&iofence_data); + read_memory_test((iofence_PPN * PAGESIZE), 8, (char *)&iofence_data); fail_if( ( iofence_data != 0x1234567812345678 ) ); fail_if( ( 0 != pr_go_requested ) ); // fix the illegal commend cqb.raw = read_register(CQB_OFFSET, 8); cqh.raw = read_register(CQH_OFFSET, 4); - read_memory(((cqb.ppn * PAGESIZE) | (cqh.index * 16)), 16, (char *)&cmd); + read_memory_test(((cqb.ppn * PAGESIZE) | (cqh.index * 16)), 16, (char *)&cmd); cmd.iofence.func3 = IOFENCE_C; - write_memory((char *)&cmd, ((cqb.ppn * PAGESIZE) | (cqh.index * 16)), 16); + write_memory_test((char *)&cmd, ((cqb.ppn * PAGESIZE) | (cqh.index * 16)), 16); // Clear the illegal write_register(CQCSR_OFFSET, 4, cqcsr.raw); process_commands(); fail_if( ( (read_register(CQH_OFFSET, 4) + 1) != read_register(CQT_OFFSET, 4) ) ); - read_memory((iofence_PPN * PAGESIZE), 8, (char *)&iofence_data); + read_memory_test((iofence_PPN * PAGESIZE), 8, (char *)&iofence_data); fail_if( ( iofence_data != 0x12345678DEADBEEF ) ); fail_if( ( 1 != pr_go_requested ) ); iofence_data = 0x1234567812345678; pr_go_requested = 0; pw_go_requested = 0; - write_memory((char *)&iofence_data, (iofence_PPN * PAGESIZE), 8); + write_memory_test((char *)&iofence_data, (iofence_PPN * PAGESIZE), 8); process_commands(); fail_if( ( (read_register(CQH_OFFSET, 4)) != read_register(CQT_OFFSET, 4) ) ); - read_memory((iofence_PPN * PAGESIZE), 8, (char *)&iofence_data); + read_memory_test((iofence_PPN * PAGESIZE), 8, (char *)&iofence_data); fail_if( ( iofence_data != 0x12345678DEADBEEF ) ); fail_if( ( 1 != pr_go_requested ) ); iofence_data = 0x1234567812345678; pr_go_requested = 0; pw_go_requested = 0; - write_memory((char *)&iofence_data, (iofence_PPN * PAGESIZE), 8); + write_memory_test((char *)&iofence_data, (iofence_PPN * PAGESIZE), 8); // Set WSI - not supported in this config iofence(IOFENCE_C, 1, 0, 1, 1, (iofence_PPN * PAGESIZE), 0xDEADBEEF); cqcsr.raw = read_register(CQCSR_OFFSET, 4); fail_if( ( cqcsr.cmd_ill != 1 ) ); - read_memory((iofence_PPN * PAGESIZE), 8, (char *)&iofence_data); + read_memory_test((iofence_PPN * PAGESIZE), 8, (char *)&iofence_data); fail_if( ( iofence_data != 0x1234567812345678 ) ); fail_if( ( 0 != pr_go_requested ) ); fail_if( ( (read_register(CQH_OFFSET, 4) + 1) != read_register(CQT_OFFSET, 4) ) ); @@ -1129,19 +1129,19 @@ main(void) { // fix the illegal commend cqb.raw = read_register(CQB_OFFSET, 8); cqh.raw = read_register(CQH_OFFSET, 4); - read_memory(((cqb.ppn * PAGESIZE) | (cqh.index * 16)), 16, (char *)&cmd); + read_memory_test(((cqb.ppn * PAGESIZE) | (cqh.index * 16)), 16, (char *)&cmd); cmd.iofence.wsi = 0; - write_memory((char *)&cmd, ((cqb.ppn * PAGESIZE) | (cqh.index * 16)), 16); + write_memory_test((char *)&cmd, ((cqb.ppn * PAGESIZE) | (cqh.index * 16)), 16); process_commands(); fail_if( ( (read_register(CQH_OFFSET, 4)) != read_register(CQT_OFFSET, 4) ) ); - read_memory((iofence_PPN * PAGESIZE), 8, (char *)&iofence_data); + read_memory_test((iofence_PPN * PAGESIZE), 8, (char *)&iofence_data); fail_if( ( iofence_data != 0x12345678DEADBEEF ) ); fail_if( ( 1 != pr_go_requested ) ); iofence_data = 0x1234567812345678; pr_go_requested = 0; pw_go_requested = 0; - write_memory((char *)&iofence_data, (iofence_PPN * PAGESIZE), 8); + write_memory_test((char *)&iofence_data, (iofence_PPN * PAGESIZE), 8); // Cause command queue memory fault cqb.raw = read_register(CQB_OFFSET, 8); @@ -1151,7 +1151,7 @@ main(void) { iofence(IOFENCE_C, 1, 0, 1, 0, (iofence_PPN * PAGESIZE), 0xDEADBEE1); cqcsr.raw = read_register(CQCSR_OFFSET, 4); fail_if( ( cqcsr.cqmf != 1 ) ); - read_memory((iofence_PPN * PAGESIZE), 8, (char *)&iofence_data); + read_memory_test((iofence_PPN * PAGESIZE), 8, (char *)&iofence_data); fail_if( ( iofence_data != 0x1234567812345678 ) ); fail_if( ( 0 != pr_go_requested ) ); fail_if( ( (read_register(CQH_OFFSET, 4) + 1) != read_register(CQT_OFFSET, 4) ) ); @@ -1159,7 +1159,7 @@ main(void) { // Queue another - since cqmf is set, head should not move iofence(IOFENCE_C, 0, 1, 1, 0, (iofence_PPN * PAGESIZE), 0xDEADBEE2); fail_if( ( (read_register(CQH_OFFSET, 4) + 2) != read_register(CQT_OFFSET, 4) ) ); - read_memory((iofence_PPN * PAGESIZE), 8, (char *)&iofence_data); + read_memory_test((iofence_PPN * PAGESIZE), 8, (char *)&iofence_data); fail_if( ( iofence_data != 0x1234567812345678 ) ); fail_if( ( 0 != pr_go_requested ) ); // Clear the cqmf @@ -1167,13 +1167,13 @@ main(void) { write_register(CQCSR_OFFSET, 4, cqcsr.raw); process_commands(); fail_if( ( (read_register(CQH_OFFSET, 4) + 1) != read_register(CQT_OFFSET, 4) ) ); - read_memory((iofence_PPN * PAGESIZE), 8, (char *)&iofence_data); + read_memory_test((iofence_PPN * PAGESIZE), 8, (char *)&iofence_data); fail_if( ( iofence_data != 0x12345678DEADBEE1 ) ); fail_if( ( 1 != pr_go_requested ) ); fail_if( ( 0 != pw_go_requested ) ); process_commands(); fail_if( ( (read_register(CQH_OFFSET, 4)) != read_register(CQT_OFFSET, 4) ) ); - read_memory((iofence_PPN * PAGESIZE), 8, (char *)&iofence_data); + read_memory_test((iofence_PPN * PAGESIZE), 8, (char *)&iofence_data); fail_if( ( iofence_data != 0x12345678DEADBEE2 ) ); fail_if( ( 0 != pr_go_requested ) ); fail_if( ( 1 != pw_go_requested ) ); @@ -1181,7 +1181,7 @@ main(void) { iofence_data = 0x1234567812345678; pr_go_requested = 0; pw_go_requested = 0; - write_memory((char *)&iofence_data, (iofence_PPN * PAGESIZE), 8); + write_memory_test((char *)&iofence_data, (iofence_PPN * PAGESIZE), 8); // Cause memory fault on completion buffer access_viol_addr = iofence_PPN * PAGESIZE; @@ -1189,7 +1189,7 @@ main(void) { iofence(IOFENCE_C, 1, 0, 1, 0, (iofence_PPN * PAGESIZE), 0xDEADBEE1); cqcsr.raw = read_register(CQCSR_OFFSET, 4); fail_if( ( cqcsr.cqmf != 1 ) ); - read_memory((iofence_PPN * PAGESIZE), 8, (char *)&iofence_data); + read_memory_test((iofence_PPN * PAGESIZE), 8, (char *)&iofence_data); fail_if( ( iofence_data != 0x1234567812345678 ) ); fail_if( ( (read_register(CQH_OFFSET, 4) + 1) != read_register(CQT_OFFSET, 4) ) ); @@ -1198,20 +1198,20 @@ main(void) { write_register(CQCSR_OFFSET, 4, cqcsr.raw); process_commands(); fail_if( ( (read_register(CQH_OFFSET, 4) ) != read_register(CQT_OFFSET, 4) ) ); - read_memory((iofence_PPN * PAGESIZE), 8, (char *)&iofence_data); + read_memory_test((iofence_PPN * PAGESIZE), 8, (char *)&iofence_data); fail_if( ( iofence_data != 0x12345678DEADBEE1 ) ); iofence_data = 0x1234567812345678; pr_go_requested = 0; pw_go_requested = 0; - write_memory((char *)&iofence_data, (iofence_PPN * PAGESIZE), 8); + write_memory_test((char *)&iofence_data, (iofence_PPN * PAGESIZE), 8); // Cause memory fault on completion buffer access_viol_addr = iofence_PPN * PAGESIZE; iofence(IOFENCE_C, 1, 0, 1, 0, (iofence_PPN * PAGESIZE), 0xDEADBEE1); cqcsr.raw = read_register(CQCSR_OFFSET, 4); fail_if( ( cqcsr.cqmf != 1 ) ); - read_memory((iofence_PPN * PAGESIZE), 8, (char *)&iofence_data); + read_memory_test((iofence_PPN * PAGESIZE), 8, (char *)&iofence_data); fail_if( ( iofence_data != 0x1234567812345678 ) ); fail_if( ( (read_register(CQH_OFFSET, 4) + 1) != read_register(CQT_OFFSET, 4) ) ); cqcsr.cqen = 0; @@ -1362,7 +1362,7 @@ main(void) { DC.iohgatp.MODE = IOHGATP_Sv39x4; gpa = 512UL * 512UL * PAGESIZE; } - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); iodir(INVAL_DDT, 1, 0x012345, 0); iotinval(GVMA, 1, 0, 0, DC.iohgatp.GSCID, 0, 0); for ( i = 0; i < 5; i++ ) { @@ -1401,7 +1401,7 @@ main(void) { gpte.X = 0; gpte.W = 0; gpte.R = 0; - write_memory((char *)&gpte, pte_addr, 8); + write_memory_test((char *)&gpte, pte_addr, 8); iotinval(GVMA, 0, 0, 0, 0, 0, 0); iommu_translate_iova(&req, &rsp); fail_if( ( rsp.status != SUCCESS ) ); @@ -1410,7 +1410,7 @@ main(void) { gpte.X = 1; gpte.W = 1; gpte.R = 1; - write_memory((char *)&gpte, pte_addr, 8); + write_memory_test((char *)&gpte, pte_addr, 8); iotinval(GVMA, 0, 0, 0, 0, 0, 0); } } @@ -1427,7 +1427,7 @@ main(void) { if ( i == 2 ) g_reg_file.capabilities.Sv48x4 = 1; if ( i == 3 ) g_reg_file.capabilities.Sv57x4 = 1; DC.iohgatp.MODE = IOHGATP_Bare; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); iodir(INVAL_DDT, 1, 0x012345, 0); iotinval(VMA, 0, 0, 0, 0, 0, 0); gpa = 512UL * 512UL * PAGESIZE; @@ -1471,16 +1471,16 @@ main(void) { DC.iohgatp.MODE = IOHGATP_Sv57x4; gpa = 512UL * 512UL * 512UL * 512UL * PAGESIZE; gpa = gpa * 16; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); iodir(INVAL_DDT, 1, 0x012345, 0); gpa = gpa | ((1 << (i * 9)) * PAGESIZE) | 2048; req.tr.iova = gpa; gpte.PPN = 512UL * 512UL * 512UL * 512UL; gpte_addr = add_g_stage_pte(DC.iohgatp, gpa, gpte, 4); - read_memory(gpte_addr, 8, (char *)&gpte); + read_memory_test(gpte_addr, 8, (char *)&gpte); gpte.U = 0; - write_memory((char *)&gpte, gpte_addr, 8); + write_memory_test((char *)&gpte, gpte_addr, 8); req.tr.read_writeAMO = WRITE; iommu_translate_iova(&req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 23, ((gpa >> 2) << 2)) < 0 ) ); @@ -1491,7 +1491,7 @@ main(void) { gpte.U = 1; gpte.W = 1; gpte.R = 0; - write_memory((char *)&gpte, gpte_addr, 8); + write_memory_test((char *)&gpte, gpte_addr, 8); req.tr.read_writeAMO = WRITE; iommu_translate_iova(&req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 23, ((gpa >> 2) << 2)) < 0 ) ); @@ -1502,7 +1502,7 @@ main(void) { gpte.X = 1; gpte.W = 0; gpte.R = 0; - write_memory((char *)&gpte, gpte_addr, 8); + write_memory_test((char *)&gpte, gpte_addr, 8); req.tr.read_writeAMO = WRITE; iommu_translate_iova(&req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 23, ((gpa >> 2) << 2)) < 0 ) ); @@ -1514,12 +1514,12 @@ main(void) { gpte.X = 1; gpte.W = 1; gpte.R = 1; - write_memory((char *)&gpte, gpte_addr, 8); + write_memory_test((char *)&gpte, gpte_addr, 8); req.tr.read_writeAMO = READ; iommu_translate_iova(&req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 21, ((gpa >> 2) << 2)) < 0 ) ); gpte.PPN = 512UL * 512UL * 512UL * 512UL; - write_memory((char *)&gpte, gpte_addr, 8); + write_memory_test((char *)&gpte, gpte_addr, 8); access_viol_addr = gpte_addr; req.tr.read_writeAMO = WRITE; @@ -1579,26 +1579,26 @@ main(void) { iommu_translate_iova(&req, &rsp); fail_if( ( rsp.status != SUCCESS ) ); gpte.PPN = 512UL * 512UL * 512UL ; - write_memory((char *)&gpte, gpte_addr, 8); + write_memory_test((char *)&gpte, gpte_addr, 8); iommu_translate_iova(&req, &rsp); fail_if( ( rsp.status != SUCCESS ) ); iotinval(GVMA, 1, 0, 0, 1, 0, 0); iommu_translate_iova(&req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 21, ((gpa >> 2) << 2)) < 0 ) ); gpte.PPN = 512UL * 512UL * 512UL * 512UL; - write_memory((char *)&gpte, gpte_addr, 8); + write_memory_test((char *)&gpte, gpte_addr, 8); iommu_translate_iova(&req, &rsp); fail_if( ( rsp.status != SUCCESS ) ); iotinval(GVMA, 1, 1, 0, 1, 0, req.tr.iova); gpte.W = 0; - write_memory((char *)&gpte, gpte_addr, 8); + write_memory_test((char *)&gpte, gpte_addr, 8); iommu_translate_iova(&req, &rsp); fail_if( ( rsp.status != SUCCESS ) ); req.tr.read_writeAMO = WRITE; iommu_translate_iova(&req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 23, ((gpa >> 2) << 2)) < 0 ) ); gpte.W = 1; - write_memory((char *)&gpte, gpte_addr, 8); + write_memory_test((char *)&gpte, gpte_addr, 8); iotinval(GVMA, 1, 1, 0, 1, 0, req.tr.iova); iommu_translate_iova(&req, &rsp); fail_if( ( rsp.status != SUCCESS ) ); @@ -1609,9 +1609,9 @@ main(void) { 1, 1, 0, 0, 0, IOHGATP_Bare, IOSATP_Sv57, PDTP_Bare, MSIPTP_Flat, 1, 0xF0F00FF0FF, 0x1903020124); - read_memory(DC_addr, 64, (char *)&DC); + read_memory_test(DC_addr, 64, (char *)&DC); DC.ta.PSCID = 10; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); req.device_id = 0x012349; req.pid_valid = 0; req.is_cxl_dev = 0; @@ -1641,7 +1641,7 @@ main(void) { DC.fsc.iosatp.MODE = IOSATP_Sv39; gva = 512UL * 512UL * PAGESIZE; } - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); iodir(INVAL_DDT, 1, 0x012349, 0); for ( i = 0; i < 5; i++ ) { if ( (i == 4) && DC.fsc.iosatp.MODE != IOSATP_Sv57 ) continue; @@ -1679,7 +1679,7 @@ main(void) { pte.X = 0; pte.W = 0; pte.R = 0; - write_memory((char *)&pte, pte_addr, 8); + write_memory_test((char *)&pte, pte_addr, 8); iotinval(VMA, 0, 0, 0, 0, 0, 0); iommu_translate_iova(&req, &rsp); fail_if( ( rsp.status != SUCCESS ) ); @@ -1688,7 +1688,7 @@ main(void) { pte.X = 1; pte.W = 1; pte.R = 1; - write_memory((char *)&pte, pte_addr, 8); + write_memory_test((char *)&pte, pte_addr, 8); iotinval(VMA, 0, 0, 0, 0, 0, 0); } } @@ -1705,7 +1705,7 @@ main(void) { if ( i == 2 ) g_reg_file.capabilities.Sv48 = 1; if ( i == 3 ) g_reg_file.capabilities.Sv57 = 1; DC.fsc.iosatp.MODE = IOSATP_Bare; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); iodir(INVAL_DDT, 1, 0x012349, 0); iotinval(VMA, 0, 0, 0, 0, 0, 0); gva = 512UL * 512UL * PAGESIZE; @@ -1755,7 +1755,7 @@ main(void) { gva = 512UL * 512UL * PAGESIZE; i = 39; } - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); iodir(INVAL_DDT, 1, 0x012349, 0); while ( i < 64 ) { @@ -1788,7 +1788,7 @@ main(void) { pte.D = 0; pte.PBMT = PMA; DC.fsc.iosatp.MODE = IOSATP_Sv57; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); iodir(INVAL_DDT, 1, 0x012349, 0); gva = 512UL * 512UL * 512UL * 512UL * PAGESIZE; gva = gva * 16; @@ -1796,12 +1796,12 @@ main(void) { req.tr.iova = gva; pte.PPN = 512UL * 512UL * 512UL * 512UL; pte_addr = add_s_stage_pte(DC.fsc.iosatp, gva, pte, 4, DC.tc.SXL); - read_memory(pte_addr, 8, (char *)&pte); + read_memory_test(pte_addr, 8, (char *)&pte); pte.U = 1; pte.W = 1; pte.R = 0; - write_memory((char *)&pte, pte_addr, 8); + write_memory_test((char *)&pte, pte_addr, 8); req.tr.read_writeAMO = WRITE; iommu_translate_iova(&req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 15, 0) < 0 ) ); @@ -1812,7 +1812,7 @@ main(void) { pte.X = 1; pte.W = 0; pte.R = 0; - write_memory((char *)&pte, pte_addr, 8); + write_memory_test((char *)&pte, pte_addr, 8); req.tr.read_writeAMO = WRITE; iommu_translate_iova(&req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 15, 0) < 0 ) ); @@ -1824,19 +1824,19 @@ main(void) { pte.X = 1; pte.W = 1; pte.R = 1; - write_memory((char *)&pte, pte_addr, 8); + write_memory_test((char *)&pte, pte_addr, 8); req.tr.read_writeAMO = READ; iommu_translate_iova(&req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 13, 0) < 0 ) ); pte.PPN = 512UL * 512UL * 512UL * 512UL; - write_memory((char *)&pte, pte_addr, 8); + write_memory_test((char *)&pte, pte_addr, 8); pte.PBMT = 3; - write_memory((char *)&pte, pte_addr, 8); + write_memory_test((char *)&pte, pte_addr, 8); iommu_translate_iova(&req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 13, 0) < 0 ) ); pte.PBMT = 0; - write_memory((char *)&pte, pte_addr, 8); + write_memory_test((char *)&pte, pte_addr, 8); access_viol_addr = pte_addr; @@ -1850,14 +1850,14 @@ main(void) { // Check DTF temp = read_register(FQT_OFFSET, 4); DC.tc.DTF = 1; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); iodir(INVAL_DDT, 1, 0x012349, 0); req.tr.read_writeAMO = READ; iommu_translate_iova(&req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 0, 0) < 0 ) ); fail_if( ( temp != read_register(FQT_OFFSET, 4) ) ); DC.tc.DTF = 0; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); iodir(INVAL_DDT, 1, 0x012349, 0); iommu_translate_iova(&req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 5, 0) < 0 ) ); @@ -1889,14 +1889,14 @@ main(void) { // Check DTF temp = read_register(FQT_OFFSET, 4); DC.tc.DTF = 1; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); iodir(INVAL_DDT, 1, 0x012349, 0); req.tr.read_writeAMO = READ; iommu_translate_iova(&req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 0, 0) < 0 ) ); fail_if( ( temp != read_register(FQT_OFFSET, 4) ) ); DC.tc.DTF = 0; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); iodir(INVAL_DDT, 1, 0x012349, 0); iommu_translate_iova(&req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 274, 0) < 0 ) ); @@ -1935,7 +1935,7 @@ main(void) { fail_if( ( rsp.status != SUCCESS ) ); // Corrupt PTE pte.PPN = 512UL * 512UL * 512UL ; - write_memory((char *)&pte, pte_addr, 8); + write_memory_test((char *)&pte, pte_addr, 8); // Hit in TLB iommu_translate_iova(&req, &rsp); fail_if( ( rsp.status != SUCCESS ) ); @@ -1946,14 +1946,14 @@ main(void) { fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 13, 0) < 0 ) ); // Correct fault pte.PPN = 512UL * 512UL * 512UL * 512UL; - write_memory((char *)&pte, pte_addr, 8); + write_memory_test((char *)&pte, pte_addr, 8); // AV=0, PSCV=1 iommu_translate_iova(&req, &rsp); fail_if( ( rsp.status != SUCCESS ) ); // Corrupt PTE pte.PPN = 512UL * 512UL * 512UL ; - write_memory((char *)&pte, pte_addr, 8); + write_memory_test((char *)&pte, pte_addr, 8); // Hit in TLB iommu_translate_iova(&req, &rsp); fail_if( ( rsp.status != SUCCESS ) ); @@ -1973,7 +1973,7 @@ main(void) { } // Correct fault pte.PPN = 512UL * 512UL * 512UL * 512UL; - write_memory((char *)&pte, pte_addr, 8); + write_memory_test((char *)&pte, pte_addr, 8); // AV=1, PSCV=0 // Fill TLB @@ -1981,7 +1981,7 @@ main(void) { fail_if( ( rsp.status != SUCCESS ) ); // Corrupt PTE pte.PPN = 512UL * 512UL * 512UL ; - write_memory((char *)&pte, pte_addr, 8); + write_memory_test((char *)&pte, pte_addr, 8); // Hit in TLB iommu_translate_iova(&req, &rsp); fail_if( ( rsp.status != SUCCESS ) ); @@ -1992,16 +1992,16 @@ main(void) { fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 13, 0) < 0 ) ); // Correct fault pte.PPN = 512UL * 512UL * 512UL * 512UL; - write_memory((char *)&pte, pte_addr, 8); + write_memory_test((char *)&pte, pte_addr, 8); } pte.W = 0; - write_memory((char *)&pte, pte_addr, 8); + write_memory_test((char *)&pte, pte_addr, 8); // Fill TLB iommu_translate_iova(&req, &rsp); fail_if( ( rsp.status != SUCCESS ) ); // Fault from TLB pte.W = 1; - write_memory((char *)&pte, pte_addr, 8); + write_memory_test((char *)&pte, pte_addr, 8); req.tr.read_writeAMO = WRITE; iommu_translate_iova(&req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 15, 0) < 0 ) ); @@ -2143,7 +2143,7 @@ main(void) { pte.PBMT = PMA; DC.fsc.iosatp.MODE = IOSATP_Sv57; DC.ta.PSCID = 10; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); iodir(INVAL_DDT, 1, 0x012349, 0); gva = 512UL * 512UL * 512UL * 512UL * PAGESIZE; gva = gva * 24; @@ -2231,9 +2231,9 @@ main(void) { 1, 1, 0, 0, 0, IOHGATP_Sv48x4, IOSATP_Bare, PD20, MSIPTP_Flat, 1, 0xFFFFFFFFFF, 0x1000000000); - read_memory(DC_addr, 64, (char *)&DC); + read_memory_test(DC_addr, 64, (char *)&DC); DC.msiptp.MODE = MSIPTP_Off; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); // Invalid non-leaf PDTE send_translation_request(0x112233, 1, 0xBABEC, 0, @@ -2280,58 +2280,58 @@ main(void) { PC.ta.ENS = 1; PC.ta.SUM = 1; PC_addr = add_process_context(&DC, &PC, 0xBABEC); - fail_if( (read_memory(PC_addr, 16, (char *)&PC) != 0) ); + fail_if( (read_memory_test(PC_addr, 16, (char *)&PC) != 0) ); // misconfigured NL PTE fail_if( (translate_gpa(DC.iohgatp, DC.fsc.pdtp.PPN * PAGESIZE, &temp) == -1) ); temp = (temp) | (get_bits(19, 17, 0xBABEC) * 8); - read_memory(temp, 8, (char *)&pdte); + read_memory_test(temp, 8, (char *)&pdte); pdte.reserved0 = 1; - write_memory((char *)&pdte, temp, 8); + write_memory_test((char *)&pdte, temp, 8); send_translation_request(0x112233, 1, 0xBABEC, 0, 0, 1, 0, ADDR_TYPE_UNTRANSLATED, 0xdeadbeef, 1, WRITE, &req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 267, 0) < 0 ) ); pdte.reserved0 = 0; - write_memory((char *)&pdte, temp, 8); + write_memory_test((char *)&pdte, temp, 8); // Misconfigured PC PC.ta.reserved0 = 1; - write_memory((char *)&PC, PC_addr, 16); + write_memory_test((char *)&PC, PC_addr, 16); send_translation_request(0x112233, 1, 0xBABEC, 0, 0, 1, 0, ADDR_TYPE_UNTRANSLATED, 0xdeadbeef, 1, WRITE, &req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 267, 0) < 0 ) ); PC.ta.reserved0 = 0; - write_memory((char *)&PC, PC_addr, 16); + write_memory_test((char *)&PC, PC_addr, 16); PC.ta.reserved1 = 1; - write_memory((char *)&PC, PC_addr, 16); + write_memory_test((char *)&PC, PC_addr, 16); send_translation_request(0x112233, 1, 0xBABEC, 0, 0, 1, 0, ADDR_TYPE_UNTRANSLATED, 0xdeadbeef, 1, WRITE, &req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 267, 0) < 0 ) ); PC.ta.reserved1 = 0; - write_memory((char *)&PC, PC_addr, 16); + write_memory_test((char *)&PC, PC_addr, 16); PC.ta.reserved0 = 1; PC.ta.reserved1 = 1; - write_memory((char *)&PC, PC_addr, 16); + write_memory_test((char *)&PC, PC_addr, 16); send_translation_request(0x112233, 1, 0xBABEC, 0, 0, 1, 0, ADDR_TYPE_UNTRANSLATED, 0xdeadbeef, 1, WRITE, &req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 267, 0) < 0 ) ); PC.ta.reserved0 = 0; PC.ta.reserved1 = 0; - write_memory((char *)&PC, PC_addr, 16); + write_memory_test((char *)&PC, PC_addr, 16); // Invalid PC PC.ta.V = 0; - write_memory((char *)&PC, PC_addr, 16); + write_memory_test((char *)&PC, PC_addr, 16); send_translation_request(0x112233, 1, 0xBABEC, 0, 0, 1, 0, ADDR_TYPE_UNTRANSLATED, 0xdeadbeef, 1, WRITE, &req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 266, 0) < 0 ) ); PC.ta.V = 1; - write_memory((char *)&PC, PC_addr, 16); + write_memory_test((char *)&PC, PC_addr, 16); // PC access violation access_viol_addr = PC_addr; @@ -2350,7 +2350,7 @@ main(void) { g_reg_file.fctl.gxl = 0; DC.tc.SXL = 0; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); iodir(INVAL_DDT, 1, 0x112233, 0); g_reg_file.capabilities.Sv57 = 0; g_reg_file.capabilities.Sv48 = 0; @@ -2358,7 +2358,7 @@ main(void) { g_reg_file.capabilities.Sv32 = 0; for ( j = 1; j < 16; j++ ) { PC.fsc.iosatp.MODE = j; - write_memory((char *)&PC, PC_addr, 16); + write_memory_test((char *)&PC, PC_addr, 16); send_translation_request(0x112233, 1, 0xBABEC, 0, 0, 1, 0, ADDR_TYPE_UNTRANSLATED, 0xdeadbeef, 1, WRITE, &req, &rsp); @@ -2369,21 +2369,21 @@ main(void) { g_reg_file.capabilities.Sv39 = 1; g_reg_file.capabilities.Sv32 = 1; PC.fsc.iosatp.MODE = IOSATP_Sv48; - write_memory((char *)&PC, PC_addr, 16); + write_memory_test((char *)&PC, PC_addr, 16); // guest page fault on PC walk gpa = (DC.fsc.pdtp.PPN * PAGESIZE) | (get_bits(19, 17, 0xBABEC) * 8); temp = translate_gpa(DC.iohgatp, gpa, &temp); fail_if( (temp == -1) ); - read_memory(temp, 8, (char *)&gpte); + read_memory_test(temp, 8, (char *)&gpte); gpte.V = 0; - write_memory((char *)&gpte, temp, 8); + write_memory_test((char *)&gpte, temp, 8); send_translation_request(0x112233, 1, 0xBABEC, 0, 0, 1, 0, ADDR_TYPE_UNTRANSLATED, 0xdeadbeef, 1, WRITE, &req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 21, ((gpa & ~0x3UL) | 1)) < 0 ) ); gpte.V = 1; - write_memory((char *)&gpte, temp, 8); + write_memory_test((char *)&gpte, temp, 8); // GPTE access fault access_viol_addr = temp; @@ -2438,7 +2438,7 @@ main(void) { // fail_if if PC was cached PC.fsc.iosatp.reserved = 1; - write_memory((char *)&PC, PC_addr, 16); + write_memory_test((char *)&PC, PC_addr, 16); iotinval(VMA, 1, 1, 1, 0x1234, 10, gva); send_translation_request(0x112233, 1, 0xBABEC, 0, 0, 1, 0, ADDR_TYPE_UNTRANSLATED, gva, @@ -2453,9 +2453,9 @@ main(void) { // fix the illegal commend cqb.raw = read_register(CQB_OFFSET, 8); cqh.raw = read_register(CQH_OFFSET, 4); - read_memory(((cqb.ppn * PAGESIZE) | (cqh.index * 16)), 16, (char *)&cmd); + read_memory_test(((cqb.ppn * PAGESIZE) | (cqh.index * 16)), 16, (char *)&cmd); cmd.iodir.dv = 1; - write_memory((char *)&cmd, ((cqb.ppn * PAGESIZE) | (cqh.index * 16)), 16); + write_memory_test((char *)&cmd, ((cqb.ppn * PAGESIZE) | (cqh.index * 16)), 16); write_register(CQCSR_OFFSET, 4, cqcsr.raw); // Invalidate PC - DID must not be too wide @@ -2478,29 +2478,29 @@ main(void) { // Fix PC Translation should succeed PC.fsc.iosatp.reserved = 0; - write_memory((char *)&PC, PC_addr, 16); + write_memory_test((char *)&PC, PC_addr, 16); send_translation_request(0x112233, 1, 0xBABEC, 0, 0, 1, 0, ADDR_TYPE_UNTRANSLATED, gva, 1, WRITE, &req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, SUCCESS, 0, 0) < 0 ) ); // Check A/D update from TLB - read_memory(pte_addr, 8, (char *)&pte); + read_memory_test(pte_addr, 8, (char *)&pte); pte.A = pte.D = 0; - write_memory((char *)&pte, pte_addr, 8); + write_memory_test((char *)&pte, pte_addr, 8); iotinval(VMA, 1, 1, 1, 0x1234, 10, gva); send_translation_request(0x112233, 1, 0xBABEC, 0, 0, 1, 0, ADDR_TYPE_UNTRANSLATED, gva, 1, READ, &req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, SUCCESS, 0, 0) < 0 ) ); - read_memory(pte_addr, 8, (char *)&pte); + read_memory_test(pte_addr, 8, (char *)&pte); fail_if( ( pte.A == 0 ) ); fail_if( ( pte.D == 1 ) ); send_translation_request(0x112233, 1, 0xBABEC, 0, 0, 1, 0, ADDR_TYPE_UNTRANSLATED, gva, 1, WRITE, &req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, SUCCESS, 0, 0) < 0 ) ); - read_memory(pte_addr, 8, (char *)&pte); + read_memory_test(pte_addr, 8, (char *)&pte); fail_if( ( pte.A == 0 ) ); fail_if( ( pte.D == 0 ) ); @@ -2514,7 +2514,7 @@ main(void) { // Test T2GPA DC.tc.T2GPA = 1; DC.tc.EN_ATS = 1; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); iodir(INVAL_DDT, 1, 0x112233, 0); send_translation_request(0x112233, 1, 0xBABEC, 0, 0, 1, 0, ADDR_TYPE_PCIE_ATS_TRANSLATION_REQUEST, gva, @@ -2529,7 +2529,7 @@ main(void) { // Disable T2GPA and test 2 stage translation DC.tc.T2GPA = 0; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); iodir(INVAL_DDT, 1, 0x112233, 0); send_translation_request(0x112233, 1, 0xBABEC, 0, 0, 1, 0, ADDR_TYPE_PCIE_ATS_TRANSLATION_REQUEST, gva, @@ -2544,7 +2544,7 @@ main(void) { // Disable supervisory requests PC.ta.ENS = 0; - write_memory((char *)&PC, PC_addr, 64); + write_memory_test((char *)&PC, PC_addr, 64); iodir(INVAL_PDT, 1, 0x112233, 0xBABEC); send_translation_request(0x112233, 1, 0xBABEC, 0, 0, 1, 0, ADDR_TYPE_PCIE_ATS_TRANSLATION_REQUEST, gva, @@ -2554,7 +2554,7 @@ main(void) { // Disable supv to user access PC.ta.ENS = 1; PC.ta.SUM = 0; - write_memory((char *)&PC, PC_addr, 64); + write_memory_test((char *)&PC, PC_addr, 64); iodir(INVAL_PDT, 1, 0x112233, 0xBABEC); send_translation_request(0x112233, 1, 0xBABEC, 0, 0, 1, 0, ADDR_TYPE_PCIE_ATS_TRANSLATION_REQUEST, gva, @@ -2576,28 +2576,28 @@ main(void) { // Too wide PID and invalid PDTP mode DC.fsc.pdtp.MODE = PD8; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); iodir(INVAL_DDT, 1, 0x112233, 0); send_translation_request(0x112233, 1, 0xBABEC, 0, 0, 1, 0, ADDR_TYPE_PCIE_ATS_TRANSLATION_REQUEST, gva, 1, WRITE, &req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 260, 0) < 0 ) ); DC.fsc.pdtp.MODE = PD17; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); iodir(INVAL_DDT, 1, 0x112233, 0); send_translation_request(0x112233, 1, 0xBABEC, 0, 0, 1, 0, ADDR_TYPE_PCIE_ATS_TRANSLATION_REQUEST, gva, 1, WRITE, &req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 260, 0) < 0 ) ); DC.fsc.pdtp.MODE = 9; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); iodir(INVAL_DDT, 1, 0x112233, 0); send_translation_request(0x112233, 1, 0xBABEC, 0, 0, 1, 0, ADDR_TYPE_PCIE_ATS_TRANSLATION_REQUEST, gva, 1, WRITE, &req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 259, 0) < 0 ) ); DC.fsc.pdtp.MODE = PD20; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); iodir(INVAL_DDT, 1, 0x112233, 0); // Do a napot PTE @@ -2638,10 +2638,10 @@ main(void) { 0, 0, 0, ADDR_TYPE_UNTRANSLATED, gva, 1, WRITE, &req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 23, gpa) < 0 ) ); - read_memory(gpte_addr, 8, (char *)&gpte); + read_memory_test(gpte_addr, 8, (char *)&gpte); gpte.PPN &= ~0x4; gpte.PPN |= 0x8; - write_memory((char *)&gpte.raw, gpte_addr, 8); + write_memory_test((char *)&gpte.raw, gpte_addr, 8); send_translation_request(0x112233, 1, 0xBABEC, 0, 0, 0, 0, ADDR_TYPE_UNTRANSLATED, gva, @@ -2653,9 +2653,9 @@ main(void) { // Guest-Page fault on NL S-stage PTE gpte_addr = translate_gpa(DC.iohgatp, (PC.fsc.iosatp.PPN * PAGESIZE), &temp); fail_if( (gpte_addr == -1) ); - read_memory(gpte_addr, 8, (char *)&gpte); + read_memory_test(gpte_addr, 8, (char *)&gpte); gpte.V = 0; - write_memory((char *)&gpte.raw, gpte_addr, 8); + write_memory_test((char *)&gpte.raw, gpte_addr, 8); send_translation_request(0x112233, 1, 0xBABEC, 0, 0, 0, 0, ADDR_TYPE_UNTRANSLATED, gva, 1, WRITE, &req, &rsp); @@ -2664,7 +2664,7 @@ main(void) { gpte.V = 1; gpte.N = 1; - write_memory((char *)&gpte.raw, gpte_addr, 8); + write_memory_test((char *)&gpte.raw, gpte_addr, 8); send_translation_request(0x112233, 1, 0xBABEC, 0, 0, 0, 0, ADDR_TYPE_UNTRANSLATED, gva, 1, WRITE, &req, &rsp); @@ -2672,7 +2672,7 @@ main(void) { ((PC.fsc.iosatp.PPN * PAGESIZE) | 3)) < 0 ) ); gpte.N = 0; gpte.PBMT = 1; - write_memory((char *)&gpte.raw, gpte_addr, 8); + write_memory_test((char *)&gpte.raw, gpte_addr, 8); send_translation_request(0x112233, 1, 0xBABEC, 0, 0, 0, 0, ADDR_TYPE_UNTRANSLATED, gva, 1, WRITE, &req, &rsp); @@ -2680,7 +2680,7 @@ main(void) { ((PC.fsc.iosatp.PPN * PAGESIZE) | 3)) < 0 ) ); gpte.N = 0; gpte.PBMT = 0; - write_memory((char *)&gpte.raw, gpte_addr, 8); + write_memory_test((char *)&gpte.raw, gpte_addr, 8); // Access violation on NL S-stage PTE access_viol_addr = gpte_addr; @@ -2726,7 +2726,7 @@ main(void) { PC.ta.ENS = 1; PC.ta.SUM = 1; PC_addr = add_process_context(&DC, &PC, 0x1000+i); - read_memory(PC_addr, 16, (char *)&PC); + read_memory_test(PC_addr, 16, (char *)&PC); pte.raw = 0; pte.V = 1; pte.R = 1; @@ -2830,7 +2830,7 @@ main(void) { // Two stage translation with default process ID // Enable default process DC.tc.DPE = 1; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); iodir(INVAL_DDT, 1, 0x112233, 0); // transaction with no PASID - should fail as no default process context @@ -2863,7 +2863,7 @@ main(void) { PC.ta.ENS = 1; PC.ta.SUM = 1; PC_addr = add_process_context(&DC, &PC, 0xBABEC); - read_memory(PC_addr, 16, (char *)&PC); + read_memory_test(PC_addr, 16, (char *)&PC); pte.raw = 0; pte.V = 1; @@ -2900,7 +2900,7 @@ main(void) { #endif DC.tc.PDTV = 1; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); iodir(INVAL_DDT, 1, 0x112233, 0); // Add process context @@ -2924,7 +2924,7 @@ main(void) { PC.ta.ENS = 1; PC.ta.SUM = 1; PC_addr = add_process_context(&DC, &PC, 0x7000); - read_memory(PC_addr, 16, (char *)&PC); + read_memory_test(PC_addr, 16, (char *)&PC); pte.raw = 0; pte.V = 1; pte.R = 1; @@ -3033,7 +3033,7 @@ main(void) { pr.DSEG = 0x11; DC.tc.EN_ATS = 0; DC.tc.EN_PRI = 0; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); iodir(INVAL_DDT, 1, 0x112233, 0); exp_msg.RID = 0x2233; exp_msg.DSEG = 0x11; @@ -3049,7 +3049,7 @@ main(void) { pr.DSEG = 0x11; DC.tc.EN_ATS = 1; DC.tc.EN_PRI = 0; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); iodir(INVAL_DDT, 1, 0x112233, 0); exp_msg.RID = 0x2233; exp_msg.DSEG = 0x11; @@ -3066,7 +3066,7 @@ main(void) { DC.tc.EN_ATS = 1; DC.tc.EN_PRI = 1; DC.tc.PRPR = 1; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); iodir(INVAL_DDT, 1, 0x112233, 0); exp_msg.RID = 0x2233; exp_msg.DSEG = 0x11; @@ -3092,7 +3092,7 @@ main(void) { pr.DSEG = 0x11; DC.tc.EN_ATS = 1; DC.tc.EN_PRI = 1; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); iodir(INVAL_DDT, 1, 0x112233, 0); message_received = 0; handle_page_request(&pr); @@ -3108,7 +3108,7 @@ main(void) { DC.tc.EN_ATS = 1; DC.tc.EN_PRI = 1; DC.tc.PRPR = 0; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); iodir(INVAL_DDT, 1, 0x112233, 0); message_received = 0; exp_msg.RID = 0x2233; @@ -3122,7 +3122,7 @@ main(void) { // Set PRPR DC.tc.PRPR = 1; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); iodir(INVAL_DDT, 1, 0x112233, 0); exp_msg.PV = 1; exp_msg.PID = 0xBABEC; @@ -3223,12 +3223,12 @@ main(void) { // Fence it - fence should block iofence_PPN = get_free_ppn(1); iofence_data = 0x1234567812345678; - write_memory((char *)&iofence_data, (iofence_PPN * PAGESIZE), 8); + write_memory_test((char *)&iofence_data, (iofence_PPN * PAGESIZE), 8); pr_go_requested = 0; pw_go_requested = 0; iofence(IOFENCE_C, 1, 1, 1, 0, (iofence_PPN * PAGESIZE), 0xDEADBEEF); // Fence should not complete - read_memory((iofence_PPN * PAGESIZE), 8, (char *)&iofence_data); + read_memory_test((iofence_PPN * PAGESIZE), 8, (char *)&iofence_data); fail_if( ( iofence_data != 0x1234567812345678 ) ); fail_if( ( pr_go_requested == 1) ); fail_if( ( pw_go_requested == 1) ); @@ -3239,7 +3239,7 @@ main(void) { ats_command(INVAL, 1, 0, 0, 0x43, 0x1234, 0x1234000000000000); fail_if( ( message_received == 1 ) ); // Fence should still not complete - read_memory((iofence_PPN * PAGESIZE), 8, (char *)&iofence_data); + read_memory_test((iofence_PPN * PAGESIZE), 8, (char *)&iofence_data); fail_if( ( iofence_data != 0x1234567812345678 ) ); fail_if( ( pr_go_requested == 1 ) ); fail_if( ( pw_go_requested == 1 ) ); @@ -3269,7 +3269,7 @@ main(void) { for ( i = 0; i < 3; i++ ) { fail_if( ( handle_invalidation_completion(&inv_cc) != 0 ) ); // Fence should still not complete - read_memory((iofence_PPN * PAGESIZE), 8, (char *)&iofence_data); + read_memory_test((iofence_PPN * PAGESIZE), 8, (char *)&iofence_data); fail_if( ( iofence_data != 0x1234567812345678 ) ); fail_if( ( pr_go_requested == 1 ) ); fail_if( ( pw_go_requested == 1 ) ); @@ -3282,7 +3282,7 @@ main(void) { for ( i = 0; i < 7; i++ ) { fail_if( ( handle_invalidation_completion(&inv_cc) != 0 ) ); // Fence should still not complete - read_memory((iofence_PPN * PAGESIZE), 8, (char *)&iofence_data); + read_memory_test((iofence_PPN * PAGESIZE), 8, (char *)&iofence_data); fail_if( ( iofence_data != 0x1234567812345678 ) ); fail_if( ( pr_go_requested == 1 ) ); fail_if( ( pw_go_requested == 1 ) ); @@ -3291,7 +3291,7 @@ main(void) { // Send the 8th one fail_if( ( handle_invalidation_completion(&inv_cc) != 0 ) ); // Fence should complete - read_memory((iofence_PPN * PAGESIZE), 8, (char *)&iofence_data); + read_memory_test((iofence_PPN * PAGESIZE), 8, (char *)&iofence_data); fail_if( ( iofence_data != 0x12345678deadbeef ) ); fail_if( ( pr_go_requested != 1 ) ); fail_if( ( pw_go_requested != 1 ) ); @@ -3306,12 +3306,12 @@ main(void) { // Fence it - fence should block iofence_data = 0x1234567812345678; - write_memory((char *)&iofence_data, (iofence_PPN * PAGESIZE), 8); + write_memory_test((char *)&iofence_data, (iofence_PPN * PAGESIZE), 8); pr_go_requested = 0; pw_go_requested = 0; iofence(IOFENCE_C, 1, 1, 1, 0, (iofence_PPN * PAGESIZE), 0xDEADBEEF); // Fence should not complete - read_memory((iofence_PPN * PAGESIZE), 8, (char *)&iofence_data); + read_memory_test((iofence_PPN * PAGESIZE), 8, (char *)&iofence_data); fail_if( ( iofence_data != 0x1234567812345678 ) ); fail_if( ( pr_go_requested == 1) ); fail_if( ( pw_go_requested == 1) ); @@ -3392,12 +3392,12 @@ main(void) { // Fence it - fence should block iofence_PPN = get_free_ppn(1); iofence_data = 0x1234567812345678; - write_memory((char *)&iofence_data, (iofence_PPN * PAGESIZE), 8); + write_memory_test((char *)&iofence_data, (iofence_PPN * PAGESIZE), 8); pr_go_requested = 0; pw_go_requested = 0; iofence(IOFENCE_C, 1, 1, 1, 0, (iofence_PPN * PAGESIZE), 0xDEADBEEF); // Fence should not complete - read_memory((iofence_PPN * PAGESIZE), 8, (char *)&iofence_data); + read_memory_test((iofence_PPN * PAGESIZE), 8, (char *)&iofence_data); fail_if( ( iofence_data != 0x1234567812345678 ) ); fail_if( ( pr_go_requested == 1) ); fail_if( ( pw_go_requested == 1) ); @@ -3433,7 +3433,7 @@ main(void) { 1, 1, 0, 0, 0, IOHGATP_Sv48x4, IOSATP_Bare, PDTP_Bare, MSIPTP_Flat, 1, 0x0000000FF, 0x280000000); - read_memory(DC_addr, 64, (char *)&DC); + read_memory_test(DC_addr, 64, (char *)&DC); gpa = 0x280000003000; // Cause a access violation @@ -3458,14 +3458,14 @@ main(void) { msipte_t msipte; msipte.V = 1; msipte.M = 0x0; - write_memory((char *)&msipte, ((DC.msiptp.PPN * PAGESIZE) + 3 * 16), 16); + write_memory_test((char *)&msipte, ((DC.msiptp.PPN * PAGESIZE) + 3 * 16), 16); send_translation_request(0x042874, 0, 0x0000, 0, 0, 0, 0, ADDR_TYPE_UNTRANSLATED, gpa, 4, WRITE, &req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 263, 0) < 0 ) ); msipte.C = 1; msipte.M = 0x0; - write_memory((char *)&msipte, ((DC.msiptp.PPN * PAGESIZE) + 3 * 16), 16); + write_memory_test((char *)&msipte, ((DC.msiptp.PPN * PAGESIZE) + 3 * 16), 16); send_translation_request(0x042874, 0, 0x0000, 0, 0, 0, 0, ADDR_TYPE_UNTRANSLATED, gpa, 4, WRITE, &req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 263, 0) < 0 ) ); @@ -3473,13 +3473,13 @@ main(void) { msipte.C = 0; msipte.M = 2; msipte.translate_rw.reserved = 0x1; - write_memory((char *)&msipte, ((DC.msiptp.PPN * PAGESIZE) + 3 * 16), 16); + write_memory_test((char *)&msipte, ((DC.msiptp.PPN * PAGESIZE) + 3 * 16), 16); send_translation_request(0x042874, 0, 0x0000, 0, 0, 0, 0, ADDR_TYPE_UNTRANSLATED, gpa, 4, WRITE, &req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 263, 0) < 0 ) ); msipte.translate_rw.reserved = 0x0; msipte.translate_rw.reserved = 0x4; - write_memory((char *)&msipte, ((DC.msiptp.PPN * PAGESIZE) + 3 * 16), 16); + write_memory_test((char *)&msipte, ((DC.msiptp.PPN * PAGESIZE) + 3 * 16), 16); send_translation_request(0x042874, 0, 0x0000, 0, 0, 0, 0, ADDR_TYPE_UNTRANSLATED, gpa, 4, WRITE, &req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 263, 0) < 0 ) ); @@ -3488,13 +3488,13 @@ main(void) { msipte.M = 0x3; msipte.translate_rw.reserved = 0x1; msipte.translate_rw.reserved0 = 0x0; - write_memory((char *)&msipte, ((DC.msiptp.PPN * PAGESIZE) + 3 * 16), 16); + write_memory_test((char *)&msipte, ((DC.msiptp.PPN * PAGESIZE) + 3 * 16), 16); send_translation_request(0x042874, 0, 0x0000, 0, 0, 0, 0, ADDR_TYPE_UNTRANSLATED, gpa, 4, WRITE, &req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 263, 0) < 0) ); msipte.translate_rw.reserved = 0x0; msipte.translate_rw.reserved = 0x4; - write_memory((char *)&msipte, ((DC.msiptp.PPN * PAGESIZE) + 3 * 16), 16); + write_memory_test((char *)&msipte, ((DC.msiptp.PPN * PAGESIZE) + 3 * 16), 16); send_translation_request(0x042874, 0, 0x0000, 0, 0, 0, 0, ADDR_TYPE_UNTRANSLATED, gpa, 4, WRITE, &req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 263, 0) < 0) ); @@ -3503,13 +3503,13 @@ main(void) { msipte.M = 0x3; msipte.translate_rw.reserved = 0x0; msipte.translate_rw.reserved0 = 0x1; - write_memory((char *)&msipte, ((DC.msiptp.PPN * PAGESIZE) + 3 * 16), 16); + write_memory_test((char *)&msipte, ((DC.msiptp.PPN * PAGESIZE) + 3 * 16), 16); send_translation_request(0x042874, 0, 0x0000, 0, 0, 0, 0, ADDR_TYPE_UNTRANSLATED, gpa, 4, WRITE, &req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 263, 0) < 0) ); msipte.translate_rw.reserved = 0x0; msipte.translate_rw.reserved = 0x4; - write_memory((char *)&msipte, ((DC.msiptp.PPN * PAGESIZE) + 3 * 16), 16); + write_memory_test((char *)&msipte, ((DC.msiptp.PPN * PAGESIZE) + 3 * 16), 16); send_translation_request(0x042874, 0, 0x0000, 0, 0, 0, 0, ADDR_TYPE_UNTRANSLATED, gpa, 4, WRITE, &req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 263, 0) < 0) ); @@ -3518,13 +3518,13 @@ main(void) { msipte.M = 0x3; msipte.translate_rw.reserved = 0x1; msipte.translate_rw.reserved0 = 0x1; - write_memory((char *)&msipte, ((DC.msiptp.PPN * PAGESIZE) + 3 * 16), 16); + write_memory_test((char *)&msipte, ((DC.msiptp.PPN * PAGESIZE) + 3 * 16), 16); send_translation_request(0x042874, 0, 0x0000, 0, 0, 0, 0, ADDR_TYPE_UNTRANSLATED, gpa, 4, WRITE, &req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 263, 0) < 0) ); msipte.translate_rw.reserved = 0x0; msipte.translate_rw.reserved = 0x4; - write_memory((char *)&msipte, ((DC.msiptp.PPN * PAGESIZE) + 3 * 16), 16); + write_memory_test((char *)&msipte, ((DC.msiptp.PPN * PAGESIZE) + 3 * 16), 16); send_translation_request(0x042874, 0, 0x0000, 0, 0, 0, 0, ADDR_TYPE_UNTRANSLATED, gpa, 4, WRITE, &req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 263, 0) < 0) ); @@ -3534,7 +3534,7 @@ main(void) { msipte.translate_rw.reserved0 = 0x0; msipte.translate_rw.M = 0x3; msipte.translate_rw.PPN = 0xdeadbeef; - write_memory((char *)&msipte, ((DC.msiptp.PPN * PAGESIZE) + 3 * 16), 16); + write_memory_test((char *)&msipte, ((DC.msiptp.PPN * PAGESIZE) + 3 * 16), 16); send_translation_request(0x042874, 0, 0x0000, 0, 0, 0, 0, ADDR_TYPE_UNTRANSLATED, gpa, 4, WRITE, &req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, SUCCESS, 0, 0) < 0 ) ); @@ -3547,7 +3547,7 @@ main(void) { // corrupt but hit from cache msipte.translate_rw.reserved = 0x1; - write_memory((char *)&msipte, ((DC.msiptp.PPN * PAGESIZE) + 3 * 16), 16); + write_memory_test((char *)&msipte, ((DC.msiptp.PPN * PAGESIZE) + 3 * 16), 16); send_translation_request(0x042874, 0, 0x0000, 0, 0, 0, 0, ADDR_TYPE_UNTRANSLATED, gpa, 4, WRITE, &req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, SUCCESS, 0, 0) < 0 ) ); @@ -3564,15 +3564,15 @@ main(void) { 0, 0, 0, ADDR_TYPE_UNTRANSLATED, gpa, 4, WRITE, &req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 263, 0) < 0 ) ); msipte.translate_rw.reserved = 0x1; - write_memory((char *)&msipte, ((DC.msiptp.PPN * PAGESIZE) + 3 * 16), 16); + write_memory_test((char *)&msipte, ((DC.msiptp.PPN * PAGESIZE) + 3 * 16), 16); msipte.translate_rw.reserved = 0x0; - write_memory((char *)&msipte, ((DC.msiptp.PPN * PAGESIZE) + 3 * 16), 16); + write_memory_test((char *)&msipte, ((DC.msiptp.PPN * PAGESIZE) + 3 * 16), 16); // Execute access - read_memory(DC_addr, 64, (char *)&DC); + read_memory_test(DC_addr, 64, (char *)&DC); DC.tc.PDTV = 1; DC.fsc.pdtp.MODE = 0; - write_memory((char *)&DC, DC_addr, 64); + write_memory_test((char *)&DC, DC_addr, 64); iodir(INVAL_DDT, 1, 0x042874, 0); send_translation_request(0x042874, 1, 0xBABEC, 0, 1, 0, 0, ADDR_TYPE_UNTRANSLATED, gpa, @@ -3595,7 +3595,7 @@ main(void) { 1, 1, 0, 0, 0, IOHGATP_Sv48x4, IOSATP_Bare, PDTP_Bare, MSIPTP_Flat, 1, 0x0000000FF, 0x280000000); - read_memory(DC_addr, 64, (char *)&DC); + read_memory_test(DC_addr, 64, (char *)&DC); msipte.mrif.V = 1; msipte.mrif.reserved1 = 0; msipte.mrif.M = 1; @@ -3608,7 +3608,7 @@ main(void) { msipte.mrif.reserved3 = 0; msipte.mrif.N10 = 0x1; msipte.mrif.reserved4 = 0; - write_memory((char *)&msipte, ((DC.msiptp.PPN * PAGESIZE) + 0x23 * 16), 16); + write_memory_test((char *)&msipte, ((DC.msiptp.PPN * PAGESIZE) + 0x23 * 16), 16); gpa = 0x280000023000; @@ -3621,12 +3621,12 @@ main(void) { // misconfigured msipte.mrif.reserved1 = 1; - write_memory((char *)&msipte, ((DC.msiptp.PPN * PAGESIZE) + 0x23 * 16), 16); + write_memory_test((char *)&msipte, ((DC.msiptp.PPN * PAGESIZE) + 0x23 * 16), 16); send_translation_request(0x121679, 0, 0x0000, 0, 0, 0, 0, ADDR_TYPE_UNTRANSLATED, gpa, 4, WRITE, &req, &rsp); fail_if( ( check_rsp_and_faults(&req, &rsp, UNSUPPORTED_REQUEST, 263, 0) < 0 ) ); msipte.mrif.reserved1 = 0; - write_memory((char *)&msipte, ((DC.msiptp.PPN * PAGESIZE) + 0x23 * 16), 16); + write_memory_test((char *)&msipte, ((DC.msiptp.PPN * PAGESIZE) + 0x23 * 16), 16); // Unsupported send_translation_request(0x121679, 0, 0x0000, 0, @@ -3855,7 +3855,7 @@ main(void) { 1, 1, 0, 0, 1, IOHGATP_Sv32x4, IOSATP_Bare, PD20, MSIPTP_Flat, 1, 0xFFFFFFFFFF, 0x1000000000); - read_memory(DC_addr, 64, (char *)&DC); + read_memory_test(DC_addr, 64, (char *)&DC); // Add process context memset(&PC, 0, 16); @@ -3878,7 +3878,7 @@ main(void) { PC.ta.ENS = 1; PC.ta.SUM = 1; PC_addr = add_process_context(&DC, &PC, 0xBABEC); - read_memory(PC_addr, 16, (char *)&PC); + read_memory_test(PC_addr, 16, (char *)&PC); pte.raw = 0; pte.V = 1; @@ -3933,7 +3933,7 @@ main(void) { for ( j = 1; j < 16; j++ ) { if (j == 8) continue; PC.fsc.iosatp.MODE = j; - write_memory((char *)&PC, PC_addr, 16); + write_memory_test((char *)&PC, PC_addr, 16); send_translation_request(0x000000, 1, 0xBABEC, 0, 0, 1, 0, ADDR_TYPE_UNTRANSLATED, 0xdeadbeef, 1, WRITE, &req, &rsp); @@ -3942,7 +3942,7 @@ main(void) { g_reg_file.capabilities.Sv32 = 0; PC.fsc.iosatp.MODE = IOSATP_Sv32; - write_memory((char *)&PC, PC_addr, 16); + write_memory_test((char *)&PC, PC_addr, 16); send_translation_request(0x000000, 1, 0xBABEC, 0, 0, 1, 0, ADDR_TYPE_UNTRANSLATED, 0xdeadbeef, 1, WRITE, &req, &rsp); @@ -3950,7 +3950,7 @@ main(void) { g_reg_file.capabilities.Sv32 = 1; PC.fsc.iosatp.MODE = IOSATP_Sv48; - write_memory((char *)&PC, PC_addr, 16); + write_memory_test((char *)&PC, PC_addr, 16); g_gxl_writeable = 1; g_reg_file.fctl.gxl = 1; @@ -4323,6 +4323,13 @@ main(void) { g_reg_file.capabilities.ats = 1; write_register(ICVEC_OFFSET, 8, 0x0000000000005555); fail_if( ( read_register(ICVEC_OFFSET, 8) != 0x0000000000005555) ); + + // test iommu_qosid + g_reg_file.capabilities.qosid = 1; + g_iommu_qosid_mask = 0x00FF00FF; + write_register(IOMMU_QOSID_OFFSET, 4, 0x01230456); + fail_if( ( read_register(IOMMU_QOSID_OFFSET, 4) != 0x00230056) ); + g_reg_file.capabilities.qosid = 0; END_TEST(); return 0; diff --git a/iommu_ref_model/test/test_utils.c b/iommu_ref_model/test/test_utils.c index 83771013..d30f5bcc 100644 --- a/iommu_ref_model/test/test_utils.c +++ b/iommu_ref_model/test/test_utils.c @@ -155,7 +155,7 @@ enable_iommu( ddtp.ppn = get_free_ppn(1); // Clear the page for ( i = 0; i < 512; i++ ) - write_memory((char *)&zero, (ddtp.ppn * PAGESIZE) | (i * 8), 8); + write_memory_test((char *)&zero, (ddtp.ppn * PAGESIZE) | (i * 8), 8); ddtp.iommu_mode = iommu_mode; write_register(DDTP_OFFSET, 8, ddtp.raw); @@ -194,7 +194,7 @@ check_exp_pq_rec(uint32_t DID, uint32_t PID, uint8_t PV, uint8_t PRIV, uint8_t E if ( read_register(PQH_OFFSET, 4) == read_register(PQT_OFFSET, 4) ) return -1; pqh.raw = read_register(PQH_OFFSET, 4); pqb.raw = read_register(PQB_OFFSET, 8); - read_memory(((pqb.ppn * PAGESIZE) | (pqh.index * PQ_ENTRY_SZ)), PQ_ENTRY_SZ, (char *)&page_rec); + read_memory_test(((pqb.ppn * PAGESIZE) | (pqh.index * PQ_ENTRY_SZ)), PQ_ENTRY_SZ, (char *)&page_rec); if ( page_rec.DID != DID ) return -1; if ( page_rec.PID != PID ) return -1; if ( page_rec.PV != PV ) return -1; @@ -225,7 +225,7 @@ check_faults( } fqb.raw = read_register(FQB_OFFSET, 8); - read_memory(((fqb.ppn * PAGESIZE) | (fqh.index * FQ_ENTRY_SZ)), FQ_ENTRY_SZ, (char *)&fault_rec); + read_memory_test(((fqb.ppn * PAGESIZE) | (fqh.index * FQ_ENTRY_SZ)), FQ_ENTRY_SZ, (char *)&fault_rec); // pop the fault record fqh.index++; @@ -319,7 +319,7 @@ add_device(uint32_t device_id, uint32_t gscid, uint8_t en_ats, uint8_t en_pri, u if ( iohgatp_mode != IOHGATP_Bare ) { DC.iohgatp.GSCID = gscid; DC.iohgatp.PPN = get_free_ppn(4); - write_memory(zero, DC.iohgatp.PPN * PAGESIZE, 16384); + write_memory_test(zero, DC.iohgatp.PPN * PAGESIZE, 16384); } DC.iohgatp.MODE = iohgatp_mode; if ( iosatp_mode != IOSATP_Bare ) { @@ -339,11 +339,11 @@ add_device(uint32_t device_id, uint32_t gscid, uint8_t en_ats, uint8_t en_pri, u gpte.D = 0; gpte.PBMT = PMA; gpte.PPN = get_free_ppn(1); - write_memory(zero, gpte.PPN * PAGESIZE, 4096); + write_memory_test(zero, gpte.PPN * PAGESIZE, 4096); add_g_stage_pte(DC.iohgatp, (PAGESIZE * DC.fsc.iosatp.PPN), gpte, 0); } else { DC.fsc.iosatp.PPN = get_free_ppn(1); - write_memory(zero, DC.fsc.iosatp.PPN * PAGESIZE, 4096); + write_memory_test(zero, DC.fsc.iosatp.PPN * PAGESIZE, 4096); } } if ( pdt_mode != PDTP_Bare ) { @@ -363,17 +363,17 @@ add_device(uint32_t device_id, uint32_t gscid, uint8_t en_ats, uint8_t en_pri, u gpte.D = 0; gpte.PBMT = PMA; gpte.PPN = get_free_ppn(1); - write_memory(zero, gpte.PPN * PAGESIZE, 4096); + write_memory_test(zero, gpte.PPN * PAGESIZE, 4096); add_g_stage_pte(DC.iohgatp, (PAGESIZE * DC.fsc.pdtp.PPN), gpte, 0); } else { DC.fsc.pdtp.PPN = get_free_ppn(1); - write_memory(zero, DC.fsc.pdtp.PPN * PAGESIZE, 4096); + write_memory_test(zero, DC.fsc.pdtp.PPN * PAGESIZE, 4096); } } DC.msiptp.MODE = msiptp_mode; if ( msiptp_mode != MSIPTP_Off ) { DC.msiptp.PPN = get_free_ppn(msiptp_pages); - write_memory(zero, DC.msiptp.PPN * PAGESIZE, 4096); + write_memory_test(zero, DC.msiptp.PPN * PAGESIZE, 4096); DC.msi_addr_mask.mask = msi_addr_mask; DC.msi_addr_pattern.pattern = msi_addr_pattern; } @@ -401,7 +401,7 @@ iotinval( cmd.iotinval.addr_63_12 = address / PAGESIZE; cqb.raw = read_register(CQB_OFFSET, 8); cqt.raw = read_register(CQT_OFFSET, 4); - write_memory((char *)&cmd, ((cqb.ppn * PAGESIZE) | (cqt.index * CQ_ENTRY_SZ)), CQ_ENTRY_SZ); + write_memory_test((char *)&cmd, ((cqb.ppn * PAGESIZE) | (cqt.index * CQ_ENTRY_SZ)), CQ_ENTRY_SZ); access_viol_addr = temp; data_corruption_addr = temp1; cqt.index++; @@ -432,7 +432,7 @@ ats_command( cqb.raw = read_register(CQB_OFFSET, 8); cqt.raw = read_register(CQT_OFFSET, 4); - write_memory((char *)&cmd, ((cqb.ppn * PAGESIZE) | (cqt.index * CQ_ENTRY_SZ)), CQ_ENTRY_SZ); + write_memory_test((char *)&cmd, ((cqb.ppn * PAGESIZE) | (cqt.index * CQ_ENTRY_SZ)), CQ_ENTRY_SZ); access_viol_addr = temp; data_corruption_addr = temp1; cqt.index++; @@ -450,7 +450,7 @@ generic_any( temp1 = data_corruption_addr; cqb.raw = read_register(CQB_OFFSET, 8); cqt.raw = read_register(CQT_OFFSET, 4); - write_memory((char *)&cmd, ((cqb.ppn * PAGESIZE) | (cqt.index * CQ_ENTRY_SZ)), CQ_ENTRY_SZ); + write_memory_test((char *)&cmd, ((cqb.ppn * PAGESIZE) | (cqt.index * CQ_ENTRY_SZ)), CQ_ENTRY_SZ); access_viol_addr = temp; data_corruption_addr = temp1; cqt.index++; @@ -478,7 +478,7 @@ iodir( cmd.iodir.pid = PID; cqb.raw = read_register(CQB_OFFSET, 8); cqt.raw = read_register(CQT_OFFSET, 4); - write_memory((char *)&cmd, ((cqb.ppn * PAGESIZE) | (cqt.index * CQ_ENTRY_SZ)), CQ_ENTRY_SZ); + write_memory_test((char *)&cmd, ((cqb.ppn * PAGESIZE) | (cqt.index * CQ_ENTRY_SZ)), CQ_ENTRY_SZ); access_viol_addr = temp; data_corruption_addr = temp1; cqt.index++; @@ -508,7 +508,7 @@ iofence( cmd.iofence.data = data; cqb.raw = read_register(CQB_OFFSET, 8); cqt.raw = read_register(CQT_OFFSET, 4); - write_memory((char *)&cmd, ((cqb.ppn * PAGESIZE) | (cqt.index * CQ_ENTRY_SZ)), CQ_ENTRY_SZ); + write_memory_test((char *)&cmd, ((cqb.ppn * PAGESIZE) | (cqt.index * CQ_ENTRY_SZ)), CQ_ENTRY_SZ); access_viol_addr = temp; data_corruption_addr = temp1; cqt.index++;