diff --git a/src/iommu_extensions.adoc b/src/iommu_extensions.adoc index 301d3b8..0ced2b9 100644 --- a/src/iommu_extensions.adoc +++ b/src/iommu_extensions.adoc @@ -11,6 +11,12 @@ Architecture: | <> |*1.0* |*Ratified* +| <> + |_0.8_ + |_Draft_ +| <> + |_0.8_ + |_Draft_ |=== [[QOSID]] @@ -93,3 +99,127 @@ different capacities. In scenarios where multiple IOATCs are implemented, such as an IOATC for each supported page size, the IOMMU can implement a capacity controller register interface for each IOATC to facilitate individual capacity allocation. + +<<< + +[[NLINV]] +=== Non-leaf PTE Invalidation Extension, Version 0.8 + +The RISC-V IOMMU Version 1.0 specification provides commands to invalidate +leaf page table entries from address translation caches when performing an +address-specific invalidation operation. The non-leaf PTE invalidation +extension provides commands to optionally also invalidate non-leaf PTE +entries from the address translation caches when performing an +address-specific invalidation operation. + +The non-leaf PTE invalidation extension is implemented if the `capabilities.NL` +(bit 42) is 1. When the `capabilities.NL` bit is 1, a non-leaf (`NL`) field is +defined at bit 34 in the `IOTINVAL.VMA` and `IOTINVAL.GVMA` commands by this +extension. When the `capabilities.NL` bit is 0, bit 34 remains reserved. + +[NOTE] +==== +The non-leaf PTE invalidation extension enables optimizations in shared +virtual addressing use cases by providing the ability to invalidate non-leaf +PTEs corresponding to the IOVA being invalidated from the IOMMU address +translation caches. +==== + +If the address range invalidation extension is also implemented, the `NL` +operand applies to the address range determined by the `ADDR` and `S` operands. + +==== Non-leaf PTE Invalidation by `IOTINVAL.VMA` + +* When the `AV` operand is 0, the `NL` operand is ignored and the `IOTINVAL.VMA` + command operations are as specified in RISC-V IOMMU Version 1.0 specification. + +* When the `AV` operand is 1 and the `NL` operand is 0, the `IOTINVAL.VMA` + command operations are as specified in RISC-V IOMMU Version 1.0 specification. + +* When both the `AV` and `NL` operands are 1, the `IOTINVAL.VMA` command + performs the following operations: + +** When `GV=0` and `PSCV=0`: Invalidates information cached from all levels of + first-stage page table entries corresponding to the IOVA in the `ADDR` + operand for all host address spaces, including entries containing global + mappings. + +** When `GV=0` and `PSCV=1`: Invalidates information cached from all levels of + first-stage page table entries corresponding to the IOVA in the `ADDR` + operand and the host address space identified by the `PSCID` operand, except + for entries containing global mappings. + +** When `GV=1` and `PSCV=0`: Invalidates information cached from all levels of + first-stage page table entries corresponding to the IOVA in the `ADDR` + operand for all VM address spaces associated with the `GSCID` operand, + including entries that contain global mappings. + +** When `GV=1` and `PSCV=1`: Invalidates information cached from all levels of + first-stage page table entries corresponding to the IOVA in the `ADDR` + operand and the VM address space identified by the `PSCID` and `GSCID` + operands, except for entries containing global mappings. + +==== Non-leaf PTE Invalidation by `IOTINVAL.GVMA` + +* When the `GV` operand is 0, both the `AV` and `NL` operands are ignored and + the `IOTINVAL.GVMA` command operations are as specified in RISC-V IOMMU + Version 1.0 specification. + +* When the `GV` operand is 1 and the `AV` operand is 0, the `NL` operand is + ignored and the `IOTINVAL.GVMA` command operations are as specified in + RISC-V IOMMU Version 1.0 specification. + +* When the `GV` and `AV` operands are 1 and the `NL` operand is 0, the + `IOTINVAL.GVMA` command operations are as specified in RISC-V IOMMU Version + 1.0 specification. + +* When `GV`, `AV`, and `NL` are all 1, the `IOTINVAL.GVMA` command performs the + following operations: + +** Invalidates information cached from all levels of second-stage page table + entries corresponding to the guest-physical address in the `ADDR` operand and + the VM address spaces identified by the `GSCID` operand. + +<<< + +[[ARINV]] +=== Address Range Invalidation Extension, Version 0.8 + +The address range invalidation extension enables specifying a range of addresses +in an IOMMU ATC invalidation command, reducing the number of commands queued to +the IOMMU. This facility is especially useful when superpages are employed in +page tables. + +The address range invalidation extension is implemented if `capabilities.S` (bit +43) is 1. When `capabilities.S` is 1, a range-size (`S`) operand is defined at +bit 73 in the `IOTINVAL.VMA` and `IOTINVAL.GVMA` commands by this extension. +When the `capabilities.S` bit is 0, bit 73 remains reserved. + +When the `GV` operand is 0, both the `AV` and `S` operands are ignored by the +`IOTINVAL.GVMA` command. When the `AV` operand is 0, the `S` operand is ignored +in both the `IOTINVAL.VMA` and `IOTINVAL.GVMA` commands. When the `S` operand is +ignored or set to 0, the operations of the `IOTINVAL.VMA` and `IOTINVAL.GVMA` +commands are as specified in the RISC-V IOMMU Version 1.0 specification. + +When the `S` operand is not ignored and is 1, the `ADDR` operand represents a +NAPOT range encoded in the operand itself. Starting from bit position 0 +of the `ADDR` operand, if the first 0 bit is at position `X`, the range size is +`2^(X+1)^ * 4` KiB. When `X` is 0, the size of the range is 8 KiB. + +If the `S` operand is not ignored and is 1 and all bits of the `ADDR` operand +are 1, the behavior is UNSPECIFIED. + +If the `S` operand is not ignored and is 1 and the most significant bit of the +`ADDR` operand is 0 while all other bits are 1, the specified address range +covers the entire address space. + +[NOTE] +==== +The NAPOT range encoding used by this extension follows the convention used by +PCIe ATS Invalidation Requests to denote address ranges. This convention is also +used to encode the translation range size in `tr_response` (<>) +register. + +Simpler implementations may invalidate all address-translation cache entries +when the `S` bit is set to 1. +==== diff --git a/src/iommu_in_memory_queues.adoc b/src/iommu_in_memory_queues.adoc index a3a2ead..5353160 100644 --- a/src/iommu_in_memory_queues.adoc +++ b/src/iommu_in_memory_queues.adoc @@ -154,10 +154,12 @@ the command-queue. To re-enable command processing software should clear the {bits: 20, name: 'PSCID'}, {bits: 1, name: 'PSCV'}, {bits: 1, name: 'GV'}, - {bits: 10, name: 'rsvd'}, + {bits: 1, name: 'NL'}, + {bits: 9, name: 'rsvd'}, {bits: 16, name: 'GSCID'}, {bits: 4, name: 'rsvd'}, - {bits: 10, name: 'rsvd'}, + {bits: 9, name: 'rsvd'}, + {bits: 1, name: 'S'}, {bits: 52, name: 'ADDR[63:12]'}, {bits: 2, name: 'rsvd'}, ], config:{lanes: 4, hspace:1024, fontsize:12}} @@ -185,6 +187,10 @@ When `AV` is 0, the `ADDR` operand is ignored. When `PSCV` operand is 0, the operand specifies an invalid address, the command may or may not perform any invalidations. +The definition of the `NL` bit is provided by the non-leaf PTE invalidation +extension <>. The definition of the `S` bit is provided by the address +range invalidation extension <>. + [NOTE] ==== When an invalid address is specified, an implementation may either complete the diff --git a/src/iommu_registers.adoc b/src/iommu_registers.adoc index 986c640..0ce0007 100644 --- a/src/iommu_registers.adoc +++ b/src/iommu_registers.adoc @@ -155,7 +155,9 @@ the IOMMU. At reset, the register shall contain the IOMMU supported features. {bits: 1, name: 'PD17'}, {bits: 1, name: 'PD20'}, {bits: 1, name: 'QOSID'}, - {bits: 14, name: 'reserved'}, + {bits: 1, name: 'NL'}, + {bits: 1, name: 'S'}, + {bits: 12, name: 'reserved'}, {bits: 8, name: 'custom'}, ], config:{lanes: 8, hspace:1024}} .... @@ -226,7 +228,9 @@ the IOMMU. At reset, the register shall contain the IOMMU supported features. |39 |`PD17` |RO | Two level PDT with 17-bit process_id supported. |40 |`PD20` |RO | Three level PDT with 20-bit process_id supported. |41 |`QOSID` |RO | Associating QoS IDs with requests is supported. -|55:42 | reserved |RO | Reserved for standard use. +|42 |`NL` |RO | Non-leaf PTE invalidation extension is supported. +|43 |`S` |RO | Address range invalidation extension is supported. +|55:44 | reserved |RO | Reserved for standard use. |63:56 |custom |RO | Designated for custom use. |===