diff --git a/src/iommu_data_structures.adoc b/src/iommu_data_structures.adoc
index 9fcc1f2..876977b 100644
--- a/src/iommu_data_structures.adoc
+++ b/src/iommu_data_structures.adoc
@@ -1314,6 +1314,14 @@ This is accomplished by setting "Untranslated Access Only" (U) field of the
 returned response to 1.
 ====
 
+[NOTE]
+====
+The translation range size returned in a Success response to an ATS translation
+request, when either stages of address translation are Bare, is
+implementation-defined. However, it is recommended that the translation range
+size be large, such as 2 MiB or 1 GiB.
+====
+
 When a Success response is generated for an ATS translation request, the setting
 of the Priv, N, CXL.io, Global, and AMA fields is as follows:
 
diff --git a/src/iommu_in_memory_queues.adoc b/src/iommu_in_memory_queues.adoc
index a3a2ead..d0c2055 100644
--- a/src/iommu_in_memory_queues.adoc
+++ b/src/iommu_in_memory_queues.adoc
@@ -293,10 +293,6 @@ Some implementations may cache an identity-mapped translation for the stage of
 address translation operating in `Bare` mode. Since these identity mappings
 are invariably correct, an explicit invalidation is unnecessary.
 
-Some implementations may cache an identity-mapped translation for the stage of
-address translation operating in `Bare` mode. Since these identity mappings
-are invariably correct, an explicit invalidation is unnecessary.
-
 A consequence of this specification is that an implementation may use any
 translation for an address that was valid at any time since the most recent
 `IOTINVAL` that subsumes that address. In particular, if a leaf PTE is
diff --git a/src/iommu_sw_guidelines.adoc b/src/iommu_sw_guidelines.adoc
index be9b2c6..39a1a00 100644
--- a/src/iommu_sw_guidelines.adoc
+++ b/src/iommu_sw_guidelines.adoc
@@ -112,13 +112,10 @@ The guidelines for initializing the IOMMU are as follows:
 .. If `Dw` is less than or equal to  7-bits and `1LVL` is supported then `M = 1LVL`
 .. If `Dw` is less than or equal to 16-bits and `2LVL` is supported then `M = 2LVL`
 .. If `Dw` is less than or equal to 24-bits and `3LVL` is supported then `M = 3LVL`
-
-+
-Program the `ddtp` register as follows:
-
-** `temp_ddtp_var.iommu_mode = M`
-** `temp_ddtp_var.PPN = B`
-** `ddtp = temp_ddtp_var`
+** Program the `ddtp` register as follows:
+.. `temp_ddtp_var.iommu_mode = M`
+.. `temp_ddtp_var.PPN = B`
+.. `ddtp = temp_ddtp_var`
 
 The IOMMU is initialized and may be now be configured with device-contexts
 for devices in scope of the IOMMU.
@@ -175,10 +172,10 @@ performed:
 
 * `IODIR.INVAL_PDT` with `DV=1`, `DID=D` and `PID=P`
 * If `DC.iohgatp.MODE != Bare`
-** `IOTINVAL.VMA` with `GV=1`, `AV=0`, `PV=1`, `GSCID=DC.iohgatp.GSCID`,
+** `IOTINVAL.VMA` with `GV=1`, `AV=0`, `PSCV=1`, `GSCID=DC.iohgatp.GSCID`,
    and `PSCID=PC.PSCID`
 * else
-** `IOTINVAL.VMA` with `GV=0`, `AV=0`, `PV=1`, and `PSCID=PC.PSCID`
+** `IOTINVAL.VMA` with `GV=0`, `AV=0`, `PSCV=1`, and `PSCID=PC.PSCID`
 
 If software changes a non-leaf-level PDT entry the following invalidations
 must be performed:
@@ -384,7 +381,7 @@ following actions:
 .. Process pending fault/event reports that need processing and remove them from
    the `FQ` by advancing the `fqh` by the number of records processed.
 . If the `ipsr.pip` bit is set then an interrupt is pending from the `PQ`.
-.. Read the `pqcsr`register.
+.. Read the `pqcsr` register.
 .. Determine if an error caused the interrupt and if so, the cause of the error
    by examining the state of the `pqmf` and `pqof` bits. If either of these bits
    are set then the `PQ` encountered an error and "Page Request" reporting is