Why aren't non-leaf PTEs invalidated when their corresponding leaf PTEs are invalidated?

[kdockser]

It seems that the normal behavior when invalidating a cached memory translation is to also invalidate the components of that translation. Why are we interpreting the existing instruction as only invalidating the leaf cell? This seems backwards - it seems like we should be defining a new instruction that invalidates the leaf cell and explicitly leaves the non-leaf cells intact.

Is this choice based on the assumption that some microarchitectures might not be able to easily invalidate non-leaf cells when their parent cell is invalidated? Or, is it based on a perception that the common case is where a leaf needs to be invalidated but the underlying non-leafs will still be useful?

[ved-rivos]

Yes, the common case was for when an address is specified to invalidate the leaf PTE and retain the non-leaf PTEs. This is also how the SFENCE.VMA instructions operate for the CPU MMU. We have recognized a need for some use cases to be able to specify that non-leaf PTEs be also invalidated along with the leaf PTE when doing an address-specific invalidation and is being pursued as a non-leaf PTE invalidation extension.