Merge pull request #492 from ved-rivos/0219

add missing is_implicit term
riscv-non-isa · Feb 19, 2025 · bb9022b · bb9022b
2 parents 72b83f5 + bb3bd11
commit bb9022b
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/iommu_ref_model/libiommu/src/iommu_second_stage_trans.c b/iommu_ref_model/libiommu/src/iommu_second_stage_trans.c
@@ -296,7 +296,7 @@ second_stage_address_translation(
         // requests that may request write permission when write permission does not
         // exist. If write permission exists then the D bit is set else D bit is not
         // set and the write permission is returned in responses as 0.
-        if ( (is_write == 1) && (amo_gpte.W == 1) ) amo_gpte.D = 1;
+        if ( (is_write == 1 || is_implicit == 1) && (amo_gpte.W == 1) ) amo_gpte.D = 1;
     }
 
     status = write_memory((char *)&amo_gpte.raw, (a + (vpn[i] * PTESIZE)), PTESIZE);