Merge pull request #497 from ved-rivos/0220

implicit G-stage D bit updates must only be qualified by SADE
riscv-non-isa · Feb 20, 2025 · 5b75f97 · 5b75f97
2 parents bb9022b + 796a4db
commit 5b75f97
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/iommu_ref_model/libiommu/src/iommu_second_stage_trans.c b/iommu_ref_model/libiommu/src/iommu_second_stage_trans.c
@@ -275,7 +275,7 @@ second_stage_address_translation(
     //      also set pte.d to 1.
     //    – If the comparison fails, return to step 2
     if ( (gpte->A == 1) && (gpte->D == 1 || is_write == 0) &&
-         (gpte->D == 1 || is_implicit == 0 || gpte->W == 0 || GADE == 0 || SADE == 0) ) goto step_8;
+         (gpte->D == 1 || is_implicit == 0 || gpte->W == 0 || SADE == 0) ) goto step_8;
 
     // A and/or D bit update needed
     if ( GADE == 0 ) return GST_PAGE_FAULT;