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plat-rz: fix CFG_NUM_THREADS and NSEC_DDR_0_SIZE for RZ/V2H.
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Signed-off-by: kaiki osakaki <kaiki.osakaki.rh@bp.renesas.com>
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kaiki osakaki committed Sep 6, 2024
1 parent 120c139 commit bfec326
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Showing 2 changed files with 2 additions and 1 deletion.
1 change: 1 addition & 0 deletions core/arch/arm/plat-rz/v2h/rzv2h_conf.mk
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Expand Up @@ -14,6 +14,7 @@ $(call force,CFG_RZ_HUK,y)
$(call force,CFG_RZ_XSPI,y)

CFG_TEE_CORE_NB_CORE ?= 4
CFG_NUM_THREADS ?= 4

CFG_TZDRAM_START ?= 0x44100000
CFG_TZDRAM_SIZE ?= 0x03D00000
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2 changes: 1 addition & 1 deletion core/arch/arm/plat-rz/v2h/rzv2h_config.h
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Expand Up @@ -34,7 +34,7 @@
#if defined(PLATFORM_FLAVOR_v2h_evk_1)
/* DDR 8Gbyte x1 */
#define NSEC_DDR_0_BASE 0x47E00000U
#define NSEC_DDR_0_SIZE 0x1F8000000U
#define NSEC_DDR_0_SIZE 0x1F8200000U

/* DDR 8Gbyte x1 */
#define NSEC_DDR_1_BASE 0x240000000U
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