From 8667ea4d51b5b467e480fe93f83476f01932c4e9 Mon Sep 17 00:00:00 2001 From: Takunori Otsuka Date: Wed, 11 Sep 2024 09:09:29 +0900 Subject: [PATCH] plat-rz: convert spaces to tabs --- core/arch/arm/plat-rz/g3s/rzg3s_config.h | 14 +++++++------- core/arch/arm/plat-rz/v2h/rzv2h_config.h | 2 +- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/core/arch/arm/plat-rz/g3s/rzg3s_config.h b/core/arch/arm/plat-rz/g3s/rzg3s_config.h index 3e28f0996..2ccae67f2 100644 --- a/core/arch/arm/plat-rz/g3s/rzg3s_config.h +++ b/core/arch/arm/plat-rz/g3s/rzg3s_config.h @@ -24,7 +24,7 @@ #define SPI_FLASH_BASE 0x20000000U #define SPI_FLASH_SIZE 0x10000000 -#define SPI_SECTOR_SIZE 0x10000 +#define SPI_SECTOR_SIZE 0x10000 #define XSPI_BASE 0x10060000U #define XSPI_REG_SIZE 0x30000 @@ -34,14 +34,14 @@ #if defined(PLATFORM_FLAVOR_g3s_dev14_1) /* DDR 1Gbyte x1 */ -#define NSEC_DDR_0_BASE 0x47E00000U -#define NSEC_DDR_0_SIZE 0x38200000 +#define NSEC_DDR_0_BASE 0x47E00000U +#define NSEC_DDR_0_SIZE 0x38200000 #elif defined(PLATFORM_FLAVOR_g3s_smarc_2) /* DDR 1Gbyte x2 */ -#define NSEC_DDR_0_BASE 0x47E00000U -#define NSEC_DDR_0_SIZE 0x38200000 -#define NSEC_DDR_1_BASE 0xC0000000U -#define NSEC_DDR_1_SIZE 0x40000000 +#define NSEC_DDR_0_BASE 0x47E00000U +#define NSEC_DDR_0_SIZE 0x38200000 +#define NSEC_DDR_1_BASE 0xC0000000U +#define NSEC_DDR_1_SIZE 0x40000000 #else #error "Unknown platform flavor" #endif diff --git a/core/arch/arm/plat-rz/v2h/rzv2h_config.h b/core/arch/arm/plat-rz/v2h/rzv2h_config.h index b41a26b9d..a8a8e9e73 100644 --- a/core/arch/arm/plat-rz/v2h/rzv2h_config.h +++ b/core/arch/arm/plat-rz/v2h/rzv2h_config.h @@ -24,7 +24,7 @@ #define SPI_FLASH_BASE 0x20000000U #define SPI_FLASH_SIZE 0x10000000 -#define SPI_SECTOR_SIZE 0x10000 +#define SPI_SECTOR_SIZE 0x10000 #define XSPI_BASE 0x11030000U #define XSPI_REG_SIZE 0x10000