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Copy path0004-target-aarch64-Add-code-to-invaldate-the-instruction.patch
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0004-target-aarch64-Add-code-to-invaldate-the-instruction.patch
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From 2075b92cc3e9890a028e67f33fb3b901e6330dcf Mon Sep 17 00:00:00 2001
From: MicBiso <michele.bisogno.ct@renesas.com>
Date: Wed, 17 Apr 2024 18:42:32 +0200
Subject: [PATCH 4/4] target/aarch64: Add code to invaldate the instruction
cache
This patch adds the code to invalidate the whole instruction cache.
This is required in cases the code in memory is replaced (e.g. self
modifying).
The I/D cache invalidate code shall not check for the caches to be enabled.
In AArch64 the SCTLR I and C bits do NOT disable the caches,
they prevent code/data allocation. So if some stale code/data is present
in the cache the CPU may (incorrectly) use it.
Change-Id: Icb40300c26d87c876c683456f994f05ec385deac
Signed-off-by: MicBiso <michele.bisogno.ct@renesas.com>
---
src/target/aarch64.c | 3 ++
src/target/armv8.c | 1 +
src/target/armv8.h | 1 +
src/target/armv8_cache.c | 90 ++++++++++++++++++++++++--------------
src/target/armv8_opcodes.c | 1 +
src/target/armv8_opcodes.h | 2 +
6 files changed, 65 insertions(+), 33 deletions(-)
diff --git a/src/target/aarch64.c b/src/target/aarch64.c
index 3b5c5c86e..351f98b13 100644
--- a/src/target/aarch64.c
+++ b/src/target/aarch64.c
@@ -148,6 +148,9 @@ static int aarch64_mmu_modify(struct target *target, int enable, int persist)
if (armv8->armv8_mmu.armv8_cache.flush_all_data_cache)
armv8->armv8_mmu.armv8_cache.flush_all_data_cache(target);
}
+ /* invalidate instruction cache armv8 function to be called */
+ if (armv8->armv8_mmu.armv8_cache.inv_all_inst_cache)
+ armv8->armv8_mmu.armv8_cache.inv_all_inst_cache(target);
if ((aarch64->system_control_reg_curr & 0x1U)) {
aarch64->system_control_reg_curr &= ~0x1U;
}
diff --git a/src/target/armv8.c b/src/target/armv8.c
index bf582ff80..a3ee402c0 100644
--- a/src/target/armv8.c
+++ b/src/target/armv8.c
@@ -1216,6 +1216,7 @@ int armv8_init_arch_info(struct target *target, struct armv8_common *armv8)
armv8->armv8_mmu.armv8_cache.l2_cache = NULL;
armv8->armv8_mmu.armv8_cache.info = -1;
armv8->armv8_mmu.armv8_cache.flush_all_data_cache = NULL;
+ armv8->armv8_mmu.armv8_cache.inv_all_inst_cache = NULL;
armv8->armv8_mmu.armv8_cache.display_cache_info = NULL;
return ERROR_OK;
}
diff --git a/src/target/armv8.h b/src/target/armv8.h
index f5aa21109..f6c225e2d 100644
--- a/src/target/armv8.h
+++ b/src/target/armv8.h
@@ -162,6 +162,7 @@ struct armv8_cache_common {
/* l2 external unified cache if some */
void *l2_cache;
int (*flush_all_data_cache)(struct target *target);
+ int (*inv_all_inst_cache)(struct target *target);
int (*display_cache_info)(struct command_invocation *cmd,
struct armv8_cache_common *armv8_cache);
};
diff --git a/src/target/armv8_cache.c b/src/target/armv8_cache.c
index 66d4e0080..8328b6d84 100644
--- a/src/target/armv8_cache.c
+++ b/src/target/armv8_cache.c
@@ -19,26 +19,6 @@
#define CACHE_LEVEL_HAS_D_CACHE 0x2
#define CACHE_LEVEL_HAS_I_CACHE 0x1
-static int armv8_d_cache_sanity_check(struct armv8_common *armv8)
-{
- struct armv8_cache_common *armv8_cache = &armv8->armv8_mmu.armv8_cache;
-
- if (armv8_cache->d_u_cache_enabled)
- return ERROR_OK;
-
- return ERROR_TARGET_INVALID;
-}
-
-static int armv8_i_cache_sanity_check(struct armv8_common *armv8)
-{
- struct armv8_cache_common *armv8_cache = &armv8->armv8_mmu.armv8_cache;
-
- if (armv8_cache->i_cache_enabled)
- return ERROR_OK;
-
- return ERROR_TARGET_INVALID;
-}
-
static int armv8_cache_d_inner_flush_level(struct armv8_common *armv8, struct armv8_cachesize *size, int cl)
{
struct arm_dpm *dpm = armv8->arm.dpm;
@@ -75,10 +55,6 @@ static int armv8_cache_d_inner_clean_inval_all(struct armv8_common *armv8)
int cl;
int retval;
- retval = armv8_d_cache_sanity_check(armv8);
- if (retval != ERROR_OK)
- return retval;
-
retval = dpm->prepare(dpm);
if (retval != ERROR_OK)
goto done;
@@ -101,6 +77,29 @@ done:
return retval;
}
+int armv8_cache_i_inner_inval_all(struct armv8_common *armv8)
+{
+ struct arm_dpm *dpm = armv8->arm.dpm;
+ int retval;
+
+ retval = dpm->prepare(dpm);
+ if (retval != ERROR_OK)
+ goto done;
+
+ retval = dpm->instr_write_data_r0(dpm,
+ armv8_opcode(armv8, ARMV8_OPC_ICIALLU), 0);
+
+ dpm->finish(dpm);
+ return retval;
+
+done:
+ LOG_ERROR("i-cache invalidate failed");
+ dpm->finish(dpm);
+
+ return retval;
+}
+
+
int armv8_cache_d_inner_flush_virt(struct armv8_common *armv8, target_addr_t va, size_t size)
{
struct arm_dpm *dpm = armv8->arm.dpm;
@@ -109,10 +108,6 @@ int armv8_cache_d_inner_flush_virt(struct armv8_common *armv8, target_addr_t va,
target_addr_t va_line, va_end;
int retval;
- retval = armv8_d_cache_sanity_check(armv8);
- if (retval != ERROR_OK)
- return retval;
-
retval = dpm->prepare(dpm);
if (retval != ERROR_OK)
goto done;
@@ -148,10 +143,6 @@ int armv8_cache_i_inner_inval_virt(struct armv8_common *armv8, target_addr_t va,
target_addr_t va_line, va_end;
int retval;
- retval = armv8_i_cache_sanity_check(armv8);
- if (retval != ERROR_OK)
- return retval;
-
retval = dpm->prepare(dpm);
if (retval != ERROR_OK)
goto done;
@@ -172,7 +163,7 @@ int armv8_cache_i_inner_inval_virt(struct armv8_common *armv8, target_addr_t va,
return retval;
done:
- LOG_ERROR("d-cache invalidate failed");
+ LOG_ERROR("i-cache invalidate failed");
dpm->finish(dpm);
return retval;
@@ -226,6 +217,11 @@ static int _armv8_flush_all_data(struct target *target)
return armv8_cache_d_inner_clean_inval_all(target_to_armv8(target));
}
+static int _armv8_inv_all_inst(struct target *target)
+{
+ return armv8_cache_i_inner_inval_all(target_to_armv8(target));
+}
+
static int armv8_flush_all_data(struct target *target)
{
int retval = ERROR_FAIL;
@@ -252,6 +248,32 @@ static int armv8_flush_all_data(struct target *target)
return retval;
}
+static int armv8_inv_all_inst(struct target *target)
+{
+ int retval = ERROR_FAIL;
+ /* check that armv8_cache is correctly identify */
+ struct armv8_common *armv8 = target_to_armv8(target);
+ if (armv8->armv8_mmu.armv8_cache.info == -1) {
+ LOG_ERROR("trying to flush un-identified cache");
+ return retval;
+ }
+
+ if (target->smp) {
+ /* look if all the other target have been flushed in order to flush level
+ * 2 */
+ struct target_list *head;
+ foreach_smp_target(head, target->smp_targets) {
+ struct target *curr = head->target;
+ if (curr->state == TARGET_HALTED) {
+ LOG_TARGET_INFO(curr, "Wait invalidating instruction l1.");
+ retval = _armv8_inv_all_inst(curr);
+ }
+ }
+ } else
+ retval = _armv8_inv_all_inst(target);
+ return retval;
+}
+
static int get_cache_info(struct arm_dpm *dpm, int cl, int ct, uint32_t *cache_reg)
{
struct armv8_common *armv8 = dpm->arm->arch_info;
@@ -410,6 +432,8 @@ int armv8_identify_cache(struct armv8_common *armv8)
armv8_handle_inner_cache_info_command;
armv8->armv8_mmu.armv8_cache.flush_all_data_cache =
armv8_flush_all_data;
+ armv8->armv8_mmu.armv8_cache.inv_all_inst_cache =
+ armv8_inv_all_inst;
}
done:
diff --git a/src/target/armv8_opcodes.c b/src/target/armv8_opcodes.c
index 2635b3ec5..044400d91 100644
--- a/src/target/armv8_opcodes.c
+++ b/src/target/armv8_opcodes.c
@@ -32,6 +32,7 @@ static const uint32_t a64_opcodes[ARMV8_OPC_NUM] = {
[ARMV8_OPC_DCCISW] = ARMV8_SYS(SYSTEM_DCCISW, 0),
[ARMV8_OPC_DCCIVAC] = ARMV8_SYS(SYSTEM_DCCIVAC, 0),
[ARMV8_OPC_ICIVAU] = ARMV8_SYS(SYSTEM_ICIVAU, 0),
+ [ARMV8_OPC_ICIALLU] = ARMV8_SYS(SYSTEM_ICIALLU, 0x1F),
[ARMV8_OPC_HLT] = ARMV8_HLT(11),
[ARMV8_OPC_LDRB_IP] = ARMV8_LDRB_IP(1, 0),
[ARMV8_OPC_LDRH_IP] = ARMV8_LDRH_IP(1, 0),
diff --git a/src/target/armv8_opcodes.h b/src/target/armv8_opcodes.h
index 8eeff2f8b..b58b58d3d 100644
--- a/src/target/armv8_opcodes.h
+++ b/src/target/armv8_opcodes.h
@@ -72,6 +72,7 @@
#define SYSTEM_DCCISW 0x43F2
#define SYSTEM_DCCSW 0x43D2
#define SYSTEM_ICIVAU 0x5BA9
+#define SYSTEM_ICIALLU 0x43A8
#define SYSTEM_DCCVAU 0x5BD9
#define SYSTEM_DCCIVAC 0x5BF1
@@ -198,6 +199,7 @@ enum armv8_opcode {
ARMV8_OPC_DCCISW,
ARMV8_OPC_DCCIVAC,
ARMV8_OPC_ICIVAU,
+ ARMV8_OPC_ICIALLU,
ARMV8_OPC_HLT,
ARMV8_OPC_STRB_IP,
ARMV8_OPC_STRH_IP,
--
2.34.1