Add support for sfence.vma instruction

libr/arch/p/riscv/riscv-opc.c

@@ -660,6 +660,7 @@ static const struct riscv_opcode riscv_builtin_opcodes[] = {
 { "hret",      "I",   "",     MATCH_HRET, MASK_HRET, match_opcode, 0 },
 { "mret",      "I",   "",     MATCH_MRET, MASK_MRET, match_opcode, 0 },
 { "dret",      "I",   "",     MATCH_DRET, MASK_DRET, match_opcode, 0 },
+{ "sfence.vma","I", "s,t", MATCH_SFENCE_VMA, MASK_SFENCE_VMA, match_opcode, 0 },
 { "sfence.vm", "I",   "",     MATCH_SFENCE_VM, MASK_SFENCE_VM | MASK_RS1, match_opcode, 0 },
 { "sfence.vm", "I",   "s",    MATCH_SFENCE_VM, MASK_SFENCE_VM, match_opcode, 0 },
 { "wfi",       "I",   "",     MATCH_WFI, MASK_WFI, match_opcode, 0 },

libr/arch/p/riscv/riscv-opc.h

@@ -225,6 +225,8 @@
 #define MASK_MRET  0xffffffff
 #define MATCH_DRET 0x7b200073
 #define MASK_DRET  0xffffffff
+#define MATCH_SFENCE_VMA 0x12000073
+#define MASK_SFENCE_VMA  0xfe007fff
 #define MATCH_SFENCE_VM 0x10400073
 #define MASK_SFENCE_VM  0xfff07fff
 #define MATCH_WFI 0x10500073

libr/asm/d/riscv.sdb.txt

@@ -225,7 +225,8 @@ sd=store double word (64 bits)
 seqz=set if equal to zero
 sext=two complement
 sextw=two complement word
-sfence.vm=supervisor-mode fence for virtual memory
+sfence.vma=supervisor-mode fence for virtual memory
+sfence.vm=supervisor-mode fence for virtual memory (Deprecated)
 sgtz=set if greater than zero
 sh=store half-word (16 bits)
 slli=shift left logically by immediate