From c30d3ce6e3ec45a63ec162e2fbedc5084e3f6344 Mon Sep 17 00:00:00 2001 From: Adel Merabet Date: Thu, 13 Jun 2024 13:29:16 +0400 Subject: [PATCH 1/2] Add support for sfence.vma instruction --- libr/arch/p/riscv/riscv-opc.c | 1 + libr/arch/p/riscv/riscv-opc.h | 2 ++ libr/asm/d/riscv.sdb.txt | 3 ++- 3 files changed, 5 insertions(+), 1 deletion(-) diff --git a/libr/arch/p/riscv/riscv-opc.c b/libr/arch/p/riscv/riscv-opc.c index 63a6b18b02d88..6e62c2d14319a 100644 --- a/libr/arch/p/riscv/riscv-opc.c +++ b/libr/arch/p/riscv/riscv-opc.c @@ -660,6 +660,7 @@ static const struct riscv_opcode riscv_builtin_opcodes[] = { { "hret", "I", "", MATCH_HRET, MASK_HRET, match_opcode, 0 }, { "mret", "I", "", MATCH_MRET, MASK_MRET, match_opcode, 0 }, { "dret", "I", "", MATCH_DRET, MASK_DRET, match_opcode, 0 }, +{ "sfence.vma","I", "s,t", MATCH_SFENCE_VMA, MASK_SFENCE_VMA, match_opcode, 0 }, { "sfence.vm", "I", "", MATCH_SFENCE_VM, MASK_SFENCE_VM | MASK_RS1, match_opcode, 0 }, { "sfence.vm", "I", "s", MATCH_SFENCE_VM, MASK_SFENCE_VM, match_opcode, 0 }, { "wfi", "I", "", MATCH_WFI, MASK_WFI, match_opcode, 0 }, diff --git a/libr/arch/p/riscv/riscv-opc.h b/libr/arch/p/riscv/riscv-opc.h index 09d680b90b466..c1ac60f76b124 100644 --- a/libr/arch/p/riscv/riscv-opc.h +++ b/libr/arch/p/riscv/riscv-opc.h @@ -225,6 +225,8 @@ #define MASK_MRET 0xffffffff #define MATCH_DRET 0x7b200073 #define MASK_DRET 0xffffffff +#define MATCH_SFENCE_VMA 0x12000073 +#define MASK_SFENCE_VMA 0xfe007fff #define MATCH_SFENCE_VM 0x10400073 #define MASK_SFENCE_VM 0xfff07fff #define MATCH_WFI 0x10500073 diff --git a/libr/asm/d/riscv.sdb.txt b/libr/asm/d/riscv.sdb.txt index 2100015e5cc63..bc735806ea3ac 100644 --- a/libr/asm/d/riscv.sdb.txt +++ b/libr/asm/d/riscv.sdb.txt @@ -225,7 +225,8 @@ sd=store double word (64 bits) seqz=set if equal to zero sext=two complement sextw=two complement word -sfence.vm=supervisor-mode fence for virtual memory +sfence.vma=supervisor-mode fence for virtual memory +sfence.vm=supervisor-mode fence for virtual memory (Deprecated) sgtz=set if greater than zero sh=store half-word (16 bits) slli=shift left logically by immediate From 36cc10d217a481fce9db09da173ebca36691237a Mon Sep 17 00:00:00 2001 From: Adel Merabet Date: Thu, 13 Jun 2024 15:23:13 +0400 Subject: [PATCH 2/2] Aligned columns to match the other rows --- libr/arch/p/riscv/riscv-opc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libr/arch/p/riscv/riscv-opc.c b/libr/arch/p/riscv/riscv-opc.c index 6e62c2d14319a..f0ea834fda88f 100644 --- a/libr/arch/p/riscv/riscv-opc.c +++ b/libr/arch/p/riscv/riscv-opc.c @@ -660,7 +660,7 @@ static const struct riscv_opcode riscv_builtin_opcodes[] = { { "hret", "I", "", MATCH_HRET, MASK_HRET, match_opcode, 0 }, { "mret", "I", "", MATCH_MRET, MASK_MRET, match_opcode, 0 }, { "dret", "I", "", MATCH_DRET, MASK_DRET, match_opcode, 0 }, -{ "sfence.vma","I", "s,t", MATCH_SFENCE_VMA, MASK_SFENCE_VMA, match_opcode, 0 }, +{ "sfence.vma","I", "s,t", MATCH_SFENCE_VMA, MASK_SFENCE_VMA, match_opcode, 0 }, { "sfence.vm", "I", "", MATCH_SFENCE_VM, MASK_SFENCE_VM | MASK_RS1, match_opcode, 0 }, { "sfence.vm", "I", "s", MATCH_SFENCE_VM, MASK_SFENCE_VM, match_opcode, 0 }, { "wfi", "I", "", MATCH_WFI, MASK_WFI, match_opcode, 0 },