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target: Update after accurate RTL dependency generation
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colluca committed Oct 3, 2024
1 parent 4606d43 commit b2e49aa
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8 changes: 8 additions & 0 deletions target/sim/Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -435,6 +435,14 @@ $(CVA6_ANNOTATED_TRACE): $(CVA6_TXT_TRACE) $(ANNOTATE_PY)
# Questasim #
#############

GENERATED_RTL_SOURCES = $(MISC_OCCAMYGEN_SV_TARGETS)
GENERATED_RTL_SOURCES += $(TARGET_TEST_DIR)/testharness.sv
GENERATED_RTL_SOURCES += $(filter %.sv,$(CLINT_OCCAMYGEN_TARGETS) $(CLINT_REGGEN_TARGETS))
GENERATED_RTL_SOURCES += $(filter %.sv,$(PLIC_PLICGEN_TARGETS) $(PLIC_REGGEN_TARGETS))
GENERATED_RTL_SOURCES += $(filter %.sv,$(SOCCTRL_OCCAMYGEN_TARGETS) $(SOCCTRL_REGGEN_TARGETS))
GENERATED_RTL_SOURCES += $(filter %.sv,$(HBMCTRL_OCCAMYGEN_TARGETS) $(HBMCTRL_REGGEN_TARGETS))
GENERATED_RTL_SOURCES += $(filter %.sv,$(QUADCTRL_OCCAMYGEN_TARGETS) $(QUADCTRL_REGGEN_TARGETS))

include $(SNITCH_ROOT)/target/common/vsim.mk

# Add dependency on bootrom
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