From 39b4a3530b480e1a98330aaff5dd9b9da31ca229 Mon Sep 17 00:00:00 2001
From: Cyril Koenig <cyril27koenig@gmail.com>
Date: Thu, 21 Nov 2024 19:31:43 +0100
Subject: [PATCH] fpga: Bootmode to PCIe and device tree to PCIe

---
 target/fpga/bootrom/Makefile   |  2 +-
 target/fpga/bootrom/bootrom.S  |  2 +-
 target/fpga/bootrom/src/main.c | 19 +++++++------------
 3 files changed, 9 insertions(+), 14 deletions(-)

diff --git a/target/fpga/bootrom/Makefile b/target/fpga/bootrom/Makefile
index ff8cbe736..eed12e79c 100644
--- a/target/fpga/bootrom/Makefile
+++ b/target/fpga/bootrom/Makefile
@@ -50,7 +50,7 @@ check-uboot:
 	@[ "${UBOOT_SPL_BIN}" ] || ( echo "UBOOT_SPL_BIN is not set"; exit 1 )
 bootrom-spl.bin: check-uboot
 
-bootrom-spl.bin: bootrom.S $(OBJS_C) bootrom.ld occamy.dtb
+bootrom-spl.bin: bootrom.S $(OBJS_C) bootrom.ld occamy_pcie.dtb
 	$(CC) $(CFLAGS) $(INCLUDES) -Tbootrom.ld -DSPLBIN=\"$(UBOOT_SPL_BIN)\" $< $(OBJS_C) -o bootrom-spl.elf
 	$(OBJDUMP) -d bootrom-spl.elf > bootrom-spl.dump
 	$(OBJCOPY) -O binary bootrom-spl.elf bootrom-spl.bin
diff --git a/target/fpga/bootrom/bootrom.S b/target/fpga/bootrom/bootrom.S
index 1d6b5e76d..d2ca6f438 100644
--- a/target/fpga/bootrom/bootrom.S
+++ b/target/fpga/bootrom/bootrom.S
@@ -92,7 +92,7 @@ _snitch_resume:
 .align 3
 .globl device_tree
 device_tree:
-    .incbin "occamy.dtb"
+    .incbin "occamy_pcie.dtb"
 
 #ifdef SPLBIN
 .align 3
diff --git a/target/fpga/bootrom/src/main.c b/target/fpga/bootrom/src/main.c
index 987d07035..579b3a694 100644
--- a/target/fpga/bootrom/src/main.c
+++ b/target/fpga/bootrom/src/main.c
@@ -5,7 +5,7 @@
 #include "uart.h"
 #define SPL_SRC 0x1001000UL
 #define SPL_SIZE 65536
-#define SPL_DEST 0x70000000UL
+#define SPL_DEST 0xD0000000UL
 
 #define BIG_ENDIAN(n)                                   \
     (((n >> 24) & 0xFFu) | (((n >> 16) & 0xFFu) << 8) | \
@@ -31,7 +31,7 @@ int main() {
     print_uart("\r\n");
 
     // Hardcode boot mode for now. TODO(niwis): derive e.g. from GPIO.
-    enum boot_mode_t boot_mode = SPL_ROM;
+    enum boot_mode_t boot_mode = PCIE;
 
     switch (boot_mode) {
         case JTAG:
@@ -71,26 +71,21 @@ int main() {
             print_uart(")\r\nOK");
 
             // Parse the DTB size
-
             uint32_t totalsize = BIG_ENDIAN(*((uint32_t *)(__dtb_start) + 1));
+
             print_uart("\r\nTotalsize = ");
             print_uart_int(totalsize);
 
-            // Copy the DBT at (SPM+4)
+            // Copy the DBT at (SPM+0)
 
             print_uart("\r\nCopying DTB at ");
-            print_uart_addr(SPL_DEST + 4);
+            print_uart_addr(SPL_DEST + 0);
             for (int i = 0; i < totalsize; i++)
-                *(uint8_t *)(SPL_DEST + 4 + i) =
+                *(uint8_t *)(SPL_DEST + 0 + i) =
                     *(((uint8_t *)__dtb_start) + i);
 
             // Assert copy is done
-            __asm__ volatile("fence.i;");
-
-            // Copy the magic at SPM+0 to indicate end of transfert (put it back
-            // in big endian)
-            *((uint32_t *)SPL_DEST) = BIG_ENDIAN(magic);
-
+            __asm__ volatile("fence;");
             __asm__ volatile("fence.i;");
 
             // Now the host driver can read the DTB, CVA6 can go to sleep