diff --git a/Bender.yml b/Bender.yml index 05231665..f5a5a21b 100644 --- a/Bender.yml +++ b/Bender.yml @@ -32,6 +32,7 @@ sources: - src/cdc_reset_ctrlr_pkg.sv - src/cf_math_pkg.sv - src/clk_int_div.sv + - src/credit_counter.sv - src/delta_counter.sv - src/ecc_pkg.sv - src/edge_propagator_tx.sv diff --git a/CHANGELOG.md b/CHANGELOG.md index aeb68b71..32851b4e 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -4,6 +4,18 @@ All notable changes to this project will be documented in this file. The format is based on [Keep a Changelog](http://keepachangelog.com/en/1.0.0/) and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.html). +## 1.37.0 - 2024-07-18 +### Added +- `credit_counter`: Add up/down counter for credit. + +### Fixed +- `mem_to_banks_detailed`: Ensure no spurious response after full dead write. + +## 1.36.0 - 2024-07-08 +### Fixed +- `registers`: Fix else statement in FFARNC macro. +- `stream_arbiter_flushable`: Do not lock priority arbiter. + ## 1.35.0 - 2024-04-22 ### Changed - `id_queue`: Add parameter to cut a critical path. diff --git a/README.md b/README.md index 8c2aa59b..d91f6b37 100644 --- a/README.md +++ b/README.md @@ -55,6 +55,7 @@ Please note that cells with status *deprecated* are not to be used for new desig | Name | Description | Status | Superseded By | | ------------------- | ----------------------------------------------------------------- | ------------ | ------------- | | `counter` | Generic up/down counter with overflow detection | active | | +| `credit_counter` | Up/down counter for credit | active | | | `delta_counter` | Up/down counter with variable delta and overflow detection | active | | | `generic_LFSR_8bit` | 8-bit linear feedback shift register (LFSR) | *deprecated* | `lfsr_8bit` | | `lfsr_8bit` | 8-bit linear feedback shift register (LFSR) | active | | diff --git a/common_cells.core b/common_cells.core index 3cb48cb1..510b1c44 100644 --- a/common_cells.core +++ b/common_cells.core @@ -1,6 +1,6 @@ CAPI=2: -name : pulp-platform.org::common_cells:1.35.0 +name : pulp-platform.org::common_cells:1.37.0 filesets: rtl: @@ -16,6 +16,7 @@ filesets: - src/cc_onehot.sv - src/cf_math_pkg.sv - src/clk_int_div.sv + - src/credit_counter.sv - src/delta_counter.sv - src/ecc_pkg.sv - src/edge_propagator_tx.sv diff --git a/src/cdc_2phase.sv b/src/cdc_2phase.sv index e1a67b44..cf020567 100644 --- a/src/cdc_2phase.sv +++ b/src/cdc_2phase.sv @@ -111,7 +111,7 @@ module cdc_2phase_src #( always_ff @(posedge clk_i or negedge rst_ni) begin if (!rst_ni) begin req_src_q <= 0; - data_src_q <= '0; + data_src_q <= T'('0); end else if (valid_i && ready_o) begin req_src_q <= ~req_src_q; data_src_q <= data_i; @@ -171,7 +171,7 @@ module cdc_2phase_dst #( // indicated by the async_req line changing levels. always_ff @(posedge clk_i or negedge rst_ni) begin if (!rst_ni) begin - data_dst_q <= '0; + data_dst_q <= T'('0); end else if (req_q0 != req_q1 && !valid_o) begin data_dst_q <= async_data_i; end diff --git a/src/cdc_fifo_2phase.sv b/src/cdc_fifo_2phase.sv index 87332d1f..d482283a 100644 --- a/src/cdc_fifo_2phase.sv +++ b/src/cdc_fifo_2phase.sv @@ -90,7 +90,7 @@ module cdc_fifo_2phase #( for (genvar i = 0; i < 2**LOG_DEPTH; i++) begin : g_word always_ff @(posedge src_clk_i, negedge src_rst_ni) begin if (!src_rst_ni) - fifo_data_q[i] <= '0; + fifo_data_q[i] <= T'('0); else if (fifo_write && fifo_widx == i) fifo_data_q[i] <= fifo_wdata; end diff --git a/src/credit_counter.sv b/src/credit_counter.sv new file mode 100644 index 00000000..2792fd5a --- /dev/null +++ b/src/credit_counter.sv @@ -0,0 +1,55 @@ +// Copyright 2020 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 + +// Author: Fabian Schuiki +// Author: Paul Scheffler + +`include "common_cells/registers.svh" +`include "common_cells/assertions.svh" + +module credit_counter #( + parameter int unsigned NumCredits = 0, + /// Whether credit is full or empty on reset + parameter bit InitCreditEmpty = 1'b0, + /// Derived parameters *Do not override* + parameter int unsigned InitNumCredits = InitCreditEmpty ? '0 : NumCredits, + parameter type credit_cnt_t = logic [$clog2(NumCredits):0] +) ( + input logic clk_i, + input logic rst_ni, + + output credit_cnt_t credit_o, + + input logic credit_give_i, + input logic credit_take_i, + input logic credit_init_i, // Reinitialize (soft-reset) credit; takes priority + + output logic credit_left_o, + output logic credit_crit_o, // Giving one more credit will fill the credits + output logic credit_full_o +); + + credit_cnt_t credit_d, credit_q; + logic increment, decrement; + + assign decrement = credit_take_i & ~credit_give_i; + assign increment = ~credit_take_i & credit_give_i; + + always_comb begin + credit_d = credit_q; + if (decrement) credit_d = credit_q - 1; + else if (increment) credit_d = credit_q + 1; + end + + `FFARNC(credit_q, credit_d, credit_init_i, InitNumCredits, clk_i, rst_ni) + + assign credit_o = credit_q; + assign credit_left_o = (credit_q != '0); + assign credit_crit_o = (credit_q == NumCredits-1); + assign credit_full_o = (credit_q == NumCredits); + + `ASSERT_NEVER(CreditUnderflow, credit_o == '0 && decrement) + `ASSERT_NEVER(CreditOverflow, credit_o == NumCredits && increment) + +endmodule diff --git a/src/delta_counter.sv b/src/delta_counter.sv index 90b5cffa..415bd11c 100644 --- a/src/delta_counter.sv +++ b/src/delta_counter.sv @@ -28,7 +28,16 @@ module delta_counter #( logic [WIDTH:0] counter_q, counter_d; if (STICKY_OVERFLOW) begin : gen_sticky_overflow logic overflow_d, overflow_q; - always_ff @(posedge clk_i or negedge rst_ni) overflow_q <= ~rst_ni ? 1'b0 : overflow_d; + + always_ff @(posedge clk_i or negedge rst_ni) + begin + if(rst_ni) begin + overflow_q <= 1'b0; + end else begin + overflow_q <= overflow_d; + end + end + always_comb begin overflow_d = overflow_q; if (clear_i || load_i) begin diff --git a/src/fifo_v3.sv b/src/fifo_v3.sv index a1b61180..83df3b23 100644 --- a/src/fifo_v3.sv +++ b/src/fifo_v3.sv @@ -131,7 +131,7 @@ module fifo_v3 #( always_ff @(posedge clk_i or negedge rst_ni) begin if(~rst_ni) begin - mem_q <= '0; + mem_q <= {FifoDepth{dtype'('0)}}; end else if (!gate_clock) begin mem_q <= mem_n; end diff --git a/src/lossy_valid_to_stream.sv b/src/lossy_valid_to_stream.sv index 68dad552..8e172dd7 100644 --- a/src/lossy_valid_to_stream.sv +++ b/src/lossy_valid_to_stream.sv @@ -125,7 +125,7 @@ module lossy_valid_to_stream #( read_ptr_q <= '0; write_ptr_q <= '0; pending_tx_counter_q <= '0; - mem_q <= '0; + mem_q <= {2{T'('0)}}; end else begin read_ptr_q <= read_ptr_d; write_ptr_q <= write_ptr_d; diff --git a/src/mem_to_banks_detailed.sv b/src/mem_to_banks_detailed.sv index 1dac044b..24160031 100644 --- a/src/mem_to_banks_detailed.sv +++ b/src/mem_to_banks_detailed.sv @@ -109,8 +109,13 @@ module mem_to_banks_detailed #( resp_valid, resp_ready; req_t [NumBanks-1:0] bank_req, bank_oup; - logic [NumBanks-1:0] bank_req_internal, bank_gnt_internal, zero_strobe, dead_response; - logic dead_write_fifo_full; + logic [NumBanks-1:0] bank_req_internal, + bank_gnt_internal, + zero_strobe, + dead_response, + dead_response_unmasked; + logic dead_write_fifo_full, + dead_write_fifo_empty; function automatic addr_t align_addr(input addr_t addr); return (addr >> $clog2(DataBytes)) << $clog2(DataBytes); @@ -148,11 +153,13 @@ module mem_to_banks_detailed #( assign bank_wuser_o[i] = bank_oup[i].wuser; assign bank_we_o[i] = bank_oup[i].we; - assign zero_strobe[i] = (bank_oup[i].strb == '0); + assign zero_strobe[i] = (bank_req[i].strb == '0); if (HideStrb) begin : gen_hide_strb - assign bank_req_o[i] = (bank_oup[i].we && zero_strobe[i]) ? 1'b0 : bank_req_internal[i]; - assign bank_gnt_internal[i] = (bank_oup[i].we && zero_strobe[i]) ? 1'b1 : bank_gnt_i[i]; + assign bank_req_o[i] = (bank_oup[i].we && (bank_oup[i].strb == '0)) ? + 1'b0 : bank_req_internal[i]; + assign bank_gnt_internal[i] = (bank_oup[i].we && (bank_oup[i].strb == '0)) ? + 1'b1 : bank_gnt_i[i]; end else begin : gen_legacy_strb assign bank_req_o[i] = bank_req_internal[i]; assign bank_gnt_internal[i] = bank_gnt_i[i]; @@ -170,19 +177,22 @@ module mem_to_banks_detailed #( ) i_dead_write_fifo ( .clk_i, .rst_ni, - .flush_i ( 1'b0 ), - .testmode_i ( 1'b0 ), - .full_o ( dead_write_fifo_full ), - .empty_o (), + .flush_i ( 1'b0 ), + .testmode_i ( 1'b0 ), + .full_o ( dead_write_fifo_full ), + .empty_o ( dead_write_fifo_empty ), .usage_o (), - .data_i ( bank_we_o & zero_strobe ), - .push_i ( req_i & gnt_o ), - .data_o ( dead_response ), - .pop_i ( rvalid_o ) + .data_i ( {NumBanks{we_i}} & zero_strobe ), + .push_i ( req_i & gnt_o ), + .data_o ( dead_response_unmasked ), + .pop_i ( rvalid_o ) ); + assign dead_response = dead_response_unmasked & {NumBanks{~dead_write_fifo_empty}}; end else begin : gen_no_dead_write_fifo + assign dead_response_unmasked = '0; assign dead_response = '0; assign dead_write_fifo_full = 1'b0; + assign dead_write_fifo_empty = 1'b1; end // Handle responses. diff --git a/src/shift_reg_gated.sv b/src/shift_reg_gated.sv index 6a9657f1..f17ae7f7 100644 --- a/src/shift_reg_gated.sv +++ b/src/shift_reg_gated.sv @@ -53,7 +53,7 @@ module shift_reg_gated #( // Gate each shift register with a valid flag to enable the synthsis tools to insert ICG for // better power comsumption. - `FFL(data_q[i], data_d[i], valid_d[i], '0, clk_i, rst_ni) + `FFL(data_q[i], data_d[i], valid_d[i], dtype'('0), clk_i, rst_ni) end // Output the shifted result. diff --git a/src/spill_register_flushable.sv b/src/spill_register_flushable.sv index 8588a43a..cea3fc88 100644 --- a/src/spill_register_flushable.sv +++ b/src/spill_register_flushable.sv @@ -41,7 +41,7 @@ module spill_register_flushable #( always_ff @(posedge clk_i or negedge rst_ni) begin : ps_a_data if (!rst_ni) - a_data_q <= '0; + a_data_q <= T'('0); else if (a_fill) a_data_q <= data_i; end @@ -60,7 +60,7 @@ module spill_register_flushable #( always_ff @(posedge clk_i or negedge rst_ni) begin : ps_b_data if (!rst_ni) - b_data_q <= '0; + b_data_q <= T'('0); else if (b_fill) b_data_q <= a_data_q; end diff --git a/src/stream_arbiter_flushable.sv b/src/stream_arbiter_flushable.sv index 2c456a32..5ba84bbe 100644 --- a/src/stream_arbiter_flushable.sv +++ b/src/stream_arbiter_flushable.sv @@ -58,7 +58,7 @@ module stream_arbiter_flushable #( .DataType (DATA_T), .ExtPrio (1'b1), .AxiVldRdy (1'b1), - .LockIn (1'b1) + .LockIn (1'b0) ) i_arbiter ( .clk_i, .rst_ni, diff --git a/src/stream_register.sv b/src/stream_register.sv index d2c1571f..247ef34c 100644 --- a/src/stream_register.sv +++ b/src/stream_register.sv @@ -34,7 +34,7 @@ module stream_register #( assign ready_o = ready_i | ~valid_o; assign reg_ena = valid_i & ready_o; // Load-enable FFs with synch clear - `FFLARNC(valid_o, valid_i, ready_o, clr_i, 1'b0, clk_i, rst_ni) - `FFLARNC(data_o, data_i, reg_ena, clr_i, '0, clk_i, rst_ni) + `FFLARNC(valid_o, valid_i, ready_o, clr_i, 1'b0 , clk_i, rst_ni) + `FFLARNC(data_o, data_i, reg_ena, clr_i, T'('0), clk_i, rst_ni) endmodule diff --git a/src_files.yml b/src_files.yml index 0449fabe..30aebdba 100644 --- a/src_files.yml +++ b/src_files.yml @@ -11,6 +11,7 @@ common_cells_all: - src/cc_onehot.sv - src/cf_math_pkg.sv - src/clk_int_div.sv + - src/credit_counter.sv - src/delta_counter.sv - src/ecc_pkg.sv - src/edge_propagator_tx.sv