Timing closure issue

[radomirvr]

First of all, many thanks for this great port!

Issue Description

I'm trying to make the bitstream, but the design fails to meet the timing requirements by around 80 ps. Most of the paths are inter clock, between the rfdc_clk_x411_ps_rfdc_bd_data_clock_mmcm_0 and the rfdc_clk_2x_x411_ps_rfdc_bd_data_clock_mmcm_0 clock. I'm attaching the timing summary below.

The original ettus design (tag v4.4.0.0, commit 5fac246) passes timing successfully.

Should the design pass the timing or is this perhaps expected?

Setup Details

• Vivado v2021.1_AR76780
• x411 branch (commit f2901c6)
• X411_X4_200 design

Expected Behavior

Timing pass.

Actual Behaviour

Timing closure failed:

CRITICAL WARNING: [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.

Steps to reproduce the problem

make X411_X4_200

Additional Information

post_route_timing_summary.log

[ptrkrysik]

This is not expected behavior. I had some issues with 10 MHz reference clock when I tried to port newer code with X440 support, but this older design should meet timing requirements. I'll try to run the build on this code again.

[ptrkrysik]

I got also failure to meet timing requirements. Thank you for reporting this issue.
I'll try to find out where it came from.