From b45a2dde891321b43745563b794af32892fd0f10 Mon Sep 17 00:00:00 2001 From: Harshit Agarwal Date: Fri, 19 Aug 2022 11:20:45 +0100 Subject: [PATCH] Squashed 'drivers/mss/mss_mmc/' changes from 62358b9..1fc98a7 1fc98a7 copyright year updated to 2022 1cdaa30 DOCGEN : Removed Example keyword from function's descriptions adec87d DOCGEN :Constant section comments updated to get proper levels of nesting in TOC c00e4eb DOCGEN : Function's Example sections updated to make correct impression in MD file 000696c DOCGEN : TYPE section enum and struct tag id is added so that it reflect in md file also 37ba9d9 CPPCHECK: solving cpp check warning of id : misra-c2012-7.2 d329ddd insert spaces instead of tabs 44ee7f2 Fix SAR SAR 124399 to implement error recovery ESWBM_MPFS-87 71d4ef1 Fix SAR 125390 to add a delay to impact on tuning value ESWBM_MPFS-85 b83b0f1 Fix SAR 124154 to check command line busy based on timeout ESWBM_MPFS-86 27f453b check device status - HS400 with DATA0 line and HS400_ES with DATA0 and CMD13 for HS mode switching 0fbe0d1 change copy right to 2022 662ca32 checking the device status instead of error 5add218 changed local variable to 32-bit to read 32-bit register 9302abf DATA0 line is used for checking device busy state and CMD13 is ignored while Switching HS200 to HS mode in HS400 mode, remove single block read after changing HS(DDR) mode because its need required phy training otherwise gets crc errors but HS400 and HS400_ES is not using phy training git-subtree-dir: drivers/mss/mss_mmc git-subtree-split: 1fc98a7ff65ec86196c342032becc755eb2f8f88 --- mss_mmc.c | 274 +++++++++++++++++++++++++++-------------- mss_mmc.h | 273 +++++++++++++++++++++++++++++++--------- mss_mmc_if.c | 54 +++++--- mss_mmc_if.h | 8 +- mss_mmc_internal_api.h | 8 +- mss_mmc_regs.h | 8 +- mss_mmc_types.h | 8 +- 7 files changed, 447 insertions(+), 186 deletions(-) diff --git a/mss_mmc.c b/mss_mmc.c index 52b5f2b..cc9338a 100644 --- a/mss_mmc.c +++ b/mss_mmc.c @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * @@ -61,6 +61,7 @@ extern "C" { #define MMC_SOFTWARE_RESET_SHIFT 0x3u #define DEBOUNCING_TIME 0x300000u #define MMC_RESET_DATA_CMD_LINE 0x06000000u +#define CMD_TYPE_ABORT 0xC0u /* SDMA boundary is 512k */ #define SIZE_32MB 0x02000000u #define SIZE_64KB 0x00010000u @@ -150,8 +151,8 @@ extern "C" { bigger than 64KB for smaller parts. Split is made by ADMA module. */ #define SDIO_CFG_SDIO_BUFFERS_COUNT 0x4000u -#define SDIO_OPCODE_INC 0x04000000 -#define SDIO_WRITE 0x80000000 +#define SDIO_OPCODE_INC 0x04000000u +#define SDIO_WRITE 0x80000000u #define SDIO_CSA_REG_ADDR 0x10Fu #define SDIO_CSA_SUPPORT 0x40u #define SDIO_CSA_ENABLE 0x80u @@ -177,7 +178,7 @@ static uint8_t g_mmc_card_sd; #ifdef MSS_MMC_INTERNAL_APIS static uint8_t g_device_hpi_set = MMC_CLEAR; static uint32_t g_trans_remain_size = MMC_CLEAR; -static uint8_t * g_trans_src_addr = MMC_CLEAR; +static uint8_t * g_trans_src_addr = NULL_POINTER; static uint32_t g_trans_dest_addr = MMC_CLEAR; #endif /* MSS_MMC_INTERNAL_APIS */ @@ -373,7 +374,7 @@ MSS_MMC_init { ret_status = MSS_MMC_NOT_INITIALISED; } - + reg = MMC->SRS09; /* If card stable is not set it means that something is wrong */ if (((reg & SRS9_CARD_STATE_STABLE) == MMC_CLEAR) && @@ -429,6 +430,7 @@ MSS_MMC_init default: ret_status = MSS_MMC_NOT_INITIALISED; + break; } } else @@ -1172,11 +1174,8 @@ MSS_MMC_sdio_single_block_read srs9 = MMC->SRS09; }while ((srs9 & (SRS9_CMD_INHIBIT_CMD | SRS9_CMD_INHIBIT_DAT)) != MMC_CLEAR); - if(data_size == BLK_SIZE) - { - data_size = MMC_CLEAR; - } - arguement = (SDIO_CSA_REG_ADDR << SHIFT_9BIT) | SDIO_OPCODE_INC | data_size; + arguement = (SDIO_CSA_REG_ADDR << SHIFT_9BIT) | SDIO_OPCODE_INC | + ((data_size == BLK_SIZE) ? MMC_CLEAR : data_size); /* Command argument */ MMC->SRS02 = arguement; /* Execute command */ @@ -1249,8 +1248,8 @@ MSS_MMC_single_block_write cif_response_t response_status; mss_mmc_status_t ret_status = MSS_MMC_NO_ERROR; uint16_t word_cnt = MMC_CLEAR; - uint8_t blk_tran_err; - uint8_t blk_write; + uint32_t blk_tran_err; + uint32_t blk_write; uint32_t srs03_data, srs9; if (g_mmc_init_complete == MMC_SET) @@ -1616,8 +1615,8 @@ mss_mmc_status_t MSS_MMC_sdio_single_block_write ) { uint16_t word_cnt = MMC_CLEAR; - uint8_t blk_tran_err; - uint8_t blk_write; + uint32_t blk_tran_err; + uint32_t blk_write; uint16_t blk_size = (data_size/WORD_SIZE); uint32_t srs03_data, srs9; uint32_t arguement; @@ -1647,13 +1646,9 @@ mss_mmc_status_t MSS_MMC_sdio_single_block_write srs9 = MMC->SRS09; }while ((srs9 & (SRS9_CMD_INHIBIT_CMD | SRS9_CMD_INHIBIT_DAT)) != MMC_CLEAR); - if (data_size == BLK_SIZE) - { - data_size = MMC_CLEAR; - } - arguement = SDIO_WRITE | (SDIO_CSA_REG_ADDR << SHIFT_9BIT) - | SDIO_OPCODE_INC | data_size; + | SDIO_OPCODE_INC + | ((data_size == (uint16_t)BLK_SIZE)?MMC_CLEAR:(uint32_t)data_size); /* Command argument */ MMC->SRS02 = arguement; /* Execute command */ @@ -1772,6 +1767,89 @@ mss_mmc_status_t MSS_MMC_erase return ret_status; } +/*-------------------------------------------------------------------------*//** + * See "mss_mmc.h" for details of how to use this function. + */ +mss_mmc_status_t MSS_MMC_error_recovery(void) +{ + uint32_t trans_status_isr, enable_int; + mss_mmc_status_t ret_status; + cif_response_t response_status; + + /* Save interrupts */ + enable_int = MMC->SRS14; + /* Disable interrupts */ + MMC->SRS14 = MMC_CLEAR; + /* Clear interrupt status */ + MMC->SRS12 = MMC_STATUS_CLEAR; + + /* Reset cmd and data line */ + MMC->SRS11 |= MMC_RESET_DATA_CMD_LINE; + while ((MMC->SRS11 & MMC_RESET_DATA_CMD_LINE) != MMC_CLEAR); + + /* Execute CMD12 command to abort command */ + send_mmc_cmd(sdcard_RCA << SHIFT_16BIT, MMC_CMD_12_STOP_TRANSMISSION | CMD_TYPE_ABORT, + MSS_MMC_RESPONSE_R1B, CHECK_IF_CMD_SENT_POLL); + + trans_status_isr = MMC->SRS12; + + if ((SRS12_COMMAND_COMPLETE == (trans_status_isr & SRS12_COMMAND_COMPLETE)) && + (MMC_CLEAR == (SRS12_ERROR_INTERRUPT & trans_status_isr))) + { + + while ((MMC->SRS09 & SRS9_DAT0_SIGNAL_LEVEL) == MMC_CLEAR); + } + else + { + /* Reset cmd and data line */ + MMC->SRS11 |= MMC_RESET_DATA_CMD_LINE; + while ((MMC->SRS11 & MMC_RESET_DATA_CMD_LINE) != MMC_CLEAR); + } + + MMC->SRS12 = trans_status_isr; + /* CMD Line error occurs */ + if (((trans_status_isr) & (SRS12_COMMAND_TIMEOUT_ERROR | SRS12_COMMAND_CRC_ERROR + | SRS12_COMMAND_END_BIT_ERROR | SRS12_COMMAND_INDEX_ERROR + | SRS12_RESPONSE_ERROR)) != MMC_CLEAR) + { + /* Read device status */ + response_status = cif_send_cmd(sdcard_RCA << SHIFT_16BIT, + MMC_CMD_13_SEND_STATUS, + MSS_MMC_RESPONSE_R1); + } /* DAT Line error occurs */ + else if (((trans_status_isr) & (SRS12_DATA_END_BIT_ERROR | SRS12_DATA_CRC_ERROR + | SRS12_DATA_TIMEOUT_ERROR)) != MMC_CLEAR) + { + response_status = TRANSFER_IF_FAIL; + } + else + { + mmc_delay(DELAY_COUNT); + if ((MMC->SRS09 & (SRS9_DAT0_SIGNAL_LEVEL | SRS9_DAT1_SIGNAL_LEVEL + | SRS9_DAT2_SIGNAL_LEVEL | SRS9_DAT3_SIGNAL_LEVEL)) == MMC_CLEAR) + { + response_status = TRANSFER_IF_FAIL; + } + else + { + response_status = TRANSFER_IF_SUCCESS; + } + } + + /* Restore interrupt settings */ + MMC->SRS14 = enable_int; + + if (response_status == TRANSFER_IF_FAIL) + { + ret_status = MSS_MMC_TRANSFER_FAIL; + } + else + { + ret_status = MSS_MMC_TRANSFER_SUCCESS; + } + + return ret_status; +} /*-------------------------------------------------------------------------*//** * See "mss_mmc.h" for details of how to use this function. */ @@ -1988,6 +2066,7 @@ MSS_MMC_cq_write for(task_id = MMC_CLEAR; ((task_id < CQ_HOST_NUMBER_OF_TASKS) && (blockcount != MMC_CLEAR)); ++task_id) { desc_offset = CQ_HOST_NUMBER_OF_TASKS * task_id; + dcmdTaskDesc = (uint32_t *)(g_desc_addr + desc_offset); flags = (uint32_t)(CQ_DESC_VALID | CQ_DESC_END | CQ_DESC_ACT_TASK | CQ_DESC_INT); @@ -2009,17 +2088,11 @@ MSS_MMC_cq_write dcmdTaskDesc[BYTES_2] = MMC_CLEAR; dcmdTaskDesc[BYTES_3] = MMC_CLEAR; - if (trans_size > MASK_16BIT) - { - /* Data buffer size is 64KB */ - size = MMC_CLEAR; - } - else - { - size = trans_size; - } /* Supports only 64KB */ - dcmdTaskDesc[BYTES_4] = (uint32_t)((CQ_DESC_VALID | CQ_DESC_ACT_TRAN | CQ_DESC_END) | (size << SHIFT_16BIT)); + dcmdTaskDesc[BYTES_4] = (uint32_t)((CQ_DESC_VALID | CQ_DESC_ACT_TRAN + | CQ_DESC_END) + | (((size >= MASK_16BIT)?MMC_CLEAR:size) << SHIFT_16BIT)); + /* Data buffer address in host memory, lower part */ dcmdTaskDesc[BYTES_5] = (uint32_t)(uintptr_t)src; /* Data buffer address in host memory, higher part */ @@ -2147,17 +2220,9 @@ MSS_MMC_cq_read dcmdTaskDesc[BYTES_2] = MMC_CLEAR; dcmdTaskDesc[BYTES_3] = MMC_CLEAR; - if (trans_size > MASK_16BIT) - { - /* Data buffer size is 64KB */ - size = MMC_CLEAR; - } - else - { - size = trans_size; - } /* Supports only 64KB */ - dcmdTaskDesc[BYTES_4] = (uint32_t)((CQ_DESC_VALID | CQ_DESC_ACT_TRAN | CQ_DESC_END) | (size << SHIFT_16BIT)); + dcmdTaskDesc[BYTES_4] = (uint32_t)((CQ_DESC_VALID | CQ_DESC_ACT_TRAN + | CQ_DESC_END) | (((size > MASK_16BIT)?MMC_CLEAR:size) << SHIFT_16BIT)); /* Data buffer address in host memory, lower part */ dcmdTaskDesc[BYTES_5] = (uint32_t)(uintptr_t)dest; /* Data buffer address in host memory, higher part */ @@ -2443,7 +2508,7 @@ MSS_MMC_pause_sdma_write_hpi g_trans_remain_size = remaining_sectors * BLK_SIZE; g_trans_dest_addr = (dest + total_sectors) - remaining_sectors; - g_trans_src_addr = (uint8_t *)(src + (prog_sector_num * BLK_SIZE)); + g_trans_src_addr = (const uint8_t *)(src + (prog_sector_num * BLK_SIZE)); g_device_hpi_set = MMC_SET; } @@ -2969,9 +3034,11 @@ MSS_MMC_cq_single_task_read static mss_mmc_status_t phy_training_mmc(uint8_t delay_type, uint32_t clk_rate) { uint8_t delay; - uint8_t max_delay; + uint32_t max_delay; uint8_t new_delay; - uint8_t pos, length, curr_length; + uint8_t pos = MMC_CLEAR; + uint8_t length = MMC_CLEAR; + uint8_t curr_length = MMC_CLEAR; uint8_t rx_buff[BLK_SIZE]; uint32_t read_srs11; uint32_t cmd_response; @@ -2988,7 +3055,6 @@ static mss_mmc_status_t phy_training_mmc(uint8_t delay_type, uint32_t clk_rate) max_delay = (MSS_MMC_CLOCK_200MHZ / clk_rate) * BYTES_2; } - pos = length = curr_length = MMC_CLEAR; /* Reset Data and cmd line */ MMC->SRS11 |= MMC_RESET_DATA_CMD_LINE; for (delay = MMC_CLEAR; delay < max_delay; delay++) @@ -3136,11 +3202,14 @@ static mss_mmc_status_t adma2_create_descriptor_table { current_subsize = size; } - adma_descriptor_table[j++] = (ADMA2_DESCRIPTOR_TYPE_TRAN + adma_descriptor_table[j] = (ADMA2_DESCRIPTOR_TYPE_TRAN | ADMA2_DESCRIPTOR_VAL | ADMA2_DESCRIPTOR_INT | ((current_subsize & MASK_16BIT) << SHIFT_16BIT)); - adma_descriptor_table[j++] = ((uint32_t)buf_address & MASK_32BIT); - adma_descriptor_table[j++] = (uint32_t)((uint64_t)buf_address >> MMC_64BIT_UPPER_ADDR_SHIFT); + j++; + adma_descriptor_table[j] = ((uint32_t)buf_address & MASK_32BIT); + j++; + adma_descriptor_table[j] = (uint32_t)((uint64_t)buf_address >> MMC_64BIT_UPPER_ADDR_SHIFT); + j++; adma_descriptor_table[j] = MMC_CLEAR; j++; @@ -3151,11 +3220,14 @@ static mss_mmc_status_t adma2_create_descriptor_table } else { - adma_descriptor_table[j++] = (ADMA2_DESCRIPTOR_TYPE_TRAN + adma_descriptor_table[j] = (ADMA2_DESCRIPTOR_TYPE_TRAN | ADMA2_DESCRIPTOR_VAL | ADMA2_DESCRIPTOR_INT | ((datasize & MASK_16BIT) << SHIFT_16BIT)); - adma_descriptor_table[j++] = ((uint32_t)buf_address & MASK_32BIT); - adma_descriptor_table[j++] = (uint32_t)((uint64_t)buf_address >> MMC_64BIT_UPPER_ADDR_SHIFT); + j++; + adma_descriptor_table[j] = ((uint32_t)buf_address & MASK_32BIT); + j++; + adma_descriptor_table[j] = (uint32_t)((uint64_t)buf_address >> MMC_64BIT_UPPER_ADDR_SHIFT); + j++; adma_descriptor_table[j] = MMC_CLEAR; i = MMC_SET; } @@ -3264,14 +3336,13 @@ static mss_mmc_status_t mmccard_oper_config(const mss_mmc_cfg_t * cfg) response_status = cif_send_cmd( MMC_DW_CSD |(MSS_MMC_DATA_WIDTH_1BIT << SHIFT_8BIT), MMC_CMD_6_SWITCH, MSS_MMC_RESPONSE_R1B); - if (TRANSFER_IF_FAIL == response_status) - { - ret_status = MSS_MMC_DWIDTH_ERR; - } - else + if (TRANSFER_IF_FAIL != response_status) { response_status = check_device_status(response_status); + } + if (TRANSFER_IF_SUCCESS == response_status) + { /* Set Phy delay for select MMC mode */ ret_status = phy_training_mmc(MSS_MMC_PHY_DELAY_INPUT_MMC_LEGACY, MSS_MMC_CLOCK_400KHZ); if (ret_status == MSS_MMC_TRANSFER_SUCCESS) @@ -3982,7 +4053,7 @@ static mss_mmc_status_t sdio_oper_config(const mss_mmc_cfg_t * cfg) mmc_delay(MASK_8BIT); sdio_host_access_fbr(SDIOHOST_CCCR_READ, &sdio_csa_support, BYTES_1, MSS_MMC_FBR_STD_SDIO_FN, MMC_SET, MMC_CLEAR); - if (sdio_csa_support & SDIO_CSA_SUPPORT != MMC_CLEAR) + if ((sdio_csa_support & SDIO_CSA_SUPPORT) != MMC_CLEAR) { sdio_host_access_fbr(SDIOHOST_CCCR_WRITE, &sdio_csa_enable, BYTES_1, MSS_MMC_FBR_STD_SDIO_FN, MMC_SET, MMC_SET); @@ -4028,7 +4099,7 @@ static mss_mmc_status_t sdio_oper_config(const mss_mmc_cfg_t * cfg) static mss_mmc_status_t change_sdio_device_bus_mode(const mss_mmc_cfg_t * cfg) { mss_mmc_status_t ret_status = MSS_MMC_NO_ERROR; - uint8_t high_speed_reg, uhsi_support; + uint8_t high_speed_reg, uhsi_support = 0; uint8_t enable_high_speed = MMC_CLEAR; uint32_t tmp; /* Get high speed register from a card */ @@ -4194,8 +4265,9 @@ static void sdio_host_access_cccr argument = (uint32_t)((register_address + i) << SHIFT_9BIT) | (raw << SHIFT_27BIT) | (uint32_t)(transfer_direction << SHIFT_31BIT) - | *data_byte++; - + | *data_byte; + data_byte++; + /* Execute command CMD52 to write data to CCCR register */ response_status = cif_send_cmd(argument, SDIO_CMD_52_IO_RW_DIRECT, @@ -4218,6 +4290,7 @@ static void sdio_host_access_fbr uint8_t number_of_bytes, i = MMC_CLEAR; uint32_t argument, response, tmp = MMC_CLEAR; cif_response_t response_status = TRANSFER_IF_SUCCESS; + uint32_t register_address_temp = MMC_CLEAR; /* Set numbers of bytes to transfer and check if the data parameter has appropriate size */ switch (register_address) { @@ -4240,11 +4313,11 @@ static void sdio_host_access_fbr } if (fun_num == MMC_CLEAR) { - register_address = register_address + SDIO_FBR_BASE_ADDR; + register_address_temp = register_address + SDIO_FBR_BASE_ADDR; } else { - register_address = register_address + (SDIO_FBR_BASE_ADDR * fun_num); + register_address_temp = register_address + (SDIO_FBR_BASE_ADDR * fun_num); } /* Read data from the CCCR register */ if (transfer_direction == MMC_CLEAR) @@ -4252,7 +4325,7 @@ static void sdio_host_access_fbr for (i = MMC_CLEAR; i < number_of_bytes; i++) { /* Set address of register to read */ - argument = (uint32_t)((register_address + i) << SHIFT_9BIT) + argument = (uint32_t)((register_address_temp + i) << SHIFT_9BIT) | (raw << SHIFT_27BIT) | (uint32_t)(transfer_direction << SHIFT_31BIT); @@ -4265,7 +4338,7 @@ static void sdio_host_access_fbr tmp |= (response & MASK_8BIT) << (i * SHIFT_8BIT); } - switch (register_address) + switch (register_address_temp) { case MSS_MMC_FBR_ADDR_CIS: case MSS_MMC_FBR_ADDR_CSA: @@ -4286,10 +4359,11 @@ static void sdio_host_access_fbr for (i = MMC_CLEAR; i < number_of_bytes; i++) { /* Set address of register to write */ - argument = (uint32_t)((register_address + i) << SHIFT_9BIT) + argument = (uint32_t)((register_address_temp + i) << SHIFT_9BIT) | (raw << SHIFT_27BIT) | (uint32_t)(transfer_direction << SHIFT_31BIT) - | *data_byte++; + | *data_byte; + data_byte++; /* Execute command CMD52 to write data to CCCR register */ response_status = cif_send_cmd(argument, @@ -4311,9 +4385,10 @@ static void sdio_host_get_tuple_from_cis uint8_t i; uint8_t next_tuple_offset; cif_response_t response_status = TRANSFER_IF_SUCCESS; + uint32_t tuple_address_temp = tuple_address; - argument = (tuple_address << SHIFT_9BIT); - while (MMC_SET) + argument = (tuple_address_temp << SHIFT_9BIT); + while (true) { uint8_t read_tuple_code; /* Read tuple code name */ @@ -4321,27 +4396,27 @@ static void sdio_host_get_tuple_from_cis SDIO_CMD_52_IO_RW_DIRECT, MSS_MMC_RESPONSE_R5); response = MMC->SRS04; - if ((response & MASK_8BIT) == MSS_MMC_TUPLE_CISTPL_END) + if ((uint32_t)MSS_MMC_TUPLE_CISTPL_END == (response & MASK_8BIT)) { /* SDIO ERR TUPLE NOT FOUND */ } - read_tuple_code = response & MASK_8BIT; + read_tuple_code = (uint8_t)response & MASK_8BIT; - tuple_address++; - argument = tuple_address << SHIFT_9BIT; + tuple_address_temp++; + argument = tuple_address_temp << SHIFT_9BIT; /* Read link to next tuple */ response_status = cif_send_cmd(argument, SDIO_CMD_52_IO_RW_DIRECT, MSS_MMC_RESPONSE_R5); response = MMC->SRS04; - if ((response & MASK_8BIT) == MSS_MMC_TUPLE_CISTPL_END) + if ((uint32_t)MSS_MMC_TUPLE_CISTPL_END == (response & MASK_8BIT)) { /* SDIO ERR TUPLE NOT FOUND */ } /* Save size of tuple body */ - next_tuple_offset = response & MASK_8BIT; - tuple_address++; + next_tuple_offset = (uint8_t)response & MASK_8BIT; + tuple_address_temp++; if (read_tuple_code == tuple_code) { @@ -4352,7 +4427,7 @@ static void sdio_host_get_tuple_from_cis for (i = MMC_CLEAR; i < next_tuple_offset; i++) { - argument = (tuple_address + i) << SHIFT_9BIT; + argument = (tuple_address_temp + i) << SHIFT_9BIT; /* Read tuple body */ response_status = cif_send_cmd(argument, SDIO_CMD_52_IO_RW_DIRECT, @@ -4365,8 +4440,8 @@ static void sdio_host_get_tuple_from_cis } else { - tuple_address += next_tuple_offset; - argument = tuple_address << SHIFT_9BIT; + tuple_address_temp += next_tuple_offset; + argument = tuple_address_temp << SHIFT_9BIT; } } @@ -4800,6 +4875,8 @@ static mss_mmc_status_t set_device_hs400_mode(const mss_mmc_cfg_t *cfg) set_host_sdclk(cfg->clk_rate); /* HS200 tuning */ ret_status = execute_tunning_mmc(MSS_MMC_DATA_WIDTH_8BIT); + if (MSS_MMC_TRANSFER_SUCCESS != ret_status) + return ret_status; ret_status = MSS_MMC_single_block_read(READ_SEND_EXT_CSD, csd_reg); if (MSS_MMC_TRANSFER_SUCCESS == ret_status) @@ -4833,7 +4910,21 @@ static mss_mmc_status_t set_device_hs400_mode(const mss_mmc_cfg_t *cfg) if (TRANSFER_IF_FAIL != response_status) { - response_status = check_device_status(response_status); + if (MSS_MMC_MODE_HS400_ES == cfg->bus_speed_mode) + { + response_status = check_device_status(response_status); + } + else + { + uint32_t srs9; + + do + { + srs9 = MMC->SRS09; + }while ((srs9 & SRS9_DAT0_SIGNAL_LEVEL) == MMC_CLEAR); + + response_status = TRANSFER_IF_SUCCESS; + } } if (TRANSFER_IF_SUCCESS == response_status) @@ -4874,17 +4965,6 @@ static mss_mmc_status_t set_device_hs400_mode(const mss_mmc_cfg_t *cfg) set_host_sdclk(MSS_MMC_CLOCK_50MHZ); - ret_status = MSS_MMC_single_block_read(READ_SEND_EXT_CSD, csd_reg); - if (MSS_MMC_TRANSFER_SUCCESS == ret_status) - { - pcsd_reg = (uint8_t *)csd_reg; - /* Offsets defined in JESD84-B51 extended CSD */ - hw_device_type = pcsd_reg[EXT_CSD_CARD_TYPE_OFFSET]; - hw_sec_count = csd_reg[EXT_CSD_SECTOR_COUNT_OFFSET/WORD_SIZE]; - hw_ext_csd_rev = pcsd_reg[EXT_CSD_REVISION_OFFSET] & BYTE_MASK; - hw_hs_timing = pcsd_reg[EXT_CSD_HS_TIMING_OFFSET]; - } - /* Set HS400 mode */ hs_timing = MMC_HS400_MODE; response_status = cif_send_cmd(hs_timing, @@ -5278,7 +5358,9 @@ static mss_mmc_status_t set_sdhost_power(uint32_t voltage) /******************************************************************************/ static void mmc_delay(uint32_t value) { - while (value--) asm volatile(""); + uint32_t tempValue = value; + + while (tempValue-- != 0u) asm volatile(""); } /******************************************************************************/ static mss_mmc_status_t cmd6_single_block_read @@ -5309,7 +5391,7 @@ static mss_mmc_status_t cmd6_single_block_read srs9 = MMC->SRS09; }while ((srs9 & (SRS9_CMD_INHIBIT_CMD | SRS9_CMD_INHIBIT_DAT)) != MMC_CLEAR); - word_cnt = (size/WORD_SIZE); + word_cnt = (uint16_t)(size/WORD_SIZE); /* Command argument */ MMC->SRS02 = src_addr; /* Execute command */ @@ -5395,6 +5477,7 @@ static mss_mmc_status_t execute_tunning_mmc(uint8_t data_width) Pos = calc_longest_valid_delay_chain_val(PatternOk); /* Delay value set to Pos */ host_mmc_tune(Pos); + mmc_delay(0xFFFu); ret_status = read_tune_block(ReadPattern, BufferSize, MMC_CMD_21_SEND_TUNE_BLK); return ret_status; } @@ -5428,7 +5511,7 @@ static mss_mmc_status_t read_tune_block srs9 = MMC->SRS09; }while ((srs9 & (SRS9_CMD_INHIBIT_CMD | SRS9_CMD_INHIBIT_DAT)) != MMC_CLEAR); - word_cnt = size/WORD_SIZE; + word_cnt = (uint16_t)size/WORD_SIZE; /* Command argument */ MMC->SRS02 = MMC_CLEAR; /* Execute command */ @@ -5581,6 +5664,7 @@ static uint8_t calc_longest_valid_delay_chain_val(const uint8_t* pattern_ok) static cif_response_t check_device_status(cif_response_t rsp_status) { uint32_t srs9; + cif_response_t device_rsp_status = rsp_status; do { @@ -5592,13 +5676,13 @@ static cif_response_t check_device_status(cif_response_t rsp_status) * so function must not return until the 'READY FOR DATA' * bit is set in the Card Status Register. */ - while (DEVICE_BUSY == rsp_status) + while (DEVICE_BUSY == device_rsp_status) { - rsp_status = cif_send_cmd(sdcard_RCA << RCA_SHIFT_BIT, + device_rsp_status = cif_send_cmd(sdcard_RCA << RCA_SHIFT_BIT, MMC_CMD_13_SEND_STATUS, MSS_MMC_RESPONSE_R1); } - return rsp_status; + return device_rsp_status; } /******************************************************************************/ diff --git a/mss_mmc.h b/mss_mmc.h index 6520bd2..3d48bc9 100644 --- a/mss_mmc.h +++ b/mss_mmc.h @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * @@ -70,8 +70,10 @@ - Initialization - Block Transfer Control - Block Transfer Status + - Block Erase - Interrupt Handling - Command Queue + - Error Recovery -------------------------------- Initialization @@ -130,6 +132,11 @@ The status of the eMMC SD block read or write transfer can be retrieved using the MSS_MMC_get_transfer_status() function. + -------------------------------- + Block Erase + -------------------------------- + The MSS_MMC_erase() function is used to erase the eMMC/SD device blocks. + -------------------------------- Interrupt Handling -------------------------------- @@ -159,10 +166,17 @@ To read a single block or multiple blocks of data stored within the eMMC device using a command queue, a call is made to the MSS_MMC_cq_read() function. This function supports up to 32 tasks. + + -------------------------------- + Error Recovery + -------------------------------- + The MSS_MMC_error_recovery() function is used to check whether the error is + recoverable or non-recoverable based on the generic operation of error + recovery procedure. *//*=========================================================================*/ -#ifndef __MSS_MMC_H -#define __MSS_MMC_H +#ifndef MSS_MMC_H +#define MSS_MMC_H #include #include @@ -171,8 +185,20 @@ extern "C" #endif -/*----------------------------------------------------------------------------*/ -/* Clock rate*/ +/*-------------------------------------------------------------------------*//** + Clock Rate + ============================ + + | Constant | Description | + |-----------------------|---------------------------| + | MSS_MMC_CLOCK_400KHZ | Clock rate of 400 KHz | + | MSS_MMC_CLOCK_12_5MHZ | Clock rate of 12.5 MHz | + | MSS_MMC_CLOCK_25MHZ | Clock rate of 25 MHz | + | MSS_MMC_CLOCK_26MHZ | Clock rate of 26 MHz | + | MSS_MMC_CLOCK_50MHZ | Clock rate of 50 MHz | + | MSS_MMC_CLOCK_100MHZ | Clock rate of 100 MHz | + | MSS_MMC_CLOCK_200MHZ | Clock rate of 200 MHz | + */ #define MSS_MMC_CLOCK_400KHZ 400u #define MSS_MMC_CLOCK_12_5MHZ 12500u #define MSS_MMC_CLOCK_25MHZ 25000u @@ -180,94 +206,162 @@ extern "C" #define MSS_MMC_CLOCK_50MHZ 50000u #define MSS_MMC_CLOCK_100MHZ 100000u #define MSS_MMC_CLOCK_200MHZ 200000u -/* card type */ + +/*-------------------------------------------------------------------------*//** + Card Type + ============================ + + | Constant | Description | + |--------------------------|---------------| + | MSS_MMC_CARD_TYPE_NONE | None | + | MSS_MMC_CARD_TYPE_MMC | MMC Card | + | MSS_MMC_CARD_TYPE_SD | SD Card | + | MSS_MMC_CARD_TYPE_SDIO | SDIO Card | + | MSS_MMC_CARD_TYPE_COMBO | COMBO Card | + */ #define MSS_MMC_CARD_TYPE_NONE 0u #define MSS_MMC_CARD_TYPE_MMC 1u #define MSS_MMC_CARD_TYPE_SD 2u #define MSS_MMC_CARD_TYPE_SDIO 3u #define MSS_MMC_CARD_TYPE_COMBO 4u -/* Host controller eMMC mode select */ +/*------------------------------------------------------------------------*//** + Host Controller eMMC Mode Select + ============================ +*/ -/* High-speed single data rate supports clock frequency up to 52 MHz and data - * bus width of 1 bit, 4 bits, and 8 bits. +/** + ## MSS_MMC_MODE_SDR + High-speed single data rate supports clock frequency up to 52 MHz and data + bus width of 1 bit, 4 bits, and 8 bits. */ #define MSS_MMC_MODE_SDR 0x2u -/* High speed double data rate supports clock frequency up to 52 MHz and data - * bus width of 4 bits and 8 bits. +/** + ## MSS_MMC_MODE_DDR + High speed double data rate supports clock frequency up to 52 MHz and data + bus width of 4 bits and 8 bits. */ #define MSS_MMC_MODE_DDR 0x3u -/* SDR data sampling supports clock frequency up to 200 MHz and data bus width - * of 4 bits and 8 bits. +/** + ## MSS_MMC_MODE_HS200 + SDR data sampling supports clock frequency up to 200 MHz and data bus width + of 4 bits and 8 bits. */ #define MSS_MMC_MODE_HS200 0x4u -/* DDR data sampling supports clock frequency up to 200 MHz and data bus width - * of 8 bits. +/** + ## MSS_MMC_MODE_HS400 + DDR data sampling supports clock frequency up to 200 MHz and data bus width + of 8 bits. */ #define MSS_MMC_MODE_HS400 0x5u -/* HS400 mode with Enhanced Strobe. */ +/** + ## MSS_MMC_MODE_HS400_ES + HS400 mode with Enhanced Strobe. + */ #define MSS_MMC_MODE_HS400_ES 0x6u -/* Backwards compatibility with legacy MMC card supports clock frequency up to - * 26MHz and data bus width of 1 bit, 4 bits, and 8 bits. +/** + ## MSS_MMC_MODE_LEGACY + Backwards compatibility with legacy MMC card supports clock frequency up to + 26MHz and data bus width of 1 bit, 4 bits, and 8 bits. */ #define MSS_MMC_MODE_LEGACY 0x7u #define MSS_MMC_MODE_MASK 0x00000007u #define MSS_MMC_MODE_SDCARD 0x0u -/* Host controller SD/SDIO card mode select */ +/*------------------------------------------------------------------------*//** + Host controller SD/SDIO card mode select + ============================ +*/ -/* Default speed supports clock frequency up to 25 MHz and data bus width of - * 4 bits. +/** ## MSS_SDCARD_MODE_DEFAULT_SPEED + Default speed supports clock frequency up to 25 MHz and data bus width of + 4 bits. */ #define MSS_SDCARD_MODE_DEFAULT_SPEED 0x8u -/* High-speed supports clock frequency up to 50 MHz and data bus width of - * 4 bits. +/** ## MSS_SDCARD_MODE_HIGH_SPEED + High-speed supports clock frequency up to 50 MHz and data bus width of + 4 bits. */ #define MSS_SDCARD_MODE_HIGH_SPEED 0x9u -/* Ultra-High speed-I (UHS-I) single data rate supports clock frequency up to - * 25 MHz and data bus width of 4 bits. +/** ## MSS_SDCARD_MODE_SDR12 + Ultra-High speed-I (UHS-I) single data rate supports clock frequency up to + 25 MHz and data bus width of 4 bits. */ #define MSS_SDCARD_MODE_SDR12 0xAu -/* Ultra-High speed-I (UHS-I) single data rate supports clock frequency up to - * 50 MHz and data bus width of 4 bits. +/** ## MSS_SDCARD_MODE_SDR25 + Ultra-High speed-I (UHS-I) single data rate supports clock frequency up to + 50 MHz and data bus width of 4 bits. */ #define MSS_SDCARD_MODE_SDR25 0xBu -/* Ultra-High speed-I (UHS-I) single data rate supports clock frequency up to - * 100 MHz and data bus width of 4 bits. +/** ## MSS_SDCARD_MODE_SDR50 + Ultra-High speed-I (UHS-I) single data rate supports clock frequency up to + 100 MHz and data bus width of 4 bits. */ #define MSS_SDCARD_MODE_SDR50 0xCu -/* Ultra-High speed-I (UHS-I) single data rate supports clock frequency up to - * 208 MHz and data bus width of 4 bits. +/** ## MSS_SDCARD_MODE_SDR104 + Ultra-High speed-I (UHS-I) single data rate supports clock frequency up to + 208 MHz and data bus width of 4 bits. */ #define MSS_SDCARD_MODE_SDR104 0xDu -/* Ultra-High speed-I (UHS-I) double data rate supports clock frequency up to - * 50 MHz and data bus width of 4 bits. +/** ## MSS_SDCARD_MODE_DDR50 + Ultra-High speed-I (UHS-I) double data rate supports clock frequency up to + 50 MHz and data bus width of 4 bits. */ #define MSS_SDCARD_MODE_DDR50 0xEu -/* Host controller data width */ +/*-------------------------------------------------------------------------*//** + Host Controller Data Width + ============================ + + | Constant | Description | + |-----------------------------|--------------------------------------| + | MSS_MMC_DATA_WIDTH_1BIT | Host Controller data width is 1 bit | + | MSS_MMC_DATA_WIDTH_4BIT | Host Controller data width is 4 bit | + | MSS_MMC_DATA_WIDTH_8BIT | Host Controller data width is 8 bit | + */ #define MSS_MMC_DATA_WIDTH_1BIT 0x00u #define MSS_MMC_DATA_WIDTH_4BIT 0x01u #define MSS_MMC_DATA_WIDTH_8BIT 0x02u -/* eMMC bus voltage */ -/* 1.8v */ +/*-------------------------------------------------------------------------*//** + eMMC Bus Voltage + ============================ + + | Constant | Description | + |-----------------------------|-----------------------| + | MSS_MMC_1_8V_BUS_VOLTAGE | Bus voltage is 1.8 V | + | MSS_MMC_3_3V_BUS_VOLTAGE | Bus voltage is 3.3 V | + */ #define MSS_MMC_1_8V_BUS_VOLTAGE 18u -/* 3.3v */ #define MSS_MMC_3_3V_BUS_VOLTAGE 33u +/*------------------------------------------------------------------------*//** + MSS SDIO Function Number + ============================ + + | Constant | Description | + |-----------------------------|-----------------------| + | MSS_SDIO_FUNCTION_NUMBER_0 | Function number is 0 | + | MSS_SDIO_FUNCTION_NUMBER_1 | Function number is 1 | + | MSS_SDIO_FUNCTION_NUMBER_2 | Function number is 2 | + | MSS_SDIO_FUNCTION_NUMBER_3 | Function number is 3 | + | MSS_SDIO_FUNCTION_NUMBER_4 | Function number is 4 | + | MSS_SDIO_FUNCTION_NUMBER_5 | Function number is 5 | + | MSS_SDIO_FUNCTION_NUMBER_6 | Function number is 6 | + | MSS_SDIO_FUNCTION_NUMBER_7 | Function number is 7 | + */ #define MSS_SDIO_FUNCTION_NUMBER_0 0u #define MSS_SDIO_FUNCTION_NUMBER_1 1u #define MSS_SDIO_FUNCTION_NUMBER_2 2u @@ -285,7 +379,7 @@ MSS_MMC_sdma_read(), MSS_MMC_adma2_write(), MSS_MMC_adma2_read(), MSS_MMC_cq_init(), MSS_MMC_cq_write(), MSS_MMC_cq_read(), MSS_MMC_sdio_single_block_read(), MSS_MMC_sdio_single_block_write() functions. */ -typedef enum +typedef enum mss_mmc_status { MSS_MMC_INIT_SUCCESS = 0u, MSS_MMC_INIT_FAILURE, @@ -342,7 +436,7 @@ typedef enum of this structure should be passed as the first parameter to the MSS_MMC_init() function. */ -typedef struct +typedef struct mss_mmc_cfg { /* Specifies the clock frequency of the eMMC/SD/SDIO devices */ uint32_t clk_rate; @@ -390,10 +484,11 @@ typedef void (*mss_mmc_handler_t)(uint32_t status); @return This function returns the initialization status of the eMMC/SD/SDIO device as a value of type mss_mmc_status_t. - - Example: + + @example The following example shows how to initialize the eMMC device and configure the data rate 25Mhz. + @code mss_mmc_cfg_t g_mmc0; @@ -443,9 +538,10 @@ MSS_MMC_init This function returns a value of type mss_mmc_status_t which specifies the transfer status of the operation. - Example: + @example The following example shows how to initialize the device, perform a single block transfer. + @code #define SECT_1 0x01u @@ -507,11 +603,12 @@ MSS_MMC_single_block_write @return This function returns a value of type mss_mmc_status_t which specifies the transfer status of the operation. - - Example: + + @example The following example shows how to initialize the device, perform a single block transfer and read back the data from the sector written to within the eMMC device. + @code #define SECT_1 0x01u @@ -589,10 +686,11 @@ MSS_MMC_single_block_read @return This function returns a value of type mss_mmc_status_t which specifies the transfer status of the operation. - - Example: + + @example The following example shows how to initialize the device, perform a multi block write transfer using SDMA. + @code #define SECT_1 0x01u @@ -667,9 +765,10 @@ MSS_MMC_sdma_write This function returns a value of type mss_mmc_status_t which specifies the transfer status of the operation. - Example: + @example The following example shows how to initialize the device, perform a multi block read transfer using SDMA. + @code #define SECT_1 0x01u @@ -743,8 +842,8 @@ MSS_MMC_sdma_read @return This function returns a value of type mss_mmc_status_t which specifies the transfer status of the operation. - - Example: + + @example The following example shows how to initialize the device, perform a multi block transfer using ADMA2. @@ -822,9 +921,10 @@ MSS_MMC_adma2_write This function returns a value of type mss_mmc_status_t which specifies the transfer status of the operation. - Example: + @example The following example shows how to initialize the device, perform a multi block read transfer using ADMA2. + @code #define SECT_1 0x01u @@ -890,7 +990,7 @@ MSS_MMC_adma2_read This function returns a value of type mss_mmc_status_t which specifies the transfer status of the operation. - Example: + @example The following example shows how to initialize the SDIO device and perform single block transfer. @@ -962,7 +1062,7 @@ MSS_MMC_sdio_single_block_write This function returns a value of type mss_mmc_status_t which specifies the transfer status of the operation. - Example: + @example The following example shows how to initialize the SDIO device and perform single block transfer. @@ -1018,7 +1118,7 @@ MSS_MMC_sdio_single_block_read - MSS_MMC_TRANSFER_FAIL - MSS_MMC_RESPONSE_ERROR - Example: + @example The following example shows the use of MSS_MMC_get_transfer_status() function. @code @@ -1051,7 +1151,7 @@ mss_mmc_status_t MSS_MMC_get_transfer_status(void); @return This function does not return a value. - Example: + @example The following example shows the use of MSS_MMC_set_handler() function. @code @@ -1166,10 +1266,11 @@ mss_mmc_status_t MSS_MMC_cq_init(void); @return This function returns a value of type mss_mmc_status_t which specifies the transfer status of the operation. - - Example: + + @example The following example shows how to initialize the device and perform a multi block transfer.. + @code #define SECT_1 0x01u @@ -1250,7 +1351,7 @@ MSS_MMC_cq_write This function returns a value of type mss_mmc_status_t which specifies the transfer status of the operation. - Example: + @example The following example shows how to initialize the device and perform a multi block transfer. @@ -1310,8 +1411,8 @@ MSS_MMC_cq_read @return This function returns a value of type mss_mmc_status_t which specifies the status of the operation. - - Example: + + @example The following example shows how to initialize the device and perform a erase functionality. @@ -1347,8 +1448,60 @@ MSS_MMC_erase uint32_t start, uint32_t count ); + +/*-------------------------------------------------------------------------*//** + The MSS_MMC_error_recovery() function is used to check whether the error is + recoverable or non-recoverable. An error is detected and reported in + interrupt status register by read or write operation. + + Note: The MSS_MMC_error_recovery() function is used for the generic operation + of error recovery procedure not for Command Queuing error recovery. + + @param + This function has no parameters. + + @return + This function returns a value of type mss_mmc_status_t. The possible return + values are: + - MSS_MMC_TRANSFER_SUCCESS - recoverable + - MSS_MMC_TRANSFER_FAIL - non-recoverable + + @example + The following example shows the use of MSS_MMC_error_recovery() function. + + @code + + mss_mmc_status_t ret_status; + ret_status = MSS_MMC_sdma_read(SECT_1, data_buffer, BUFFER_SIZE); + do + { + ret_status = MSS_MMC_get_transfer_status(); + } while(ret_status == MSS_MMC_TRANSFER_IN_PROGRESS) + + if (ret_status == MSS_MMC_TRANSFER_FAIL) + { + ret_status = MSS_MMC_error_recovery(); + if (ret_status == MSS_MMC_TRANSFER_SUCCESS) + { + // recoverable + ret_status = MSS_MMC_sdma_read(SECT_1, data_buffer,BUFFER_SIZE); + do + { + ret_status = MSS_MMC_get_transfer_status(); + } while(ret_status == MSS_MMC_TRANSFER_IN_PROGRESS); + } + else + { + // non-recoverable + } + } + + @endcode + */ +mss_mmc_status_t MSS_MMC_error_recovery(void); + #ifdef __cplusplus } #endif -#endif /* __MSS_MMC_H */ +#endif /* MSS_MMC_H */ diff --git a/mss_mmc_if.c b/mss_mmc_if.c index ce543a2..60b854b 100644 --- a/mss_mmc_if.c +++ b/mss_mmc_if.c @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * @@ -23,6 +23,10 @@ extern "C" { #define MMC_SET 1u #define SHIFT_16BIT 16u #define DELAY_COUNT 0xFFFFu +#define SDHCI_CMD_MAX_TIMEOUT 3200u +#define SDHCI_CMD_DEFAULT_TIMEOUT 100u +#define CMD_INDEX_MASK 0x3Fu +#define CMD_TYPE_MASK 0xC0u /***************************************************************************//** * Local Function Prototypes @@ -43,9 +47,30 @@ cif_response_t cif_send_cmd { uint32_t trans_status_isr; cif_response_t ret_status = TRANSFER_IF_FAIL; + uint32_t time = MMC_CLEAR; + uint32_t cmd_timeout = SDHCI_CMD_DEFAULT_TIMEOUT; + uint32_t value = DELAY_COUNT; - /* clear all status interrupts except: - * current limit error, card interrupt, card removal, card insertion */ + /* check if command line is not busy */ + while ((MMC->SRS09 & SRS9_CMD_INHIBIT_CMD) != NO_CMD_INHIBIT) + { + if (time >= cmd_timeout) + { + if ((2u * cmd_timeout) <= SDHCI_CMD_MAX_TIMEOUT) + { + cmd_timeout += cmd_timeout; + } + else + { + return TRANSFER_IF_FAIL; + } + } + time++; + while (value-- != 0u); + value = DELAY_COUNT; + } + /* clear all status interrupts except: + * current limit error, card interrupt, card removal, card insertion */ MMC->SRS12 = ~(SRS12_CURRENT_LIMIT_ERROR | SRS12_CARD_INTERRUPT | SRS12_CARD_REMOVAL @@ -60,10 +85,12 @@ cif_response_t cif_send_cmd { trans_status_isr = MMC->SRS12; - if (SRS12_COMMAND_COMPLETE == (trans_status_isr & SRS12_COMMAND_COMPLETE)) + if ((SRS12_COMMAND_COMPLETE == (trans_status_isr & SRS12_COMMAND_COMPLETE)) && + (MMC_CLEAR == (SRS12_ERROR_INTERRUPT & trans_status_isr))) { /* If the response is an R1/B response */ - if ((MSS_MMC_RESPONSE_R1 == resp_type) || (MSS_MMC_RESPONSE_R1B == resp_type)) + if ((MSS_MMC_RESPONSE_R1 == (MSS_MMC_response_type)resp_type) + || (MSS_MMC_RESPONSE_R1B == (MSS_MMC_response_type)resp_type)) { ret_status = response_1_parser(); } @@ -107,19 +134,16 @@ void send_mmc_cmd cmd_response_check_options cmd_option ) { - uint32_t command_information; - uint32_t srs9, trans_status_isr; - - /* check if command line is not busy */ - do - { - srs9 = MMC->SRS09; - }while ((srs9 & SRS9_CMD_INHIBIT_CMD) != NO_CMD_INHIBIT); + uint32_t cmd_index, command_information; + uint32_t trans_status_isr; + uint32_t cmd_type_temp = MMC_CLEAR; command_information = process_request_checkresptype(resp_type); + cmd_index = cmd_type & CMD_INDEX_MASK; + cmd_type_temp = (cmd_type & CMD_TYPE_MASK) << SHIFT_16BIT; MMC->SRS02 = cmd_arg; - MMC->SRS03 = (uint32_t)((cmd_type << CMD_SHIFT) | command_information); + MMC->SRS03 = (uint32_t)((cmd_index << CMD_SHIFT) | cmd_type_temp | command_information); switch (cmd_option) { @@ -307,7 +331,7 @@ static cif_response_t cq_execute_task(uint8_t task_id) reg = MMC_SET << task_id; MMC->CQRS10 = reg; - while (value--); + while (value-- != 0u); do { diff --git a/mss_mmc_if.h b/mss_mmc_if.h index 6b368f5..0322f5d 100644 --- a/mss_mmc_if.h +++ b/mss_mmc_if.h @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * @@ -11,8 +11,8 @@ * */ -#ifndef __MSS_MMC_IF_H -#define __MSS_MMC_IF_H +#ifndef MSS_MMC_IF_H +#define MSS_MMC_IF_H #include #include @@ -158,4 +158,4 @@ cif_response_t cif_send_cq_direct_command } #endif -#endif /* __MSS_MMC_IF_H */ +#endif /* MSS_MMC_IF_H */ diff --git a/mss_mmc_internal_api.h b/mss_mmc_internal_api.h index 2405359..678f088 100644 --- a/mss_mmc_internal_api.h +++ b/mss_mmc_internal_api.h @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * @@ -61,8 +61,8 @@ only. *//*=========================================================================*/ -#ifndef __MSS_MMC_INTERNAL_API_H -#define __MSS_MMC_INTERNAL_API_H +#ifndef MSS_MMC_INTERNAL_API_H +#define MSS_MMC_INTERNAL_API_H #ifdef __cplusplus extern "C" @@ -607,4 +607,4 @@ MSS_MMC_cq_single_task_read } #endif -#endif /* __MSS_MMC_INTERNAL_API_H */ +#endif /* MSS_MMC_INTERNAL_API_H */ diff --git a/mss_mmc_regs.h b/mss_mmc_regs.h index 3d3113e..038a1f1 100644 --- a/mss_mmc_regs.h +++ b/mss_mmc_regs.h @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * @@ -7,8 +7,8 @@ * */ -#ifndef __MSS_MMC_REGS_H_ -#define __MSS_MMC_REGS_H_ +#ifndef MSS_MMC_REGS_H_ +#define MSS_MMC_REGS_H_ #ifdef __cplusplus extern "C" { @@ -1216,4 +1216,4 @@ static inline uint32_t CQ_DESC_DCMD_SET_CMD_INDEX(uint32_t idx) } #endif -#endif /* __MSS_MMC_REGS_H_ */ +#endif /* MSS_MMC_REGS_H_ */ diff --git a/mss_mmc_types.h b/mss_mmc_types.h index ccf8e24..fd0c020 100644 --- a/mss_mmc_types.h +++ b/mss_mmc_types.h @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * @@ -10,8 +10,8 @@ * */ -#ifndef __MSS_MMC_TYPE_H -#define __MSS_MMC_TYPE_H +#ifndef MSS_MMC_TYPE_H +#define MSS_MMC_TYPE_H #ifdef __cplusplus extern "C" @@ -244,4 +244,4 @@ typedef enum } #endif -#endif /* __MSS_MMC_TYPE_H */ +#endif /* MSS_MMC_TYPE_H */